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GET /api/patches/2194339/?format=api
{ "id": 2194339, "url": "http://patchwork.ozlabs.org/api/patches/2194339/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260208180746.2024338-11-mmaddireddy@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260208180746.2024338-11-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-02-08T18:07:43", "name": "[V5,10/13] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "56d70cfb280fbe4c1099a8674c6cffb4f602d5ce", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260208180746.2024338-11-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 491428, "url": "http://patchwork.ozlabs.org/api/series/491428/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=491428", "date": "2026-02-08T18:07:33", "name": "Fixes to pcie-tegra194 driver", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491428/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194339/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194339/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-11865-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": 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216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Manikanta Maddireddy <mmaddireddy@nvidia.com>", "To": "<bhelgaas@google.com>, <lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, \"Manikanta\n Maddireddy\" <mmaddireddy@nvidia.com>", "Subject": "[V5,10/13] PCI: tegra194: Apply pinctrl settings for both PCIe RP and\n EP", "Date": "Sun, 8 Feb 2026 23:37:43 +0530", "Message-ID": "<20260208180746.2024338-11-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260208180746.2024338-1-mmaddireddy@nvidia.com>", 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"X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(7416014)(376014)(36860700013)(921020);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t2jX1ZBa7TcP1Meo6hOi0wDNr/Jdcj/g3oSyoFX2Jf991xjBsT/rtw5GfaYFqk9YgExtOvHblBrykwoeXVggWsOgIPIr4XJF1QwbpjXyosWZea1zyimOJrqQaTRtNSScYxu4sFl27NjmBskj49UVUFCgqV/jb3+eEAmTuCRiF3R7BK6hZK/LKabE0RdKLgFAxj8T1gurPZXnxJIxZRH5Bp2QwAMkPeFynKy50EjF2ZF1MhNUBT6eSeEfyYhurKqdyvsdq8JXtkD4TNs3vDKQXRCEojiExGrQ669oKkB/22rSXYPJCEUQWHh7bpM0+TAeBp4sFieocHlOtCO8zegLrW1zEYiLgz/hGJ1PrI/i+R6x1rCeYV3EVBomn+x2RnCdWH33K5NsSrsqt3+noUHo7v3bhv7QIvVuZpVmxlFiSkjeuVyp5eN3IqozgvlOGpTF2", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Feb 2026 18:09:16.8343\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 593f377f-c05a-401d-fce8-08de673d2c72", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tMWH0EPF000971E4.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ2PR12MB9114" }, "content": "From: Vidya Sagar <vidyas@nvidia.com>\n\nPERST# and CLKREQ# pinctrl settings should be applied for both root port\nand endpoint mode. Move pinctrl_pm_select_default_state() function call\nfrom root port specific configuration function to probe().\n\nFixes: c57247f940e8 (\"PCI: tegra: Add support for PCIe endpoint mode in Tegra194\")\nSigned-off-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nV5:\n* Use dev_err_probe() function\n\nV4:\n* None\n\nV3:\n* None\n\nV2:\n* None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 10 ++++------\n 1 file changed, 4 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex bed6edb3d795..ea1f6b26f8ec 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -1609,12 +1609,6 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)\n \t\tgoto fail_pm_get_sync;\n \t}\n \n-\tret = pinctrl_pm_select_default_state(dev);\n-\tif (ret < 0) {\n-\t\tdev_err(dev, \"Failed to configure sideband pins: %d\\n\", ret);\n-\t\tgoto fail_pm_get_sync;\n-\t}\n-\n \tret = tegra_pcie_init_controller(pcie);\n \tif (ret < 0) {\n \t\tdev_err(dev, \"Failed to initialize controller: %d\\n\", ret);\n@@ -2079,6 +2073,10 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)\n \tpp = &pci->pp;\n \tpp->num_vectors = MAX_MSI_IRQS;\n \n+\tret = pinctrl_pm_select_default_state(dev);\n+\tif (ret < 0)\n+\t\treturn dev_err_probe(dev, ret, \"Failed to configure sideband pins: %d\\n\", ret);\n+\n \tret = tegra_pcie_dw_parse_dt(pcie);\n \tif (ret < 0) {\n \t\tconst char *level = KERN_ERR;\n", "prefixes": [ "V5", "10/13" ] }