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GET /api/patches/2194336/?format=api
{ "id": 2194336, "url": "http://patchwork.ozlabs.org/api/patches/2194336/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260208180746.2024338-4-mmaddireddy@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260208180746.2024338-4-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-02-08T18:07:36", "name": "[V5,03/13] PCI: tegra194: Don't force the device into the D0 state before L2", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7fe5107bf3a9949c79aa93e109609d617ac1c514", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260208180746.2024338-4-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 491429, "url": "http://patchwork.ozlabs.org/api/series/491429/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491429", "date": "2026-02-08T18:07:33", "name": "Fixes to pcie-tegra194 driver", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491429/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194336/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194336/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-46944-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Manikanta Maddireddy <mmaddireddy@nvidia.com>", "To": "<bhelgaas@google.com>, <lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, \"Manikanta\n Maddireddy\" <mmaddireddy@nvidia.com>", "Subject": "[V5,03/13] PCI: tegra194: Don't force the device into the D0 state\n before L2", "Date": "Sun, 8 Feb 2026 23:37:36 +0530", "Message-ID": "<20260208180746.2024338-4-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260208180746.2024338-1-mmaddireddy@nvidia.com>", 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"X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(7416014)(376014)(82310400026)(921020);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tbJqgStkyK2jq+CcOY381D/IRcp2O184qIGD7uHGQJQvJdyngM8TEscTT2aWBF73lL2hIEdJ5skIvsqdwQmA8GldfHJhAHjGDaC4T/w7eWlUE/7Q+djxaY/BZzXL/w/ej+SKYl7IcUFoB3Jjb2PsjGf9JeAIi2X0HKUYmF+srIqusUGlRLdNrliRkpwL/Hzny8J/Av7xqmijEHEOyRsBI5Mz2y2X0cjfwQg2vZOlf/Y7zpbRayogEWkUmmo+7HMsq8LpsiXmxD6BGKoK6CCgFMsjnvLiH9Er0Z7/kK3n1Fu1XhkPdtPBCeg4zH4k1F974WuBC4vDsdI5EEQrAia6RqgiCSTBrX09OfHIjGyX1e3YcbGG1WRVPZb5OQIbXezvHd0H4n18hHBHM8FQkirxsDwtqxA8B9S95Dj+YCDkkGuGRBksHdnk29ANJrQW6pFBL", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Feb 2026 18:08:37.6299\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a899ebba-7693-4b09-ed93-08de673d1518", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tMWH0EPF000971E3.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ0PR12MB6925" }, "content": "From: Vidya Sagar <vidyas@nvidia.com>\n\nAs per PCIe CEM spec rev 4.0 ver 1.0 sec 2.3, the PCIe endpoint device\nshould be in D3 state to assert wake# pin. This takes precedence over PCI\nExpress Base r4.0 v1.0 September 27-2017, 5.2 Link State Power Management\nwhich states that the device can be put into D0 state before taking the\nlink to L2 state. So, to enable the wake functionality for endpoints, do\nnot force the devices to D0 state before taking the link to L2 state.\nThere is no functional issue with the endpoints where the link doesn't go\ninto L2 state (the reason why the earlier change was made in the first\nplace) as the root port proceeds with the usual flow post PME timeout.\n\nFixes: 56e15a238d92 (\"PCI: tegra: Add Tegra194 PCIe support\")\nSigned-off-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nV5:\n* None\n\nV4:\n* None\n\nV3:\n* None\n\nV2:\n* None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 41 ----------------------\n 1 file changed, 41 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 4ac6b1cea13f..808a1e213b79 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -1261,44 +1261,6 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,\n \treturn 0;\n }\n \n-static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)\n-{\n-\tstruct dw_pcie_rp *pp = &pcie->pci.pp;\n-\tstruct pci_bus *child, *root_port_bus = NULL;\n-\tstruct pci_dev *pdev;\n-\n-\t/*\n-\t * link doesn't go into L2 state with some of the endpoints with Tegra\n-\t * if they are not in D0 state. So, need to make sure that immediate\n-\t * downstream devices are in D0 state before sending PME_TurnOff to put\n-\t * link into L2 state.\n-\t * This is as per PCI Express Base r4.0 v1.0 September 27-2017,\n-\t * 5.2 Link State Power Management (Page #428).\n-\t */\n-\n-\tlist_for_each_entry(child, &pp->bridge->bus->children, node) {\n-\t\tif (child->parent == pp->bridge->bus) {\n-\t\t\troot_port_bus = child;\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\tif (!root_port_bus) {\n-\t\tdev_err(pcie->dev, \"Failed to find downstream bus of Root Port\\n\");\n-\t\treturn;\n-\t}\n-\n-\t/* Bring downstream devices to D0 if they are not already in */\n-\tlist_for_each_entry(pdev, &root_port_bus->devices, bus_list) {\n-\t\tif (PCI_SLOT(pdev->devfn) == 0) {\n-\t\t\tif (pci_set_power_state(pdev, PCI_D0))\n-\t\t\t\tdev_err(pcie->dev,\n-\t\t\t\t\t\"Failed to transition %s to D0 state\\n\",\n-\t\t\t\t\tdev_name(&pdev->dev));\n-\t\t}\n-\t}\n-}\n-\n static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie)\n {\n \tpcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, \"vpcie3v3\");\n@@ -1627,7 +1589,6 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)\n \n static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)\n {\n-\ttegra_pcie_downstream_dev_to_D0(pcie);\n \tdw_pcie_host_deinit(&pcie->pci.pp);\n \ttegra_pcie_dw_pme_turnoff(pcie);\n \ttegra_pcie_unconfig_controller(pcie);\n@@ -2337,7 +2298,6 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev)\n \tif (!pcie->link_state)\n \t\treturn 0;\n \n-\ttegra_pcie_downstream_dev_to_D0(pcie);\n \ttegra_pcie_dw_pme_turnoff(pcie);\n \ttegra_pcie_unconfig_controller(pcie);\n \n@@ -2411,7 +2371,6 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev)\n \t\t\treturn;\n \n \t\tdebugfs_remove_recursive(pcie->debugfs);\n-\t\ttegra_pcie_downstream_dev_to_D0(pcie);\n \n \t\tdisable_irq(pcie->pci.pp.irq);\n \t\tif (IS_ENABLED(CONFIG_PCI_MSI))\n", "prefixes": [ "V5", "03/13" ] }