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GET /api/patches/2194335/?format=api
{ "id": 2194335, "url": "http://patchwork.ozlabs.org/api/patches/2194335/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260208180746.2024338-7-mmaddireddy@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260208180746.2024338-7-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-02-08T18:07:39", "name": "[V5,06/13] PCI: tegra194: Fix CBB timeout caused by DBI access before core power-on", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4133c07bbe37370b17fb883337c8c5af14b6e59c", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260208180746.2024338-7-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 491428, "url": "http://patchwork.ozlabs.org/api/series/491428/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=491428", "date": "2026-02-08T18:07:33", "name": "Fixes to pcie-tegra194 driver", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491428/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194335/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194335/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-11860-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": 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216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Manikanta Maddireddy <mmaddireddy@nvidia.com>", "To": "<bhelgaas@google.com>, <lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, \"Manikanta\n Maddireddy\" <mmaddireddy@nvidia.com>", "Subject": "[V5,06/13] PCI: tegra194: Fix CBB timeout caused by DBI access before\n core power-on", "Date": "Sun, 8 Feb 2026 23:37:39 +0530", "Message-ID": "<20260208180746.2024338-7-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": 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"X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(7416014)(36860700013)(921020);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t+oDCxAYw6tZXuFA0fsCHPY0KJDd0YXC/oFHrZwIPq7jTKH/vxBpBROmZh362UEp27rUgDqwRXKktKzjMtBsaodK+1yd5cjbNB+8WTBNkRz3rqGYqQON52DMNjOrubqcaXIAnHw/VOxiuMETC373uCBfPVCkt9tO8YDHSLD6gdHt9FmI9tF1WM7UBTKIXawUNjpgRAKbXNRqFz/6OeuOWbC4RjEbB+TzBgsK5rvJekhOByUWsn7pwqsWJlIcdIJQFrGLRa6DzLSjNkNeqC54gkgs1mKG1/w2iNZPBn68Va9FZkBkb4YbND5VowxGVTURUsVs5iuz9IySTw7q4ZJWqRGfmcojshFVLxghHDEPNyKUuGf3fFI2TahEbdmwihi4AJrKnqAR9958XXJKpE6oUD9n4quEKaTKTfb3KS/WVEGrgS1DM1fQmEVIrvMeUUu4v", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Feb 2026 18:08:55.6718\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e59a912e-b66e-4e21-5609-08de673d1fda", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tMWH0EPF000971E8.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY5PR12MB9053" }, "content": "When PERST# is deasserted twice (assert -> deassert -> assert -> deassert),\na CBB (Control Backbone) timeout occurs at DBI register offset 0x8bc\n(PCIE_MISC_CONTROL_1_OFF). This happens because pci_epc_deinit_notify()\nand dw_pcie_ep_cleanup() are called before reset_control_deassert() powers\non the controller core.\n\nThe call chain that causes the timeout:\n pex_ep_event_pex_rst_deassert()\n pci_epc_deinit_notify()\n pci_epf_test_epc_deinit()\n pci_epf_test_clear_bar()\n pci_epc_clear_bar()\n dw_pcie_ep_clear_bar()\n __dw_pcie_ep_reset_bar()\n dw_pcie_dbi_ro_wr_en() <- Accesses 0x8bc DBI register\n reset_control_deassert(pcie->core_rst) <- Core powered on HERE\n\nThe DBI registers, including PCIE_MISC_CONTROL_1_OFF (0x8bc), are only\naccessible after the controller core is powered on via\nreset_control_deassert(pcie->core_rst). Accessing them before this point\nresults in a CBB timeout because the hardware is not yet operational.\n\nFix this by moving pci_epc_deinit_notify() and dw_pcie_ep_cleanup() to\nafter reset_control_deassert(pcie->core_rst), ensuring the controller is\nfully powered on before any DBI register accesses occur.\n\nFixes: 40e2125381dc (\"PCI: tegra194: Move controller cleanups to pex_ep_event_pex_rst_deassert()\")\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nV5:\n* None\n\nV4:\n* None\n\nV3:\n* None\n\nV2:\n* None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 3924ac123183..bc9a66ba53e2 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -1742,10 +1742,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)\n \t\tgoto fail_phy;\n \t}\n \n-\t/* Perform cleanup that requires refclk */\n-\tpci_epc_deinit_notify(pcie->pci.ep.epc);\n-\tdw_pcie_ep_cleanup(&pcie->pci.ep);\n-\n \t/* Clear any stale interrupt statuses */\n \tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);\n \tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);\n@@ -1806,6 +1802,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)\n \n \treset_control_deassert(pcie->core_rst);\n \n+\t/* Perform cleanup that requires refclk and core reset deasserted */\n+\tpci_epc_deinit_notify(pcie->pci.ep.epc);\n+\tdw_pcie_ep_cleanup(&pcie->pci.ep);\n+\n \tif (pcie->update_fc_fixup) {\n \t\tval = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);\n \t\tval |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;\n", "prefixes": [ "V5", "06/13" ] }