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GET /api/patches/2194331/?format=api
{ "id": 2194331, "url": "http://patchwork.ozlabs.org/api/patches/2194331/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260208180746.2024338-3-mmaddireddy@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260208180746.2024338-3-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-02-08T18:07:35", "name": "[V5,02/13] PCI: tegra194: Refactor LTSSM state polling on surprise down", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "184e1cc32f4c856a3070a53e34a89214a566113c", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260208180746.2024338-3-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 491428, "url": "http://patchwork.ozlabs.org/api/series/491428/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=491428", "date": "2026-02-08T18:07:33", "name": "Fixes to pcie-tegra194 driver", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491428/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194331/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194331/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-11856-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Manikanta Maddireddy <mmaddireddy@nvidia.com>", "To": "<bhelgaas@google.com>, <lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, \"Manikanta\n Maddireddy\" <mmaddireddy@nvidia.com>", "Subject": "[V5,02/13] PCI: tegra194: Refactor LTSSM state polling on surprise\n down", "Date": "Sun, 8 Feb 2026 23:37:35 +0530", "Message-ID": "<20260208180746.2024338-3-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260208180746.2024338-1-mmaddireddy@nvidia.com>", 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"X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014)(7416014)(921020);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tfxJJUPHE+OBk0eYpUqFzH53qpknAhDYbIkHquRvnsN9rJvCCvKlj9evhcqVf4xb1K2q8lyWBygGbfS7SGYHOO42nrLTKoGjFXAsvXZETALl87Px7k0yQFIPlNjwHnfkRA+JCsBwCcW96x8TV6ZTy3idTN3Jiz29by6N104LB2dFExBbV3RshbDpgElkwNeKm+5sAfa6JqZZHHkOnxhmvP34Enh2NPSXR7Kcqwyw2IHBXmNaTCyvswEnKUvY3wFyj65eu80fvAZJ6uTeLlW2PCU08i+ErIQ628b2Bq8VoblgnFzmnHey49SLxVLxmBmUZIWcfDrNaJkb58w4uOfuZdg/P3nH8NUwzJfpinaHGr0q6XE1NGvdP4jM5KFT6XnA1KHcKcMns3VFzly9+PxO/AK0pm0qmxUkwpl/dKY5xYDSx+6ooU8zyR3quq0+Myo8v", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Feb 2026 18:08:32.3774\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b73e56cd-9455-4e7c-ac59-08de673d11f5", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tMWH0EPF000971E3.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB6604" }, "content": "From: Vidya Sagar <vidyas@nvidia.com>\n\nOn surprise down, LTSSM state transits from L0 -> Recovery.RcvrLock ->\nRecovery.RcvrSpeed -> Gen1 Recovery.RcvrLock -> Detect. Recovery.RcvrLock\nand Recovery.RcvrSpeed transit times are 24 msec and 48 msec respectively.\nSo, the total time taken to transit from L0 to detect state is ~96 msec.\nHence, increase the poll time to 120 msec.\n\nDisable the LTSSM state after it transits to detect to avoid LTSSM\ntoggling between polling and detect states.\n\ntegra_pcie_dw_pme_turnoff() function is called in non-atomic context\nonly, so use the non-atomic poll function.\n\nFixes: 56e15a238d92 (\"PCI: tegra: Add Tegra194 PCIe support\")\nFixes: c57247f940e8 (\"PCI: tegra: Add support for PCIe endpoint mode in Tegra194\")\nSigned-off-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nV5:\n* None\n\nV4:\n* None\n\nV3:\n* None\n\nV2:\n* None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 55 +++++++++++++---------\n 1 file changed, 32 insertions(+), 23 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 96d38571a7e7..4ac6b1cea13f 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -137,7 +137,11 @@\n #define APPL_DEBUG_PM_LINKST_IN_L0\t\t0x11\n #define APPL_DEBUG_LTSSM_STATE_MASK\t\tGENMASK(8, 3)\n #define APPL_DEBUG_LTSSM_STATE_SHIFT\t\t3\n-#define LTSSM_STATE_PRE_DETECT\t\t\t5\n+#define LTSSM_STATE_DETECT_QUIET\t\t0x00\n+#define LTSSM_STATE_DETECT_ACT\t\t\t0x08\n+#define LTSSM_STATE_PRE_DETECT_QUIET\t\t0x28\n+#define LTSSM_STATE_DETECT_WAIT\t\t\t0x30\n+#define LTSSM_STATE_L2_IDLE\t\t\t0xa8\n \n #define APPL_RADM_STATUS\t\t\t0xE4\n #define APPL_PM_XMT_TURNOFF_STATE\t\tBIT(0)\n@@ -201,7 +205,8 @@\n #define PME_ACK_DELAY\t\t100 /* 100 us */\n #define PME_ACK_TIMEOUT\t\t10000 /* 10 ms */\n \n-#define LTSSM_TIMEOUT 50000\t/* 50ms */\n+#define LTSSM_DELAY\t\t10000\t/* 10 ms */\n+#define LTSSM_TIMEOUT\t\t120000\t/* 120 ms */\n \n #define GEN3_GEN4_EQ_PRESET_INIT\t5\n \n@@ -1591,23 +1596,22 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)\n \t\tdata &= ~APPL_PINMUX_PEX_RST;\n \t\tappl_writel(pcie, data, APPL_PINMUX);\n \n+\t\terr = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, data,\n+\t\t\t((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) ||\n+\t\t\t((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||\n+\t\t\t((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_PRE_DETECT_QUIET) ||\n+\t\t\t((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_WAIT),\n+\t\t\tLTSSM_DELAY, LTSSM_TIMEOUT);\n+\t\tif (err)\n+\t\t\tdev_info(pcie->dev, \"Link didn't go to detect state\\n\");\n+\n \t\t/*\n-\t\t * Some cards do not go to detect state even after de-asserting\n-\t\t * PERST#. So, de-assert LTSSM to bring link to detect state.\n+\t\t * Deassert LTSSM state to stop the state toggling between\n+\t\t * polling and detect.\n \t\t */\n \t\tdata = readl(pcie->appl_base + APPL_CTRL);\n \t\tdata &= ~APPL_CTRL_LTSSM_EN;\n \t\twritel(data, pcie->appl_base + APPL_CTRL);\n-\n-\t\terr = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG,\n-\t\t\t\t\t\tdata,\n-\t\t\t\t\t\t((data &\n-\t\t\t\t\t\tAPPL_DEBUG_LTSSM_STATE_MASK) >>\n-\t\t\t\t\t\tAPPL_DEBUG_LTSSM_STATE_SHIFT) ==\n-\t\t\t\t\t\tLTSSM_STATE_PRE_DETECT,\n-\t\t\t\t\t\t1, LTSSM_TIMEOUT);\n-\t\tif (err)\n-\t\t\tdev_info(pcie->dev, \"Link didn't go to detect state\\n\");\n \t}\n \t/*\n \t * DBI registers may not be accessible after this as PLL-E would be\n@@ -1681,19 +1685,24 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)\n \tif (pcie->ep_state == EP_STATE_DISABLED)\n \t\treturn;\n \n-\t/* Disable LTSSM */\n+\tret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,\n+\t\t((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) ||\n+\t\t((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||\n+\t\t((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_PRE_DETECT_QUIET) ||\n+\t\t((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_WAIT) ||\n+\t\t((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_L2_IDLE),\n+\t\tLTSSM_DELAY, LTSSM_TIMEOUT);\n+\tif (ret)\n+\t\tdev_err(pcie->dev, \"LTSSM state: 0x%x timeout: %d\\n\", val, ret);\n+\n+\t/*\n+\t * Deassert LTSSM state to stop the state toggling between\n+\t * polling and detect.\n+\t */\n \tval = appl_readl(pcie, APPL_CTRL);\n \tval &= ~APPL_CTRL_LTSSM_EN;\n \tappl_writel(pcie, val, APPL_CTRL);\n \n-\tret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,\n-\t\t\t\t ((val & APPL_DEBUG_LTSSM_STATE_MASK) >>\n-\t\t\t\t APPL_DEBUG_LTSSM_STATE_SHIFT) ==\n-\t\t\t\t LTSSM_STATE_PRE_DETECT,\n-\t\t\t\t 1, LTSSM_TIMEOUT);\n-\tif (ret)\n-\t\tdev_err(pcie->dev, \"Failed to go Detect state: %d\\n\", ret);\n-\n \treset_control_assert(pcie->core_rst);\n \n \ttegra_pcie_disable_phy(pcie);\n", "prefixes": [ "V5", "02/13" ] }