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GET /api/patches/2194328/?format=api
{ "id": 2194328, "url": "http://patchwork.ozlabs.org/api/patches/2194328/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260208180746.2024338-2-mmaddireddy@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260208180746.2024338-2-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-02-08T18:07:34", "name": "[V5,01/13] PCI: tegra194: Fix polling delay for L2 state", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0101f7039a05689985dadbb2c66724861f4b90d4", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260208180746.2024338-2-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 491428, "url": "http://patchwork.ozlabs.org/api/series/491428/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=491428", "date": "2026-02-08T18:07:33", "name": "Fixes to pcie-tegra194 driver", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491428/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194328/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194328/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-11855-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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<lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, \"Manikanta\n Maddireddy\" <mmaddireddy@nvidia.com>", "Subject": "[V5,01/13] PCI: tegra194: Fix polling delay for L2 state", "Date": "Sun, 8 Feb 2026 23:37:34 +0530", "Message-ID": "<20260208180746.2024338-2-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260208180746.2024338-1-mmaddireddy@nvidia.com>", "References": "<20260208180746.2024338-1-mmaddireddy@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": 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"X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(7416014)(1800799024)(376014)(921020);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tb06rhFMiPQ7CrcblZFaoItdxBqlXZ1+KwEXlxDS/f8HidgT6MoQMuyQ98+C1byg1O5zQGy/wt3ZV739x+ePWAQz+GxCxEOueqjeZaj7medhk9HkF5nLRxy176tfldVKItXM/6ZuxdCI4axk33NQnZENz0tJy228+P0UWmrn0iw9ZH31/gqnZiepZt+UT08AziS96mP9qImwZqzvtZjBGJhIn+v4V6NqGIfjEGhFJXzZ6LKhBnL1WC1U2bNglRqX68lWIx7PcNymIXY4PTb7TsjAKd8wEYUvaFmgC38NfDpkABUpfSZlun9OwoG7yTJSlBhTrmS6wkdPcgagqYqZqerFUnGk2OyxbZ9jMff/W9//U92YO+AdkOSXSJ5s8aT0tBhshYxB7Ng9M9KoPGifUZm+d4hi0IgEDVObqwYEEAhfIeOv002spq/AgH6gihtXu", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Feb 2026 18:08:23.1284\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 746ba36e-50a3-483a-7ee3-08de673d0c62", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSJ1PEPF000023D8.namprd21.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH7PR12MB5709" }, "content": "From: Vidya Sagar <vidyas@nvidia.com>\n\nAs per PCIe spec r6.0, sec 5.3.3.2.1, after sending PME_Turn_Off message,\nRoot port should wait for 1~10 msec for PME_TO_Ack message. Currently,\ndriver is polling for 10 msec with 1 usec delay which is aggressive.\nChange it to 10 msec polling with 100 usec delay. Since this function\nis used in non-atomic context only, use non-atomic poll function.\n\nFixes: 56e15a238d92 (\"PCI: tegra: Add Tegra194 PCIe support\")\nSigned-off-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nV5:\n* None\n\nV4:\n* None\n\nV3:\n* None\n\nV2:\n* None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 9 +++++----\n 1 file changed, 5 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 0ddeef70726d..96d38571a7e7 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -198,7 +198,8 @@\n #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK\tGENMASK(11, 8)\n #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT\t8\n \n-#define PME_ACK_TIMEOUT 10000\n+#define PME_ACK_DELAY\t\t100 /* 100 us */\n+#define PME_ACK_TIMEOUT\t\t10000 /* 10 ms */\n \n #define LTSSM_TIMEOUT 50000\t/* 50ms */\n \n@@ -1553,9 +1554,9 @@ static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie)\n \tval |= APPL_PM_XMT_TURNOFF_STATE;\n \tappl_writel(pcie, val, APPL_RADM_STATUS);\n \n-\treturn readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val,\n-\t\t\t\t val & APPL_DEBUG_PM_LINKST_IN_L2_LAT,\n-\t\t\t\t 1, PME_ACK_TIMEOUT);\n+\treturn readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,\n+\t\t\t\t val & APPL_DEBUG_PM_LINKST_IN_L2_LAT,\n+\t\t\t\t PME_ACK_DELAY, PME_ACK_TIMEOUT);\n }\n \n static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)\n", "prefixes": [ "V5", "01/13" ] }