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GET /api/patches/2194311/?format=api
{ "id": 2194311, "url": "http://patchwork.ozlabs.org/api/patches/2194311/?format=api", "web_url": "http://patchwork.ozlabs.org/project/buildroot/patch/20260208143604.1477756-6-ju.o@free.fr/", "project": { "id": 27, "url": "http://patchwork.ozlabs.org/api/projects/27/?format=api", "name": "Buildroot development", "link_name": "buildroot", "list_id": "buildroot.buildroot.org", "list_email": "buildroot@buildroot.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260208143604.1477756-6-ju.o@free.fr>", "list_archive_url": null, "date": "2026-02-08T14:36:04", "name": "[RFC,5/5] arch: mark a set of target configurations as secondary", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e533e06735ee04ec43c0042b2011d0086b0fc5f2", "submitter": { "id": 80537, "url": "http://patchwork.ozlabs.org/api/people/80537/?format=api", "name": "Julien Olivain", "email": "ju.o@free.fr" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/buildroot/patch/20260208143604.1477756-6-ju.o@free.fr/mbox/", "series": [ { "id": 491421, "url": "http://patchwork.ozlabs.org/api/series/491421/?format=api", "web_url": "http://patchwork.ozlabs.org/project/buildroot/list/?series=491421", "date": "2026-02-08T14:35:59", "name": "Mark a set of target configurations as secondary", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491421/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194311/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194311/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<buildroot-bounces@buildroot.org>", "X-Original-To": [ "incoming-buildroot@patchwork.ozlabs.org", "buildroot@buildroot.org" ], "Delivered-To": [ "patchwork-incoming-buildroot@legolas.ozlabs.org", "buildroot@buildroot.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=buildroot.org header.i=@buildroot.org\n header.a=rsa-sha256 header.s=default header.b=p1mEdOFk;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=buildroot.org\n (client-ip=2605:bc80:3010::138; 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receiver=<UNKNOWN>", "DMARC-Filter": "OpenDMARC Filter v1.4.2 smtp1.osuosl.org 56A658222B", "To": "buildroot@buildroot.org", "Cc": "Mark Corbin <mark@dibsco.co.uk>,\n Thomas Petazzoni <thomas.petazzoni@bootlin.com>,\n Julien Olivain <ju.o@free.fr>", "Date": "Sun, 8 Feb 2026 15:36:04 +0100", "Message-ID": "<20260208143604.1477756-6-ju.o@free.fr>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260208143604.1477756-1-ju.o@free.fr>", "References": "<20260208143604.1477756-1-ju.o@free.fr>", "MIME-Version": "1.0", "X-Mailman-Original-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=free.fr; s=smtp-20201208; t=1770561407;\n bh=47bqJBMmNy5Jw/kuZuAFioBLqxwh2L48ZYy9leQyW50=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=dUBXRyG8Jjoz3Ztbv8BGLXlgLel4FWZsdMosqSa0Di3jCqvOUQPU6cWQo3TQwQCxL\n 3PWkDt5RNwnRkjMEXMDAXvaFsSTZn/E5c0r3L8Y9Rz9VH69io5h5nm7eLyp2wavQKK\n pkbf9XxBMIBhLhPu1ZVclWr5zuiVcCXG6CN5QfZeSDOjvu8agzjtZP9v5hzF7NC4Cb\n PvZNmqS6m3jmquFRgm9EGJ07Rdqa74Ph3pGVjeTfmGsTVG6LUgphWf7qTnVXlU6gil\n JZDJwYU1pV9384PUbA32Ec4c/vXR59RVxBZRFzUCWzW2+/djmoGMpmiAEserlyfbzz\n rmXOVxGJVgQmg==", "X-Mailman-Original-Authentication-Results": [ "smtp1.osuosl.org;\n dmarc=pass (p=quarantine dis=none)\n header.from=free.fr", "smtp1.osuosl.org;\n dkim=pass (2048-bit key) header.d=free.fr header.i=@free.fr\n header.a=rsa-sha256 header.s=smtp-20201208 header.b=dUBXRyG8" ], "Subject": "[Buildroot] [PATCH RFC 5/5] arch: mark a set of target\n configurations as secondary", "X-BeenThere": "buildroot@buildroot.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Discussion and development of buildroot <buildroot.buildroot.org>", "List-Unsubscribe": "<https://lists.buildroot.org/mailman/options/buildroot>,\n <mailto:buildroot-request@buildroot.org?subject=unsubscribe>", "List-Archive": "<http://lists.buildroot.org/pipermail/buildroot/>", "List-Post": "<mailto:buildroot@buildroot.org>", "List-Help": "<mailto:buildroot-request@buildroot.org?subject=help>", "List-Subscribe": "<https://lists.buildroot.org/mailman/listinfo/buildroot>,\n <mailto:buildroot-request@buildroot.org?subject=subscribe>", "From": "Julien Olivain via buildroot <buildroot@buildroot.org>", "Reply-To": "Julien Olivain <ju.o@free.fr>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "buildroot-bounces@buildroot.org", "Sender": "\"buildroot\" <buildroot-bounces@buildroot.org>" }, "content": "Those target configurations marked as \"secondary\" will be tested with a\nlower probability in autobuilders. The intent is to focus the Buildroot\ndevelopment (and bugfixes) on mainstream configurations, while still\nkeeping some other, less common, configurations.\n\nThis commit marks the following CPU architectures as secondary:\n\nBR2_arcle (ARC little endian)\nBR2_armeb (ARM big endian)\nBR2_aarch64_be (AArch64 big endian)\nBR2_hppa (PA-RISC)\nBR2_loongarch64\nBR2_m68k\nBR2_microblazeel (Microblaze AXI, little endian)\nBR2_microblazebe (Microblaze non-AXI, big endian)\nBR2_mips (MIPS, big endian)\nBR2_mipsel (MIPS, little endian)\nBR2_mips64 (MIPS64 big endian)\nBR2_or1k (OpenRISC)\nBR2_powerpc (PowerPC, big endian)\nBR2_powerpc64 (PowerPC64, big endian)\nBR2_s390x\nBR2_sh (SuperH)\nBR2_sparc\nBR2_sparc64\nBR2_xtensa\n\nIn the following CPU architecture, only specific configurations are\nmarked secondary:\n\nIn BR2_armeb (ARM little endian),\n- armv4 cores (arm920t, arm922t, fa526/626, strongarm sa110/sa1100)\n\nIn BR2_riscv:\n- all 32-bit configurations\n- 64-bit no-MMU\n\nIn BR2_i386 (x86 32-bit),\n- i486, i586 and X1000 CPU\n\nThere was no strict rule established to build this list of secondary\nconfigurations. This list was built mainly from the observation of\nwhich architecture/CPUs are still widely used in the field\n(disregarding its age), the quality of their upstream support and\nthe general relevance in the Buildroot project.\n\nSigned-off-by: Julien Olivain <ju.o@free.fr>\n---\n arch/Config.in | 19 +++++++++++++++++++\n arch/Config.in.arm | 5 +++++\n arch/Config.in.riscv | 2 ++\n arch/Config.in.x86 | 3 +++\n 4 files changed, 29 insertions(+)", "diff": "diff --git a/arch/Config.in b/arch/Config.in\nindex e6b4fd040e..c97836a506 100644\n--- a/arch/Config.in\n+++ b/arch/Config.in\n@@ -44,6 +44,7 @@ choice\n \n config BR2_arcle\n \tbool \"ARC (little endian)\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_USE_MMU\n \thelp\n \t Synopsys' DesignWare ARC Processor Cores are a family of\n@@ -62,6 +63,7 @@ config BR2_arm\n \n config BR2_armeb\n \tbool \"ARM (big endian)\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_USE_MMU\n \thelp\n \t ARM is a 32-bit reduced instruction set computer (RISC)\n@@ -80,6 +82,7 @@ config BR2_aarch64\n \n config BR2_aarch64_be\n \tbool \"AArch64 (big endian)\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_ARCH_IS_64\n \thelp\n \t Aarch64 is a 64-bit architecture developed by ARM Holdings.\n@@ -88,6 +91,7 @@ config BR2_aarch64_be\n \n config BR2_hppa\n \tbool \"HPPA\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_USE_MMU\n \thelp\n \t Precision Architecture (a.k.a. PA-RISC) is a 32-bit\n@@ -103,6 +107,7 @@ config BR2_i386\n \n config BR2_loongarch64\n \tbool \"LoongArch64\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_USE_MMU\n \tselect BR2_ARCH_IS_64\n \tselect BR2_ARCH_NEEDS_GCC_AT_LEAST_12\n@@ -113,6 +118,7 @@ config BR2_loongarch64\n \n config BR2_m68k\n \tbool \"m68k\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \t# MMU support is set by the subarchitecture file, arch/Config.in.m68k\n \thelp\n \t Motorola 68000 family microprocessor\n@@ -120,6 +126,7 @@ config BR2_m68k\n \n config BR2_microblazeel\n \tbool \"Microblaze AXI (little endian)\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_USE_MMU\n \thelp\n \t Soft processor core designed for Xilinx FPGAs from Xilinx. AXI\n@@ -129,6 +136,7 @@ config BR2_microblazeel\n \n config BR2_microblazebe\n \tbool \"Microblaze non-AXI (big endian)\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_USE_MMU\n \thelp\n \t Soft processor core designed for Xilinx FPGAs from Xilinx. PLB\n@@ -138,6 +146,7 @@ config BR2_microblazebe\n \n config BR2_mips\n \tbool \"MIPS (big endian)\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_USE_MMU\n \thelp\n \t MIPS is a RISC microprocessor from MIPS Technologies. Big\n@@ -147,6 +156,7 @@ config BR2_mips\n \n config BR2_mipsel\n \tbool \"MIPS (little endian)\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_USE_MMU\n \thelp\n \t MIPS is a RISC microprocessor from MIPS Technologies. Little\n@@ -156,6 +166,7 @@ config BR2_mipsel\n \n config BR2_mips64\n \tbool \"MIPS64 (big endian)\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_ARCH_IS_64\n \tselect BR2_USE_MMU\n \thelp\n@@ -176,6 +187,7 @@ config BR2_mips64el\n \n config BR2_or1k\n \tbool \"OpenRISC\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_USE_MMU\n \thelp\n \t OpenRISC is a free and open processor for embedded system.\n@@ -183,6 +195,7 @@ config BR2_or1k\n \n config BR2_powerpc\n \tbool \"PowerPC\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_USE_MMU\n \thelp\n \t PowerPC is a RISC architecture created by Apple-IBM-Motorola\n@@ -192,6 +205,7 @@ config BR2_powerpc\n \n config BR2_powerpc64\n \tbool \"PowerPC64 (big endian)\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_ARCH_IS_64\n \tselect BR2_USE_MMU\n \thelp\n@@ -222,6 +236,7 @@ config BR2_riscv\n \n config BR2_s390x\n \tbool \"s390x\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_ARCH_IS_64\n \tselect BR2_USE_MMU\n \thelp\n@@ -231,6 +246,7 @@ config BR2_s390x\n \n config BR2_sh\n \tbool \"SuperH\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_USE_MMU\n \thelp\n \t SuperH (or SH) is a 32-bit reduced instruction set computer\n@@ -241,6 +257,7 @@ config BR2_sh\n \n config BR2_sparc\n \tbool \"SPARC\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_USE_MMU\n \thelp\n \t SPARC (from Scalable Processor Architecture) is a RISC\n@@ -251,6 +268,7 @@ config BR2_sparc\n \n config BR2_sparc64\n \tbool \"SPARC64\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_ARCH_IS_64\n \tselect BR2_USE_MMU\n \thelp\n@@ -271,6 +289,7 @@ config BR2_x86_64\n \n config BR2_xtensa\n \tbool \"Xtensa\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \t# MMU support is set by the subarchitecture file, arch/Config.in.xtensa\n \thelp\n \t Xtensa is a Tensilica processor IP architecture.\ndiff --git a/arch/Config.in.arm b/arch/Config.in.arm\nindex a0bf6c3386..80e197529c 100644\n--- a/arch/Config.in.arm\n+++ b/arch/Config.in.arm\n@@ -112,22 +112,27 @@ choice\n \n if !BR2_ARCH_IS_64\n comment \"armv4 cores\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n config BR2_arm920t\n \tbool \"arm920t\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_ARM_CPU_HAS_ARM\n \tselect BR2_ARM_CPU_HAS_THUMB\n \tselect BR2_ARM_CPU_ARMV4\n config BR2_arm922t\n \tbool \"arm922t\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_ARM_CPU_HAS_ARM\n \tselect BR2_ARM_CPU_HAS_THUMB\n \tselect BR2_ARM_CPU_ARMV4\n config BR2_fa526\n \tbool \"fa526/626\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_ARM_CPU_HAS_ARM\n \tselect BR2_ARM_CPU_ARMV4\n config BR2_strongarm\n \tbool \"strongarm sa110/sa1100\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tselect BR2_ARM_CPU_HAS_ARM\n \tselect BR2_ARM_CPU_ARMV4\n \ndiff --git a/arch/Config.in.riscv b/arch/Config.in.riscv\nindex 299190f364..4ca2ff74c2 100644\n--- a/arch/Config.in.riscv\n+++ b/arch/Config.in.riscv\n@@ -58,10 +58,12 @@ choice\n \n config BR2_RISCV_32\n \tbool \"32-bit\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \n config BR2_RISCV_64\n \tbool \"64-bit\"\n \tselect BR2_ARCH_IS_64\n+\tselect BR2_RISCV_USE_MMU if !BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \n endchoice\n \ndiff --git a/arch/Config.in.x86 b/arch/Config.in.x86\nindex 548bef9226..64bdb2cd86 100644\n--- a/arch/Config.in.x86\n+++ b/arch/Config.in.x86\n@@ -42,12 +42,15 @@ choice\n \n config BR2_x86_i486\n \tbool \"i486\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tdepends on !BR2_x86_64\n config BR2_x86_i586\n \tbool \"i586\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tdepends on !BR2_x86_64\n config BR2_x86_x1000\n \tbool \"x1000\"\n+\tdepends on BR2_SHOW_SECONDARY_TARGET_OPTIONS\n \tdepends on !BR2_x86_64\n \thelp\n \t The Intel X1000 is a Pentium class microprocessor in the\n", "prefixes": [ "RFC", "5/5" ] }