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GET /api/patches/2194247/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2194247,
    "url": "http://patchwork.ozlabs.org/api/patches/2194247/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260207180632.1042754-3-brian.cain@oss.qualcomm.com/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260207180632.1042754-3-brian.cain@oss.qualcomm.com>",
    "list_archive_url": null,
    "date": "2026-02-07T18:06:30",
    "name": "[v2,2/4] target/hexagon: Reject duplex encodings with duplicate dest registers",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "6e0e6ddb2a45ea8235acb08c96198e0167272585",
    "submitter": {
        "id": 89839,
        "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api",
        "name": "Brian Cain",
        "email": "brian.cain@oss.qualcomm.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260207180632.1042754-3-brian.cain@oss.qualcomm.com/mbox/",
    "series": [
        {
            "id": 491391,
            "url": "http://patchwork.ozlabs.org/api/series/491391/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491391",
            "date": "2026-02-07T18:06:28",
            "name": "Handle some invalid encodings",
            "version": 2,
            "mbox": "http://patchwork.ozlabs.org/series/491391/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2194247/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2194247/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        ],
        "From": "Brian Cain <brian.cain@oss.qualcomm.com>",
        "To": "qemu-devel@nongnu.org",
        "Cc": "brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com, alex@alexrp.com,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>",
        "Subject": "[PATCH v2 2/4] target/hexagon: Reject duplex encodings with duplicate\n dest registers",
        "Date": "Sat,  7 Feb 2026 10:06:30 -0800",
        "Message-Id": "<20260207180632.1042754-3-brian.cain@oss.qualcomm.com>",
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    },
    "content": "A duplex encoding like 0x00000000 decodes as two loads that both write r0.\n\nAdd a check in decode_insns() after both sub-instructions decode\nsuccessfully to verify they don't write the same destination register.\n\nResolves: https://gitlab.com/qemu-project/qemu/-/issues/2696\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\nReviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>\n---\n target/hexagon/decode.c              | 12 ++++++++++++\n tests/tcg/hexagon/invalid-encoding.c | 29 ++++++++++++++++++++++++++++\n 2 files changed, 41 insertions(+)",
    "diff": "diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c\nindex 69ba1ec96c..90499fc320 100644\n--- a/target/hexagon/decode.c\n+++ b/target/hexagon/decode.c\n@@ -501,12 +501,24 @@ decode_insns(DisasContext *ctx, Insn *insn, uint32_t encoding)\n \n         /* The slot1 subinsn needs to be in the packet first */\n         if (decode_slot1_subinsn(ctx, slot1_subinsn)) {\n+            Insn *slot1_insn = insn;\n             insn->generate = opcode_genptr[insn->opcode];\n             insn->iclass = iclass_bits(encoding);\n             ctx->insn = ++insn;\n             if (decode_slot0_subinsn(ctx, slot0_subinsn)) {\n                 insn->generate = opcode_genptr[insn->opcode];\n                 insn->iclass = iclass_bits(encoding);\n+                /*\n+                 * Check that the two sub-instructions don't write the same\n+                 * destination register (e.g., encoding 0x0 decodes as two\n+                 * loads both writing R0, which is an invalid packet).\n+                 */\n+                if (insn->dest_idx >= 0 && slot1_insn->dest_idx >= 0 &&\n+                    insn->regno[insn->dest_idx] ==\n+                        slot1_insn->regno[slot1_insn->dest_idx]) {\n+                    ctx->insn = --insn;\n+                    return 0;\n+                }\n                 return 2;\n             }\n             /*\ndiff --git a/tests/tcg/hexagon/invalid-encoding.c b/tests/tcg/hexagon/invalid-encoding.c\nindex 010a5eb741..1bbd312b61 100644\n--- a/tests/tcg/hexagon/invalid-encoding.c\n+++ b/tests/tcg/hexagon/invalid-encoding.c\n@@ -65,6 +65,34 @@ static int test_invalid_duplex(void)\n     return sig;\n }\n \n+/*\n+ * Duplex with duplicate destination registers (issue #2696):\n+ * The encoding 0x00000000 decodes as a duplex with parse bits\n+ * [15:14] = 0b00:\n+ *   slot1: SL1_loadri_io R0 = memw(R0+#0x0)\n+ *   slot0: SL1_loadri_io R0 = memw(R0+#0x0)\n+ *\n+ * Both sub-instructions write R0, which is an invalid packet (duplicate\n+ * destination register).  This should raise SIGILL.\n+ */\n+static int test_invalid_dups(void)\n+{\n+    int sig;\n+\n+    asm volatile(\n+        \"r0 = #0\\n\"\n+        \"r1 = ##1f\\n\"\n+        \"memw(%1) = r1\\n\"\n+        \".word 0x00000000\\n\"\n+        \"1:\\n\"\n+        \"%0 = r0\\n\"\n+        : \"=r\"(sig)\n+        : \"r\"(&resume_pc)\n+        : \"r0\", \"r1\", \"memory\");\n+\n+    return sig;\n+}\n+\n int main()\n {\n     struct sigaction act;\n@@ -75,6 +103,7 @@ int main()\n     assert(sigaction(SIGILL, &act, NULL) == 0);\n \n     assert(test_invalid_duplex() == SIGILL);\n+    assert(test_invalid_dups() == SIGILL);\n \n     puts(\"PASS\");\n     return EXIT_SUCCESS;\n",
    "prefixes": [
        "v2",
        "2/4"
    ]
}