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GET /api/patches/2194218/?format=api
{ "id": 2194218, "url": "http://patchwork.ozlabs.org/api/patches/2194218/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260207130642.2833312-2-festevam@gmail.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260207130642.2833312-2-festevam@gmail.com>", "list_archive_url": null, "date": "2026-02-07T13:06:42", "name": "[v2,2/2] pinctrl: rockchip: Add RV1103B pinctrl support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "921b04552ed7d904c2e5616260cf3c19d5d424ae", "submitter": { "id": 6978, "url": "http://patchwork.ozlabs.org/api/people/6978/?format=api", "name": "Fabio Estevam", "email": "festevam@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260207130642.2833312-2-festevam@gmail.com/mbox/", "series": [ { "id": 491378, "url": "http://patchwork.ozlabs.org/api/series/491378/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=491378", "date": "2026-02-07T13:06:41", "name": "[v2,1/2] dt-bindings: pinctrl: rockchip: Add RV1103B compatible", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/491378/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194218/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194218/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-31503-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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AJvYcCW4W7aXLdYDJr+G5K1bzIdbHBGCRGx6XPWDY3HKPTaCqXL7DtoOTCAxx4Tl/q6F0o3luAnaMvg5u3EF@vger.kernel.org", "X-Gm-Message-State": "AOJu0YyuibJvbruvySpx9nFkOUXm0z08+LRWXJFhMQGH9IA/UM2u8T20\n\t1skLkaNODDAwCnASJX0BzXIxqKJ52M8mAtrsxbGn5SGsdSMMBkPdupTr", "X-Gm-Gg": "AZuq6aK2yk7LQIAc+Wy3MOxILnnPwsotKIfrzd7MZqrxJK8Dk8jkV/y9G559qHn0nmM\n\tXUeSHkl8hqTWGgn0RoX80r+3wqhqixAgzroC/2WgLn3LEISTvLOXwlA5YRd0TLRpsjAaKcIJhyt\n\tuCjmyXWY85izUp1hOUX43z59pIOlyPe7zBQkvCnql92Q5PS1OIkVKWyF9QaXUZnBJsAojguvfv7\n\t1Z+e7wJhOuRv3w36GlSrQVAYE0YeaxFpOv/8FC+h368gdEbEaA625QB1DAmPlBw08tnB1X+xgG6\n\ta/YABL1GycNQxYfIGX4//mQtb4OHZxtk8cLRx72M74WNyk6wJL9v+2vdFVE6GXM27zhlJcXlpxp\n\tAV7wzOSnbFwWjD3rM652603l3EOLOY65RMehTgGAZQVb1CmLnXgYGZVC3+dqaUz7ttCC/rUI7tv\n\taFBkPTNoNA3UH0H1MmKsNJ1/0c", "X-Received": "by 2002:a05:690e:144a:b0:649:ef5b:aeaf with SMTP id\n 956f58d0204a3-649ef5bbc11mr6283624d50.25.1770469616826;\n Sat, 07 Feb 2026 05:06:56 -0800 (PST)", "From": "Fabio Estevam <festevam@gmail.com>", "To": "linusw@kernel.org", "Cc": "heiko@sntech.de,\n\trobh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tlinux-gpio@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-rockchip@lists.infradead.org,\n\tjonas@kwiboo.se,\n\tFabio Estevam <festevam@nabladev.com>", "Subject": "[PATCH v2 2/2] pinctrl: rockchip: Add RV1103B pinctrl support", "Date": "Sat, 7 Feb 2026 10:06:42 -0300", "Message-Id": "<20260207130642.2833312-2-festevam@gmail.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260207130642.2833312-1-festevam@gmail.com>", "References": "<20260207130642.2833312-1-festevam@gmail.com>", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "From: Fabio Estevam <festevam@nabladev.com>\n\nAdd pinctrl support for the RV1103B.\n\nBased on the 5.10 Rockchip vendor kernel driver.\n\nSigned-off-by: Fabio Estevam <festevam@nabladev.com>\n---\nChanges since v1:\n - None.\n \n drivers/pinctrl/pinctrl-rockchip.c | 313 ++++++++++++++++++++++++++++-\n drivers/pinctrl/pinctrl-rockchip.h | 1 +\n 2 files changed, 313 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c\nindex 2fc67aeafdb3..092ce4cac9cf 100644\n--- a/drivers/pinctrl/pinctrl-rockchip.c\n+++ b/drivers/pinctrl/pinctrl-rockchip.c\n@@ -467,6 +467,22 @@ static const struct pinctrl_ops rockchip_pctrl_ops = {\n * Hardware access\n */\n \n+static struct rockchip_mux_recalced_data rv1103b_mux_recalced_data[] = {\n+\t{\n+\t\t.num = 1,\n+\t\t.pin = 6,\n+\t\t.reg = 0x10024,\n+\t\t.bit = 8,\n+\t\t.mask = 0xf\n+\t}, {\n+\t\t.num = 1,\n+\t\t.pin = 7,\n+\t\t.reg = 0x10024,\n+\t\t.bit = 12,\n+\t\t.mask = 0xf\n+\t},\n+};\n+\n static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {\n \t{\n \t\t.num = 1,\n@@ -1172,6 +1188,9 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)\n \telse\n \t\tregmap = info->regmap_base;\n \n+\tif (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12)\n+\t\treturn 0;\n+\n \tif (ctrl->type == RK3506) {\n \t\tif (bank->bank_num == 1)\n \t\t\tregmap = info->regmap_ioc1;\n@@ -1298,6 +1317,9 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)\n \telse\n \t\tregmap = info->regmap_base;\n \n+\tif (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12)\n+\t\treturn 0;\n+\n \tif (ctrl->type == RK3506) {\n \t\tif (bank->bank_num == 1)\n \t\t\tregmap = info->regmap_ioc1;\n@@ -1495,6 +1517,214 @@ static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,\n \treturn 0;\n }\n \n+#define RV1103B_DRV_BITS_PER_PIN\t\t8\n+#define RV1103B_DRV_PINS_PER_REG\t\t2\n+#define RV1103B_DRV_GPIO0_A_OFFSET\t\t0x40100\n+#define RV1103B_DRV_GPIO0_B_OFFSET\t\t0x50110\n+#define RV1103B_DRV_GPIO1_A01_OFFSET\t\t0x140\n+#define RV1103B_DRV_GPIO1_A67_OFFSET\t\t0x1014C\n+#define RV1103B_DRV_GPIO2_OFFSET\t\t0x30180\n+#define RV1103B_DRV_GPIO2_SARADC_OFFSET\t\t0x3080C\n+\n+static int rv1103b_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,\n+\t\t\t\t int pin_num, struct regmap **regmap,\n+\t\t\t\t int *reg, u8 *bit)\n+{\n+\tstruct rockchip_pinctrl *info = bank->drvdata;\n+\tint ret = 0;\n+\n+\t*regmap = info->regmap_base;\n+\tswitch (bank->bank_num) {\n+\tcase 0:\n+\t\tif (pin_num < 7)\n+\t\t\t*reg = RV1103B_DRV_GPIO0_A_OFFSET;\n+\t\telse if (pin_num > 7 && pin_num < 14)\n+\t\t\t*reg = RV1103B_DRV_GPIO0_B_OFFSET - 0x10;\n+\t\telse\n+\t\t\tret = -EINVAL;\n+\t\tbreak;\n+\n+\tcase 1:\n+\t\tif (pin_num < 6)\n+\t\t\t*reg = RV1103B_DRV_GPIO1_A01_OFFSET;\n+\t\telse if (pin_num >= 6 && pin_num < 23)\n+\t\t\t*reg = RV1103B_DRV_GPIO1_A67_OFFSET - 0xc;\n+\t\telse if (pin_num >= 24 && pin_num < 30)\n+\t\t\t*reg = RV1103B_DRV_GPIO1_A67_OFFSET - 0xc;\n+\t\telse\n+\t\t\tret = -EINVAL;\n+\t\tbreak;\n+\n+\tcase 2:\n+\t\tif (pin_num < 12) {\n+\t\t\t*reg = RV1103B_DRV_GPIO2_OFFSET;\n+\t\t} else if (pin_num >= 16) {\n+\t\t\tret = -EINVAL;\n+\t\t} else {\n+\t\t\t*reg = RV1103B_DRV_GPIO2_SARADC_OFFSET;\n+\t\t\t*bit = 10;\n+\n+\t\t\treturn 0;\n+\t\t}\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\tif (ret) {\n+\t\tdev_err(info->dev, \"unsupported bank_num %d pin_num %d\\n\", bank->bank_num, pin_num);\n+\n+\t\treturn ret;\n+\t}\n+\n+\t*reg += ((pin_num / RV1103B_DRV_PINS_PER_REG) * 4);\n+\t*bit = pin_num % RV1103B_DRV_PINS_PER_REG;\n+\t*bit *= RV1103B_DRV_BITS_PER_PIN;\n+\n+\treturn 0;\n+}\n+\n+#define RV1103B_PULL_BITS_PER_PIN\t\t2\n+#define RV1103B_PULL_PINS_PER_REG\t\t8\n+#define RV1103B_PULL_GPIO0_A_OFFSET\t\t0x40200\n+#define RV1103B_PULL_GPIO0_B_OFFSET\t\t0x50204\n+#define RV1103B_PULL_GPIO1_A01_OFFSET\t\t0x210\n+#define RV1103B_PULL_GPIO1_A67_OFFSET\t\t0x10210\n+#define RV1103B_PULL_GPIO2_OFFSET\t\t0x30220\n+#define RV1103B_PULL_GPIO2_SARADC_OFFSET\t0x3080C\n+\n+static int rv1103b_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,\n+\t\t\t\t\tint pin_num, struct regmap **regmap,\n+\t\t\t\t\tint *reg, u8 *bit)\n+{\n+\tstruct rockchip_pinctrl *info = bank->drvdata;\n+\tint ret = 0;\n+\n+\t*regmap = info->regmap_base;\n+\tswitch (bank->bank_num) {\n+\tcase 0:\n+\t\tif (pin_num < 7)\n+\t\t\t*reg = RV1103B_PULL_GPIO0_A_OFFSET;\n+\t\telse if (pin_num > 7 && pin_num < 14)\n+\t\t\t*reg = RV1103B_PULL_GPIO0_B_OFFSET - 0x4;\n+\t\telse\n+\t\t\tret = -EINVAL;\n+\t\tbreak;\n+\n+\tcase 1:\n+\t\tif (pin_num < 6)\n+\t\t\t*reg = RV1103B_PULL_GPIO1_A01_OFFSET;\n+\t\telse if (pin_num >= 6 && pin_num < 23)\n+\t\t\t*reg = RV1103B_PULL_GPIO1_A67_OFFSET;\n+\t\telse if (pin_num >= 24 && pin_num < 30)\n+\t\t\t*reg = RV1103B_PULL_GPIO1_A67_OFFSET;\n+\t\telse\n+\t\t\tret = -EINVAL;\n+\t\tbreak;\n+\n+\tcase 2:\n+\t\tif (pin_num < 12) {\n+\t\t\t*reg = RV1103B_PULL_GPIO2_OFFSET;\n+\t\t} else if (pin_num >= 16) {\n+\t\t\tret = -EINVAL;\n+\t\t} else {\n+\t\t\t*reg = RV1103B_PULL_GPIO2_SARADC_OFFSET;\n+\t\t\t*bit = 13;\n+\n+\t\t\treturn 0;\n+\t\t}\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\tif (ret) {\n+\t\tdev_err(info->dev, \"unsupported bank_num %d pin_num %d\\n\", bank->bank_num, pin_num);\n+\n+\t\treturn ret;\n+\t}\n+\n+\t*reg += ((pin_num / RV1103B_PULL_PINS_PER_REG) * 4);\n+\t*bit = pin_num % RV1103B_PULL_PINS_PER_REG;\n+\t*bit *= RV1103B_PULL_BITS_PER_PIN;\n+\n+\treturn 0;\n+}\n+\n+#define RV1103B_SMT_BITS_PER_PIN\t\t1\n+#define RV1103B_SMT_PINS_PER_REG\t\t8\n+#define RV1103B_SMT_GPIO0_A_OFFSET\t\t0x40400\n+#define RV1103B_SMT_GPIO0_B_OFFSET\t\t0x50404\n+#define RV1103B_SMT_GPIO1_A01_OFFSET\t\t0x410\n+#define RV1103B_SMT_GPIO1_A67_OFFSET\t\t0x10410\n+#define RV1103B_SMT_GPIO2_OFFSET\t\t0x30420\n+#define RV1103B_SMT_GPIO2_SARADC_OFFSET\t\t0x3080C\n+\n+static int rv1103b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,\n+\t\t\t\t\t int pin_num,\n+\t\t\t\t\t struct regmap **regmap,\n+\t\t\t\t\t int *reg, u8 *bit)\n+{\n+\tstruct rockchip_pinctrl *info = bank->drvdata;\n+\tint ret = 0;\n+\n+\t*regmap = info->regmap_base;\n+\tswitch (bank->bank_num) {\n+\tcase 0:\n+\t\tif (pin_num < 7)\n+\t\t\t*reg = RV1103B_SMT_GPIO0_A_OFFSET;\n+\t\telse if (pin_num > 7 && pin_num < 14)\n+\t\t\t*reg = RV1103B_SMT_GPIO0_B_OFFSET - 0x4;\n+\t\telse\n+\t\t\tret = -EINVAL;\n+\t\tbreak;\n+\n+\tcase 1:\n+\t\tif (pin_num < 6)\n+\t\t\t*reg = RV1103B_SMT_GPIO1_A01_OFFSET;\n+\t\telse if (pin_num >= 6 && pin_num < 23)\n+\t\t\t*reg = RV1103B_SMT_GPIO1_A67_OFFSET;\n+\t\telse if (pin_num >= 24 && pin_num < 30)\n+\t\t\t*reg = RV1103B_SMT_GPIO1_A67_OFFSET;\n+\t\telse\n+\t\t\tret = -EINVAL;\n+\t\tbreak;\n+\n+\tcase 2:\n+\t\tif (pin_num < 12) {\n+\t\t\t*reg = RV1103B_SMT_GPIO2_OFFSET;\n+\t\t} else if (pin_num >= 16) {\n+\t\t\tret = -EINVAL;\n+\t\t} else {\n+\t\t\t*reg = RV1103B_SMT_GPIO2_SARADC_OFFSET;\n+\t\t\t*bit = 8;\n+\n+\t\t\treturn 0;\n+\t\t}\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\tif (ret) {\n+\t\tdev_err(info->dev, \"unsupported bank_num %d pin_num %d\\n\", bank->bank_num, pin_num);\n+\n+\t\treturn ret;\n+\t}\n+\n+\t*reg += ((pin_num / RV1103B_SMT_PINS_PER_REG) * 4);\n+\t*bit = pin_num % RV1103B_SMT_PINS_PER_REG;\n+\t*bit *= RV1103B_SMT_BITS_PER_PIN;\n+\n+\treturn 0;\n+}\n+\n #define RV1108_PULL_PMU_OFFSET\t\t0x10\n #define RV1108_PULL_OFFSET\t\t0x110\n #define RV1108_PULL_PINS_PER_REG\t8\n@@ -2982,6 +3212,9 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,\n \tu8 bit;\n \tint drv_type = bank->drv[pin_num / 8].drv_type;\n \n+\tif (ctrl->type == RV1103B && pin_num >= 12)\n+\t\tdrv_type = DRV_TYPE_IO_LEVEL_2_BIT;\n+\n \tret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);\n \tif (ret)\n \t\treturn ret;\n@@ -3043,6 +3276,11 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,\n \tif (ret)\n \t\treturn ret;\n \n+\tif (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {\n+\t\tdata = data >> 10;\n+\t\treturn data & 0x3;\n+\t}\n+\n \tdata >>= bit;\n \tdata &= (1 << rmask_bits) - 1;\n \n@@ -3071,7 +3309,8 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,\n \t\trmask_bits = RK3588_DRV_BITS_PER_PIN;\n \t\tret = strength;\n \t\tgoto config;\n-\t} else if (ctrl->type == RK3506 ||\n+\t} else if (ctrl->type == RV1103B ||\n+\t\t ctrl->type == RK3506 ||\n \t\t ctrl->type == RK3528 ||\n \t\t ctrl->type == RK3562 ||\n \t\t ctrl->type == RK3568) {\n@@ -3182,6 +3421,12 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,\n \t\t\tret = strength;\n \t\t}\n \t}\n+\n+\tif (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {\n+\t\trmask_bits = 2;\n+\t\tret = strength;\n+\t}\n+\n \t/* enable the write to the equivalent lower bits */\n \tdata = ((1 << rmask_bits) - 1) << (bit + 16);\n \trmask = data | (data >> 16);\n@@ -3236,6 +3481,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)\n \t\t\t\t? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT\n \t\t\t\t: PIN_CONFIG_BIAS_DISABLE;\n \tcase PX30:\n+\tcase RV1103B:\n \tcase RV1108:\n \tcase RK3188:\n \tcase RK3288:\n@@ -3251,6 +3497,9 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)\n \t\tpull_type = bank->pull_type[pin_num / 8];\n \t\tdata >>= bit;\n \t\tdata &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;\n+\n+\t\tif (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12)\n+\t\t\tpull_type = 1;\n \t\t/*\n \t\t * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,\n \t\t * where that pull up value becomes 3.\n@@ -3297,6 +3546,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,\n \t\tret = regmap_write(regmap, reg, data);\n \t\tbreak;\n \tcase PX30:\n+\tcase RV1103B:\n \tcase RV1108:\n \tcase RV1126:\n \tcase RK3188:\n@@ -3312,6 +3562,8 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,\n \tcase RK3576:\n \tcase RK3588:\n \t\tpull_type = bank->pull_type[pin_num / 8];\n+\t\tif (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12)\n+\t\t\tpull_type = 1;\n \t\tret = -EINVAL;\n \t\tfor (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);\n \t\t\ti++) {\n@@ -3417,6 +3669,11 @@ static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)\n \tif (ret)\n \t\treturn ret;\n \n+\tif (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {\n+\t\tdata >>= 8;\n+\t\treturn data & 0x3;\n+\t}\n+\n \tdata >>= bit;\n \tswitch (ctrl->type) {\n \tcase RK3562:\n@@ -3473,6 +3730,12 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,\n \t\t}\n \t}\n \n+\tif (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {\n+\t\tdata = 0x3 << (bit + 16);\n+\t\trmask = data | (data >> 16);\n+\t\tdata |= ((enable ? 0x3 : 0) << bit);\n+\t}\n+\n \treturn regmap_update_bits(regmap, reg, rmask, data);\n }\n \n@@ -3579,6 +3842,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,\n \tcase RK3066B:\n \t\treturn pull ? false : true;\n \tcase PX30:\n+\tcase RV1103B:\n \tcase RV1108:\n \tcase RV1126:\n \tcase RK3188:\n@@ -4319,6 +4583,51 @@ static struct rockchip_pin_ctrl px30_pin_ctrl = {\n \t\t.schmitt_calc_reg\t= px30_calc_schmitt_reg_and_bit,\n };\n \n+static struct rockchip_pin_bank rv1103b_pin_banks[] = {\n+\tPIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(0, 32, \"gpio0\",\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t 0x40000, 0x50008, 0x50010, 0x50018,\n+\t\t\t\t DRV_TYPE_IO_LEVEL_8_BIT,\n+\t\t\t\t DRV_TYPE_IO_LEVEL_8_BIT,\n+\t\t\t\t DRV_TYPE_IO_LEVEL_8_BIT,\n+\t\t\t\t DRV_TYPE_IO_LEVEL_8_BIT),\n+\tPIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, \"gpio1\",\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t 0x20, 0x10028, 0x10030, 0x10038,\n+\t\t\t\t DRV_TYPE_IO_LEVEL_8_BIT,\n+\t\t\t\t DRV_TYPE_IO_LEVEL_8_BIT,\n+\t\t\t\t DRV_TYPE_IO_LEVEL_8_BIT,\n+\t\t\t\t DRV_TYPE_IO_LEVEL_8_BIT),\n+\tPIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, \"gpio2\",\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t 0x30040, 0x30048, 0x30050, 0x30058,\n+\t\t\t\t DRV_TYPE_IO_LEVEL_8_BIT,\n+\t\t\t\t DRV_TYPE_IO_LEVEL_8_BIT,\n+\t\t\t\t DRV_TYPE_IO_LEVEL_8_BIT,\n+\t\t\t\t DRV_TYPE_IO_LEVEL_8_BIT),\n+};\n+\n+static struct rockchip_pin_ctrl rv1103b_pin_ctrl __maybe_unused = {\n+\t.pin_banks\t\t= rv1103b_pin_banks,\n+\t.nr_banks\t\t= ARRAY_SIZE(rv1103b_pin_banks),\n+\t.label\t\t\t= \"RV1103B-GPIO\",\n+\t.type\t\t\t= RV1103B,\n+\t.iomux_recalced\t\t= rv1103b_mux_recalced_data,\n+\t.niomux_recalced\t= ARRAY_SIZE(rv1103b_mux_recalced_data),\n+\t.pull_calc_reg\t\t= rv1103b_calc_pull_reg_and_bit,\n+\t.drv_calc_reg\t\t= rv1103b_calc_drv_reg_and_bit,\n+\t.schmitt_calc_reg\t= rv1103b_calc_schmitt_reg_and_bit,\n+};\n+\n static struct rockchip_pin_bank rv1108_pin_banks[] = {\n \tPIN_BANK_IOMUX_FLAGS(0, 32, \"gpio0\", IOMUX_SOURCE_PMU,\n \t\t\t\t\t IOMUX_SOURCE_PMU,\n@@ -4955,6 +5264,8 @@ static struct rockchip_pin_ctrl rk3588_pin_ctrl = {\n static const struct of_device_id rockchip_pinctrl_dt_match[] = {\n \t{ .compatible = \"rockchip,px30-pinctrl\",\n \t\t.data = &px30_pin_ctrl },\n+\t{ .compatible = \"rockchip,rv1103b-pinctrl\",\n+\t\t.data = &rv1103b_pin_ctrl },\n \t{ .compatible = \"rockchip,rv1108-pinctrl\",\n \t\t.data = &rv1108_pin_ctrl },\n \t{ .compatible = \"rockchip,rv1126-pinctrl\",\ndiff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h\nindex 4f4aff42a80a..bb0e803e3b8a 100644\n--- a/drivers/pinctrl/pinctrl-rockchip.h\n+++ b/drivers/pinctrl/pinctrl-rockchip.h\n@@ -185,6 +185,7 @@\n \n enum rockchip_pinctrl_type {\n \tPX30,\n+\tRV1103B,\n \tRV1108,\n \tRV1126,\n \tRK2928,\n", "prefixes": [ "v2", "2/2" ] }