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GET /api/patches/2194199/?format=api
{ "id": 2194199, "url": "http://patchwork.ozlabs.org/api/patches/2194199/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/patch/20260207102602.2917520-6-anup.patel@oss.qualcomm.com/", "project": { "id": 67, "url": "http://patchwork.ozlabs.org/api/projects/67/?format=api", "name": "OpenSBI development", "link_name": "opensbi", "list_id": "opensbi.lists.infradead.org", "list_email": "opensbi@lists.infradead.org", "web_url": "https://github.com/riscv/opensbi", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "https://github.com/riscv/opensbi/commit/{}" }, "msgid": "<20260207102602.2917520-6-anup.patel@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-02-07T10:25:59", "name": "[5/8] lib: sbi_irqchip: Support irqchip device targetting subset of harts", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9d20d9dcc85ddc7c1eea912128b3e445514bffe9", "submitter": { "id": 92322, "url": "http://patchwork.ozlabs.org/api/people/92322/?format=api", "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/opensbi/patch/20260207102602.2917520-6-anup.patel@oss.qualcomm.com/mbox/", "series": [ { "id": 491373, "url": "http://patchwork.ozlabs.org/api/series/491373/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/list/?series=491373", "date": "2026-02-07T10:26:02", "name": "Extend irqchip framework for M-mode interrupts", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491373/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194199/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194199/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=TTod1TRv;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=DT0rrTWo;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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s=qcppdkim1; bh=a1qCr7UtBjH\n\tH5UxewCkdtSHRdajuKNogDcss+nPGQLc=; b=DT0rrTWonSDS7TrMpU8MvEDTVB5\n\t715N+qA0jTbxCZ1uaYtUJs9HSjK8+njd49qtpOvaOWJXd2z/HrWJqBdtr+CLD7hI\n\tGL/JeZAjDzwIH11bmZN34+MbPkTHljfWylwmR9fkuEA7K2w+ilubzfZ10xnCveh4\n\ta+GLBnyp5xUtpKg3IiYX/AiIuOv0ptFjkCuEvK6A5+19y9DuPR//kOYnFCrZl1nC\n\td+79Mm4X+Jkm3idaBymY9Nc1zp9UT6gb/xt4cgrOB4ZGd7zyQieKBPDz051iWrVa\n\tehxbqKDImcRmwogIR6ZRypQuPr0H2CSKRGUaECi8J4UQUBqQsRNyK8UFgdw==" ], "From": "Anup Patel <anup.patel@oss.qualcomm.com>", "To": "Atish Patra <atish.patra@linux.dev>", "Cc": "Andrew Jones <andrew.jones@oss.qualcomm.com>,\n Raymond Mao <raymond.mao@riscstar.com>,\n Dave Patel <dave.patel@riscstar.com>,\n Samuel Holland <samuel.holland@sifive.com>,\n Anup Patel <anup@brainfault.org>, opensbi@lists.infradead.org,\n Anup Patel <anup.patel@oss.qualcomm.com>", "Subject": "[PATCH 5/8] lib: sbi_irqchip: Support irqchip device targetting\n subset of harts", "Date": "Sat, 7 Feb 2026 15:55:59 +0530", "Message-ID": "<20260207102602.2917520-6-anup.patel@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260207102602.2917520-1-anup.patel@oss.qualcomm.com>", "References": "<20260207102602.2917520-1-anup.patel@oss.qualcomm.com>", "MIME-Version": "1.0", "X-QCInternal": [ "smtphost", "smtphost" ], "X-Proofpoint-Virus-Version": [ "vendor=nai engine=6200 definitions=5800\n signatures=585085", "vendor=nai engine=6200 definitions=5800\n signatures=585085", "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-06_05,2026-02-05_03,2025-10-01_01" ], "X-Authority-Analysis": "v=2.4 cv=Ddcaa/tW c=1 sm=1 tr=0 ts=69871340 cx=c_pps\n a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22\n a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=7a4fK-ezoZRecfey04UA:9", "X-Proofpoint-ORIG-GUID": "c6aB1bJk-0WsKXiBJET-Nrq9fM3HnBYA", "X-Proofpoint-GUID": "c6aB1bJk-0WsKXiBJET-Nrq9fM3HnBYA", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMjA3MDA4MiBTYWx0ZWRfX+DaW2Y2M+cfV\n bMOYN/6AsRQgBzbLZhVyUw065lo3eSTOoEVP5kmaZQqXPqw5Lm23OizCydP3TtIL/ZljxFIQ6M+\n tMRQFY25ROp6olm13mJYa/+D1Wzb7B14QRSuJq/vyrGj1E8fbpQz5MbLybFosZ/NmJWRYb2VTLu\n fV3qbY1KI5O9ZX9ttajPGEVLOpOisOHXhbFLtszbW+xspEMqJ+JO/y8sxFS5RVFPSONqb0rxIqO\n ezoV30Kz/WLrLmmZH0IGl7mEbgyQgA7jUpdJNeEcrkVvRKhX6rhDYDGiOLFkoOeX9NJjp89R6dE\n nuiDvPOo0yfxn0nM7jqe1kg6f3uD0nSkcm4V2jy9TnByvLfcdQsmbtyXQ5FRDFZyynT0QK8kVn/\n cBCBALuRU4ynLfncZOitUbGmJNLP5T9sKma42L6o8csdgMRuhkVh9y6UsJ57cXkHfK5NoRKnhRe\n EwpNPbwsrpAcJ1yMotw==", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n bulkscore=0 spamscore=0 clxscore=1011 suspectscore=0 impostorscore=0\n malwarescore=0 lowpriorityscore=0 adultscore=0 phishscore=0\n priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000\n definitions=main-2602070082", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20260207_022614_997122_44B80E10 ", "X-CRM114-Status": "GOOD ( 20.46 )", "X-Spam-Score": "-2.7 (--)", "X-Spam-Report": "Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam. The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: It is possible to have platform where an irqchip device\n targets\n a subset of harts and there are multiple irqchip devices to cover all\n harts.\n To support this scenario: 1) Add target_harts hartmask to struct\n sbi_irqchip_device\n which represents the set of harts targetted by the irqchip device 2) Call\n warm_init() and irq_handle() callbacks of [...]\n Content analysis details: (-2.7 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low\n trust\n [205.220.168.131 listed in list.dnswl.org]\n 0.0 RCVD_IN_VALIDITY_CERTIFIED_BLOCKED RBL: ADMINISTRATOR NOTICE: The\n query to Validity was blocked. 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See\n https://knowledge.validity.com/hc/en-us/articles/20961730681243\n for more information.\n [205.220.168.131 listed in\n bl.score.senderscore.com]", "X-BeenThere": "opensbi@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "<opensbi.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/opensbi/>", "List-Post": "<mailto:opensbi@lists.infradead.org>", "List-Help": "<mailto:opensbi-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"opensbi\" <opensbi-bounces@lists.infradead.org>", "Errors-To": "opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "It is possible to have platform where an irqchip device targets\na subset of harts and there are multiple irqchip devices to cover\nall harts.\n\nTo support this scenario:\n1) Add target_harts hartmask to struct sbi_irqchip_device which\n represents the set of harts targetted by the irqchip device\n2) Call warm_init() and irq_handle() callbacks of an irqchip device\n on a hart only if irqchip device targets that particular hart\n\nSigned-off-by: Anup Patel <anup.patel@oss.qualcomm.com>\n---\n include/sbi/sbi_irqchip.h | 8 +++++--\n lib/sbi/sbi_irqchip.c | 48 ++++++++++++++++++++++++++++-----------\n lib/utils/irqchip/aplic.c | 12 +++++++++-\n lib/utils/irqchip/imsic.c | 7 ++++--\n lib/utils/irqchip/plic.c | 5 ++--\n 5 files changed, 59 insertions(+), 21 deletions(-)", "diff": "diff --git a/include/sbi/sbi_irqchip.h b/include/sbi/sbi_irqchip.h\nindex cda1e50f..c3ded271 100644\n--- a/include/sbi/sbi_irqchip.h\n+++ b/include/sbi/sbi_irqchip.h\n@@ -10,6 +10,7 @@\n #ifndef __SBI_IRQCHIP_H__\n #define __SBI_IRQCHIP_H__\n \n+#include <sbi/sbi_hartmask.h>\n #include <sbi/sbi_list.h>\n #include <sbi/sbi_types.h>\n \n@@ -20,11 +21,14 @@ struct sbi_irqchip_device {\n \t/** Node in the list of irqchip devices */\n \tstruct sbi_dlist node;\n \n+\t/** Set of harts targetted by this irqchip */\n+\tstruct sbi_hartmask target_harts;\n+\n \t/** Initialize per-hart state for the current hart */\n \tint (*warm_init)(struct sbi_irqchip_device *chip);\n \n \t/** Process hardware interrupts from this irqchip */\n-\tint (*process_hwirqs)(void);\n+\tint (*process_hwirqs)(struct sbi_irqchip_device *chip);\n };\n \n /**\n@@ -38,7 +42,7 @@ struct sbi_irqchip_device {\n int sbi_irqchip_process(void);\n \n /** Register an irqchip device to receive callbacks */\n-void sbi_irqchip_add_device(struct sbi_irqchip_device *chip);\n+int sbi_irqchip_add_device(struct sbi_irqchip_device *chip);\n \n /** Initialize interrupt controllers */\n int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot);\ndiff --git a/lib/sbi/sbi_irqchip.c b/lib/sbi/sbi_irqchip.c\nindex 3b970527..77ec05af 100644\n--- a/lib/sbi/sbi_irqchip.c\n+++ b/lib/sbi/sbi_irqchip.c\n@@ -13,24 +13,44 @@\n \n static SBI_LIST_HEAD(irqchip_list);\n \n-static int default_irqfn(void)\n+int sbi_irqchip_process(void)\n {\n-\treturn SBI_ENODEV;\n-}\n+\tstruct sbi_irqchip_device *chip;\n+\tint rc = SBI_ENODEV;\n \n-static int (*ext_irqfn)(void) = default_irqfn;\n+\tsbi_list_for_each_entry(chip, &irqchip_list, node) {\n+\t\tif (!chip->process_hwirqs)\n+\t\t\tcontinue;\n+\t\tif (!sbi_hartmask_test_hartindex(current_hartindex(), &chip->target_harts))\n+\t\t\tcontinue;\n+\t\trc = chip->process_hwirqs(chip);\n+\t\tif (rc)\n+\t\t\tbreak;\n+\t}\n \n-int sbi_irqchip_process(void)\n-{\n-\treturn ext_irqfn();\n+\treturn rc;\n }\n \n-void sbi_irqchip_add_device(struct sbi_irqchip_device *chip)\n+int sbi_irqchip_add_device(struct sbi_irqchip_device *chip)\n {\n-\tsbi_list_add_tail(&chip->node, &irqchip_list);\n+\tstruct sbi_irqchip_device *c;\n+\tstruct sbi_hartmask hm;\n+\n+\tif (!chip || !sbi_hartmask_weight(&chip->target_harts))\n+\t\treturn SBI_EINVAL;\n+\n+\tif (chip->process_hwirqs) {\n+\t\tsbi_list_for_each_entry(c, &irqchip_list, node) {\n+\t\t\tif (!c->process_hwirqs)\n+\t\t\t\tcontinue;\n+\t\t\tsbi_hartmask_and(&hm, &c->target_harts, &chip->target_harts);\n+\t\t\tif (sbi_hartmask_weight(&hm))\n+\t\t\t\treturn SBI_EINVAL;\n+\t\t}\n+\t}\n \n-\tif (chip->process_hwirqs)\n-\t\text_irqfn = chip->process_hwirqs;\n+\tsbi_list_add_tail(&chip->node, &irqchip_list);\n+\treturn 0;\n }\n \n int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot)\n@@ -48,12 +68,14 @@ int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot)\n \tsbi_list_for_each_entry(chip, &irqchip_list, node) {\n \t\tif (!chip->warm_init)\n \t\t\tcontinue;\n+\t\tif (!sbi_hartmask_test_hartindex(current_hartindex(), &chip->target_harts))\n+\t\t\tcontinue;\n \t\trc = chip->warm_init(chip);\n \t\tif (rc)\n \t\t\treturn rc;\n \t}\n \n-\tif (ext_irqfn != default_irqfn)\n+\tif (!sbi_list_empty(&irqchip_list))\n \t\tcsr_set(CSR_MIE, MIP_MEIP);\n \n \treturn 0;\n@@ -61,6 +83,6 @@ int sbi_irqchip_init(struct sbi_scratch *scratch, bool cold_boot)\n \n void sbi_irqchip_exit(struct sbi_scratch *scratch)\n {\n-\tif (ext_irqfn != default_irqfn)\n+\tif (!sbi_list_empty(&irqchip_list))\n \t\tcsr_clear(CSR_MIE, MIP_MEIP);\n }\ndiff --git a/lib/utils/irqchip/aplic.c b/lib/utils/irqchip/aplic.c\nindex 8d0db168..ea5cb7c4 100644\n--- a/lib/utils/irqchip/aplic.c\n+++ b/lib/utils/irqchip/aplic.c\n@@ -297,8 +297,18 @@ int aplic_cold_irqchip_init(struct aplic_data *aplic)\n \t\t\treturn rc;\n \t}\n \n+\tif (aplic->num_idc) {\n+\t\tfor (i = 0; i < aplic->num_idc; i++)\n+\t\t\tsbi_hartmask_set_hartindex(aplic->idc_map[i],\n+\t\t\t\t\t\t &aplic->irqchip.target_harts);\n+\t} else {\n+\t\tsbi_hartmask_set_all(&aplic->irqchip.target_harts);\n+\t}\n+\n \t/* Register irqchip device */\n-\tsbi_irqchip_add_device(&aplic->irqchip);\n+\trc = sbi_irqchip_add_device(&aplic->irqchip);\n+\tif (rc)\n+\t\treturn rc;\n \n \t/* Attach to the aplic list */\n \tsbi_list_add_tail(&aplic->node, &aplic_list);\ndiff --git a/lib/utils/irqchip/imsic.c b/lib/utils/irqchip/imsic.c\nindex 0e9917da..5ec9dff4 100644\n--- a/lib/utils/irqchip/imsic.c\n+++ b/lib/utils/irqchip/imsic.c\n@@ -147,7 +147,7 @@ int imsic_get_target_file(u32 hartindex)\n \treturn imsic_get_hart_file(scratch);\n }\n \n-static int imsic_process_hwirqs(void)\n+static int imsic_process_hwirqs(struct sbi_irqchip_device *chip)\n {\n \tulong mirq;\n \n@@ -391,7 +391,10 @@ int imsic_cold_irqchip_init(struct imsic_data *imsic)\n \t}\n \n \t/* Register irqchip device */\n-\tsbi_irqchip_add_device(&imsic_device);\n+\tsbi_hartmask_set_all(&imsic_device.target_harts);\n+\trc = sbi_irqchip_add_device(&imsic_device);\n+\tif (rc)\n+\t\treturn rc;\n \n \t/* Register IPI device */\n \tsbi_ipi_add_device(&imsic_ipi_device);\ndiff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c\nindex 7989a962..25cc2787 100644\n--- a/lib/utils/irqchip/plic.c\n+++ b/lib/utils/irqchip/plic.c\n@@ -276,11 +276,10 @@ int plic_cold_irqchip_init(struct plic_data *plic)\n \t\t\tcontinue;\n \n \t\tplic_set_hart_data_ptr(sbi_hartindex_to_scratch(i), plic);\n+\t\tsbi_hartmask_set_hartindex(i, &plic->irqchip.target_harts);\n \t}\n \n \t/* Register irqchip device */\n \tplic->irqchip.warm_init = plic_warm_irqchip_init;\n-\tsbi_irqchip_add_device(&plic->irqchip);\n-\n-\treturn 0;\n+\treturn sbi_irqchip_add_device(&plic->irqchip);\n }\n", "prefixes": [ "5/8" ] }