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{
    "id": 2194193,
    "url": "http://patchwork.ozlabs.org/api/patches/2194193/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/tencent_326708D02875274DF25B10B91402B3828606@qq.com/",
    "project": {
        "id": 42,
        "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api",
        "name": "Linux GPIO development",
        "link_name": "linux-gpio",
        "list_id": "linux-gpio.vger.kernel.org",
        "list_email": "linux-gpio@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<tencent_326708D02875274DF25B10B91402B3828606@qq.com>",
    "list_archive_url": null,
    "date": "2026-02-07T09:42:35",
    "name": "tof: Add VL53L4CX TOF drivers",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "0c7c1765573e302e510c3b44e5305a917067b052",
    "submitter": {
        "id": 92594,
        "url": "http://patchwork.ozlabs.org/api/people/92594/?format=api",
        "name": null,
        "email": "434779359@qq.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/tencent_326708D02875274DF25B10B91402B3828606@qq.com/mbox/",
    "series": [
        {
            "id": 491368,
            "url": "http://patchwork.ozlabs.org/api/series/491368/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=491368",
            "date": "2026-02-07T09:42:35",
            "name": "tof: Add VL53L4CX TOF drivers",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/491368/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2194193/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2194193/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "X-QQ-XMRINFO": "Nq+8W0+stu50tPAe92KXseR0ZZmBTk3gLg==",
        "From": "434779359@qq.com",
        "To": "Jonathan Cameron <jic23@kernel.org>",
        "Cc": "David Lechner <dlechner@baylibre.com>,\n =?utf-8?q?Nuno_S=C3=A1?= <nuno.sa@analog.com>,\n Andy Shevchenko <andy@kernel.org>, Liam Girdwood <lgirdwood@gmail.com>,\n Mark Brown <broonie@kernel.org>, Linus Walleij <linusw@kernel.org>,\n Bartosz Golaszewski <brgl@kernel.org>, liufulin <frank.liu@faiot.com>,\n Waqar Hameed <waqar.hameed@axis.com>, linux-kernel@vger.kernel.org,\n linux-iio@vger.kernel.org, linux-gpio@vger.kernel.org",
        "Subject": "[PATCH] tof: Add VL53L4CX TOF drivers",
        "Date": "Sat,  7 Feb 2026 17:42:35 +0800",
        "X-OQ-MSGID": "<20260207094235.1780679-1-434779359@qq.com>",
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        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit"
    },
    "content": "From: liufulin <frank.liu@faiot.com>\n\nThis patch adds support for the vl53l4cx tof ic\nICs used in Qualcomm reference designs\n\nSigned-off-by: liufulin <frank.liu@faiot.com>\n---\n drivers/iio/proximity/Kconfig        |    10 +\n drivers/iio/proximity/Makefile       |     1 +\n drivers/iio/proximity/vl53l4cx-i2c.c | 18161 +++++++++++++++++++++++++\n 3 files changed, 18172 insertions(+)\n create mode 100644 drivers/iio/proximity/vl53l4cx-i2c.c",
    "diff": "diff --git a/drivers/iio/proximity/Kconfig b/drivers/iio/proximity/Kconfig\nindex 6070974c2c85..a2fcb39e444e 100644\n--- a/drivers/iio/proximity/Kconfig\n+++ b/drivers/iio/proximity/Kconfig\n@@ -255,4 +255,14 @@ config AW96103\n \t  To compile this driver as a module, choose M here: the\n \t  module will be called aw96103.\n \n+config VL53L4CX_I2C\n+\ttristate \"STMicroelectronics VL53L0X ToF ranger sensor (I2C)\"\n+\tdepends on I2C\n+\thelp\n+\t  Say Y here to build a driver for STMicroelectronics VL53L0X\n+\t  ToF ranger sensors with i2c interface.\n+\t  This driver can be used to measure the distance of objects.\n+\t  To compile this driver as a module, choose M here: the\n+\t  module will be called vl53l0x-i2c.\n+\n endmenu\ndiff --git a/drivers/iio/proximity/Makefile b/drivers/iio/proximity/Makefile\nindex 152034d38c49..8a682bbed50b 100644\n--- a/drivers/iio/proximity/Makefile\n+++ b/drivers/iio/proximity/Makefile\n@@ -24,4 +24,5 @@ obj-$(CONFIG_SX9500)\t\t+= sx9500.o\n obj-$(CONFIG_VCNL3020)\t\t+= vcnl3020.o\n obj-$(CONFIG_VL53L0X_I2C)\t+= vl53l0x-i2c.o\n obj-$(CONFIG_AW96103)\t\t+= aw96103.o\n+obj-$(CONFIG_VL53L4CX_I2C)\t+= vl53l4cx-i2c.o\n \ndiff --git a/drivers/iio/proximity/vl53l4cx-i2c.c b/drivers/iio/proximity/vl53l4cx-i2c.c\nnew file mode 100644\nindex 000000000000..df9ae9786966\n--- /dev/null\n+++ b/drivers/iio/proximity/vl53l4cx-i2c.c\n@@ -0,0 +1,18161 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Support for ST VL53L0X FlightSense ToF Ranging Sensor on a i2c bus.\n+ *\n+ * Copyright (C) 2016 STMicroelectronics Imaging Division.\n+ * Copyright (C) 2018 Song Qiang <songqiang1304521@gmail.com>\n+ * Copyright (C) 2020 Ivan Drobyshevskyi <drobyshevskyi@gmail.com>\n+ *\n+ * Datasheet available at\n+ * <https://www.st.com/resource/en/datasheet/vl53l0x.pdf>\n+ *\n+ * Default 7-bit i2c slave address 0x29.\n+ *\n+ * TODO: FIFO buffer, continuous mode, range selection, sensor ID check.\n+ */\n+\n+#include <linux/delay.h>\n+#include <linux/gpio/consumer.h>\n+#include <linux/i2c.h>\n+#include <linux/irq.h>\n+#include <linux/interrupt.h>\n+#include <linux/module.h>\n+\n+#include <linux/iio/iio.h>\n+#include <linux/miscdevice.h>\n+#include <linux/of_gpio.h>\n+#include <linux/input.h>\n+\n+#define STMVL53LX_DRV_NAME\t\"stmvl53lx\"\n+#define STMVL53LX_SLAVE_ADDR\t(0x52>>1)\n+\n+#define VL_REG_SYSRANGE_START\t\t\t\t0x00\n+\n+#define MODI2C_DEBUG\t0\n+\n+#if 0\n+#define DEBUG\t1\n+#endif\n+#if 0\n+#define FORCE_CONSOLE_DEBUG\n+#endif\n+\n+extern int stmvl53lx_enable_debug;\n+\n+#ifdef DEBUG\n+#\tifdef FORCE_CONSOLE_DEBUG\n+#define vl53lx_dbgmsg(str, ...) do { \\\n+\tif (stmvl53lx_enable_debug) \\\n+\t\tpr_info(\"%s: \" str, __func__, ##__VA_ARGS__); \\\n+} while (0)\n+#\telse\n+#define vl53lx_dbgmsg(str, ...) do { \\\n+\tif (stmvl53lx_enable_debug) \\\n+\t\tpr_debug(\"%s: \" str, __func__, ##__VA_ARGS__); \\\n+} while (0)\n+#\tendif\n+#else\n+#\tdefine vl53lx_dbgmsg(...) ((void)0)\n+#endif\n+\n+#define WORK_DEBUG\t0\n+#if WORK_DEBUG\n+#\tdefine work_dbg(msg, ...)\\\n+\tprintk(\"[D WK53L1] :\" msg \"\\n\", ##__VA_ARGS__)\n+#else\n+#\tdefine work_dbg(...) ((void)0)\n+#endif\n+\n+#define vl53lx_info(str, args...) \\\n+\tpr_info(\"%s: \" str \"\\n\", __func__, ##args)\n+\n+#define vl53lx_errmsg(str, args...) \\\n+\tpr_err(\"%s: \" str, __func__, ##args)\n+\n+#define vl53lx_wanrmsg(str, args...) \\\n+\tpr_warn(\"%s: \" str, __func__, ##args)\n+\n+#ifndef STMVL53LX_LOG_POLL_TIMING\n+#\tdefine STMVL53LX_LOG_POLL_TIMING\t0\n+#endif\n+#ifndef STMVL53LX_LOG_CCI_TIMING\n+#\tdefine STMVL53LX_LOG_CCI_TIMING\t0\n+#endif\n+\n+#define modi2c_warn(fmt, ...)\\\n+\tdev_WARN(&i2c_data->client->dev, fmt, ##__VA_ARGS__)\n+\n+#define modi2c_err(fmt, ...)\\\n+\tdev_err(&i2c_data->client->dev, fmt, ##__VA_ARGS__)\n+\n+#if MODI2C_DEBUG\n+#define modi2c_dbg(fmt, ...)\\\n+\t\tpr_devel(\"%s \"fmt\"\\n\", __func__, ##__VA_ARGS__)\n+#else\n+#define modi2c_dbg(...)\t((void)0)\n+#endif\n+\n+#define VL_REG_SYSRANGE_MODE_MASK\t\t\tGENMASK(3, 0)\n+#define VL_REG_SYSRANGE_MODE_SINGLESHOT\t\t\t0x00\n+#define VL_REG_SYSRANGE_MODE_START_STOP\t\t\tBIT(0)\n+#define VL_REG_SYSRANGE_MODE_BACKTOBACK\t\t\tBIT(1)\n+#define VL_REG_SYSRANGE_MODE_TIMED\t\t\tBIT(2)\n+#define VL_REG_SYSRANGE_MODE_HISTOGRAM\t\t\tBIT(3)\n+\n+#define VL_REG_SYSTEM_INTERRUPT_CONFIG_GPIO\t\t0x0A\n+#define VL_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY\tBIT(2)\n+\n+#define VL_REG_SYSTEM_INTERRUPT_CLEAR\t\t\t0x0B\n+\n+#define VL_REG_RESULT_INT_STATUS\t\t\t0x13\n+#define VL_REG_RESULT_RANGE_STATUS\t\t\t0x14\n+#define VL_REG_RESULT_RANGE_STATUS_COMPLETE\t\tBIT(0)\n+\n+#define VL53LX_FIRMWARE_BOOT_TIME_US            1200\n+#define VL53LX_I2C_SLAVE__DEVICE_ADDRESS        0x0001\n+\n+#define VL53LX_NVM_PEAK_RATE_MAP_SAMPLES  25\n+\n+#define VL53LX_MAX_USER_ZONES                5\n+\n+#define VL53LX_MAX_RANGE_RESULTS 4\n+\n+#define VL53LX_MAX_STRING_LENGTH 512\n+\n+#define VL53LX_RTN_SPAD_BUFFER_SIZE                   32\n+\n+#define  VL53LX_MAX_BIN_SEQUENCE_LENGTH  6\n+\n+#define  VL53LX_XTALK_HISTO_BINS        12\n+\n+#define VL53LX_MAX_XTALK_RANGE_RESULTS        5\n+\n+#define VL53LX_BIN_REC_SIZE 6\n+\n+#define VL53LX_MAX_OFFSET_RANGE_RESULTS       3\n+\n+#define VL53LX_TIMING_CONF_A_B_SIZE 2\n+\n+#define  VL53LX_HISTOGRAM_BUFFER_SIZE   24\n+\n+#define VL53LX_FRAME_WAIT_EVENT\t6\n+\n+#define VL53LX_RANGE_STATUS__RANGE_STATUS_MASK          0x1F\n+#define VL53LX_RANGE_STATUS__MAX_THRESHOLD_HIT_MASK     0x20\n+#define VL53LX_RANGE_STATUS__MIN_THRESHOLD_HIT_MASK     0x40\n+#define VL53LX_RANGE_STATUS__GPH_ID_RANGE_STATUS_MASK   0x80\n+\n+#define VL53LX_INTERRUPT_STATUS__INT_STATUS_MASK            0x07\n+#define VL53LX_INTERRUPT_STATUS__INT_ERROR_STATUS_MASK      0x18\n+#define VL53LX_INTERRUPT_STATUS__GPH_ID_INT_STATUS_MASK     0x20\n+\n+#define  VL53LX_MAX_BIN_SEQUENCE_LENGTH  6\n+#define  VL53LX_MAX_BIN_SEQUENCE_CODE   15\n+#define  VL53LX_HISTOGRAM_BUFFER_SIZE   24\n+#define  VL53LX_XTALK_HISTO_BINS        12\n+\n+#define VL53LX_BOOT_COMPLETION_POLLING_TIMEOUT_MS     500\n+\n+#define VL53LX_BOOT_COMPLETION_POLLING_TIMEOUT_MS     500\n+#define VL53LX_RANGE_COMPLETION_POLLING_TIMEOUT_MS   2000\n+#define VL53LX_TEST_COMPLETION_POLLING_TIMEOUT_MS   60000\n+\n+#define VL53LX_POLLING_DELAY_MS                         1\n+\n+#define VL53LX_FIRMWARE__SYSTEM_STATUS 0x00E5\n+\n+#define VL53LX_GROUPEDPARAMETERHOLD_ID_MASK             0x02\n+\n+#define VL53LX_SYSTEM_CONTROL_I2C_SIZE_BYTES                5\n+\n+#define STMVL53LX_MAX_CCI_XFER_SZ\t256\n+\n+#define FDA_MAX_TIMING_BUDGET_US 550000\n+#define L4_FDA_MAX_TIMING_BUDGET_US 200000\n+\n+#define WRITE_MULTIPLE_CHUNK_MAX\t32\n+\n+#define VL53LX_POWER_MANAGEMENT__GO1_POWER_FORCE 0x0083\n+\n+#define VL53LX_DEVICEMEASUREMENTMODE_MODE_MASK          0xF0\n+#define VL53LX_DEVICEMEASUREMENTMODE_STOP_MASK          0x0F\n+\n+#define VL53LX_MAX_AMBIENT_DMAX_VALUES        5\n+\n+#define VL53LX_PATCH__CTRL 0x0470\n+\n+#define VL53LX_FIRMWARE__ENABLE 0x0085\n+\n+#define VL53LX_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES         23\n+\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_0 0x000D\n+\n+#define IGNORE_DIVISION_BY_ZERO                                0\n+\n+#define IGNORE_XTALK_EXTRACTION_NO_SAMPLE_FAIL                 0\n+#define IGNORE_XTALK_EXTRACTION_SIGMA_LIMIT_FAIL               0\n+#define IGNORE_XTALK_EXTRACTION_NO_SAMPLE_FOR_GRADIENT_WARN    0\n+#define IGNORE_XTALK_EXTRACTION_SIGMA_LIMIT_FOR_GRADIENT_WARN  0\n+#define IGNORE_XTALK_EXTRACTION_MISSING_SAMPLES_WARN           0\n+\n+#define IGNORE_REF_SPAD_CHAR_NOT_ENOUGH_SPADS                  0\n+#define IGNORE_REF_SPAD_CHAR_RATE_TOO_HIGH                     0\n+#define IGNORE_REF_SPAD_CHAR_RATE_TOO_LOW                      0\n+\n+#define IGNORE_OFFSET_CAL_MISSING_SAMPLES                      0\n+#define IGNORE_OFFSET_CAL_SIGMA_TOO_HIGH                       0\n+#define IGNORE_OFFSET_CAL_RATE_TOO_HIGH                        0\n+#define IGNORE_OFFSET_CAL_SPAD_COUNT_TOO_LOW\t\t\t\t   0\n+\n+#define IGNORE_ZONE_CAL_MISSING_SAMPLES                        0\n+#define IGNORE_ZONE_CAL_SIGMA_TOO_HIGH                         0\n+#define IGNORE_ZONE_CAL_RATE_TOO_HIGH                          0\n+\n+#ifndef SUPPRESS_UNUSED_WARNING\n+#define SUPPRESS_UNUSED_WARNING(x) ((void) (x))\n+#endif\n+\n+#define\t\tVL53LX_TRACE_LEVEL_NONE\t\t\t0x00000000\n+#define\t\tVL53LX_TRACE_LEVEL_ERRORS\t\t0x00000001\n+#define\t\tVL53LX_TRACE_LEVEL_WARNING\t\t0x00000002\n+#define\t\tVL53LX_TRACE_LEVEL_INFO\t\t\t0x00000004\n+#define\t\tVL53LX_TRACE_LEVEL_DEBUG\t\t0x00000008\n+#define\t\tVL53LX_TRACE_LEVEL_ALL\t\t\t0x00000010\n+#define\t\tVL53LX_TRACE_LEVEL_IGNORE\t\t0x00000020\n+#define\t\tVL53LX_TRACE_FUNCTION_NONE\t\t0x00000000\n+#define\t\tVL53LX_TRACE_FUNCTION_I2C\t\t0x00000001\n+#define\t\tVL53LX_TRACE_FUNCTION_ALL\t\t0x7fffffff\n+#define\t\tVL53LX_TRACE_MODULE_NONE\t\t0x00000000\n+#define\t\tVL53LX_TRACE_MODULE_API\t\t\t0x00000001\n+#define\t\tVL53LX_TRACE_MODULE_CORE\t\t0x00000002\n+#define\t\tVL53LX_TRACE_MODULE_PROTECTED\t\t0x00000004\n+#define\t\tVL53LX_TRACE_MODULE_HISTOGRAM\t\t0x00000008\n+#define\t\tVL53LX_TRACE_MODULE_REGISTERS\t\t0x00000010\n+#define\t\tVL53LX_TRACE_MODULE_PLATFORM\t\t0x00000020\n+#define\t\tVL53LX_TRACE_MODULE_NVM\t\t\t0x00000040\n+#define\t\tVL53LX_TRACE_MODULE_CALIBRATION_DATA\t0x00000080\n+#define\t\tVL53LX_TRACE_MODULE_NVM_DATA\t\t0x00000100\n+#define\t\tVL53LX_TRACE_MODULE_HISTOGRAM_DATA\t0x00000200\n+#define\t\tVL53LX_TRACE_MODULE_RANGE_RESULTS_DATA\t0x00000400\n+#define\t\tVL53LX_TRACE_MODULE_XTALK_DATA\t\t0x00000800\n+#define\t\tVL53LX_TRACE_MODULE_OFFSET_DATA\t\t0x00001000\n+#define\t\tVL53LX_TRACE_MODULE_DATA_INIT\t\t0x00002000\n+#define\t\tVL53LX_TRACE_MODULE_REF_SPAD_CHAR\t0x00004000\n+#define\t\tVL53LX_TRACE_MODULE_SPAD_RATE_MAP\t0x00008000\n+#define\t\tVL53LX_TRACE_MODULE_CUSTOMER_API\t0x40000000\n+#define\t\tVL53LX_TRACE_MODULE_ALL\t\t\t0x7fffffff\n+\n+#define DISABLE_WARNINGS()\n+#define ENABLE_WARNINGS()\n+\n+#define IGNORE_STATUS(__FUNCTION_ID__, __ERROR_STATUS_CHECK__, __STATUS__) \\\n+\tdo { \\\n+\t\tDISABLE_WARNINGS(); \\\n+\t\tif (__FUNCTION_ID__) { \\\n+\t\t\tif (__STATUS__ == __ERROR_STATUS_CHECK__) { \\\n+\t\t\t\t__STATUS__ = VL53LX_ERROR_NONE; \\\n+\t\t\t} \\\n+\t\t} \\\n+\t\tENABLE_WARNINGS(); \\\n+\t} \\\n+\twhile (0)\n+\n+#define VL53LX_COPYSTRING(str, ...) \\\n+\t(strncpy(str, ##__VA_ARGS__, VL53LX_MAX_STRING_LENGTH-1))\n+\n+#define\t VL53LX_RANGESTATUS_NONE\t\t\t\t255\n+\n+#define VL53LX_MAX_I2C_XFER_SIZE 256\n+\n+#define STMVL53LX_CFG_MAX_DEV\t2\n+\n+#define do_division_u(dividend, divisor) div64_u64(dividend, divisor)\n+#define do_division_s(dividend, divisor) div64_s64(dividend, divisor)\n+\n+#define VL53LX_SPEED_OF_LIGHT_IN_AIR                299704\n+\n+#define VL53LX_SPEED_OF_LIGHT_IN_AIR_DIV_8          (299704 >> 3)\n+\n+#define VL53LX_STATIC_NVM_MANAGED_I2C_SIZE_BYTES           11\n+\n+#define VL53LX_STATIC_NVM_MANAGED_I2C_INDEX             \\\n+\tVL53LX_I2C_SLAVE__DEVICE_ADDRESS\n+#define VL53LX_CUSTOMER_NVM_MANAGED_I2C_INDEX           \\\n+\tVL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_0\n+#define VL53LX_STATIC_CONFIG_I2C_INDEX                  \\\n+\tVL53LX_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS\n+#define VL53LX_GENERAL_CONFIG_I2C_INDEX                  \\\n+\tVL53LX_GPH_CONFIG__STREAM_COUNT_UPDATE_VALUE\n+#define VL53LX_TIMING_CONFIG_I2C_INDEX                  \\\n+\tVL53LX_MM_CONFIG__TIMEOUT_MACROP_A_HI\n+#define VL53LX_DYNAMIC_CONFIG_I2C_INDEX                 \\\n+\tVL53LX_SYSTEM__GROUPED_PARAMETER_HOLD_0\n+#define VL53LX_SYSTEM_CONTROL_I2C_INDEX                 \\\n+\tVL53LX_POWER_MANAGEMENT__GO1_POWER_FORCE\n+#define VL53LX_SYSTEM_RESULTS_I2C_INDEX                 \\\n+\tVL53LX_RESULT__INTERRUPT_STATUS\n+#define VL53LX_CORE_RESULTS_I2C_INDEX                   \\\n+\tVL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0\n+#define VL53LX_DEBUG_RESULTS_I2C_INDEX                  \\\n+\tVL53LX_PHASECAL_RESULT__REFERENCE_PHASE\n+#define VL53LX_NVM_COPY_DATA_I2C_INDEX                 \\\n+\tVL53LX_IDENTIFICATION__MODEL_ID\n+#define VL53LX_PREV_SHADOW_SYSTEM_RESULTS_I2C_INDEX    \\\n+\tVL53LX_PREV_SHADOW_RESULT__INTERRUPT_STATUS\n+#define VL53LX_PREV_SHADOW_CORE_RESULTS_I2C_INDEX      \\\n+\tVL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0\n+#define VL53LX_PATCH_DEBUG_I2C_INDEX                   \\\n+\tVL53LX_RESULT__DEBUG_STATUS\n+#define VL53LX_GPH_GENERAL_CONFIG_I2C_INDEX            \\\n+\tVL53LX_GPH__SYSTEM__THRESH_RATE_HIGH\n+#define VL53LX_GPH_STATIC_CONFIG_I2C_INDEX             \\\n+\tVL53LX_GPH__DSS_CONFIG__ROI_MODE_CONTROL\n+#define VL53LX_GPH_TIMING_CONFIG_I2C_INDEX             \\\n+\tVL53LX_GPH__MM_CONFIG__TIMEOUT_MACROP_A_HI\n+#define VL53LX_FW_INTERNAL_I2C_INDEX                   \\\n+\tVL53LX_FIRMWARE__INTERNAL_STREAM_COUNT_DIV\n+#define VL53LX_PATCH_RESULTS_I2C_INDEX                 \\\n+\tVL53LX_DSS_CALC__ROI_CTRL\n+#define VL53LX_SHADOW_SYSTEM_RESULTS_I2C_INDEX         \\\n+\tVL53LX_SHADOW_PHASECAL_RESULT__VCSEL_START\n+#define VL53LX_SHADOW_CORE_RESULTS_I2C_INDEX           \\\n+\tVL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0\n+\n+#define CONT_CONTINUE\t0\n+#define CONT_NEXT_LOOP\t1\n+#define CONT_RESET\t2\n+\n+#define VL53LX_STATIC_NVM_MANAGED_I2C_SIZE_BYTES           11\n+#define VL53LX_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES         23\n+#define VL53LX_STATIC_CONFIG_I2C_SIZE_BYTES                32\n+#define VL53LX_GENERAL_CONFIG_I2C_SIZE_BYTES               22\n+#define VL53LX_TIMING_CONFIG_I2C_SIZE_BYTES                23\n+#define VL53LX_DYNAMIC_CONFIG_I2C_SIZE_BYTES               18\n+#define VL53LX_SYSTEM_CONTROL_I2C_SIZE_BYTES                5\n+#define VL53LX_SYSTEM_RESULTS_I2C_SIZE_BYTES               44\n+#define VL53LX_CORE_RESULTS_I2C_SIZE_BYTES                 33\n+#define VL53LX_DEBUG_RESULTS_I2C_SIZE_BYTES                56\n+#define VL53LX_NVM_COPY_DATA_I2C_SIZE_BYTES                49\n+#define VL53LX_PREV_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES   44\n+#define VL53LX_PREV_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES     33\n+#define VL53LX_PATCH_DEBUG_I2C_SIZE_BYTES                   2\n+#define VL53LX_GPH_GENERAL_CONFIG_I2C_SIZE_BYTES            5\n+#define VL53LX_GPH_STATIC_CONFIG_I2C_SIZE_BYTES             6\n+#define VL53LX_GPH_TIMING_CONFIG_I2C_SIZE_BYTES            16\n+#define VL53LX_FW_INTERNAL_I2C_SIZE_BYTES                   2\n+#define VL53LX_PATCH_RESULTS_I2C_SIZE_BYTES                90\n+#define VL53LX_SHADOW_SYSTEM_RESULTS_I2C_SIZE_BYTES        82\n+#define VL53LX_SHADOW_CORE_RESULTS_I2C_SIZE_BYTES          33\n+\n+#define VL53LX_ADDITIONAL_CALIBRATION_DATA_STRUCT_VERSION  0x20\n+\n+#define VL53LX_LL_CALIBRATION_DATA_STRUCT_VERSION       0xECAB0102\n+\n+#define VL53LX_CALIBRATION_DATA_STRUCT_VERSION \\\n+\t\t(VL53LX_LL_CALIBRATION_DATA_STRUCT_VERSION + \\\n+\t\tVL53LX_ADDITIONAL_CALIBRATION_DATA_STRUCT_VERSION)\n+\n+#define\t VL53LX_RANGESTATUS_RANGE_VALID\t\t\t\t0\n+#define\t VL53LX_RANGESTATUS_SIGMA_FAIL\t\t\t\t1\n+#define\t VL53LX_RANGESTATUS_SIGNAL_FAIL\t\t\t\t2\n+#define\t VL53LX_RANGESTATUS_RANGE_VALID_MIN_RANGE_CLIPPED\t3\n+#define\t VL53LX_RANGESTATUS_OUTOFBOUNDS_FAIL\t\t\t4\n+#define\t VL53LX_RANGESTATUS_HARDWARE_FAIL\t\t\t5\n+#define\t VL53LX_RANGESTATUS_RANGE_VALID_NO_WRAP_CHECK_FAIL\t6\n+#define\tVL53LX_RANGESTATUS_WRAP_TARGET_FAIL\t\t\t7\n+#define\tVL53LX_RANGESTATUS_PROCESSING_FAIL\t\t\t8\n+#define\tVL53LX_RANGESTATUS_XTALK_SIGNAL_FAIL\t\t\t9\n+#define\tVL53LX_RANGESTATUS_SYNCRONISATION_INT\t\t\t10\n+#define\tVL53LX_RANGESTATUS_RANGE_VALID_MERGED_PULSE\t\t11\n+#define\tVL53LX_RANGESTATUS_TARGET_PRESENT_LACK_OF_SIGNAL\t12\n+#define\tVL53LX_RANGESTATUS_MIN_RANGE_FAIL\t\t\t13\n+#define\tVL53LX_RANGESTATUS_RANGE_INVALID\t\t\t14\n+#define\t VL53LX_RANGESTATUS_NONE\t\t\t\t255\n+\n+#define VL53LX_Dev_t VL53LX_DevData_t\n+#define VL53LX_DEV VL53LX_DevData_t *\n+\n+#define VL53LXDevDataGet(Dev, field) (Dev->field)\n+#define VL53LXDevDataSet(Dev, field, data) ((Dev->field) = (data))\n+\n+#define VL53LXDevStructGetLLDriverHandle(Dev) (&VL53LXDevDataGet(Dev, LLData))\n+#define VL53LXDevStructGetLLResultsHandle(Dev) (&VL53LXDevDataGet(Dev,\\\n+\t\tllresults))\n+\n+#define VL53LX_SETPARAMETERFIELD(Dev, field, value) \\\n+\t(VL53LXDevDataSet(Dev, CurrentParameters.field, value))\n+\n+#define VL53LX_GETPARAMETERFIELD(Dev, field, variable) \\\n+\t(variable = VL53LXDevDataGet(Dev, CurrentParameters).field)\n+\n+#define VL53LX_SETARRAYPARAMETERFIELD(Dev, field, index, value) \\\n+\t(VL53LXDevDataSet(Dev, CurrentParameters.field[index], value))\n+\n+#define VL53LX_GETARRAYPARAMETERFIELD(Dev, field, index, variable) \\\n+\t(variable = VL53LXDevDataGet(Dev, CurrentParameters).field[index])\n+\n+#define VL53LX_SETDEVICESPECIFICPARAMETER(Dev, field, value) \\\n+\t(VL53LXDevDataSet(Dev, DeviceSpecificParameters.field, value))\n+\n+#define VL53LX_GETDEVICESPECIFICPARAMETER(Dev, field) \\\n+\t(VL53LXDevDataGet(Dev, DeviceSpecificParameters).field)\n+\n+#define stvm531_get_max_meas_err(...) 3\n+#define stvm531_get_max_stream_err(...) 6\n+\n+#define VL53LX_D_001    8\n+#define VL53LX_D_002    0xFFFF\n+#define VL53LX_D_008\t0xFFFF\n+#define VL53LX_D_003\t0xFFFFFF\n+#define VL53LX_D_007\t0xFFFFFFFF\n+#define VL53LX_D_005\t0x7FFFFFFFFF\n+#define VL53LX_D_009\t0xFFFFFFFFFF\n+#define VL53LX_D_010\t0xFFFFFFFFFFFF\n+#define VL53LX_D_004\t0xFFFFFFFFFFFFFF\n+#define VL53LX_D_006\t0x7FFFFFFFFFFFFFFF\n+#define VL53LX_D_011\t0xFFFFFFFFFFFFFFFF\n+\n+\n+typedef uint32_t FixPoint1616_t;\n+\n+#define VL53LX_FIXPOINT1616TOFIXPOINT44(Value) ((uint16_t)((Value>>12)&0xFFFF))\n+#define VL53LX_FIXPOINT44TOFIXPOINT1616(Value) ((FixPoint1616_t)((uint32_t)Value<<12))\n+\n+#define VL53LX_FIXPOINT1616TOFIXPOINT72(Value) ((uint16_t)((Value>>14)&0xFFFF))\n+#define VL53LX_FIXPOINT72TOFIXPOINT1616(Value) ((FixPoint1616_t)((uint32_t)Value<<14))\n+\n+#define VL53LX_FIXPOINT1616TOFIXPOINT97(Value) ((uint16_t)((Value>>9)&0xFFFF))\n+#define VL53LX_FIXPOINT97TOFIXPOINT1616(Value) ((FixPoint1616_t)((uint32_t)Value<<9))\n+\n+#define VL53LX_FIXPOINT1616TOFIXPOINT88(Value) ((uint16_t)((Value>>8)&0xFFFF))\n+#define VL53LX_FIXPOINT88TOFIXPOINT1616(Value) ((FixPoint1616_t)((uint32_t)Value<<8))\n+\n+#define VL53LX_FIXPOINT1616TOFIXPOINT412(Value) ((uint16_t)((Value>>4)&0xFFFF))\n+#define VL53LX_FIXPOINT412TOFIXPOINT1616(Value) ((FixPoint1616_t)((uint32_t)Value<<4))\n+\n+#define VL53LX_FIXPOINT1616TOFIXPOINT313(Value) ((uint16_t)((Value>>3)&0xFFFF))\n+#define VL53LX_FIXPOINT313TOFIXPOINT1616(Value) ((FixPoint1616_t)((uint32_t)Value<<3))\n+\n+#define VL53LX_FIXPOINT1616TOFIXPOINT08(Value) ((uint8_t)((Value>>8)&0x00FF))\n+#define VL53LX_FIXPOINT08TOFIXPOINT1616(Value) ((FixPoint1616_t)((uint32_t)Value<<8))\n+\n+#define VL53LX_FIXPOINT1616TOFIXPOINT53(Value) ((uint8_t)((Value>>13)&0x00FF))\n+#define VL53LX_FIXPOINT53TOFIXPOINT1616(Value) ((FixPoint1616_t)((uint32_t)Value<<13))\n+\n+#define VL53LX_FIXPOINT1616TOFIXPOINT102(Value) ((uint16_t)((Value>>14)&0x0FFF))\n+#define VL53LX_FIXPOINT102TOFIXPOINT1616(Value) ((FixPoint1616_t)((uint32_t)Value<<14))\n+\n+#define VL53LX_FIXPOINT1616TOFIXPOINT142(Value) ((uint16_t)((Value>>14)&0xFFFF))\n+#define VL53LX_FIXPOINT142TOFIXPOINT1616(Value) ((FixPoint1616_t)((uint32_t)Value<<14))\n+\n+#define VL53LX_FIXPOINT1616TOFIXPOINT160(Value) ((uint16_t)((Value>>16)&0xFFFF))\n+#define VL53LX_FIXPOINT160TOFIXPOINT1616(Value) ((FixPoint1616_t)((uint32_t)Value<<16))\n+\n+#define VL53LX_MAKEUINT16(lsb, msb) ((uint16_t)((((uint16_t)msb)<<8) + (uint16_t)lsb))\n+\n+#define ABNORMAL_STOP_1 1\n+#define ABNORMAL_STOP_2 2\n+#define ABNORMAL_STOP_3 3\n+\n+#define VL53LX_MISC_DEV_NAME\t\t\"stmvl53lx_ranging\"\n+\n+enum __stmv53lx_parameter_name_e {\n+\tVL53LX_XTALKENABLE_PAR = 2,\n+\tVL53LX_POLLDELAY_PAR = 10,\n+\tVL53LX_TIMINGBUDGET_PAR = 11,\n+\tVL53LX_DISTANCEMODE_PAR = 12,\n+\tVL53LX_FORCEDEVICEONEN_PAR = 14,\n+\tVL53LX_LASTERROR_PAR = 15,\n+\tVL53LX_OFFSETCORRECTIONMODE_PAR = 16,\n+\tVL53LX_OPTICALCENTER_PAR = 17,\n+\tVL53LX_TUNING_PAR = 20,\n+\tVL53LX_SMUDGECORRECTIONMODE_PAR = 21,\n+\tVL53LX_ISXTALKVALUECHANGED_PAR = 22,\n+};\n+#define stmv53lx_parameter_name_e enum __stmv53lx_parameter_name_e\n+\n+struct stmvl53lx_parameter {\n+\tuint32_t is_read;\n+\tstmv53lx_parameter_name_e name;\n+\tint32_t value;\n+\tint32_t value2;\n+\tint32_t status;\n+};\n+\n+typedef struct {\n+\tuint8_t   TopLeftX;\n+\tuint8_t   TopLeftY;\n+\tuint8_t   BotRightX;\n+\tuint8_t   BotRightY;\n+} VL53LX_UserRoi_t;\n+\n+struct stmvl53lx_ioctl_roi_t {\n+\tint32_t\tis_read;\n+\tVL53LX_UserRoi_t Roi;\n+};\n+\n+typedef uint8_t VL53LX_WaitMethod;\n+\n+#define VL53LX_WAIT_METHOD_BLOCKING               ((VL53LX_WaitMethod)  0)\n+#define VL53LX_WAIT_METHOD_NON_BLOCKING           ((VL53LX_WaitMethod)  1)\n+\n+#define VL53LX_RETURN_ARRAY_ONLY                   0x01\n+#define VL53LX_REFERENCE_ARRAY_ONLY                0x10\n+#define VL53LX_BOTH_RETURN_AND_REFERENCE_ARRAYS    0x11\n+#define VL53LX_NEITHER_RETURN_AND_REFERENCE_ARRAYS 0x00\n+#define VL53LX_DEVICEINTERRUPTLEVEL_ACTIVE_HIGH               0x00\n+#define VL53LX_DEVICEINTERRUPTLEVEL_ACTIV\n+#define VL53LX_DEVICEINTERRUPTLEVEL_ACTIVE_MASK               0x10\n+#define VL53LX_POLLING_DELAY_US                     1000\n+#define VL53LX_SOFTWARE_RESET_DURATION_US            100\n+#define VL53LX_FIRMWARE_BOOT_TIME_US                1200\n+#define VL53LX_ENABLE_POWERFORCE_SETTLING_TIME_US    250\n+#define VL53LX_SPAD_ARRAY_WIDTH                       16\n+#define VL53LX_SPAD_ARRAY_HEIGHT                      16\n+#define VL53LX_NVM_SIZE_IN_BYTES                     512\n+#define VL53LX_NO_OF_SPAD_ENABLES                    256\n+#define VL53LX_RTN_SPAD_BUFFER_SIZE                   32\n+#define VL53LX_REF_SPAD_BUFFER_SIZE                    6\n+#define VL53LX_AMBIENT_WINDOW_VCSEL_PERIODS          256\n+#define VL53LX_RANGING_WINDOW_VCSEL_PERIODS         2048\n+#define VL53LX_MACRO_PERIOD_VCSEL_PERIODS \\\n+\t(VL53LX_AMBIENT_WINDOW_VCSEL_PERIODS + \\\n+\t\tVL53LX_RANGING_WINDOW_VCSEL_PERIODS)\n+#define VL53LX_MAX_ALLOWED_PHASE                    0xFFFF\n+#define VL53LX_RTN_SPAD_UNITY_TRANSMISSION      0x0100\n+#define VL53LX_RTN_SPAD_APERTURE_TRANSMISSION   0x0038\n+#define VL53LX_SPAD_TOTAL_COUNT_MAX                 ((0x01 << 29) - 1)\n+#define VL53LX_SPAD_TOTAL_COUNT_RES_THRES            (0x01 << 24)\n+#define VL53LX_COUNT_RATE_INTERNAL_MAX              ((0x01 << 24) - 1)\n+#define VL53LX_SPEED_OF_LIGHT_IN_AIR                299704\n+#define VL53LX_SPEED_OF_LIGHT_IN_AIR_DIV_8          (299704 >> 3)\n+\n+typedef uint8_t VL53LX_DeviceError;\n+\n+#define VL53LX_DEVICEERROR_NOUPDATE                   \\\n+\t((VL53LX_DeviceError) 0)\n+#define VL53LX_DEVICEERROR_VCSELCONTINUITYTESTFAILURE \\\n+\t((VL53LX_DeviceError) 1)\n+#define VL53LX_DEVICEERROR_VCSELWATCHDOGTESTFAILURE   \\\n+\t((VL53LX_DeviceError) 2)\n+#define VL53LX_DEVICEERROR_NOVHVVALUEFOUND            \\\n+\t((VL53LX_DeviceError) 3)\n+#define VL53LX_DEVICEERROR_MSRCNOTARGET               \\\n+\t((VL53LX_DeviceError) 4)\n+#define VL53LX_DEVICEERROR_RANGEPHASECHECK            \\\n+\t((VL53LX_DeviceError) 5)\n+#define VL53LX_DEVICEERROR_SIGMATHRESHOLDCHECK        \\\n+\t((VL53LX_DeviceError) 6)\n+#define VL53LX_DEVICEERROR_PHASECONSISTENCY           \\\n+\t((VL53LX_DeviceError) 7)\n+#define VL53LX_DEVICEERROR_MINCLIP                    \\\n+\t((VL53LX_DeviceError) 8)\n+#define VL53LX_DEVICEERROR_RANGECOMPLETE               \\\n+\t((VL53LX_DeviceError) 9)\n+#define VL53LX_DEVICEERROR_ALGOUNDERFLOW               \\\n+\t((VL53LX_DeviceError) 10)\n+#define VL53LX_DEVICEERROR_ALGOOVERFLOW                \\\n+\t((VL53LX_DeviceError) 11)\n+#define VL53LX_DEVICEERROR_RANGEIGNORETHRESHOLD       \\\n+\t((VL53LX_DeviceError) 12)\n+#define VL53LX_DEVICEERROR_USERROICLIP                \\\n+\t((VL53LX_DeviceError) 13)\n+#define VL53LX_DEVICEERROR_REFSPADCHARNOTENOUGHDPADS   \\\n+\t((VL53LX_DeviceError) 14)\n+#define VL53LX_DEVICEERROR_REFSPADCHARMORETHANTARGET  \\\n+\t((VL53LX_DeviceError) 15)\n+#define VL53LX_DEVICEERROR_REFSPADCHARLESSTHANTARGET  \\\n+\t((VL53LX_DeviceError) 16)\n+#define VL53LX_DEVICEERROR_MULTCLIPFAIL                \\\n+\t((VL53LX_DeviceError) 17)\n+#define VL53LX_DEVICEERROR_GPHSTREAMCOUNT0READY        \\\n+\t((VL53LX_DeviceError) 18)\n+#define VL53LX_DEVICEERROR_RANGECOMPLETE_NO_WRAP_CHECK \\\n+\t((VL53LX_DeviceError) 19)\n+#define VL53LX_DEVICEERROR_EVENTCONSISTENCY           \\\n+\t((VL53LX_DeviceError) 20)\n+#define VL53LX_DEVICEERROR_MINSIGNALEVENTCHECK        \\\n+\t((VL53LX_DeviceError) 21)\n+#define VL53LX_DEVICEERROR_RANGECOMPLETE_MERGED_PULSE \\\n+\t((VL53LX_DeviceError) 22)\n+#define VL53LX_DEVICEERROR_PREV_RANGE_NO_TARGETS      \\\n+\t((VL53LX_DeviceError) 23)\n+\n+#define STMVL53LX_CFG_POLL_DELAY_MS\t5\n+\n+#define STMVL53LX_CFG_TIMING_BUDGET_US\t30000\n+\n+#define STMVL53LX_CFG_DEFAULT_DISTANCE_MODE\tVL53LX_DISTANCEMODE_MEDIUM\n+\n+#define STMVL53LX_CFG_DEFAULT_CROSSTALK_ENABLE\t0\n+\n+#define STMVL53LX_CFG_DEFAULT_OFFSET_CORRECTION_MODE \\\n+\tVL53LX_OFFSETCORRECTIONMODE_STANDARD\n+\n+#define STMVL53LX_CFG_DEFAULT_DMAX_MODE\t\tVL53LX_DMAXMODE_CUSTCAL_DATA\n+\n+#define STMVL53LX_CFG_DEFAULT_SMUDGE_CORRECTION_MODE \\\n+\tVL53LX_SMUDGE_CORRECTION_NONE\n+\n+#define VL53LX_NVM_PEAK_RATE_MAP_SAMPLES  25\n+\n+#define VL53LX_NVM_PEAK_RATE_MAP_WIDTH     5\n+\n+#define VL53LX_NVM_PEAK_RATE_MAP_HEIGHT     5\n+\n+#define VL53LX_DSS_CONTROL__ROI_SUBTRACT                0x20\n+#define VL53LX_DSS_CONTROL__ROI_INTERSECT               0x10\n+\n+#define VL53LX_DSS_CONTROL__MODE_DISABLED               0x00\n+#define VL53LX_DSS_CONTROL__MODE_TARGET_RATE            0x01\n+#define VL53LX_DSS_CONTROL__MODE_EFFSPADS               0x02\n+#define VL53LX_DSS_CONTROL__MODE_BLOCKSELECT            0x03\n+\n+#define VL53LX_LL_API_IMPLEMENTATION_VER_MAJOR       1\n+\n+#define VL53LX_LL_API_IMPLEMENTATION_VER_MINOR       1\n+\n+#define VL53LX_LL_API_IMPLEMENTATION_VER_SUB         1\n+\n+#define VL53LX_LL_API_IMPLEMENTATION_VER_REVISION   0\n+\n+#define VL53LX_LL_API_IMPLEMENTATION_VER_STRING \"1.1.1\"\n+\n+#define VL53LX_SOFT_RESET 0x0000\n+#define VL53LX_I2C_SLAVE__DEVICE_ADDRESS 0x0001\n+#define VL53LX_ANA_CONFIG__VHV_REF_SEL_VDDPIX 0x0002\n+#define VL53LX_ANA_CONFIG__VHV_REF_SEL_VQUENCH 0x0003\n+#define VL53LX_ANA_CONFIG__REG_AVDD1V2_SEL 0x0004\n+#define VL53LX_ANA_CONFIG__FAST_OSC__TRIM 0x0005\n+#define VL53LX_OSC_MEASURED__FAST_OSC__FREQUENCY 0x0006\n+#define VL53LX_OSC_MEASURED__FAST_OSC__FREQUENCY_HI 0x0006\n+#define VL53LX_OSC_MEASURED__FAST_OSC__FREQUENCY_LO 0x0007\n+#define VL53LX_VHV_CONFIG__TIMEOUT_MACROP_LOOP_BOUND 0x0008\n+#define VL53LX_VHV_CONFIG__COUNT_THRESH 0x0009\n+#define VL53LX_VHV_CONFIG__OFFSET 0x000A\n+#define VL53LX_VHV_CONFIG__INIT 0x000B\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_0 0x000D\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_1 0x000E\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_2 0x000F\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_3 0x0010\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_4 0x0011\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_5 0x0012\n+#define VL53LX_GLOBAL_CONFIG__REF_EN_START_SELECT 0x0013\n+#define VL53LX_REF_SPAD_MAN__NUM_REQUESTED_REF_SPADS 0x0014\n+#define VL53LX_REF_SPAD_MAN__REF_LOCATION 0x0015\n+#define VL53LX_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS 0x0016\n+#define VL53LX_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_HI 0x0016\n+#define VL53LX_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_LO 0x0017\n+#define VL53LX_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS 0x0018\n+#define VL53LX_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_HI 0x0018\n+#define VL53LX_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_LO 0x0019\n+#define VL53LX_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS 0x001A\n+#define VL53LX_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_HI 0x001A\n+#define VL53LX_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_LO 0x001B\n+#define VL53LX_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS 0x001C\n+#define VL53LX_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS_HI 0x001C\n+#define VL53LX_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS_LO 0x001D\n+#define VL53LX_ALGO__PART_TO_PART_RANGE_OFFSET_MM 0x001E\n+#define VL53LX_ALGO__PART_TO_PART_RANGE_OFFSET_MM_HI 0x001E\n+#define VL53LX_ALGO__PART_TO_PART_RANGE_OFFSET_MM_LO 0x001F\n+#define VL53LX_MM_CONFIG__INNER_OFFSET_MM 0x0020\n+#define VL53LX_MM_CONFIG__INNER_OFFSET_MM_HI 0x0020\n+#define VL53LX_MM_CONFIG__INNER_OFFSET_MM_LO 0x0021\n+#define VL53LX_MM_CONFIG__OUTER_OFFSET_MM 0x0022\n+#define VL53LX_MM_CONFIG__OUTER_OFFSET_MM_HI 0x0022\n+#define VL53LX_MM_CONFIG__OUTER_OFFSET_MM_LO 0x0023\n+#define VL53LX_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS 0x0024\n+#define VL53LX_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS_HI 0x0024\n+#define VL53LX_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS_LO 0x0025\n+#define VL53LX_DEBUG__CTRL 0x0026\n+#define VL53LX_TEST_MODE__CTRL 0x0027\n+#define VL53LX_CLK_GATING__CTRL 0x0028\n+#define VL53LX_NVM_BIST__CTRL 0x0029\n+#define VL53LX_NVM_BIST__NUM_NVM_WORDS 0x002A\n+#define VL53LX_NVM_BIST__START_ADDRESS 0x002B\n+#define VL53LX_HOST_IF__STATUS 0x002C\n+#define VL53LX_PAD_I2C_HV__CONFIG 0x002D\n+#define VL53LX_PAD_I2C_HV__EXTSUP_CONFIG 0x002E\n+#define VL53LX_GPIO_HV_PAD__CTRL 0x002F\n+#define VL53LX_GPIO_HV_MUX__CTRL 0x0030\n+#define VL53LX_GPIO__TIO_HV_STATUS 0x0031\n+#define VL53LX_GPIO__FIO_HV_STATUS 0x0032\n+#define VL53LX_ANA_CONFIG__SPAD_SEL_PSWIDTH 0x0033\n+#define VL53LX_ANA_CONFIG__VCSEL_PULSE_WIDTH_OFFSET 0x0034\n+#define VL53LX_ANA_CONFIG__FAST_OSC__CONFIG_CTRL 0x0035\n+#define VL53LX_SIGMA_ESTIMATOR__EFFECTIVE_PULSE_WIDTH_NS 0x0036\n+#define VL53LX_SIGMA_ESTIMATOR__EFFECTIVE_AMBIENT_WIDTH_NS 0x0037\n+#define VL53LX_SIGMA_ESTIMATOR__SIGMA_REF_MM 0x0038\n+#define VL53LX_ALGO__CROSSTALK_COMPENSATION_VALID_HEIGHT_MM 0x0039\n+#define VL53LX_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_0 0x003A\n+#define VL53LX_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_1 0x003B\n+#define VL53LX_ALGO__RANGE_IGNORE_THRESHOLD_MCPS 0x003C\n+#define VL53LX_ALGO__RANGE_IGNORE_THRESHOLD_MCPS_HI 0x003C\n+#define VL53LX_ALGO__RANGE_IGNORE_THRESHOLD_MCPS_LO 0x003D\n+#define VL53LX_ALGO__RANGE_IGNORE_VALID_HEIGHT_MM 0x003E\n+#define VL53LX_ALGO__RANGE_MIN_CLIP 0x003F\n+#define VL53LX_ALGO__CONSISTENCY_CHECK__TOLERANCE 0x0040\n+#define VL53LX_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_2 0x0041\n+#define VL53LX_SD_CONFIG__RESET_STAGES_MSB 0x0042\n+#define VL53LX_SD_CONFIG__RESET_STAGES_LSB 0x0043\n+#define VL53LX_GPH_CONFIG__STREAM_COUNT_UPDATE_VALUE 0x0044\n+#define VL53LX_GLOBAL_CONFIG__STREAM_DIVIDER 0x0045\n+#define VL53LX_SYSTEM__INTERRUPT_CONFIG_GPIO 0x0046\n+#define VL53LX_CAL_CONFIG__VCSEL_START 0x0047\n+#define VL53LX_CAL_CONFIG__REPEAT_RATE 0x0048\n+#define VL53LX_CAL_CONFIG__REPEAT_RATE_HI 0x0048\n+#define VL53LX_CAL_CONFIG__REPEAT_RATE_LO 0x0049\n+#define VL53LX_GLOBAL_CONFIG__VCSEL_WIDTH 0x004A\n+#define VL53LX_PHASECAL_CONFIG__TIMEOUT_MACROP 0x004B\n+#define VL53LX_PHASECAL_CONFIG__TARGET 0x004C\n+#define VL53LX_PHASECAL_CONFIG__OVERRIDE 0x004D\n+#define VL53LX_DSS_CONFIG__ROI_MODE_CONTROL 0x004F\n+#define VL53LX_SYSTEM__THRESH_RATE_HIGH 0x0050\n+#define VL53LX_SYSTEM__THRESH_RATE_HIGH_HI 0x0050\n+#define VL53LX_SYSTEM__THRESH_RATE_HIGH_LO 0x0051\n+#define VL53LX_SYSTEM__THRESH_RATE_LOW 0x0052\n+#define VL53LX_SYSTEM__THRESH_RATE_LOW_HI 0x0052\n+#define VL53LX_SYSTEM__THRESH_RATE_LOW_LO 0x0053\n+#define VL53LX_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT 0x0054\n+#define VL53LX_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_HI 0x0054\n+#define VL53LX_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_LO 0x0055\n+#define VL53LX_DSS_CONFIG__MANUAL_BLOCK_SELECT 0x0056\n+#define VL53LX_DSS_CONFIG__APERTURE_ATTENUATION 0x0057\n+#define VL53LX_DSS_CONFIG__MAX_SPADS_LIMIT 0x0058\n+#define VL53LX_DSS_CONFIG__MIN_SPADS_LIMIT 0x0059\n+#define VL53LX_MM_CONFIG__TIMEOUT_MACROP_A_HI 0x005A\n+#define VL53LX_MM_CONFIG__TIMEOUT_MACROP_A_LO 0x005B\n+#define VL53LX_MM_CONFIG__TIMEOUT_MACROP_B_HI 0x005C\n+#define VL53LX_MM_CONFIG__TIMEOUT_MACROP_B_LO 0x005D\n+#define VL53LX_RANGE_CONFIG__TIMEOUT_MACROP_A_HI 0x005E\n+#define VL53LX_RANGE_CONFIG__TIMEOUT_MACROP_A_LO 0x005F\n+#define VL53LX_RANGE_CONFIG__VCSEL_PERIOD_A 0x0060\n+#define VL53LX_RANGE_CONFIG__TIMEOUT_MACROP_B_HI 0x0061\n+#define VL53LX_RANGE_CONFIG__TIMEOUT_MACROP_B_LO 0x0062\n+#define VL53LX_RANGE_CONFIG__VCSEL_PERIOD_B 0x0063\n+#define VL53LX_RANGE_CONFIG__SIGMA_THRESH 0x0064\n+#define VL53LX_RANGE_CONFIG__SIGMA_THRESH_HI 0x0064\n+#define VL53LX_RANGE_CONFIG__SIGMA_THRESH_LO 0x0065\n+#define VL53LX_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS 0x0066\n+#define VL53LX_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI 0x0066\n+#define VL53LX_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO 0x0067\n+#define VL53LX_RANGE_CONFIG__VALID_PHASE_LOW 0x0068\n+#define VL53LX_RANGE_CONFIG__VALID_PHASE_HIGH 0x0069\n+#define VL53LX_SYSTEM__INTERMEASUREMENT_PERIOD 0x006C\n+#define VL53LX_SYSTEM__INTERMEASUREMENT_PERIOD_3 0x006C\n+#define VL53LX_SYSTEM__INTERMEASUREMENT_PERIOD_2 0x006D\n+#define VL53LX_SYSTEM__INTERMEASUREMENT_PERIOD_1 0x006E\n+#define VL53LX_SYSTEM__INTERMEASUREMENT_PERIOD_0 0x006F\n+#define VL53LX_SYSTEM__FRACTIONAL_ENABLE 0x0070\n+#define VL53LX_SYSTEM__GROUPED_PARAMETER_HOLD_0 0x0071\n+#define VL53LX_SYSTEM__THRESH_HIGH 0x0072\n+#define VL53LX_SYSTEM__THRESH_HIGH_HI 0x0072\n+#define VL53LX_SYSTEM__THRESH_HIGH_LO 0x0073\n+#define VL53LX_SYSTEM__THRESH_LOW 0x0074\n+#define VL53LX_SYSTEM__THRESH_LOW_HI 0x0074\n+#define VL53LX_SYSTEM__THRESH_LOW_LO 0x0075\n+#define VL53LX_SYSTEM__ENABLE_XTALK_PER_QUADRANT 0x0076\n+#define VL53LX_SYSTEM__SEED_CONFIG 0x0077\n+#define VL53LX_SD_CONFIG__WOI_SD0 0x0078\n+#define VL53LX_SD_CONFIG__WOI_SD1 0x0079\n+#define VL53LX_SD_CONFIG__INITIAL_PHASE_SD0 0x007A\n+#define VL53LX_SD_CONFIG__INITIAL_PHASE_SD1 0x007B\n+#define VL53LX_SYSTEM__GROUPED_PARAMETER_HOLD_1 0x007C\n+#define VL53LX_SD_CONFIG__FIRST_ORDER_SELECT 0x007D\n+#define VL53LX_SD_CONFIG__QUANTIFIER 0x007E\n+#define VL53LX_ROI_CONFIG__USER_ROI_CENTRE_SPAD 0x007F\n+#define VL53LX_ROI_CONFIG__USER_ROI_REQUESTED_GLOBAL_XY_SIZE 0x0080\n+#define VL53LX_SYSTEM__SEQUENCE_CONFIG 0x0081\n+#define VL53LX_SYSTEM__GROUPED_PARAMETER_HOLD 0x0082\n+#define VL53LX_POWER_MANAGEMENT__GO1_POWER_FORCE 0x0083\n+#define VL53LX_SYSTEM__STREAM_COUNT_CTRL 0x0084\n+#define VL53LX_FIRMWARE__ENABLE 0x0085\n+#define VL53LX_SYSTEM__INTERRUPT_CLEAR 0x0086\n+#define VL53LX_SYSTEM__MODE_START 0x0087\n+#define VL53LX_RESULT__INTERRUPT_STATUS 0x0088\n+#define VL53LX_RESULT__RANGE_STATUS 0x0089\n+#define VL53LX_RESULT__REPORT_STATUS 0x008A\n+#define VL53LX_RESULT__STREAM_COUNT 0x008B\n+#define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x008C\n+#define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x008C\n+#define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x008D\n+#define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x008E\n+#define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x008E\n+#define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x008F\n+#define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0090\n+#define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0090\n+#define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0091\n+#define VL53LX_RESULT__SIGMA_SD0 0x0092\n+#define VL53LX_RESULT__SIGMA_SD0_HI 0x0092\n+#define VL53LX_RESULT__SIGMA_SD0_LO 0x0093\n+#define VL53LX_RESULT__PHASE_SD0 0x0094\n+#define VL53LX_RESULT__PHASE_SD0_HI 0x0094\n+#define VL53LX_RESULT__PHASE_SD0_LO 0x0095\n+#define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0096\n+#define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0096\n+#define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0097\n+#define VL53LX_PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0098\n+#define VL53LX__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0098\n+#define VL53LX___PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0099\n+#define VL53LX_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x009A\n+#define VL53LX_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x009A\n+#define VL53LX_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x009B\n+#define VL53LX_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x009C\n+#define VL53LX_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x009C\n+#define VL53LX_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x009D\n+#define VL53LX_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x009E\n+#define VL53LX_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x009E\n+#define VL53LX_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x009F\n+#define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x00A0\n+#define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x00A0\n+#define VL53LX_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x00A1\n+#define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x00A2\n+#define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x00A2\n+#define VL53LX_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x00A3\n+#define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x00A4\n+#define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x00A4\n+#define VL53LX_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x00A5\n+#define VL53LX_RESULT__SIGMA_SD1 0x00A6\n+#define VL53LX_RESULT__SIGMA_SD1_HI 0x00A6\n+#define VL53LX_RESULT__SIGMA_SD1_LO 0x00A7\n+#define VL53LX_RESULT__PHASE_SD1 0x00A8\n+#define VL53LX_RESULT__PHASE_SD1_HI 0x00A8\n+#define VL53LX_RESULT__PHASE_SD1_LO 0x00A9\n+#define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x00AA\n+#define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x00AA\n+#define VL53LX_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x00AB\n+#define VL53LX_RESULT__SPARE_0_SD1 0x00AC\n+#define VL53LX_RESULT__SPARE_0_SD1_HI 0x00AC\n+#define VL53LX_RESULT__SPARE_0_SD1_LO 0x00AD\n+#define VL53LX_RESULT__SPARE_1_SD1 0x00AE\n+#define VL53LX_RESULT__SPARE_1_SD1_HI 0x00AE\n+#define VL53LX_RESULT__SPARE_1_SD1_LO 0x00AF\n+#define VL53LX_RESULT__SPARE_2_SD1 0x00B0\n+#define VL53LX_RESULT__SPARE_2_SD1_HI 0x00B0\n+#define VL53LX_RESULT__SPARE_2_SD1_LO 0x00B1\n+#define VL53LX_RESULT__SPARE_3_SD1 0x00B2\n+#define VL53LX_RESULT__THRESH_INFO 0x00B3\n+#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x00B4\n+#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x00B4\n+#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x00B5\n+#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x00B6\n+#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x00B7\n+#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x00B8\n+#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x00B8\n+#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x00B9\n+#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x00BA\n+#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x00BB\n+#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x00BC\n+#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x00BC\n+#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x00BD\n+#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x00BE\n+#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x00BF\n+#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x00C0\n+#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x00C0\n+#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x00C1\n+#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x00C2\n+#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x00C3\n+#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x00C4\n+#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x00C4\n+#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x00C5\n+#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x00C6\n+#define VL53LX_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x00C7\n+#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x00C8\n+#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x00C8\n+#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x00C9\n+#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x00CA\n+#define VL53LX_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x00CB\n+#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x00CC\n+#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x00CC\n+#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x00CD\n+#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x00CE\n+#define VL53LX_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x00CF\n+#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x00D0\n+#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x00D0\n+#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x00D1\n+#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x00D2\n+#define VL53LX_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x00D3\n+#define VL53LX_RESULT_CORE__SPARE_0 0x00D4\n+#define VL53LX_PHASECAL_RESULT__REFERENCE_PHASE 0x00D6\n+#define VL53LX_PHASECAL_RESULT__REFERENCE_PHASE_HI 0x00D6\n+#define VL53LX_PHASECAL_RESULT__REFERENCE_PHASE_LO 0x00D7\n+#define VL53LX_PHASECAL_RESULT__VCSEL_START 0x00D8\n+#define VL53LX_REF_SPAD_CHAR_RESULT__NUM_ACTUAL_REF_SPADS 0x00D9\n+#define VL53LX_REF_SPAD_CHAR_RESULT__REF_LOCATION 0x00DA\n+#define VL53LX_VHV_RESULT__COLDBOOT_STATUS 0x00DB\n+#define VL53LX_VHV_RESULT__SEARCH_RESULT 0x00DC\n+#define VL53LX_VHV_RESULT__LATEST_SETTING 0x00DD\n+#define VL53LX_RESULT__OSC_CALIBRATE_VAL 0x00DE\n+#define VL53LX_RESULT__OSC_CALIBRATE_VAL_HI 0x00DE\n+#define VL53LX_RESULT__OSC_CALIBRATE_VAL_LO 0x00DF\n+#define VL53LX_ANA_CONFIG__POWERDOWN_GO1 0x00E0\n+#define VL53LX_ANA_CONFIG__REF_BG_CTRL 0x00E1\n+#define VL53LX_ANA_CONFIG__REGDVDD1V2_CTRL 0x00E2\n+#define VL53LX_ANA_CONFIG__OSC_SLOW_CTRL 0x00E3\n+#define VL53LX_TEST_MODE__STATUS 0x00E4\n+#define VL53LX_FIRMWARE__SYSTEM_STATUS 0x00E5\n+#define VL53LX_FIRMWARE__MODE_STATUS 0x00E6\n+#define VL53LX_FIRMWARE__SECONDARY_MODE_STATUS 0x00E7\n+#define VL53LX_FIRMWARE__CAL_REPEAT_RATE_COUNTER 0x00E8\n+#define VL53LX_FIRMWARE__CAL_REPEAT_RATE_COUNTER_HI 0x00E8\n+#define VL53LX_FIRMWARE__CAL_REPEAT_RATE_COUNTER_LO 0x00E9\n+#define VL53LX_FIRMWARE__HISTOGRAM_BIN 0x00EA\n+#define VL53LX_GPH__SYSTEM__THRESH_HIGH 0x00EC\n+#define VL53LX_GPH__SYSTEM__THRESH_HIGH_HI 0x00EC\n+#define VL53LX_GPH__SYSTEM__THRESH_HIGH_LO 0x00ED\n+#define VL53LX_GPH__SYSTEM__THRESH_LOW 0x00EE\n+#define VL53LX_GPH__SYSTEM__THRESH_LOW_HI 0x00EE\n+#define VL53LX_GPH__SYSTEM__THRESH_LOW_LO 0x00EF\n+#define VL53LX_GPH__SYSTEM__ENABLE_XTALK_PER_QUADRANT 0x00F0\n+#define VL53LX_GPH__SPARE_0 0x00F1\n+#define VL53LX_GPH__SD_CONFIG__WOI_SD0 0x00F2\n+#define VL53LX_GPH__SD_CONFIG__WOI_SD1 0x00F3\n+#define VL53LX_GPH__SD_CONFIG__INITIAL_PHASE_SD0 0x00F4\n+#define VL53LX_GPH__SD_CONFIG__INITIAL_PHASE_SD1 0x00F5\n+#define VL53LX_GPH__SD_CONFIG__FIRST_ORDER_SELECT 0x00F6\n+#define VL53LX_GPH__SD_CONFIG__QUANTIFIER 0x00F7\n+#define VL53LX_GPH__ROI_CONFIG__USER_ROI_CENTRE_SPAD 0x00F8\n+#define VL53LX_GPH__ROI_CONFIG__USER_ROI_REQUESTED_GLOBAL_XY_SIZE 0x00F9\n+#define VL53LX_GPH__SYSTEM__SEQUENCE_CONFIG 0x00FA\n+#define VL53LX_GPH__GPH_ID 0x00FB\n+#define VL53LX_SYSTEM__INTERRUPT_SET 0x00FC\n+#define VL53LX_INTERRUPT_MANAGER__ENABLES 0x00FD\n+#define VL53LX_INTERRUPT_MANAGER__CLEAR 0x00FE\n+#define VL53LX_INTERRUPT_MANAGER__STATUS 0x00FF\n+#define VL53LX_MCU_TO_HOST_BANK__WR_ACCESS_EN 0x0100\n+#define VL53LX_POWER_MANAGEMENT__GO1_RESET_STATUS 0x0101\n+#define VL53LX_PAD_STARTUP_MODE__VALUE_RO 0x0102\n+#define VL53LX_PAD_STARTUP_MODE__VALUE_CTRL 0x0103\n+#define VL53LX_PLL_PERIOD_US 0x0104\n+#define VL53LX_PLL_PERIOD_US_3 0x0104\n+#define VL53LX_PLL_PERIOD_US_2 0x0105\n+#define VL53LX_PLL_PERIOD_US_1 0x0106\n+#define VL53LX_PLL_PERIOD_US_0 0x0107\n+#define VL53LX_INTERRUPT_SCHEDULER__DATA_OUT 0x0108\n+#define VL53LX_INTERRUPT_SCHEDULER__DATA_OUT_3 0x0108\n+#define VL53LX_INTERRUPT_SCHEDULER__DATA_OUT_2 0x0109\n+#define VL53LX_INTERRUPT_SCHEDULER__DATA_OUT_1 0x010A\n+#define VL53LX_INTERRUPT_SCHEDULER__DATA_OUT_0 0x010B\n+#define VL53LX_NVM_BIST__COMPLETE 0x010C\n+#define VL53LX_NVM_BIST__STATUS 0x010D\n+#define VL53LX_IDENTIFICATION__MODEL_ID 0x010F\n+#define VL53LX_IDENTIFICATION__MODULE_TYPE 0x0110\n+#define VL53LX_IDENTIFICATION__REVISION_ID 0x0111\n+#define VL53LX_IDENTIFICATION__MODULE_ID 0x0112\n+#define VL53LX_IDENTIFICATION__MODULE_ID_HI 0x0112\n+#define VL53LX_IDENTIFICATION__MODULE_ID_LO 0x0113\n+#define VL53LX_ANA_CONFIG__FAST_OSC__TRIM_MAX 0x0114\n+#define VL53LX_ANA_CONFIG__FAST_OSC__FREQ_SET 0x0115\n+#define VL53LX_ANA_CONFIG__VCSEL_TRIM 0x0116\n+#define VL53LX_ANA_CONFIG__VCSEL_SELION 0x0117\n+#define VL53LX_ANA_CONFIG__VCSEL_SELION_MAX 0x0118\n+#define VL53LX_PROTECTED_LASER_SAFETY__LOCK_BIT 0x0119\n+#define VL53LX_LASER_SAFETY__KEY 0x011A\n+#define VL53LX_LASER_SAFETY__KEY_RO 0x011B\n+#define VL53LX_LASER_SAFETY__CLIP 0x011C\n+#define VL53LX_LASER_SAFETY__MULT 0x011D\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_0 0x011E\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_1 0x011F\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_2 0x0120\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_3 0x0121\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_4 0x0122\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_5 0x0123\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_6 0x0124\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_7 0x0125\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_8 0x0126\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_9 0x0127\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_10 0x0128\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_11 0x0129\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_12 0x012A\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_13 0x012B\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_14 0x012C\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_15 0x012D\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_16 0x012E\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_17 0x012F\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_18 0x0130\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_19 0x0131\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_20 0x0132\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_21 0x0133\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_22 0x0134\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_23 0x0135\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_24 0x0136\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_25 0x0137\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_26 0x0138\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_27 0x0139\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_28 0x013A\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_29 0x013B\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_30 0x013C\n+#define VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_RTN_31 0x013D\n+#define VL53LX_ROI_CONFIG__MODE_ROI_CENTRE_SPAD 0x013E\n+#define VL53LX_ROI_CONFIG__MODE_ROI_XY_SIZE 0x013F\n+#define VL53LX_GO2_HOST_BANK_ACCESS__OVERRIDE 0x0300\n+#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLICAND 0x0400\n+#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLICAND_3 0x0400\n+#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLICAND_2 0x0401\n+#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLICAND_1 0x0402\n+#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLICAND_0 0x0403\n+#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLIER 0x0404\n+#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLIER_3 0x0404\n+#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLIER_2 0x0405\n+#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLIER_1 0x0406\n+#define VL53LX_MCU_UTIL_MULTIPLIER__MULTIPLIER_0 0x0407\n+#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_HI 0x0408\n+#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_HI_3 0x0408\n+#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_HI_2 0x0409\n+#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_HI_1 0x040A\n+#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_HI_0 0x040B\n+#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_LO 0x040C\n+#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_LO_3 0x040C\n+#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_LO_2 0x040D\n+#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_LO_1 0x040E\n+#define VL53LX_MCU_UTIL_MULTIPLIER__PRODUCT_LO_0 0x040F\n+#define VL53LX_MCU_UTIL_MULTIPLIER__START 0x0410\n+#define VL53LX_MCU_UTIL_MULTIPLIER__STATUS 0x0411\n+#define VL53LX_MCU_UTIL_DIVIDER__START 0x0412\n+#define VL53LX_MCU_UTIL_DIVIDER__STATUS 0x0413\n+#define VL53LX_MCU_UTIL_DIVIDER__DIVIDEND 0x0414\n+#define VL53LX_MCU_UTIL_DIVIDER__DIVIDEND_3 0x0414\n+#define VL53LX_MCU_UTIL_DIVIDER__DIVIDEND_2 0x0415\n+#define VL53LX_MCU_UTIL_DIVIDER__DIVIDEND_1 0x0416\n+#define VL53LX_MCU_UTIL_DIVIDER__DIVIDEND_0 0x0417\n+#define VL53LX_MCU_UTIL_DIVIDER__DIVISOR 0x0418\n+#define VL53LX_MCU_UTIL_DIVIDER__DIVISOR_3 0x0418\n+#define VL53LX_MCU_UTIL_DIVIDER__DIVISOR_2 0x0419\n+#define VL53LX_MCU_UTIL_DIVIDER__DIVISOR_1 0x041A\n+#define VL53LX_MCU_UTIL_DIVIDER__DIVISOR_0 0x041B\n+#define VL53LX_MCU_UTIL_DIVIDER__QUOTIENT 0x041C\n+#define VL53LX_MCU_UTIL_DIVIDER__QUOTIENT_3 0x041C\n+#define VL53LX_MCU_UTIL_DIVIDER__QUOTIENT_2 0x041D\n+#define VL53LX_MCU_UTIL_DIVIDER__QUOTIENT_1 0x041E\n+#define VL53LX_MCU_UTIL_DIVIDER__QUOTIENT_0 0x041F\n+#define VL53LX_TIMER0__VALUE_IN 0x0420\n+#define VL53LX_TIMER0__VALUE_IN_3 0x0420\n+#define VL53LX_TIMER0__VALUE_IN_2 0x0421\n+#define VL53LX_TIMER0__VALUE_IN_1 0x0422\n+#define VL53LX_TIMER0__VALUE_IN_0 0x0423\n+#define VL53LX_TIMER1__VALUE_IN 0x0424\n+#define VL53LX_TIMER1__VALUE_IN_3 0x0424\n+#define VL53LX_TIMER1__VALUE_IN_2 0x0425\n+#define VL53LX_TIMER1__VALUE_IN_1 0x0426\n+#define VL53LX_TIMER1__VALUE_IN_0 0x0427\n+#define VL53LX_TIMER0__CTRL 0x0428\n+#define VL53LX_TIMER1__CTRL 0x0429\n+#define VL53LX_MCU_GENERAL_PURPOSE__GP_0 0x042C\n+#define VL53LX_MCU_GENERAL_PURPOSE__GP_1 0x042D\n+#define VL53LX_MCU_GENERAL_PURPOSE__GP_2 0x042E\n+#define VL53LX_MCU_GENERAL_PURPOSE__GP_3 0x042F\n+#define VL53LX_MCU_RANGE_CALC__CONFIG 0x0430\n+#define VL53LX_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE 0x0432\n+#define VL53LX_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE_HI 0x0432\n+#define VL53LX_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE_LO 0x0433\n+#define VL53LX_MCU_RANGE_CALC__SPARE_4 0x0434\n+#define VL53LX_MCU_RANGE_CALC__SPARE_4_3 0x0434\n+#define VL53LX_MCU_RANGE_CALC__SPARE_4_2 0x0435\n+#define VL53LX_MCU_RANGE_CALC__SPARE_4_1 0x0436\n+#define VL53LX_MCU_RANGE_CALC__SPARE_4_0 0x0437\n+#define VL53LX_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC 0x0438\n+#define VL53LX_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC_HI 0x0438\n+#define VL53LX_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC_LO 0x0439\n+#define VL53LX_MCU_RANGE_CALC__ALGO_VCSEL_PERIOD 0x043C\n+#define VL53LX_MCU_RANGE_CALC__SPARE_5 0x043D\n+#define VL53LX_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS 0x043E\n+#define VL53LX_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS_HI 0x043E\n+#define VL53LX_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS_LO 0x043F\n+#define VL53LX_MCU_RANGE_CALC__ALGO_ACCUM_PHASE 0x0440\n+#define VL53LX_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_3 0x0440\n+#define VL53LX_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_2 0x0441\n+#define VL53LX_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_1 0x0442\n+#define VL53LX_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_0 0x0443\n+#define VL53LX_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS 0x0444\n+#define VL53LX_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_3 0x0444\n+#define VL53LX_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_2 0x0445\n+#define VL53LX_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_1 0x0446\n+#define VL53LX_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_0 0x0447\n+#define VL53LX_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS 0x0448\n+#define VL53LX_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_3 0x0448\n+#define VL53LX_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_2 0x0449\n+#define VL53LX_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_1 0x044A\n+#define VL53LX_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_0 0x044B\n+#define VL53LX_MCU_RANGE_CALC__SPARE_6 0x044C\n+#define VL53LX_MCU_RANGE_CALC__SPARE_6_HI 0x044C\n+#define VL53LX_MCU_RANGE_CALC__SPARE_6_LO 0x044D\n+#define VL53LX_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD 0x044E\n+#define VL53LX_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD_HI 0x044E\n+#define VL53LX_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD_LO 0x044F\n+#define VL53LX_MCU_RANGE_CALC__NUM_SPADS 0x0450\n+#define VL53LX_MCU_RANGE_CALC__NUM_SPADS_HI 0x0450\n+#define VL53LX_MCU_RANGE_CALC__NUM_SPADS_LO 0x0451\n+#define VL53LX_MCU_RANGE_CALC__PHASE_OUTPUT 0x0452\n+#define VL53LX_MCU_RANGE_CALC__PHASE_OUTPUT_HI 0x0452\n+#define VL53LX_MCU_RANGE_CALC__PHASE_OUTPUT_LO 0x0453\n+#define VL53LX_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS 0x0454\n+#define VL53LX_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_3 0x0454\n+#define VL53LX_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_2 0x0455\n+#define VL53LX_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_1 0x0456\n+#define VL53LX_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_0 0x0457\n+#define VL53LX_MCU_RANGE_CALC__SPARE_7 0x0458\n+#define VL53LX_MCU_RANGE_CALC__SPARE_8 0x0459\n+#define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS 0x045A\n+#define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS_HI 0x045A\n+#define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS_LO 0x045B\n+#define VL53LX_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS 0x045C\n+#define VL53LX_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS_HI 0x045C\n+#define VL53LX_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS_LO 0x045D\n+#define VL53LX_MCU_RANGE_CALC__AMBIENT_RATE_MCPS 0x045E\n+#define VL53LX_MCU_RANGE_CALC__AMBIENT_RATE_MCPS_HI 0x045E\n+#define VL53LX_MCU_RANGE_CALC__AMBIENT_RATE_MCPS_LO 0x045F\n+#define VL53LX_MCU_RANGE_CALC__XTALK 0x0460\n+#define VL53LX_MCU_RANGE_CALC__XTALK_HI 0x0460\n+#define VL53LX_MCU_RANGE_CALC__XTALK_LO 0x0461\n+#define VL53LX_MCU_RANGE_CALC__CALC_STATUS 0x0462\n+#define VL53LX_MCU_RANGE_CALC__DEBUG 0x0463\n+#define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS 0x0464\n+#define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_HI 0x0464\n+#define VL53LX_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_LO 0x0465\n+#define VL53LX_MCU_RANGE_CALC__SPARE_0 0x0468\n+#define VL53LX_MCU_RANGE_CALC__SPARE_1 0x0469\n+#define VL53LX_MCU_RANGE_CALC__SPARE_2 0x046A\n+#define VL53LX_MCU_RANGE_CALC__SPARE_3 0x046B\n+#define VL53LX_PATCH__CTRL 0x0470\n+#define VL53LX_PATCH__JMP_ENABLES 0x0472\n+#define VL53LX_PATCH__JMP_ENABLES_HI 0x0472\n+#define VL53LX_PATCH__JMP_ENABLES_LO 0x0473\n+#define VL53LX_PATCH__DATA_ENABLES 0x0474\n+#define VL53LX_PATCH__DATA_ENABLES_HI 0x0474\n+#define VL53LX_PATCH__DATA_ENABLES_LO 0x0475\n+#define VL53LX_PATCH__OFFSET_0 0x0476\n+#define VL53LX_PATCH__OFFSET_0_HI 0x0476\n+#define VL53LX_PATCH__OFFSET_0_LO 0x0477\n+#define VL53LX_PATCH__OFFSET_1 0x0478\n+#define VL53LX_PATCH__OFFSET_1_HI 0x0478\n+#define VL53LX_PATCH__OFFSET_1_LO 0x0479\n+#define VL53LX_PATCH__OFFSET_2 0x047A\n+#define VL53LX_PATCH__OFFSET_2_HI 0x047A\n+#define VL53LX_PATCH__OFFSET_2_LO 0x047B\n+#define VL53LX_PATCH__OFFSET_3 0x047C\n+#define VL53LX_PATCH__OFFSET_3_HI 0x047C\n+#define VL53LX_PATCH__OFFSET_3_LO 0x047D\n+#define VL53LX_PATCH__OFFSET_4 0x047E\n+#define VL53LX_PATCH__OFFSET_4_HI 0x047E\n+#define VL53LX_PATCH__OFFSET_4_LO 0x047F\n+#define VL53LX_PATCH__OFFSET_5 0x0480\n+#define VL53LX_PATCH__OFFSET_5_HI 0x0480\n+#define VL53LX_PATCH__OFFSET_5_LO 0x0481\n+#define VL53LX_PATCH__OFFSET_6 0x0482\n+#define VL53LX_PATCH__OFFSET_6_HI 0x0482\n+#define VL53LX_PATCH__OFFSET_6_LO 0x0483\n+#define VL53LX_PATCH__OFFSET_7 0x0484\n+#define VL53LX_PATCH__OFFSET_7_HI 0x0484\n+#define VL53LX_PATCH__OFFSET_7_LO 0x0485\n+#define VL53LX_PATCH__OFFSET_8 0x0486\n+#define VL53LX_PATCH__OFFSET_8_HI 0x0486\n+#define VL53LX_PATCH__OFFSET_8_LO 0x0487\n+#define VL53LX_PATCH__OFFSET_9 0x0488\n+#define VL53LX_PATCH__OFFSET_9_HI 0x0488\n+#define VL53LX_PATCH__OFFSET_9_LO 0x0489\n+#define VL53LX_PATCH__OFFSET_10 0x048A\n+#define VL53LX_PATCH__OFFSET_10_HI 0x048A\n+#define VL53LX_PATCH__OFFSET_10_LO 0x048B\n+#define VL53LX_PATCH__OFFSET_11 0x048C\n+#define VL53LX_PATCH__OFFSET_11_HI 0x048C\n+#define VL53LX_PATCH__OFFSET_11_LO 0x048D\n+#define VL53LX_PATCH__OFFSET_12 0x048E\n+#define VL53LX_PATCH__OFFSET_12_HI 0x048E\n+#define VL53LX_PATCH__OFFSET_12_LO 0x048F\n+#define VL53LX_PATCH__OFFSET_13 0x0490\n+#define VL53LX_PATCH__OFFSET_13_HI 0x0490\n+#define VL53LX_PATCH__OFFSET_13_LO 0x0491\n+#define VL53LX_PATCH__OFFSET_14 0x0492\n+#define VL53LX_PATCH__OFFSET_14_HI 0x0492\n+#define VL53LX_PATCH__OFFSET_14_LO 0x0493\n+#define VL53LX_PATCH__OFFSET_15 0x0494\n+#define VL53LX_PATCH__OFFSET_15_HI 0x0494\n+#define VL53LX_PATCH__OFFSET_15_LO 0x0495\n+#define VL53LX_PATCH__ADDRESS_0 0x0496\n+#define VL53LX_PATCH__ADDRESS_0_HI 0x0496\n+#define VL53LX_PATCH__ADDRESS_0_LO 0x0497\n+#define VL53LX_PATCH__ADDRESS_1 0x0498\n+#define VL53LX_PATCH__ADDRESS_1_HI 0x0498\n+#define VL53LX_PATCH__ADDRESS_1_LO 0x0499\n+#define VL53LX_PATCH__ADDRESS_2 0x049A\n+#define VL53LX_PATCH__ADDRESS_2_HI 0x049A\n+#define VL53LX_PATCH__ADDRESS_2_LO 0x049B\n+#define VL53LX_PATCH__ADDRESS_3 0x049C\n+#define VL53LX_PATCH__ADDRESS_3_HI 0x049C\n+#define VL53LX_PATCH__ADDRESS_3_LO 0x049D\n+#define VL53LX_PATCH__ADDRESS_4 0x049E\n+#define VL53LX_PATCH__ADDRESS_4_HI 0x049E\n+#define VL53LX_PATCH__ADDRESS_4_LO 0x049F\n+#define VL53LX_PATCH__ADDRESS_5 0x04A0\n+#define VL53LX_PATCH__ADDRESS_5_HI 0x04A0\n+#define VL53LX_PATCH__ADDRESS_5_LO 0x04A1\n+#define VL53LX_PATCH__ADDRESS_6 0x04A2\n+#define VL53LX_PATCH__ADDRESS_6_HI 0x04A2\n+#define VL53LX_PATCH__ADDRESS_6_LO 0x04A3\n+#define VL53LX_PATCH__ADDRESS_7 0x04A4\n+#define VL53LX_PATCH__ADDRESS_7_HI 0x04A4\n+#define VL53LX_PATCH__ADDRESS_7_LO 0x04A5\n+#define VL53LX_PATCH__ADDRESS_8 0x04A6\n+#define VL53LX_PATCH__ADDRESS_8_HI 0x04A6\n+#define VL53LX_PATCH__ADDRESS_8_LO 0x04A7\n+#define VL53LX_PATCH__ADDRESS_9 0x04A8\n+#define VL53LX_PATCH__ADDRESS_9_HI 0x04A8\n+#define VL53LX_PATCH__ADDRESS_9_LO 0x04A9\n+#define VL53LX_PATCH__ADDRESS_10 0x04AA\n+#define VL53LX_PATCH__ADDRESS_10_HI 0x04AA\n+#define VL53LX_PATCH__ADDRESS_10_LO 0x04AB\n+#define VL53LX_PATCH__ADDRESS_11 0x04AC\n+#define VL53LX_PATCH__ADDRESS_11_HI 0x04AC\n+#define VL53LX_PATCH__ADDRESS_11_LO 0x04AD\n+#define VL53LX_PATCH__ADDRESS_12 0x04AE\n+#define VL53LX_PATCH__ADDRESS_12_HI 0x04AE\n+#define VL53LX_PATCH__ADDRESS_12_LO 0x04AF\n+#define VL53LX_PATCH__ADDRESS_13 0x04B0\n+#define VL53LX_PATCH__ADDRESS_13_HI 0x04B0\n+#define VL53LX_PATCH__ADDRESS_13_LO 0x04B1\n+#define VL53LX_PATCH__ADDRESS_14 0x04B2\n+#define VL53LX_PATCH__ADDRESS_14_HI 0x04B2\n+#define VL53LX_PATCH__ADDRESS_14_LO 0x04B3\n+#define VL53LX_PATCH__ADDRESS_15 0x04B4\n+#define VL53LX_PATCH__ADDRESS_15_HI 0x04B4\n+#define VL53LX_PATCH__ADDRESS_15_LO 0x04B5\n+#define VL53LX_SPI_ASYNC_MUX__CTRL 0x04C0\n+#define VL53LX_CLK__CONFIG 0x04C4\n+#define VL53LX_GPIO_LV_MUX__CTRL 0x04CC\n+#define VL53LX_GPIO_LV_PAD__CTRL 0x04CD\n+#define VL53LX_PAD_I2C_LV__CONFIG 0x04D0\n+#define VL53LX_PAD_STARTUP_MODE__VALUE_RO_GO1 0x04D4\n+#define VL53LX_HOST_IF__STATUS_GO1 0x04D5\n+#define VL53LX_MCU_CLK_GATING__CTRL 0x04D8\n+#define VL53LX_TEST__BIST_ROM_CTRL 0x04E0\n+#define VL53LX_TEST__BIST_ROM_RESULT 0x04E1\n+#define VL53LX_TEST__BIST_ROM_MCU_SIG 0x04E2\n+#define VL53LX_TEST__BIST_ROM_MCU_SIG_HI 0x04E2\n+#define VL53LX_TEST__BIST_ROM_MCU_SIG_LO 0x04E3\n+#define VL53LX_TEST__BIST_RAM_CTRL 0x04E4\n+#define VL53LX_TEST__BIST_RAM_RESULT 0x04E5\n+#define VL53LX_TEST__TMC 0x04E8\n+#define VL53LX_TEST__PLL_BIST_MIN_THRESHOLD 0x04F0\n+#define VL53LX_TEST__PLL_BIST_MIN_THRESHOLD_HI 0x04F0\n+#define VL53LX_TEST__PLL_BIST_MIN_THRESHOLD_LO 0x04F1\n+#define VL53LX_TEST__PLL_BIST_MAX_THRESHOLD 0x04F2\n+#define VL53LX_TEST__PLL_BIST_MAX_THRESHOLD_HI 0x04F2\n+#define VL53LX_TEST__PLL_BIST_MAX_THRESHOLD_LO 0x04F3\n+#define VL53LX_TEST__PLL_BIST_COUNT_OUT 0x04F4\n+#define VL53LX_TEST__PLL_BIST_COUNT_OUT_HI 0x04F4\n+#define VL53LX_TEST__PLL_BIST_COUNT_OUT_LO 0x04F5\n+#define VL53LX_TEST__PLL_BIST_GONOGO 0x04F6\n+#define VL53LX_TEST__PLL_BIST_CTRL 0x04F7\n+#define VL53LX_RANGING_CORE__DEVICE_ID 0x0680\n+#define VL53LX_RANGING_CORE__REVISION_ID 0x0681\n+#define VL53LX_RANGING_CORE__CLK_CTRL1 0x0683\n+#define VL53LX_RANGING_CORE__CLK_CTRL2 0x0684\n+#define VL53LX_RANGING_CORE__WOI_1 0x0685\n+#define VL53LX_RANGING_CORE__WOI_REF_1 0x0686\n+#define VL53LX_RANGING_CORE__START_RANGING 0x0687\n+#define VL53LX_RANGING_CORE__LOW_LIMIT_1 0x0690\n+#define VL53LX_RANGING_CORE__HIGH_LIMIT_1 0x0691\n+#define VL53LX_RANGING_CORE__LOW_LIMIT_REF_1 0x0692\n+#define VL53LX_RANGING_CORE__HIGH_LIMIT_REF_1 0x0693\n+#define VL53LX_RANGING_CORE__QUANTIFIER_1_MSB 0x0694\n+#define VL53LX_RANGING_CORE__QUANTIFIER_1_LSB 0x0695\n+#define VL53LX_RANGING_CORE__QUANTIFIER_REF_1_MSB 0x0696\n+#define VL53LX_RANGING_CORE__QUANTIFIER_REF_1_LSB 0x0697\n+#define VL53LX_RANGING_CORE__AMBIENT_OFFSET_1_MSB 0x0698\n+#define VL53LX_RANGING_CORE__AMBIENT_OFFSET_1_LSB 0x0699\n+#define VL53LX_RANGING_CORE__AMBIENT_OFFSET_REF_1_MSB 0x069A\n+#define VL53LX_RANGING_CORE__AMBIENT_OFFSET_REF_1_LSB 0x069B\n+#define VL53LX_RANGING_CORE__FILTER_STRENGTH_1 0x069C\n+#define VL53LX_RANGING_CORE__FILTER_STRENGTH_REF_1 0x069D\n+#define VL53LX_RANGING_CORE__SIGNAL_EVENT_LIMIT_1_MSB 0x069E\n+#define VL53LX_RANGING_CORE__SIGNAL_EVENT_LIMIT_1_LSB 0x069F\n+#define VL53LX_RANGING_CORE__SIGNAL_EVENT_LIMIT_REF_1_MSB 0x06A0\n+#define VL53LX_RANGING_CORE__SIGNAL_EVENT_LIMIT_REF_1_LSB 0x06A1\n+#define VL53LX_RANGING_CORE__TIMEOUT_OVERALL_PERIODS_MSB 0x06A4\n+#define VL53LX_RANGING_CORE__TIMEOUT_OVERALL_PERIODS_LSB 0x06A5\n+#define VL53LX_RANGING_CORE__INVERT_HW 0x06A6\n+#define VL53LX_RANGING_CORE__FORCE_HW 0x06A7\n+#define VL53LX_RANGING_CORE__STATIC_HW_VALUE 0x06A8\n+#define VL53LX_RANGING_CORE__FORCE_CONTINUOUS_AMBIENT 0x06A9\n+#define VL53LX_RANGING_CORE__TEST_PHASE_SELECT_TO_FILTER 0x06AA\n+#define VL53LX_RANGING_CORE__TEST_PHASE_SELECT_TO_TIMING_GEN 0x06AB\n+#define VL53LX_RANGING_CORE__INITIAL_PHASE_VALUE_1 0x06AC\n+#define VL53LX_RANGING_CORE__INITIAL_PHASE_VALUE_REF_1 0x06AD\n+#define VL53LX_RANGING_CORE__FORCE_UP_IN 0x06AE\n+#define VL53LX_RANGING_CORE__FORCE_DN_IN 0x06AF\n+#define VL53LX_RANGING_CORE__STATIC_UP_VALUE_1 0x06B0\n+#define VL53LX_RANGING_CORE__STATIC_UP_VALUE_REF_1 0x06B1\n+#define VL53LX_RANGING_CORE__STATIC_DN_VALUE_1 0x06B2\n+#define VL53LX_RANGING_CORE__STATIC_DN_VALUE_REF_1 0x06B3\n+#define VL53LX_RANGING_CORE__MONITOR_UP_DN 0x06B4\n+#define VL53LX_RANGING_CORE__INVERT_UP_DN 0x06B5\n+#define VL53LX_RANGING_CORE__CPUMP_1 0x06B6\n+#define VL53LX_RANGING_CORE__CPUMP_2 0x06B7\n+#define VL53LX_RANGING_CORE__CPUMP_3 0x06B8\n+#define VL53LX_RANGING_CORE__OSC_1 0x06B9\n+#define VL53LX_RANGING_CORE__PLL_1 0x06BB\n+#define VL53LX_RANGING_CORE__PLL_2 0x06BC\n+#define VL53LX_RANGING_CORE__REFERENCE_1 0x06BD\n+#define VL53LX_RANGING_CORE__REFERENCE_3 0x06BF\n+#define VL53LX_RANGING_CORE__REFERENCE_4 0x06C0\n+#define VL53LX_RANGING_CORE__REFERENCE_5 0x06C1\n+#define VL53LX_RANGING_CORE__REGAVDD1V2 0x06C3\n+#define VL53LX_RANGING_CORE__CALIB_1 0x06C4\n+#define VL53LX_RANGING_CORE__CALIB_2 0x06C5\n+#define VL53LX_RANGING_CORE__CALIB_3 0x06C6\n+#define VL53LX_RANGING_CORE__TST_MUX_SEL1 0x06C9\n+#define VL53LX_RANGING_CORE__TST_MUX_SEL2 0x06CA\n+#define VL53LX_RANGING_CORE__TST_MUX 0x06CB\n+#define VL53LX_RANGING_CORE__GPIO_OUT_TESTMUX 0x06CC\n+#define VL53LX_RANGING_CORE__CUSTOM_FE 0x06CD\n+#define VL53LX_RANGING_CORE__CUSTOM_FE_2 0x06CE\n+#define VL53LX_RANGING_CORE__SPAD_READOUT 0x06CF\n+#define VL53LX_RANGING_CORE__SPAD_READOUT_1 0x06D0\n+#define VL53LX_RANGING_CORE__SPAD_READOUT_2 0x06D1\n+#define VL53LX_RANGING_CORE__SPAD_PS 0x06D2\n+#define VL53LX_RANGING_CORE__LASER_SAFETY_2 0x06D4\n+#define VL53LX_RANGING_CORE__NVM_CTRL__MODE 0x0780\n+#define VL53LX_RANGING_CORE__NVM_CTRL__PDN 0x0781\n+#define VL53LX_RANGING_CORE__NVM_CTRL__PROGN 0x0782\n+#define VL53LX_RANGING_CORE__NVM_CTRL__READN 0x0783\n+#define VL53LX_RANGING_CORE__NVM_CTRL__PULSE_WIDTH_MSB 0x0784\n+#define VL53LX_RANGING_CORE__NVM_CTRL__PULSE_WIDTH_LSB 0x0785\n+#define VL53LX_RANGING_CORE__NVM_CTRL__HV_RISE_MSB 0x0786\n+#define VL53LX_RANGING_CORE__NVM_CTRL__HV_RISE_LSB 0x0787\n+#define VL53LX_RANGING_CORE__NVM_CTRL__HV_FALL_MSB 0x0788\n+#define VL53LX_RANGING_CORE__NVM_CTRL__HV_FALL_LSB 0x0789\n+#define VL53LX_RANGING_CORE__NVM_CTRL__TST 0x078A\n+#define VL53LX_RANGING_CORE__NVM_CTRL__TESTREAD 0x078B\n+#define VL53LX_RANGING_CORE__NVM_CTRL__DATAIN_MMM 0x078C\n+#define VL53LX_RANGING_CORE__NVM_CTRL__DATAIN_LMM 0x078D\n+#define VL53LX_RANGING_CORE__NVM_CTRL__DATAIN_LLM 0x078E\n+#define VL53LX_RANGING_CORE__NVM_CTRL__DATAIN_LLL 0x078F\n+#define VL53LX_RANGING_CORE__NVM_CTRL__DATAOUT_MMM 0x0790\n+#define VL53LX_RANGING_CORE__NVM_CTRL__DATAOUT_LMM 0x0791\n+#define VL53LX_RANGING_CORE__NVM_CTRL__DATAOUT_LLM 0x0792\n+#define VL53LX_RANGING_CORE__NVM_CTRL__DATAOUT_LLL 0x0793\n+#define VL53LX_RANGING_CORE__NVM_CTRL__ADDR 0x0794\n+#define VL53LX_RANGING_CORE__NVM_CTRL__DATAOUT_ECC 0x0795\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_0 0x0796\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_1 0x0797\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_2 0x0798\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_3 0x0799\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_4 0x079A\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_5 0x079B\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_6 0x079C\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_7 0x079D\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_8 0x079E\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_9 0x079F\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_10 0x07A0\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_11 0x07A1\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_12 0x07A2\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_13 0x07A3\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_14 0x07A4\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_15 0x07A5\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_16 0x07A6\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_17 0x07A7\n+#define VL53LX_RANGING_CORE__SPAD_SHIFT_EN 0x07BA\n+#define VL53LX_RANGING_CORE__SPAD_DISABLE_CTRL 0x07BB\n+#define VL53LX_RANGING_CORE__SPAD_EN_SHIFT_OUT_DEBUG 0x07BC\n+#define VL53LX_RANGING_CORE__SPI_MODE 0x07BD\n+#define VL53LX_RANGING_CORE__GPIO_DIR 0x07BE\n+#define VL53LX_RANGING_CORE__VCSEL_PERIOD 0x0880\n+#define VL53LX_RANGING_CORE__VCSEL_START 0x0881\n+#define VL53LX_RANGING_CORE__VCSEL_STOP 0x0882\n+#define VL53LX_RANGING_CORE__VCSEL_1 0x0885\n+#define VL53LX_RANGING_CORE__VCSEL_STATUS 0x088D\n+#define VL53LX_RANGING_CORE__STATUS 0x0980\n+#define VL53LX_RANGING_CORE__LASER_CONTINUITY_STATE 0x0981\n+#define VL53LX_RANGING_CORE__RANGE_1_MMM 0x0982\n+#define VL53LX_RANGING_CORE__RANGE_1_LMM 0x0983\n+#define VL53LX_RANGING_CORE__RANGE_1_LLM 0x0984\n+#define VL53LX_RANGING_CORE__RANGE_1_LLL 0x0985\n+#define VL53LX_RANGING_CORE__RANGE_REF_1_MMM 0x0986\n+#define VL53LX_RANGING_CORE__RANGE_REF_1_LMM 0x0987\n+#define VL53LX_RANGING_CORE__RANGE_REF_1_LLM 0x0988\n+#define VL53LX_RANGING_CORE__RANGE_REF_1_LLL 0x0989\n+#define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_MMM 0x098A\n+#define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LMM 0x098B\n+#define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LLM 0x098C\n+#define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LLL 0x098D\n+#define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_1_MMM 0x098E\n+#define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LMM 0x098F\n+#define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LLM 0x0990\n+#define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LLL 0x0991\n+#define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_MMM 0x0992\n+#define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LMM 0x0993\n+#define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LLM 0x0994\n+#define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LLL 0x0995\n+#define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_MM 0x0996\n+#define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_LM 0x0997\n+#define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_LL 0x0998\n+#define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_MM 0x0999\n+#define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_LM 0x099A\n+#define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_LL 0x099B\n+#define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_MMM 0x099C\n+#define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LMM 0x099D\n+#define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LLM 0x099E\n+#define VL53LX_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LLL 0x099F\n+#define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_MMM 0x09A0\n+#define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LMM 0x09A1\n+#define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LLM 0x09A2\n+#define VL53LX_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LLL 0x09A3\n+#define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_MMM 0x09A4\n+#define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LMM 0x09A5\n+#define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LLM 0x09A6\n+#define VL53LX_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LLL 0x09A7\n+#define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_MM 0x09A8\n+#define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_LM 0x09A9\n+#define VL53LX_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_LL 0x09AA\n+#define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_REF_MM 0x09AB\n+#define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_REF_LM 0x09AC\n+#define VL53LX_RANGING_CORE__AMBIENT_MISMATCH_REF_LL 0x09AD\n+#define VL53LX_RANGING_CORE__GPIO_CONFIG__A0 0x0A00\n+#define VL53LX_RANGING_CORE__RESET_CONTROL__A0 0x0A01\n+#define VL53LX_RANGING_CORE__INTR_MANAGER__A0 0x0A02\n+#define VL53LX_RANGING_CORE__POWER_FSM_TIME_OSC__A0 0x0A06\n+#define VL53LX_RANGING_CORE__VCSEL_ATEST__A0 0x0A07\n+#define VL53LX_RANGING_CORE__VCSEL_PERIOD_CLIPPED__A0 0x0A08\n+#define VL53LX_RANGING_CORE__VCSEL_STOP_CLIPPED__A0 0x0A09\n+#define VL53LX_RANGING_CORE__CALIB_2__A0 0x0A0A\n+#define VL53LX_RANGING_CORE__STOP_CONDITION__A0 0x0A0B\n+#define VL53LX_RANGING_CORE__STATUS_RESET__A0 0x0A0C\n+#define VL53LX_RANGING_CORE__READOUT_CFG__A0 0x0A0D\n+#define VL53LX_RANGING_CORE__WINDOW_SETTING__A0 0x0A0E\n+#define VL53LX_RANGING_CORE__VCSEL_DELAY__A0 0x0A1A\n+#define VL53LX_RANGING_CORE__REFERENCE_2__A0 0x0A1B\n+#define VL53LX_RANGING_CORE__REGAVDD1V2__A0 0x0A1D\n+#define VL53LX_RANGING_CORE__TST_MUX__A0 0x0A1F\n+#define VL53LX_RANGING_CORE__CUSTOM_FE_2__A0 0x0A20\n+#define VL53LX_RANGING_CORE__SPAD_READOUT__A0 0x0A21\n+#define VL53LX_RANGING_CORE__CPUMP_1__A0 0x0A22\n+#define VL53LX_RANGING_CORE__SPARE_REGISTER__A0 0x0A23\n+#define VL53LX_RANGING_CORE__VCSEL_CONT_STAGE5_BYPASS__A0 0x0A24\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_18 0x0A25\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_19 0x0A26\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_20 0x0A27\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_21 0x0A28\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_22 0x0A29\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_23 0x0A2A\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_24 0x0A2B\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_25 0x0A2C\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_26 0x0A2D\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_27 0x0A2E\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_28 0x0A2F\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_29 0x0A30\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_30 0x0A31\n+#define VL53LX_RANGING_CORE__RET_SPAD_EN_31 0x0A32\n+#define VL53LX_RANGING_CORE__REF_SPAD_EN_0__EWOK 0x0A33\n+#define VL53LX_RANGING_CORE__REF_SPAD_EN_1__EWOK 0x0A34\n+#define VL53LX_RANGING_CORE__REF_SPAD_EN_2__EWOK 0x0A35\n+#define VL53LX_RANGING_CORE__REF_SPAD_EN_3__EWOK 0x0A36\n+#define VL53LX_RANGING_CORE__REF_SPAD_EN_4__EWOK 0x0A37\n+#define VL53LX_RANGING_CORE__REF_SPAD_EN_5__EWOK 0x0A38\n+#define VL53LX_RANGING_CORE__REF_EN_START_SELECT 0x0A39\n+#define VL53LX_RANGING_CORE__REGDVDD1V2_ATEST__EWOK 0x0A41\n+#define VL53LX_PRIVATE__PATCH_BASE_ADDR_RSLV 0x0E00\n+#define VL53LX_PREV_SHADOW_RESULT__INTERRUPT_STATUS 0x0ED0\n+#define VL53LX_PREV_SHADOW_RESULT__RANGE_STATUS 0x0ED1\n+#define VL53LX_PREV_SHADOW_RESULT__REPORT_STATUS 0x0ED2\n+#define VL53LX_PREV_SHADOW_RESULT__STREAM_COUNT 0x0ED3\n+#define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x0ED4\n+#define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0ED4\n+#define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0ED5\n+#define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x0ED6\n+#define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0ED6\n+#define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0ED7\n+#define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0ED8\n+#define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0ED8\n+#define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0ED9\n+#define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD0 0x0EDA\n+#define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD0_HI 0x0EDA\n+#define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD0_LO 0x0EDB\n+#define VL53LX_PREV_SHADOW_RESULT__PHASE_SD0 0x0EDC\n+#define VL53LX_PREV_SHADOW_RESULT__PHASE_SD0_HI 0x0EDC\n+#define VL53LX_PREV_SHADOW_RESULT__PHASE_SD0_LO 0x0EDD\n+#define VL53LX_PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0EDE\n+#define VL53LX_PREV__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0EDE\n+#define VL53LX_PREV__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0EDF\n+#define VL53LX_PREV__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0EE0\n+#define VL53LX_PPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0EE0\n+#define VL53LX_PPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0EE1\n+#define VL53LX_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0EE2\n+#define VL53LX_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0EE2\n+#define VL53LX_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0EE3\n+#define VL53LX_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0EE4\n+#define VL53LX_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0EE4\n+#define VL53LX_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0EE5\n+#define VL53LX_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x0EE6\n+#define VL53LX_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0EE6\n+#define VL53LX_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0EE7\n+#define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x0EE8\n+#define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x0EE8\n+#define VL53LX_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x0EE9\n+#define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x0EEA\n+#define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x0EEA\n+#define VL53LX_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x0EEB\n+#define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x0EEC\n+#define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x0EEC\n+#define VL53LX_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x0EED\n+#define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD1 0x0EEE\n+#define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD1_HI 0x0EEE\n+#define VL53LX_PREV_SHADOW_RESULT__SIGMA_SD1_LO 0x0EEF\n+#define VL53LX_PREV_SHADOW_RESULT__PHASE_SD1 0x0EF0\n+#define VL53LX_PREV_SHADOW_RESULT__PHASE_SD1_HI 0x0EF0\n+#define VL53LX_PREV_SHADOW_RESULT__PHASE_SD1_LO 0x0EF1\n+#define VL53LX_PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x0EF2\n+#define VL53LX_PFINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x0EF2\n+#define VL53LX_PFINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x0EF3\n+#define VL53LX_PREV_SHADOW_RESULT__SPARE_0_SD1 0x0EF4\n+#define VL53LX_PREV_SHADOW_RESULT__SPARE_0_SD1_HI 0x0EF4\n+#define VL53LX_PREV_SHADOW_RESULT__SPARE_0_SD1_LO 0x0EF5\n+#define VL53LX_PREV_SHADOW_RESULT__SPARE_1_SD1 0x0EF6\n+#define VL53LX_PREV_SHADOW_RESULT__SPARE_1_SD1_HI 0x0EF6\n+#define VL53LX_PREV_SHADOW_RESULT__SPARE_1_SD1_LO 0x0EF7\n+#define VL53LX_PREV_SHADOW_RESULT__SPARE_2_SD1 0x0EF8\n+#define VL53LX_PREV_SHADOW_RESULT__SPARE_2_SD1_HI 0x0EF8\n+#define VL53LX_PREV_SHADOW_RESULT__SPARE_2_SD1_LO 0x0EF9\n+#define VL53LX_PREV_SHADOW_RESULT__SPARE_3_SD1 0x0EFA\n+#define VL53LX_PREV_SHADOW_RESULT__SPARE_3_SD1_HI 0x0EFA\n+#define VL53LX_PREV_SHADOW_RESULT__SPARE_3_SD1_LO 0x0EFB\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x0EFC\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x0EFC\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x0EFD\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x0EFE\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x0EFF\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x0F00\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x0F00\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x0F01\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x0F02\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x0F03\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x0F04\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x0F04\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x0F05\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x0F06\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x0F07\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x0F08\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x0F08\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x0F09\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x0F0A\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x0F0B\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x0F0C\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x0F0C\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x0F0D\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x0F0E\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x0F0F\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x0F10\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x0F10\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x0F11\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x0F12\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x0F13\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x0F14\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x0F14\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x0F15\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x0F16\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x0F17\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x0F18\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x0F18\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x0F19\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x0F1A\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x0F1B\n+#define VL53LX_PREV_SHADOW_RESULT_CORE__SPARE_0 0x0F1C\n+#define VL53LX_RESULT__DEBUG_STATUS 0x0F20\n+#define VL53LX_RESULT__DEBUG_STAGE 0x0F21\n+#define VL53LX_GPH__SYSTEM__THRESH_RATE_HIGH 0x0F24\n+#define VL53LX_GPH__SYSTEM__THRESH_RATE_HIGH_HI 0x0F24\n+#define VL53LX_GPH__SYSTEM__THRESH_RATE_HIGH_LO 0x0F25\n+#define VL53LX_GPH__SYSTEM__THRESH_RATE_LOW 0x0F26\n+#define VL53LX_GPH__SYSTEM__THRESH_RATE_LOW_HI 0x0F26\n+#define VL53LX_GPH__SYSTEM__THRESH_RATE_LOW_LO 0x0F27\n+#define VL53LX_GPH__SYSTEM__INTERRUPT_CONFIG_GPIO 0x0F28\n+#define VL53LX_GPH__DSS_CONFIG__ROI_MODE_CONTROL 0x0F2F\n+#define VL53LX_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT 0x0F30\n+#define VL53LX_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_HI 0x0F30\n+#define VL53LX_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_LO 0x0F31\n+#define VL53LX_GPH__DSS_CONFIG__MANUAL_BLOCK_SELECT 0x0F32\n+#define VL53LX_GPH__DSS_CONFIG__MAX_SPADS_LIMIT 0x0F33\n+#define VL53LX_GPH__DSS_CONFIG__MIN_SPADS_LIMIT 0x0F34\n+#define VL53LX_GPH__MM_CONFIG__TIMEOUT_MACROP_A_HI 0x0F36\n+#define VL53LX_GPH__MM_CONFIG__TIMEOUT_MACROP_A_LO 0x0F37\n+#define VL53LX_GPH__MM_CONFIG__TIMEOUT_MACROP_B_HI 0x0F38\n+#define VL53LX_GPH__MM_CONFIG__TIMEOUT_MACROP_B_LO 0x0F39\n+#define VL53LX_GPH__RANGE_CONFIG__TIMEOUT_MACROP_A_HI 0x0F3A\n+#define VL53LX_GPH__RANGE_CONFIG__TIMEOUT_MACROP_A_LO 0x0F3B\n+#define VL53LX_GPH__RANGE_CONFIG__VCSEL_PERIOD_A 0x0F3C\n+#define VL53LX_GPH__RANGE_CONFIG__VCSEL_PERIOD_B 0x0F3D\n+#define VL53LX_GPH__RANGE_CONFIG__TIMEOUT_MACROP_B_HI 0x0F3E\n+#define VL53LX_GPH__RANGE_CONFIG__TIMEOUT_MACROP_B_LO 0x0F3F\n+#define VL53LX_GPH__RANGE_CONFIG__SIGMA_THRESH 0x0F40\n+#define VL53LX_GPH__RANGE_CONFIG__SIGMA_THRESH_HI 0x0F40\n+#define VL53LX_GPH__RANGE_CONFIG__SIGMA_THRESH_LO 0x0F41\n+#define VL53LX_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS 0x0F42\n+#define VL53LX_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI 0x0F42\n+#define VL53LX_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO 0x0F43\n+#define VL53LX_GPH__RANGE_CONFIG__VALID_PHASE_LOW 0x0F44\n+#define VL53LX_GPH__RANGE_CONFIG__VALID_PHASE_HIGH 0x0F45\n+#define VL53LX_FIRMWARE__INTERNAL_STREAM_COUNT_DIV 0x0F46\n+#define VL53LX_FIRMWARE__INTERNAL_STREAM_COUNTER_VAL 0x0F47\n+#define VL53LX_DSS_CALC__ROI_CTRL 0x0F54\n+#define VL53LX_DSS_CALC__SPARE_1 0x0F55\n+#define VL53LX_DSS_CALC__SPARE_2 0x0F56\n+#define VL53LX_DSS_CALC__SPARE_3 0x0F57\n+#define VL53LX_DSS_CALC__SPARE_4 0x0F58\n+#define VL53LX_DSS_CALC__SPARE_5 0x0F59\n+#define VL53LX_DSS_CALC__SPARE_6 0x0F5A\n+#define VL53LX_DSS_CALC__SPARE_7 0x0F5B\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_0 0x0F5C\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_1 0x0F5D\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_2 0x0F5E\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_3 0x0F5F\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_4 0x0F60\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_5 0x0F61\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_6 0x0F62\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_7 0x0F63\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_8 0x0F64\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_9 0x0F65\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_10 0x0F66\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_11 0x0F67\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_12 0x0F68\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_13 0x0F69\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_14 0x0F6A\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_15 0x0F6B\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_16 0x0F6C\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_17 0x0F6D\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_18 0x0F6E\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_19 0x0F6F\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_20 0x0F70\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_21 0x0F71\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_22 0x0F72\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_23 0x0F73\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_24 0x0F74\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_25 0x0F75\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_26 0x0F76\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_27 0x0F77\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_28 0x0F78\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_29 0x0F79\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_30 0x0F7A\n+#define VL53LX_DSS_CALC__USER_ROI_SPAD_EN_31 0x0F7B\n+#define VL53LX_DSS_CALC__USER_ROI_0 0x0F7C\n+#define VL53LX_DSS_CALC__USER_ROI_1 0x0F7D\n+#define VL53LX_DSS_CALC__MODE_ROI_0 0x0F7E\n+#define VL53LX_DSS_CALC__MODE_ROI_1 0x0F7F\n+#define VL53LX_SIGMA_ESTIMATOR_CALC__SPARE_0 0x0F80\n+#define VL53LX_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS 0x0F82\n+#define VL53LX_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS_HI 0x0F82\n+#define VL53LX_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS_LO 0x0F83\n+#define VL53LX_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF 0x0F84\n+#define VL53LX_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_3 0x0F84\n+#define VL53LX_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_2 0x0F85\n+#define VL53LX_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_1 0x0F86\n+#define VL53LX_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_0 0x0F87\n+#define VL53LX_PHASECAL_RESULT__PHASE_OUTPUT_REF 0x0F88\n+#define VL53LX_PHASECAL_RESULT__PHASE_OUTPUT_REF_HI 0x0F88\n+#define VL53LX_PHASECAL_RESULT__PHASE_OUTPUT_REF_LO 0x0F89\n+#define VL53LX_DSS_RESULT__TOTAL_RATE_PER_SPAD 0x0F8A\n+#define VL53LX_DSS_RESULT__TOTAL_RATE_PER_SPAD_HI 0x0F8A\n+#define VL53LX_DSS_RESULT__TOTAL_RATE_PER_SPAD_LO 0x0F8B\n+#define VL53LX_DSS_RESULT__ENABLED_BLOCKS 0x0F8C\n+#define VL53LX_DSS_RESULT__NUM_REQUESTED_SPADS 0x0F8E\n+#define VL53LX_DSS_RESULT__NUM_REQUESTED_SPADS_HI 0x0F8E\n+#define VL53LX_DSS_RESULT__NUM_REQUESTED_SPADS_LO 0x0F8F\n+#define VL53LX_MM_RESULT__INNER_INTERSECTION_RATE 0x0F92\n+#define VL53LX_MM_RESULT__INNER_INTERSECTION_RATE_HI 0x0F92\n+#define VL53LX_MM_RESULT__INNER_INTERSECTION_RATE_LO 0x0F93\n+#define VL53LX_MM_RESULT__OUTER_COMPLEMENT_RATE 0x0F94\n+#define VL53LX_MM_RESULT__OUTER_COMPLEMENT_RATE_HI 0x0F94\n+#define VL53LX_MM_RESULT__OUTER_COMPLEMENT_RATE_LO 0x0F95\n+#define VL53LX_MM_RESULT__TOTAL_OFFSET 0x0F96\n+#define VL53LX_MM_RESULT__TOTAL_OFFSET_HI 0x0F96\n+#define VL53LX_MM_RESULT__TOTAL_OFFSET_LO 0x0F97\n+#define VL53LX_XTALK_CALC__XTALK_FOR_ENABLED_SPADS 0x0F98\n+#define VL53LX_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_3 0x0F98\n+#define VL53LX_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_2 0x0F99\n+#define VL53LX_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_1 0x0F9A\n+#define VL53LX_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_0 0x0F9B\n+#define VL53LX_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS 0x0F9C\n+#define VL53LX_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_3 0x0F9C\n+#define VL53LX_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_2 0x0F9D\n+#define VL53LX_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_1 0x0F9E\n+#define VL53LX_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_0 0x0F9F\n+#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS 0x0FA0\n+#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_3 0x0FA0\n+#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_2 0x0FA1\n+#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_1 0x0FA2\n+#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_0 0x0FA3\n+#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS 0x0FA4\n+#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_3 0x0FA4\n+#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_2 0x0FA5\n+#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_1 0x0FA6\n+#define VL53LX_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_0 0x0FA7\n+#define VL53LX_RANGE_RESULT__ACCUM_PHASE 0x0FA8\n+#define VL53LX_RANGE_RESULT__ACCUM_PHASE_3 0x0FA8\n+#define VL53LX_RANGE_RESULT__ACCUM_PHASE_2 0x0FA9\n+#define VL53LX_RANGE_RESULT__ACCUM_PHASE_1 0x0FAA\n+#define VL53LX_RANGE_RESULT__ACCUM_PHASE_0 0x0FAB\n+#define VL53LX_RANGE_RESULT__OFFSET_CORRECTED_RANGE 0x0FAC\n+#define VL53LX_RANGE_RESULT__OFFSET_CORRECTED_RANGE_HI 0x0FAC\n+#define VL53LX_RANGE_RESULT__OFFSET_CORRECTED_RANGE_LO 0x0FAD\n+#define VL53LX_SHADOW_PHASECAL_RESULT__VCSEL_START 0x0FAE\n+#define VL53LX_SHADOW_RESULT__INTERRUPT_STATUS 0x0FB0\n+#define VL53LX_SHADOW_RESULT__RANGE_STATUS 0x0FB1\n+#define VL53LX_SHADOW_RESULT__REPORT_STATUS 0x0FB2\n+#define VL53LX_SHADOW_RESULT__STREAM_COUNT 0x0FB3\n+#define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FB4\n+#define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FB4\n+#define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FB5\n+#define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x0FB6\n+#define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0FB6\n+#define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0FB7\n+#define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0FB8\n+#define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0FB8\n+#define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0FB9\n+#define VL53LX_SHADOW_RESULT__SIGMA_SD0 0x0FBA\n+#define VL53LX_SHADOW_RESULT__SIGMA_SD0_HI 0x0FBA\n+#define VL53LX_SHADOW_RESULT__SIGMA_SD0_LO 0x0FBB\n+#define VL53LX_SHADOW_RESULT__PHASE_SD0 0x0FBC\n+#define VL53LX_SHADOW_RESULT__PHASE_SD0_HI 0x0FBC\n+#define VL53LX_SHADOW_RESULT__PHASE_SD0_LO 0x0FBD\n+#define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0FBE\n+#define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0FBE\n+#define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0FBF\n+#define VL53LX_SHPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0FC0\n+#define VL53LX_SHPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0FC0\n+#define VL53LX_SHPEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0FC1\n+#define VL53LX_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FC2\n+#define VL53LX_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FC2\n+#define VL53LX_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FC3\n+#define VL53LX_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FC4\n+#define VL53LX_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FC4\n+#define VL53LX_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FC5\n+#define VL53LX_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x0FC6\n+#define VL53LX_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0FC6\n+#define VL53LX_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0FC7\n+#define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x0FC8\n+#define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x0FC8\n+#define VL53LX_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x0FC9\n+#define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x0FCA\n+#define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x0FCA\n+#define VL53LX_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x0FCB\n+#define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x0FCC\n+#define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x0FCC\n+#define VL53LX_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x0FCD\n+#define VL53LX_SHADOW_RESULT__SIGMA_SD1 0x0FCE\n+#define VL53LX_SHADOW_RESULT__SIGMA_SD1_HI 0x0FCE\n+#define VL53LX_SHADOW_RESULT__SIGMA_SD1_LO 0x0FCF\n+#define VL53LX_SHADOW_RESULT__PHASE_SD1 0x0FD0\n+#define VL53LX_SHADOW_RESULT__PHASE_SD1_HI 0x0FD0\n+#define VL53LX_SHADOW_RESULT__PHASE_SD1_LO 0x0FD1\n+#define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x0FD2\n+#define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x0FD2\n+#define VL53LX_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x0FD3\n+#define VL53LX_SHADOW_RESULT__SPARE_0_SD1 0x0FD4\n+#define VL53LX_SHADOW_RESULT__SPARE_0_SD1_HI 0x0FD4\n+#define VL53LX_SHADOW_RESULT__SPARE_0_SD1_LO 0x0FD5\n+#define VL53LX_SHADOW_RESULT__SPARE_1_SD1 0x0FD6\n+#define VL53LX_SHADOW_RESULT__SPARE_1_SD1_HI 0x0FD6\n+#define VL53LX_SHADOW_RESULT__SPARE_1_SD1_LO 0x0FD7\n+#define VL53LX_SHADOW_RESULT__SPARE_2_SD1 0x0FD8\n+#define VL53LX_SHADOW_RESULT__SPARE_2_SD1_HI 0x0FD8\n+#define VL53LX_SHADOW_RESULT__SPARE_2_SD1_LO 0x0FD9\n+#define VL53LX_SHADOW_RESULT__SPARE_3_SD1 0x0FDA\n+#define VL53LX_SHADOW_RESULT__THRESH_INFO 0x0FDB\n+#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x0FDC\n+#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x0FDC\n+#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x0FDD\n+#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x0FDE\n+#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x0FDF\n+#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x0FE0\n+#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x0FE0\n+#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x0FE1\n+#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x0FE2\n+#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x0FE3\n+#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x0FE4\n+#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x0FE4\n+#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x0FE5\n+#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x0FE6\n+#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x0FE7\n+#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x0FE8\n+#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x0FE8\n+#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x0FE9\n+#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x0FEA\n+#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x0FEB\n+#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x0FEC\n+#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x0FEC\n+#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x0FED\n+#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x0FEE\n+#define VL53LX_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x0FEF\n+#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x0FF0\n+#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x0FF0\n+#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x0FF1\n+#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x0FF2\n+#define VL53LX_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x0FF3\n+#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x0FF4\n+#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x0FF4\n+#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x0FF5\n+#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x0FF6\n+#define VL53LX_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x0FF7\n+#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x0FF8\n+#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x0FF8\n+#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x0FF9\n+#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x0FFA\n+#define VL53LX_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x0FFB\n+#define VL53LX_SHADOW_RESULT_CORE__SPARE_0 0x0FFC\n+#define VL53LX_SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_HI 0x0FFE\n+#define VL53LX_SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_LO 0x0FFF\n+\n+#define VL53LX_HISTOGRAM_CONFIG__OPCODE_SEQUENCE_0 VL53LX_SIGMA_ESTIMATOR__EFFECTIVE_PULSE_WIDTH_NS\n+#define VL53LX_HISTOGRAM_CONFIG__OPCODE_SEQUENCE_1 VL53LX_SIGMA_ESTIMATOR__EFFECTIVE_AMBIENT_WIDTH_NS\n+#define VL53LX_HISTOGRAM_CONFIG__OPCODE_SEQUENCE_2 VL53LX_SIGMA_ESTIMATOR__SIGMA_REF_MM\n+#define VL53LX_HISTOGRAM_CONFIG__AMB_THRESH_HIGH VL53LX_ALGO__RANGE_IGNORE_THRESHOLD_MCPS\n+\n+#define VL53LX_RESULT__HISTOGRAM_BIN_0_2                               0x008E\n+#define VL53LX_RESULT__HISTOGRAM_BIN_0_1                               0x008F\n+#define VL53LX_RESULT__HISTOGRAM_BIN_0_0                               0x0090\n+#define VL53LX_RESULT__HISTOGRAM_BIN_23_2                              0x00D3\n+#define VL53LX_RESULT__HISTOGRAM_BIN_23_1                              0x00D4\n+#define VL53LX_RESULT__HISTOGRAM_BIN_23_0                              0x00D5\n+#define VL53LX_RESULT__HISTOGRAM_BIN_23_0_MSB                          0x00D9\n+#define VL53LX_RESULT__HISTOGRAM_BIN_23_0_LSB                          0x00DA\n+\n+#define VL53LX_HISTOGRAM_BIN_DATA_I2C_INDEX       VL53LX_RESULT__INTERRUPT_STATUS\n+#define VL53LX_HISTOGRAM_BIN_DATA_I2C_SIZE_BYTES  (VL53LX_RESULT__HISTOGRAM_BIN_23_0_LSB - VL53LX_RESULT__INTERRUPT_STATUS + 1)\n+\n+#define VL53LX_TUNINGPARM_VERSION_DEFAULT \\\n+((uint16_t) 30)\n+#define VL53LX_TUNINGPARM_KEY_TABLE_VERSION_DEFAULT \\\n+((uint16_t) 14)\n+#define VL53LX_TUNINGPARM_LLD_VERSION_DEFAULT \\\n+((uint16_t) 12180)\n+#define VL53LX_TUNINGPARM_HIST_ALGO_SELECT_DEFAULT \\\n+((uint8_t) 4)\n+#define VL53LX_TUNINGPARM_HIST_TARGET_ORDER_DEFAULT \\\n+((uint8_t) 1)\n+#define VL53LX_TUNINGPARM_HIST_FILTER_WOI_0_DEFAULT \\\n+((uint8_t) 1)\n+#define VL53LX_TUNINGPARM_HIST_FILTER_WOI_1_DEFAULT \\\n+((uint8_t) 2)\n+#define VL53LX_TUNINGPARM_HIST_AMB_EST_METHOD_DEFAULT \\\n+((uint8_t) 1)\n+#define VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_0_DEFAULT \\\n+((uint8_t) 80)\n+#define VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_1_DEFAULT \\\n+((uint8_t) 100)\n+#define VL53LX_TUNINGPARM_HIST_MIN_AMB_THRESH_EVENTS_DEFAULT \\\n+((int32_t) 16)\n+#define VL53LX_TUNINGPARM_HIST_AMB_EVENTS_SCALER_DEFAULT \\\n+((uint16_t) 4157)\n+#define VL53LX_TUNINGPARM_HIST_NOISE_THRESHOLD_DEFAULT \\\n+((uint16_t) 50)\n+#define VL53LX_TUNINGPARM_HIST_SIGNAL_TOTAL_EVENTS_LIMIT_DEFAULT \\\n+((int32_t) 100)\n+#define VL53LX_TUNINGPARM_HIST_SIGMA_EST_REF_MM_DEFAULT \\\n+((uint8_t) 1)\n+#define VL53LX_TUNINGPARM_HIST_SIGMA_THRESH_MM_DEFAULT \\\n+((uint16_t) 180)\n+#define VL53LX_TUNINGPARM_HIST_GAIN_FACTOR_DEFAULT \\\n+((uint16_t) 2020)\n+#define VL53LX_TUNINGPARM_CONSISTENCY_HIST_PHASE_TOLERANCE_DEFAULT \\\n+((uint8_t) 8)\n+#define VL53LX_TUNINGPARM_CONSISTENCY_HIST_MIN_MAX_TOLERANCE_MM_DEFAULT \\\n+((uint16_t) 0)\n+#define VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA_DEFAULT \\\n+((uint8_t) 0)\n+#define VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA_MIN_SPAD_LIMIT_DEFAULT \\\n+((uint16_t) 2048)\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_LONG_RANGE_DEFAULT \\\n+((uint8_t) 9)\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_MED_RANGE_DEFAULT \\\n+((uint8_t) 5)\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_SHORT_RANGE_DEFAULT \\\n+((uint8_t) 3)\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_LONG_RANGE_DEFAULT \\\n+((uint8_t) 6)\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_MED_RANGE_DEFAULT \\\n+((uint8_t) 6)\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_SHORT_RANGE_DEFAULT \\\n+((uint8_t) 6)\n+#define VL53LX_TUNINGPARM_XTALK_DETECT_MIN_VALID_RANGE_MM_DEFAULT \\\n+((int16_t) -50)\n+#define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RANGE_MM_DEFAULT \\\n+((int16_t) 50)\n+#define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_SIGMA_MM_DEFAULT \\\n+((uint16_t) 140)\n+#define VL53LX_TUNINGPARM_XTALK_DETECT_MIN_MAX_TOLERANCE_DEFAULT \\\n+((uint16_t) 50)\n+#define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RATE_KCPS_DEFAULT \\\n+((uint16_t) 400)\n+#define VL53LX_TUNINGPARM_XTALK_DETECT_EVENT_SIGMA_DEFAULT \\\n+((uint8_t) 80)\n+#define VL53LX_TUNINGPARM_HIST_XTALK_MARGIN_KCPS_DEFAULT \\\n+((int16_t) 0)\n+#define VL53LX_TUNINGPARM_CONSISTENCY_LITE_PHASE_TOLERANCE_DEFAULT \\\n+((uint8_t) 2)\n+#define VL53LX_TUNINGPARM_PHASECAL_TARGET_DEFAULT \\\n+((uint8_t) 33)\n+#define VL53LX_TUNINGPARM_LITE_CAL_REPEAT_RATE_DEFAULT \\\n+((uint16_t) 0)\n+#define VL53LX_TUNINGPARM_LITE_RANGING_GAIN_FACTOR_DEFAULT \\\n+((uint16_t) 2011)\n+#define VL53LX_TUNINGPARM_LITE_MIN_CLIP_MM_DEFAULT \\\n+((uint8_t) 0)\n+#define VL53LX_TUNINGPARM_LITE_LONG_SIGMA_THRESH_MM_DEFAULT \\\n+((uint16_t) 60)\n+#define VL53LX_TUNINGPARM_LITE_MED_SIGMA_THRESH_MM_DEFAULT \\\n+((uint16_t) 60)\n+#define VL53LX_TUNINGPARM_LITE_SHORT_SIGMA_THRESH_MM_DEFAULT \\\n+((uint16_t) 60)\n+#define VL53LX_TUNINGPARM_LITE_LONG_MIN_COUNT_RATE_RTN_MCPS_DEFAULT \\\n+((uint16_t) 128)\n+#define VL53LX_TUNINGPARM_LITE_MED_MIN_COUNT_RATE_RTN_MCPS_DEFAULT \\\n+((uint16_t) 128)\n+#define VL53LX_TUNINGPARM_LITE_SHORT_MIN_COUNT_RATE_RTN_MCPS_DEFAULT \\\n+((uint16_t) 128)\n+#define VL53LX_TUNINGPARM_LITE_SIGMA_EST_PULSE_WIDTH_DEFAULT \\\n+((uint8_t) 8)\n+#define VL53LX_TUNINGPARM_LITE_SIGMA_EST_AMB_WIDTH_NS_DEFAULT \\\n+((uint8_t) 16)\n+#define VL53LX_TUNINGPARM_LITE_SIGMA_REF_MM_DEFAULT \\\n+((uint8_t) 1)\n+#define VL53LX_TUNINGPARM_LITE_RIT_MULT_DEFAULT \\\n+((uint8_t) 64)\n+#define VL53LX_TUNINGPARM_LITE_SEED_CONFIG_DEFAULT \\\n+((uint8_t) 2)\n+#define VL53LX_TUNINGPARM_LITE_QUANTIFIER_DEFAULT \\\n+((uint8_t) 2)\n+#define VL53LX_TUNINGPARM_LITE_FIRST_ORDER_SELECT_DEFAULT \\\n+((uint8_t) 0)\n+#define VL53LX_TUNINGPARM_LITE_XTALK_MARGIN_KCPS_DEFAULT \\\n+((int16_t) 0)\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_LONG_RANGE_DEFAULT \\\n+((uint8_t) 14)\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_MED_RANGE_DEFAULT \\\n+((uint8_t) 10)\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_SHORT_RANGE_DEFAULT \\\n+((uint8_t) 6)\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_LONG_RANGE_DEFAULT \\\n+((uint8_t) 14)\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_MED_RANGE_DEFAULT \\\n+((uint8_t) 10)\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_SHORT_RANGE_DEFAULT \\\n+((uint8_t) 6)\n+#define VL53LX_TUNINGPARM_TIMED_SEED_CONFIG_DEFAULT \\\n+((uint8_t) 1)\n+#define VL53LX_TUNINGPARM_DMAX_CFG_SIGNAL_THRESH_SIGMA_DEFAULT \\\n+((uint8_t) 32)\n+#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_0_DEFAULT \\\n+((uint16_t) 15)\n+#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_1_DEFAULT \\\n+((uint16_t) 52)\n+#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_2_DEFAULT \\\n+((uint16_t) 200)\n+#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_3_DEFAULT \\\n+((uint16_t) 364)\n+#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_4_DEFAULT \\\n+((uint16_t) 400)\n+#define VL53LX_TUNINGPARM_VHV_LOOPBOUND_DEFAULT \\\n+((uint8_t) 129)\n+#define VL53LX_TUNINGPARM_REFSPADCHAR_DEVICE_TEST_MODE_DEFAULT \\\n+((uint8_t) 8)\n+#define VL53LX_TUNINGPARM_REFSPADCHAR_VCSEL_PERIOD_DEFAULT \\\n+((uint8_t) 11)\n+#define VL53LX_TUNINGPARM_REFSPADCHAR_PHASECAL_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 1000)\n+#define VL53LX_TUNINGPARM_REFSPADCHAR_TARGET_COUNT_RATE_MCPS_DEFAULT \\\n+((uint16_t) 2560)\n+#define VL53LX_TUNINGPARM_REFSPADCHAR_MIN_COUNTRATE_LIMIT_MCPS_DEFAULT \\\n+((uint16_t) 1280)\n+#define VL53LX_TUNINGPARM_REFSPADCHAR_MAX_COUNTRATE_LIMIT_MCPS_DEFAULT \\\n+((uint16_t) 5120)\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_NUM_OF_SAMPLES_DEFAULT \\\n+((uint8_t) 7)\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_MIN_FILTER_THRESH_MM_DEFAULT \\\n+((int16_t) -70)\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_FILTER_THRESH_MM_DEFAULT \\\n+((int16_t) 70)\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_RATE_MCPS_DEFAULT \\\n+((uint16_t) 5120)\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_PHASECAL_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 15000)\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_VALID_RATE_KCPS_DEFAULT \\\n+((uint16_t) 640)\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_SIGMA_THRESHOLD_MM_DEFAULT \\\n+((uint16_t) 140)\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 2000)\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_BIN_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 10000)\n+#define VL53LX_TUNINGPARM_OFFSET_CAL_DSS_RATE_MCPS_DEFAULT \\\n+((uint16_t) 2560)\n+#define VL53LX_TUNINGPARM_OFFSET_CAL_PHASECAL_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 15000)\n+#define VL53LX_TUNINGPARM_OFFSET_CAL_MM_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 13000)\n+#define VL53LX_TUNINGPARM_OFFSET_CAL_RANGE_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 13000)\n+#define VL53LX_TUNINGPARM_OFFSET_CAL_PRE_SAMPLES_DEFAULT \\\n+((uint8_t) 8)\n+#define VL53LX_TUNINGPARM_OFFSET_CAL_MM1_SAMPLES_DEFAULT \\\n+((uint8_t) 40)\n+#define VL53LX_TUNINGPARM_OFFSET_CAL_MM2_SAMPLES_DEFAULT \\\n+((uint8_t) 9)\n+#define VL53LX_TUNINGPARM_ZONE_CAL_DSS_RATE_MCPS_DEFAULT \\\n+((uint16_t) 5120)\n+#define VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 15000)\n+#define VL53LX_TUNINGPARM_ZONE_CAL_DSS_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 2000)\n+#define VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_NUM_SAMPLES_DEFAULT \\\n+((uint16_t) 16)\n+#define VL53LX_TUNINGPARM_ZONE_CAL_RANGE_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 1000)\n+#define VL53LX_TUNINGPARM_ZONE_CAL_ZONE_NUM_SAMPLES_DEFAULT \\\n+((uint16_t) 8)\n+#define VL53LX_TUNINGPARM_SPADMAP_VCSEL_PERIOD_DEFAULT \\\n+((uint8_t) 18)\n+#define VL53LX_TUNINGPARM_SPADMAP_VCSEL_START_DEFAULT \\\n+((uint8_t) 15)\n+#define VL53LX_TUNINGPARM_SPADMAP_RATE_LIMIT_MCPS_DEFAULT \\\n+((uint16_t) 12)\n+#define VL53LX_TUNINGPARM_LITE_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT \\\n+((uint16_t) 2560)\n+#define VL53LX_TUNINGPARM_RANGING_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT \\\n+((uint16_t) 2560)\n+#define VL53LX_TUNINGPARM_MZ_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT \\\n+((uint16_t) 5120)\n+#define VL53LX_TUNINGPARM_TIMED_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT \\\n+((uint16_t) 2560)\n+#define VL53LX_TUNINGPARM_LITE_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 1000)\n+#define VL53LX_TUNINGPARM_RANGING_LONG_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 15000)\n+#define VL53LX_TUNINGPARM_RANGING_MED_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 15000)\n+#define VL53LX_TUNINGPARM_RANGING_SHORT_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 15000)\n+#define VL53LX_TUNINGPARM_MZ_LONG_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 15000)\n+#define VL53LX_TUNINGPARM_MZ_MED_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 9000)\n+#define VL53LX_TUNINGPARM_MZ_SHORT_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 6000)\n+#define VL53LX_TUNINGPARM_TIMED_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 1000)\n+#define VL53LX_TUNINGPARM_LITE_MM_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 2000)\n+#define VL53LX_TUNINGPARM_RANGING_MM_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 2000)\n+#define VL53LX_TUNINGPARM_MZ_MM_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 2000)\n+#define VL53LX_TUNINGPARM_TIMED_MM_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 2000)\n+#define VL53LX_TUNINGPARM_LITE_RANGE_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 63000)\n+#define VL53LX_TUNINGPARM_RANGING_RANGE_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 2500)\n+#define VL53LX_TUNINGPARM_MZ_RANGE_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 2500)\n+#define VL53LX_TUNINGPARM_TIMED_RANGE_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 13000)\n+#define VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_MARGIN_DEFAULT \\\n+((uint16_t) 0)\n+#define VL53LX_TUNINGPARM_DYNXTALK_NOISE_MARGIN_DEFAULT \\\n+((uint32_t) 100)\n+#define VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT_DEFAULT \\\n+((uint32_t) 0)\n+#define VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT_HI_DEFAULT \\\n+((uint8_t) 0)\n+#define VL53LX_TUNINGPARM_DYNXTALK_SAMPLE_LIMIT_DEFAULT \\\n+((uint32_t) 200)\n+#define VL53LX_TUNINGPARM_DYNXTALK_SINGLE_XTALK_DELTA_DEFAULT \\\n+((uint32_t) 2048)\n+#define VL53LX_TUNINGPARM_DYNXTALK_AVERAGED_XTALK_DELTA_DEFAULT \\\n+((uint32_t) 308)\n+#define VL53LX_TUNINGPARM_DYNXTALK_CLIP_LIMIT_DEFAULT \\\n+((uint32_t) 10240)\n+#define VL53LX_TUNINGPARM_DYNXTALK_SCALER_CALC_METHOD_DEFAULT \\\n+((uint8_t) 0)\n+#define VL53LX_TUNINGPARM_DYNXTALK_XGRADIENT_SCALER_DEFAULT \\\n+((int16_t) 256)\n+#define VL53LX_TUNINGPARM_DYNXTALK_YGRADIENT_SCALER_DEFAULT \\\n+((int16_t) 256)\n+#define VL53LX_TUNINGPARM_DYNXTALK_USER_SCALER_SET_DEFAULT \\\n+((uint8_t) 0)\n+#define VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_COR_SINGLE_APPLY_DEFAULT \\\n+((uint8_t) 0)\n+#define VL53LX_TUNINGPARM_DYNXTALK_XTALK_AMB_THRESHOLD_DEFAULT \\\n+((uint32_t) 128)\n+#define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_AMB_THRESHOLD_KCPS_DEFAULT \\\n+((uint32_t) 57671680)\n+#define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_SAMPLE_LIMIT_DEFAULT \\\n+((uint32_t) 40)\n+#define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_XTALK_OFFSET_KCPS_DEFAULT \\\n+((uint32_t) 410)\n+#define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_MIN_RANGE_MM_DEFAULT \\\n+((uint16_t) 900)\n+#define VL53LX_TUNINGPARM_LOWPOWERAUTO_VHV_LOOP_BOUND_DEFAULT \\\n+((uint8_t) 3)\n+#define VL53LX_TUNINGPARM_LOWPOWERAUTO_MM_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 1)\n+#define VL53LX_TUNINGPARM_LOWPOWERAUTO_RANGE_CONFIG_TIMEOUT_US_DEFAULT \\\n+((uint32_t) 8000)\n+#define VL53LX_TUNINGPARM_VERY_SHORT_DSS_RATE_MCPS_DEFAULT \\\n+((uint16_t) 10240)\n+#define VL53LX_TUNINGPARM_PHASECAL_PATCH_POWER_DEFAULT \\\n+((uint32_t) 1)\n+#define VL53LX_TUNINGPARM_HIST_MERGE_DEFAULT \\\n+((uint8_t) 1)\n+#define VL53LX_TUNINGPARM_RESET_MERGE_THRESHOLD_DEFAULT \\\n+((uint32_t) 15000)\n+#define VL53LX_TUNINGPARM_HIST_MERGE_MAX_SIZE_DEFAULT \\\n+((uint8_t) 6)\n+#define VL53LX_TUNINGPARM_DYNXTALK_MAX_SMUDGE_FACTOR_DEFAULT \\\n+((uint32_t) 2000)\n+#define VL53LX_TUNINGPARM_UWR_ENABLE_DEFAULT \\\n+((uint8_t) 1)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_1_MIN_DEFAULT \\\n+((int16_t) 2000)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_1_MAX_DEFAULT \\\n+((int16_t) 2750)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_2_MIN_DEFAULT \\\n+((int16_t) 250)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_2_MAX_DEFAULT \\\n+((int16_t) 1000)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_3_MIN_DEFAULT \\\n+((int16_t) 1250)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_3_MAX_DEFAULT \\\n+((int16_t) 1750)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_4_MIN_DEFAULT \\\n+((int16_t) 1250)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_4_MAX_DEFAULT \\\n+((int16_t) 1750)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_5_MIN_DEFAULT \\\n+((int16_t) -200)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_5_MAX_DEFAULT \\\n+((int16_t) 200)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_1_RANGEA_DEFAULT \\\n+((int16_t) 2360)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_1_RANGEB_DEFAULT \\\n+((int16_t) 0)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_2_RANGEA_DEFAULT \\\n+((int16_t) 2375)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_2_RANGEB_DEFAULT \\\n+((int16_t) 3125)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_3_RANGEA_DEFAULT \\\n+((int16_t) 4720)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_3_RANGEB_DEFAULT \\\n+((int16_t) 3230)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_4_RANGEA_DEFAULT \\\n+((int16_t) 4750)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_4_RANGEB_DEFAULT \\\n+((int16_t) 6350)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_5_RANGEA_DEFAULT \\\n+((int16_t) 0)\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_5_RANGEB_DEFAULT \\\n+((int16_t) 0)\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_1_MIN_DEFAULT \\\n+((int16_t) 250)\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_1_MAX_DEFAULT \\\n+((int16_t) 1250)\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_2_MIN_DEFAULT \\\n+((int16_t) 3250)\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_2_MAX_DEFAULT \\\n+((int16_t) 4500)\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_3_MIN_DEFAULT \\\n+((int16_t) -200)\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_3_MAX_DEFAULT \\\n+((int16_t) 200)\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_4_MIN_DEFAULT \\\n+((int16_t) 0)\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_4_MAX_DEFAULT \\\n+((int16_t) 0)\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_5_MIN_DEFAULT \\\n+((int16_t) 0)\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_5_MAX_DEFAULT \\\n+((int16_t) 0)\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_1_RANGEA_DEFAULT \\\n+((int16_t) 3850)\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_1_RANGEB_DEFAULT \\\n+((int16_t) 4600)\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_2_RANGEA_DEFAULT \\\n+((int16_t) 3850)\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_2_RANGEB_DEFAULT \\\n+((int16_t) 0)\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_3_RANGEA_DEFAULT \\\n+((int16_t) 0)\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_3_RANGEB_DEFAULT \\\n+((int16_t) 0)\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_4_RANGEA_DEFAULT \\\n+((int16_t) 0)\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_4_RANGEB_DEFAULT \\\n+((int16_t) 0)\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_5_RANGEA_DEFAULT \\\n+((int16_t) 0)\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_5_RANGEB_DEFAULT \\\n+((int16_t) 0)\n+\n+#define VL53LX_IOCTL_START\t\t\t_IO('p', 0x01)\n+\n+#define VL53LX_IOCTL_STOP\t\t\t_IO('p', 0x05)\n+\n+#define VL53LX_IOCTL_PARAMETER \\\n+\t_IOWR('p', 0x0d, struct stmvl53lx_parameter)\n+\n+#define VL53LX_IOCTL_ROI\\\n+\t_IOWR('p', 0x0e, struct stmvl53lx_ioctl_roi_t)\n+\n+#define VL53LX_IOCTL_MZ_DATA\\\n+\t_IOR('p', 0x0f, VL53LX_MultiRangingData_t)\n+\n+#define VL53LX_IOCTL_MZ_DATA_BLOCKING\\\n+\t_IOR('p', 0x11, VL53LX_MultiRangingData_t)\n+\n+#define VL53LX_IOCTL_CALIBRATION_DATA\\\n+\t_IOWR('p', 0x12, struct stmvl53lx_ioctl_calibration_data_t)\n+\n+#define VL53LX_IOCTL_PERFORM_CALIBRATION\\\n+\t_IOW('p', 0x13, struct stmvl53lx_ioctl_perform_calibration_t)\n+\n+\n+\n+struct stmvl53lx_register {\n+\tuint32_t is_read;\n+\tuint32_t index;\n+\tuint32_t cnt;\n+\tint32_t status;\n+\tunion reg_data_t {\n+\t\tuint8_t b;\n+\t\tuint16_t w;\n+\t\tuint32_t dw;\n+\t\tuint8_t bytes[256];\n+\t} data;\n+};\n+\n+struct stmvl53lx_register_flexi {\n+\tuint32_t is_read;\n+\tuint32_t index;\n+\tuint32_t cnt;\n+\tint32_t status;\n+\tuint8_t data[];\n+};\n+\n+#define VL53LX_IOCTL_REGISTER   _IOWR('p', 0x0c, struct stmvl53lx_register)\n+\n+#define VL53LX_IOCTL_MZ_DATA_ADDITIONAL\\\n+\t\t\t_IOR('p', 0x15, struct stmvl53lx_data_with_additional)\n+\n+#define VL53LX_IOCTL_MZ_DATA_ADDITIONAL_BLOCKING\\\n+\t\t\t_IOR('p', 0x16, struct stmvl53lx_data_with_additional)\n+\n+#define VL53LX_NVM_POWER_UP_DELAY_US             50\n+#define VL53LX_NVM_READ_TRIGGER_DELAY_US          5\n+#define VL53LX_NVM__IDENTIFICATION__MODEL_ID 0x0008\n+#define VL53LX_NVM__IDENTIFICATION__MODULE_TYPE 0x000C\n+#define VL53LX_NVM__IDENTIFICATION__REVISION_ID 0x000D\n+#define VL53LX_NVM__IDENTIFICATION__MODULE_ID 0x000E\n+#define VL53LX_NVM__I2C_VALID 0x0010\n+#define VL53LX_NVM__I2C_SLAVE__DEVICE_ADDRESS 0x0011\n+#define VL53LX_NVM__EWS__OSC_MEASURED__FAST_OSC_FREQUENCY 0x0014\n+#define VL53LX_NVM__EWS__FAST_OSC_TRIM_MAX 0x0016\n+#define VL53LX_NVM__EWS__FAST_OSC_FREQ_SET 0x0017\n+#define VL53LX_NVM__EWS__SLOW_OSC_CALIBRATION 0x0018\n+#define VL53LX_NVM__FMT__OSC_MEASURED__FAST_OSC_FREQUENCY 0x001C\n+#define VL53LX_NVM__FMT__FAST_OSC_TRIM_MAX 0x001E\n+#define VL53LX_NVM__FMT__FAST_OSC_FREQ_SET 0x001F\n+#define VL53LX_NVM__FMT__SLOW_OSC_CALIBRATION 0x0020\n+#define VL53LX_NVM__VHV_CONFIG_UNLOCK 0x0028\n+#define VL53LX_NVM__REF_SELVDDPIX 0x0029\n+#define VL53LX_NVM__REF_SELVQUENCH 0x002A\n+#define VL53LX_NVM__REGAVDD1V2_SEL_REGDVDD1V2_SEL 0x002B\n+#define VL53LX_NVM__VHV_CONFIG__TIMEOUT_MACROP_LOOP_BOUND 0x002C\n+#define VL53LX_NVM__VHV_CONFIG__COUNT_THRESH 0x002D\n+#define VL53LX_NVM__VHV_CONFIG__OFFSET 0x002E\n+#define VL53LX_NVM__VHV_CONFIG__INIT 0x002F\n+#define VL53LX_NVM__LASER_SAFETY__VCSEL_TRIM_LL 0x0030\n+#define VL53LX_NVM__LASER_SAFETY__VCSEL_SELION_LL 0x0031\n+#define VL53LX_NVM__LASER_SAFETY__VCSEL_SELION_MAX_LL 0x0032\n+#define VL53LX_NVM__LASER_SAFETY__MULT_LL 0x0034\n+#define VL53LX_NVM__LASER_SAFETY__CLIP_LL 0x0035\n+#define VL53LX_NVM__LASER_SAFETY__VCSEL_TRIM_LD 0x0038\n+#define VL53LX_NVM__LASER_SAFETY__VCSEL_SELION_LD 0x0039\n+#define VL53LX_NVM__LASER_SAFETY__VCSEL_SELION_MAX_LD 0x003A\n+#define VL53LX_NVM__LASER_SAFETY__MULT_LD 0x003C\n+#define VL53LX_NVM__LASER_SAFETY__CLIP_LD 0x003D\n+#define VL53LX_NVM__LASER_SAFETY_LOCK_BYTE 0x0040\n+#define VL53LX_NVM__LASER_SAFETY_UNLOCK_BYTE 0x0044\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_0_ 0x0048\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_1_ 0x0049\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_2_ 0x004A\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_3_ 0x004B\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_4_ 0x004C\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_5_ 0x004D\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_6_ 0x004E\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_7_ 0x004F\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_8_ 0x0050\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_9_ 0x0051\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_10_ 0x0052\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_11_ 0x0053\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_12_ 0x0054\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_13_ 0x0055\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_14_ 0x0056\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_15_ 0x0057\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_16_ 0x0058\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_17_ 0x0059\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_18_ 0x005A\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_19_ 0x005B\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_20_ 0x005C\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_21_ 0x005D\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_22_ 0x005E\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_23_ 0x005F\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_24_ 0x0060\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_25_ 0x0061\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_26_ 0x0062\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_27_ 0x0063\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_28_ 0x0064\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_29_ 0x0065\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_30_ 0x0066\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_RTN_31_ 0x0067\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_0_ 0x0068\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_1_ 0x0069\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_2_ 0x006A\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_3_ 0x006B\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_4_ 0x006C\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC1_5_ 0x006D\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_0_ 0x0070\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_1_ 0x0071\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_2_ 0x0072\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_3_ 0x0073\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_4_ 0x0074\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC2_5_ 0x0075\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_0_ 0x0078\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_1_ 0x0079\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_2_ 0x007A\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_3_ 0x007B\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_4_ 0x007C\n+#define VL53LX_NVM__EWS__SPAD_ENABLES_REF__LOC3_5_ 0x007D\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_0_ 0x0080\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_1_ 0x0081\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_2_ 0x0082\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_3_ 0x0083\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_4_ 0x0084\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_5_ 0x0085\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_6_ 0x0086\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_7_ 0x0087\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_8_ 0x0088\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_9_ 0x0089\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_10_ 0x008A\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_11_ 0x008B\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_12_ 0x008C\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_13_ 0x008D\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_14_ 0x008E\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_15_ 0x008F\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_16_ 0x0090\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_17_ 0x0091\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_18_ 0x0092\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_19_ 0x0093\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_20_ 0x0094\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_21_ 0x0095\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_22_ 0x0096\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_23_ 0x0097\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_24_ 0x0098\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_25_ 0x0099\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_26_ 0x009A\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_27_ 0x009B\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_28_ 0x009C\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_29_ 0x009D\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_30_ 0x009E\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_RTN_31_ 0x009F\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_0_ 0x00A0\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_1_ 0x00A1\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_2_ 0x00A2\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_3_ 0x00A3\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_4_ 0x00A4\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC1_5_ 0x00A5\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_0_ 0x00A8\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_1_ 0x00A9\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_2_ 0x00AA\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_3_ 0x00AB\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_4_ 0x00AC\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC2_5_ 0x00AD\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_0_ 0x00B0\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_1_ 0x00B1\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_2_ 0x00B2\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_3_ 0x00B3\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_4_ 0x00B4\n+#define VL53LX_NVM__FMT__SPAD_ENABLES_REF__LOC3_5_ 0x00B5\n+#define VL53LX_NVM__FMT__ROI_CONFIG__MODE_ROI_CENTRE_SPAD 0x00B8\n+#define VL53LX_NVM__FMT__ROI_CONFIG__MODE_ROI_XY_SIZE 0x00B9\n+#define VL53LX_NVM__FMT__REF_SPAD_APPLY__NUM_REQUESTED_REF_SPAD 0x00BC\n+#define VL53LX_NVM__FMT__REF_SPAD_MAN__REF_LOCATION 0x00BD\n+#define VL53LX_NVM__FMT__MM_CONFIG__INNER_OFFSET_MM 0x00C0\n+#define VL53LX_NVM__FMT__MM_CONFIG__OUTER_OFFSET_MM 0x00C2\n+#define VL53LX_NVM__FMT__ALGO__PART_TO_PART_RANGE_OFFSET_MM 0x00C4\n+#define VL53LX_NVM__FMT__ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS 0x00C8\n+#define VL53LX_NVM__FMT__ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS 0x00CA\n+#define VL53LX_NVM__FMT__ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS 0x00CC\n+#define VL53LX_NVM__FMT__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_0 0x00CE\n+#define VL53LX_NVM__FMT__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_1 0x00CF\n+#define VL53LX_NVM__CUSTOMER_NVM_SPACE_PROGRAMMED 0x00E0\n+#define VL53LX_NVM__CUST__I2C_SLAVE__DEVICE_ADDRESS 0x00E4\n+#define VL53LX_NVM__CUST__REF_SPAD_APPLY__NUM_REQUESTED_REF_SPAD 0x00E8\n+#define VL53LX_NVM__CUST__REF_SPAD_MAN__REF_LOCATION 0x00E9\n+#define VL53LX_NVM__CUST__MM_CONFIG__INNER_OFFSET_MM 0x00EC\n+#define VL53LX_NVM__CUST__MM_CONFIG__OUTER_OFFSET_MM 0x00EE\n+#define VL53LX_NVM__CUST__ALGO__PART_TO_PART_RANGE_OFFSET_MM 0x00F0\n+#define VL53LX_NVM__CUST__ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS 0x00F4\n+#define VL53LX_NVM__CUST__ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS 0x00F6\n+#define VL53LX_NVM__CUST__ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS 0x00F8\n+#define VL53LX_NVM__CUST__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_0 0x00FA\n+#define VL53LX_NVM__CUST__SPARE_HOST_CONFIG__NVM_CONFIG_SPARE_1 0x00FB\n+#define VL53LX_NVM__FMT__FGC__BYTE_0 0x01DC\n+#define VL53LX_NVM__FMT__FGC__BYTE_1 0x01DD\n+#define VL53LX_NVM__FMT__FGC__BYTE_2 0x01DE\n+#define VL53LX_NVM__FMT__FGC__BYTE_3 0x01DF\n+#define VL53LX_NVM__FMT__FGC__BYTE_4 0x01E0\n+#define VL53LX_NVM__FMT__FGC__BYTE_5 0x01E1\n+#define VL53LX_NVM__FMT__FGC__BYTE_6 0x01E2\n+#define VL53LX_NVM__FMT__FGC__BYTE_7 0x01E3\n+#define VL53LX_NVM__FMT__FGC__BYTE_8 0x01E4\n+#define VL53LX_NVM__FMT__FGC__BYTE_9 0x01E5\n+#define VL53LX_NVM__FMT__FGC__BYTE_10 0x01E6\n+#define VL53LX_NVM__FMT__FGC__BYTE_11 0x01E7\n+#define VL53LX_NVM__FMT__FGC__BYTE_12 0x01E8\n+#define VL53LX_NVM__FMT__FGC__BYTE_13 0x01E9\n+#define VL53LX_NVM__FMT__FGC__BYTE_14 0x01EA\n+#define VL53LX_NVM__FMT__FGC__BYTE_15 0x01EB\n+#define VL53LX_NVM__FMT__TEST_PROGRAM_MAJOR_MINOR 0x01EC\n+#define VL53LX_NVM__FMT__MAP_MAJOR_MINOR 0x01ED\n+#define VL53LX_NVM__FMT__YEAR_MONTH 0x01EE\n+#define VL53LX_NVM__FMT__DAY_MODULE_DATE_PHASE 0x01EF\n+#define VL53LX_NVM__FMT__TIME 0x01F0\n+#define VL53LX_NVM__FMT__TESTER_ID 0x01F2\n+#define VL53LX_NVM__FMT__SITE_ID 0x01F3\n+#define VL53LX_NVM__EWS__TEST_PROGRAM_MAJOR_MINOR 0x01F4\n+#define VL53LX_NVM__EWS__PROBE_CARD_MAJOR_MINOR 0x01F5\n+#define VL53LX_NVM__EWS__TESTER_ID 0x01F6\n+#define VL53LX_NVM__EWS__LOT__BYTE_0 0x01F8\n+#define VL53LX_NVM__EWS__LOT__BYTE_1 0x01F9\n+#define VL53LX_NVM__EWS__LOT__BYTE_2 0x01FA\n+#define VL53LX_NVM__EWS__LOT__BYTE_3 0x01FB\n+#define VL53LX_NVM__EWS__LOT__BYTE_4 0x01FC\n+#define VL53LX_NVM__EWS__LOT__BYTE_5 0x01FD\n+#define VL53LX_NVM__EWS__WAFER 0x01FD\n+#define VL53LX_NVM__EWS__XCOORD 0x01FE\n+#define VL53LX_NVM__EWS__YCOORD 0x01FF\n+#define VL53LX_NVM__FMT__OPTICAL_CENTRE_DATA_INDEX 0x00B8\n+#define VL53LX_NVM__FMT__OPTICAL_CENTRE_DATA_SIZE      4\n+#define VL53LX_NVM__FMT__CAL_PEAK_RATE_MAP_DATA_INDEX 0x015C\n+#define VL53LX_NVM__FMT__CAL_PEAK_RATE_MAP_DATA_SIZE   56\n+#define VL53LX_NVM__FMT__ADDITIONAL_OFFSET_CAL_DATA_INDEX 0x0194\n+#define VL53LX_NVM__FMT__ADDITIONAL_OFFSET_CAL_DATA_SIZE   8\n+#define VL53LX_NVM__FMT__RANGE_RESULTS__140MM_MM_PRE_RANGE 0x019C\n+#define VL53LX_NVM__FMT__RANGE_RESULTS__140MM_DARK 0x01AC\n+#define VL53LX_NVM__FMT__RANGE_RESULTS__400MM_DARK 0x01BC\n+#define VL53LX_NVM__FMT__RANGE_RESULTS__400MM_AMBIENT 0x01CC\n+#define VL53LX_NVM__FMT__RANGE_RESULTS__SIZE_BYTES         16\n+\n+\n+typedef uint8_t VL53LX_SmudgeCorrectionModes;\n+#define VL53LX_SMUDGE_CORRECTION_NONE       ((VL53LX_SmudgeCorrectionModes)  0)\n+#define VL53LX_SMUDGE_CORRECTION_CONTINUOUS ((VL53LX_SmudgeCorrectionModes)  1)\n+#define VL53LX_SMUDGE_CORRECTION_SINGLE     ((VL53LX_SmudgeCorrectionModes)  2)\n+#define VL53LX_SMUDGE_CORRECTION_DEBUG      ((VL53LX_SmudgeCorrectionModes)  3)\n+\n+typedef uint8_t VL53LX_OffsetCorrectionModes;\n+#define VL53LX_OFFSETCORRECTIONMODE_STANDARD ((VL53LX_OffsetCorrectionModes)  1)\n+#define VL53LX_OFFSETCORRECTIONMODE_PERVCSEL ((VL53LX_OffsetCorrectionModes)  3)\n+\n+typedef int8_t VL53LX_Error;\n+\n+#define VL53LX_ERROR_NONE                              ((VL53LX_Error)  0)\n+#define VL53LX_ERROR_CALIBRATION_WARNING               ((VL53LX_Error) - 1)\n+#define VL53LX_ERROR_MIN_CLIPPED                       ((VL53LX_Error) - 2)\n+#define VL53LX_ERROR_UNDEFINED                         ((VL53LX_Error) - 3)\n+#define VL53LX_ERROR_INVALID_PARAMS                    ((VL53LX_Error) - 4)\n+#define VL53LX_ERROR_NOT_SUPPORTED                     ((VL53LX_Error) - 5)\n+#define VL53LX_ERROR_RANGE_ERROR                       ((VL53LX_Error) - 6)\n+#define VL53LX_ERROR_TIME_OUT                          ((VL53LX_Error) - 7)\n+#define VL53LX_ERROR_MODE_NOT_SUPPORTED                ((VL53LX_Error) - 8)\n+#define VL53LX_ERROR_BUFFER_TOO_SMALL                  ((VL53LX_Error) - 9)\n+#define VL53LX_ERROR_COMMS_BUFFER_TOO_SMALL            ((VL53LX_Error) - 10)\n+#define VL53LX_ERROR_GPIO_NOT_EXISTING                 ((VL53LX_Error) - 11)\n+#define VL53LX_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED  ((VL53LX_Error) - 12)\n+#define VL53LX_ERROR_CONTROL_INTERFACE                 ((VL53LX_Error) - 13)\n+#define VL53LX_ERROR_INVALID_COMMAND                   ((VL53LX_Error) - 14)\n+#define VL53LX_ERROR_DIVISION_BY_ZERO                  ((VL53LX_Error) - 15)\n+#define VL53LX_ERROR_REF_SPAD_INIT                     ((VL53LX_Error) - 16)\n+#define VL53LX_ERROR_GPH_SYNC_CHECK_FAIL               ((VL53LX_Error) - 17)\n+#define VL53LX_ERROR_STREAM_COUNT_CHECK_FAIL           ((VL53LX_Error) - 18)\n+#define VL53LX_ERROR_GPH_ID_CHECK_FAIL                 ((VL53LX_Error) - 19)\n+#define VL53LX_ERROR_ZONE_STREAM_COUNT_CHECK_FAIL      ((VL53LX_Error) - 20)\n+#define VL53LX_ERROR_ZONE_GPH_ID_CHECK_FAIL            ((VL53LX_Error) - 21)\n+#define VL53LX_ERROR_XTALK_EXTRACTION_NO_SAMPLE_FAIL   ((VL53LX_Error) - 22)\n+#define VL53LX_ERROR_XTALK_EXTRACTION_SIGMA_LIMIT_FAIL ((VL53LX_Error) - 23)\n+#define VL53LX_ERROR_OFFSET_CAL_NO_SAMPLE_FAIL           ((VL53LX_Error) - 24)\n+#define VL53LX_ERROR_OFFSET_CAL_NO_SPADS_ENABLED_FAIL    ((VL53LX_Error) - 25)\n+#define VL53LX_ERROR_ZONE_CAL_NO_SAMPLE_FAIL             ((VL53LX_Error) - 26)\n+#define VL53LX_ERROR_TUNING_PARM_KEY_MISMATCH             ((VL53LX_Error) - 27)\n+#define VL53LX_WARNING_REF_SPAD_CHAR_NOT_ENOUGH_SPADS   ((VL53LX_Error) - 28)\n+#define VL53LX_WARNING_REF_SPAD_CHAR_RATE_TOO_HIGH      ((VL53LX_Error) - 29)\n+#define VL53LX_WARNING_REF_SPAD_CHAR_RATE_TOO_LOW       ((VL53LX_Error) - 30)\n+#define VL53LX_WARNING_OFFSET_CAL_MISSING_SAMPLES       ((VL53LX_Error) - 31)\n+#define VL53LX_WARNING_OFFSET_CAL_SIGMA_TOO_HIGH        ((VL53LX_Error) - 32)\n+#define VL53LX_WARNING_OFFSET_CAL_RATE_TOO_HIGH         ((VL53LX_Error) - 33)\n+#define VL53LX_WARNING_OFFSET_CAL_SPAD_COUNT_TOO_LOW    ((VL53LX_Error) - 34)\n+#define VL53LX_WARNING_ZONE_CAL_MISSING_SAMPLES       ((VL53LX_Error) - 35)\n+#define VL53LX_WARNING_ZONE_CAL_SIGMA_TOO_HIGH        ((VL53LX_Error) - 36)\n+#define VL53LX_WARNING_ZONE_CAL_RATE_TOO_HIGH         ((VL53LX_Error) - 37)\n+#define VL53LX_WARNING_XTALK_MISSING_SAMPLES             ((VL53LX_Error) - 38)\n+#define VL53LX_WARNING_XTALK_NO_SAMPLES_FOR_GRADIENT     ((VL53LX_Error) - 39)\n+#define VL53LX_WARNING_XTALK_SIGMA_LIMIT_FOR_GRADIENT    ((VL53LX_Error) - 40)\n+#define VL53LX_ERROR_NOT_IMPLEMENTED                   ((VL53LX_Error) - 41)\n+#define VL53LX_ERROR_PLATFORM_SPECIFIC_START           ((VL53LX_Error) - 60)\n+\n+#define VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS  0x8000\n+#define VL53LX_TUNINGPARM_PRIVATE_PAGE_BASE_ADDRESS 0xC000\n+\n+#define VL53LX_CALIBRATION_REF_SPAD\t\t0\n+#define VL53LX_CALIBRATION_CROSSTALK\t\t1\n+#define VL53LX_CALIBRATION_OFFSET\t\t2\n+#define VL53LX_CALIBRATION_OFFSET_SIMPLE\t4\n+#define VL53LX_CALIBRATION_OFFSET_PER_VCSEL\t5\n+#define VL53LX_CALIBRATION_OFFSET_ZERO_DISTANCE\t6\n+\n+typedef uint8_t VL53LX_DeviceZonePreset;\n+\n+typedef uint8_t VL53LX_DevicePresetModes;\n+\n+#define VL53LX_DEVICEPRESETMODE_NONE                            \\\n+\t((VL53LX_DevicePresetModes)  0)\n+#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_LONG_RANGE            \\\n+\t((VL53LX_DevicePresetModes) 27)\n+#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_MEDIUM_RANGE          \\\n+\t((VL53LX_DevicePresetModes) 30)\n+#define VL53LX_DEVICEPRESETMODE_HISTOGRAM_SHORT_RANGE           \\\n+\t((VL53LX_DevicePresetModes) 33)\n+\n+typedef uint8_t VL53LX_DeviceMeasurementModes;\n+\n+#define VL53LX_DEVICEMEASUREMENTMODE_STOP          \\\n+\t((VL53LX_DeviceMeasurementModes)  0x00)\n+#define VL53LX_DEVICEMEASUREMENTMODE_SINGLESHOT     \\\n+\t((VL53LX_DeviceMeasurementModes)  0x10)\n+#define VL53LX_DEVICEMEASUREMENTMODE_BACKTOBACK      \\\n+\t((VL53LX_DeviceMeasurementModes)  0x20)\n+#define VL53LX_DEVICEMEASUREMENTMODE_TIMED          \\\n+\t((VL53LX_DeviceMeasurementModes)  0x40)\n+#define VL53LX_DEVICEMEASUREMENTMODE_ABORT          \\\n+\t((VL53LX_DeviceMeasurementModes)  0x80)\n+\n+typedef uint8_t VL53LX_OffsetCalibrationMode;\n+\n+#define VL53LX_OFFSETCALIBRATIONMODE__NONE                \\\n+\t((VL53LX_OffsetCalibrationMode)  0)\n+#define VL53LX_OFFSETCALIBRATIONMODE__MM1_MM2__STANDARD    \\\n+\t((VL53LX_OffsetCalibrationMode)  1)\n+#define VL53LX_OFFSETCALIBRATIONMODE__MM1_MM2__HISTOGRAM    \\\n+\t((VL53LX_OffsetCalibrationMode)  2)\n+#define VL53LX_OFFSETCALIBRATIONMODE__MM1_MM2__STANDARD_PRE_RANGE_ONLY \\\n+\t((VL53LX_OffsetCalibrationMode)  3)\n+#define VL53LX_OFFSETCALIBRATIONMODE__MM1_MM2__HISTOGRAM_PRE_RANGE_ONLY \\\n+\t((VL53LX_OffsetCalibrationMode)  4)\n+\n+typedef uint8_t VL53LX_OffsetCorrectionMode;\n+\n+#define VL53LX_OFFSETCORRECTIONMODE__NONE             \\\n+\t((VL53LX_OffsetCorrectionMode)  0)\n+#define VL53LX_OFFSETCORRECTIONMODE__MM1_MM2_OFFSETS  \\\n+\t((VL53LX_OffsetCorrectionMode)  1)\n+#define VL53LX_OFFSETCORRECTIONMODE__PER_VCSEL_OFFSETS  \\\n+\t((VL53LX_OffsetCorrectionMode)  3)\n+\n+typedef uint8_t VL53LX_DeviceDmaxMode;\n+\n+#define VL53LX_DEVICEDMAXMODE__NONE                 \\\n+\t((VL53LX_DeviceDmaxMode)  0)\n+#define VL53LX_DEVICEDMAXMODE__FMT_CAL_DATA          \\\n+\t((VL53LX_DeviceDmaxMode)  1)\n+#define VL53LX_DEVICEDMAXMODE__CUST_CAL_DATA         \\\n+\t((VL53LX_DeviceDmaxMode)  2)\n+\n+typedef uint8_t VL53LX_DeviceState;\n+\n+#define VL53LX_DEVICESTATE_POWERDOWN              ((VL53LX_DeviceState)  0)\n+#define VL53LX_DEVICESTATE_HW_STANDBY             ((VL53LX_DeviceState)  1)\n+#define VL53LX_DEVICESTATE_FW_COLDBOOT            ((VL53LX_DeviceState)  2)\n+#define VL53LX_DEVICESTATE_SW_STANDBY             ((VL53LX_DeviceState)  3)\n+#define VL53LX_DEVICESTATE_RANGING_DSS_AUTO       ((VL53LX_DeviceState)  4)\n+#define VL53LX_DEVICESTATE_RANGING_DSS_MANUAL     ((VL53LX_DeviceState)  5)\n+#define VL53LX_DEVICESTATE_RANGING_WAIT_GPH_SYNC  ((VL53LX_DeviceState)  6)\n+#define VL53LX_DEVICESTATE_RANGING_GATHER_DATA    ((VL53LX_DeviceState)  7)\n+#define VL53LX_DEVICESTATE_RANGING_OUTPUT_DATA    ((VL53LX_DeviceState)  8)\n+\n+#define VL53LX_DEVICESTATE_UNKNOWN               ((VL53LX_DeviceState) 98)\n+#define VL53LX_DEVICESTATE_ERROR                 ((VL53LX_DeviceState) 99)\n+\n+typedef uint8_t VL53LX_GPIO_Interrupt_Mode;\n+\n+#define VL53LX_GPIOINTMODE_LEVEL_LOW \\\n+\t((VL53LX_GPIO_Interrupt_Mode) 0)\n+#define VL53LX_GPIOINTMODE_LEVEL_HIGH \\\n+\t((VL53LX_GPIO_Interrupt_Mode) 1)\n+#define VL53LX_GPIOINTMODE_OUT_OF_WINDOW \\\n+\t((VL53LX_GPIO_Interrupt_Mode) 2)\n+#define VL53LX_GPIOINTMODE_IN_WINDOW \\\n+\t((VL53LX_GPIO_Interrupt_Mode) 3)\n+\n+typedef uint8_t VL53LX_DeviceSscArray;\n+\n+#define VL53LX_DEVICESSCARRAY_RTN ((VL53LX_DeviceSscArray) 0x00)\n+\n+#define VL53LX_DEVICETESTMODE_REF ((VL53LX_DeviceSscArray) 0x01)\n+\n+typedef uint8_t VL53LX_HistAlgoSelect;\n+\n+#define VL53LX_HIST_ALGO_SELECT__PW_HIST_GEN1 \\\n+\t((VL53LX_HistAlgoSelect) 1)\n+#define VL53LX_HIST_ALGO_SELECT__PW_HIST_GEN2 \\\n+\t((VL53LX_HistAlgoSelect) 2)\n+#define VL53LX_HIST_ALGO_SELECT__PW_HIST_GEN3 \\\n+\t((VL53LX_HistAlgoSelect) 3)\n+#define VL53LX_HIST_ALGO_SELECT__PW_HIST_GEN4 \\\n+\t((VL53LX_HistAlgoSelect) 4)\n+\n+\n+typedef uint8_t VL53LX_HistTargetOrder;\n+\n+#define VL53LX_HIST_TARGET_ORDER__INCREASING_DISTANCE \\\n+\t((VL53LX_HistTargetOrder) 1)\n+#define VL53LX_HIST_TARGET_ORDER__STRONGEST_FIRST \\\n+\t((VL53LX_HistTargetOrder) 2)\n+\n+typedef uint8_t VL53LX_HistAmbEstMethod;\n+\n+#define VL53LX_HIST_AMB_EST_METHOD__AMBIENT_BINS \\\n+\t((VL53LX_HistAmbEstMethod) 1)\n+#define VL53LX_HIST_AMB_EST_METHOD__THRESHOLDED_BINS  \\\n+\t((VL53LX_HistAmbEstMethod) 2)\n+\n+typedef uint16_t VL53LX_TuningParms;\n+\n+#define VL53LX_TUNINGPARMS_LLD_PUBLIC_MIN_ADDRESS \\\n+\t((VL53LX_TuningParms) VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS)\n+#define VL53LX_TUNINGPARMS_LLD_PUBLIC_MAX_ADDRESS \\\n+\t((VL53LX_TuningParms) VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_5_RANGEB)\n+\n+#define VL53LX_TUNINGPARMS_LLD_PRIVATE_MIN_ADDRESS \\\n+\t((VL53LX_TuningParms) VL53LX_TUNINGPARM_PRIVATE_PAGE_BASE_ADDRESS)\n+#define VL53LX_TUNINGPARMS_LLD_PRIVATE_MAX_ADDRESS \\\n+\t((VL53LX_TuningParms) VL53LX_TUNINGPARMS_LLD_PRIVATE_MIN_ADDRESS)\n+\n+typedef uint8_t VL53LX_DistanceModes;\n+\n+#define VL53LX_DISTANCEMODE_SHORT             ((VL53LX_DistanceModes)  1)\n+#define VL53LX_DISTANCEMODE_MEDIUM            ((VL53LX_DistanceModes)  2)\n+#define VL53LX_DISTANCEMODE_LONG              ((VL53LX_DistanceModes)  3)\n+\n+typedef uint8_t VL53LX_DeviceInterruptPolarity;\n+\n+#define VL53LX_DEVICEINTERRUPTPOLARITY_ACTIVE_HIGH        \\\n+\t((VL53LX_DeviceInterruptPolarity)  0x00)\n+#define VL53LX_DEVICEINTERRUPTPOLARITY_ACTIVE_LOW         \\\n+\t((VL53LX_DeviceInterruptPolarity)  0x10)\n+#define VL53LX_DEVICEINTERRUPTPOLARITY_BIT_MASK           \\\n+\t((VL53LX_DeviceInterruptPolarity)  0x10)\n+#define VL53LX_DEVICEINTERRUPTPOLARITY_CLEAR_MASK         \\\n+\t((VL53LX_DeviceInterruptPolarity)  0xEF)\n+\n+typedef uint8_t VL53LX_ZoneConfig_BinConfig_select;\n+\n+#define VL53LX_ZONECONFIG_BINCONFIG__LOWAMB \\\n+\t((VL53LX_ZoneConfig_BinConfig_select) 1)\n+#define VL53LX_ZONECONFIG_BINCONFIG__MIDAMB \\\n+\t((VL53LX_ZoneConfig_BinConfig_select) 2)\n+#define VL53LX_ZONECONFIG_BINCONFIG__HIGHAMB \\\n+\t((VL53LX_ZoneConfig_BinConfig_select) 3)\n+\n+typedef uint8_t VL53LX_DeviceConfigLevel;\n+\n+#define VL53LX_DEVICECONFIGLEVEL_SYSTEM_CONTROL  \\\n+\t((VL53LX_DeviceConfigLevel)  0)\n+\n+#define VL53LX_DEVICECONFIGLEVEL_DYNAMIC_ONWARDS \\\n+\t((VL53LX_DeviceConfigLevel)  1)\n+\n+#define VL53LX_DEVICECONFIGLEVEL_TIMING_ONWARDS \\\n+\t((VL53LX_DeviceConfigLevel)  2)\n+\n+#define VL53LX_DEVICECONFIGLEVEL_GENERAL_ONWARDS \\\n+\t((VL53LX_DeviceConfigLevel)  3)\n+\n+#define VL53LX_DEVICECONFIGLEVEL_STATIC_ONWARDS  \\\n+\t((VL53LX_DeviceConfigLevel)  4)\n+\n+#define VL53LX_DEVICECONFIGLEVEL_CUSTOMER_ONWARDS  \\\n+\t((VL53LX_DeviceConfigLevel)  5)\n+\n+#define VL53LX_DEVICECONFIGLEVEL_FULL  \\\n+\t((VL53LX_DeviceConfigLevel)  6)\n+\n+typedef uint8_t VL53LX_DeviceResultsLevel;\n+\n+#define VL53LX_DEVICERESULTSLEVEL_SYSTEM_RESULTS  \\\n+\t((VL53LX_DeviceResultsLevel)  0)\n+\n+#define VL53LX_DEVICERESULTSLEVEL_UPTO_CORE  \\\n+\t((VL53LX_DeviceResultsLevel)  1)\n+\n+#define VL53LX_DEVICERESULTSLEVEL_FULL  \\\n+\t((VL53LX_DeviceResultsLevel)  2)\n+\n+typedef uint8_t VL53LX_DeviceReportStatus;\n+\n+#define VL53LX_DEVICEREPORTSTATUS_NOUPDATE                 \\\n+\t((VL53LX_DeviceReportStatus) 0)\n+\n+#define VL53LX_DEVICEREPORTSTATUS_ROI_SETUP               \\\n+\t((VL53LX_DeviceReportStatus)  1)\n+#define VL53LX_DEVICEREPORTSTATUS_VHV                     \\\n+\t((VL53LX_DeviceReportStatus)  2)\n+#define VL53LX_DEVICEREPORTSTATUS_PHASECAL                \\\n+\t((VL53LX_DeviceReportStatus)  3)\n+#define VL53LX_DEVICEREPORTSTATUS_REFERENCE_PHASE         \\\n+\t((VL53LX_DeviceReportStatus)  4)\n+#define VL53LX_DEVICEREPORTSTATUS_DSS1                    \\\n+\t((VL53LX_DeviceReportStatus)  5)\n+#define VL53LX_DEVICEREPORTSTATUS_DSS2                    \\\n+\t((VL53LX_DeviceReportStatus)  6)\n+#define VL53LX_DEVICEREPORTSTATUS_MM1                     \\\n+\t((VL53LX_DeviceReportStatus)  7)\n+#define VL53LX_DEVICEREPORTSTATUS_MM2                     \\\n+\t((VL53LX_DeviceReportStatus)  8)\n+#define VL53LX_DEVICEREPORTSTATUS_RANGE                   \\\n+\t((VL53LX_DeviceReportStatus)  9)\n+#define VL53LX_DEVICEREPORTSTATUS_HISTOGRAM               \\\n+\t((VL53LX_DeviceReportStatus) 10)\n+\n+typedef uint8_t VL53LX_DeviceGpioMode;\n+\n+#define VL53LX_DEVICEGPIOMODE_OUTPUT_CONSTANT_ZERO                \\\n+\t((VL53LX_DeviceGpioMode)  0x00)\n+#define VL53LX_DEVICEGPIOMODE_OUTPUT_RANGE_AND_ERROR_INTERRUPTS    \\\n+\t((VL53LX_DeviceGpioMode)  0x01)\n+#define VL53LX_DEVICEGPIOMODE_OUTPUT_TIMIER_INTERRUPTS             \\\n+\t((VL53LX_DeviceGpioMode)  0x02)\n+#define VL53LX_DEVICEGPIOMODE_OUTPUT_RANGE_MODE_INTERRUPT_STATUS  \\\n+\t((VL53LX_DeviceGpioMode)  0x03)\n+#define VL53LX_DEVICEGPIOMODE_OUTPUT_SLOW_OSCILLATOR_CLOCK        \\\n+\t((VL53LX_DeviceGpioMode)  0x04)\n+#define VL53LX_DEVICEGPIOMODE_BIT_MASK                           \\\n+\t((VL53LX_DeviceGpioMode)  0x0F)\n+#define VL53LX_DEVICEGPIOMODE_CLEAR_MASK                        \\\n+\t((VL53LX_DeviceGpioMode)  0xF0)\n+\n+typedef uint8_t VL53LX_DeviceDssMode;\n+\n+#define VL53LX_DEVICEDSSMODE__DISABLED \\\n+\t((VL53LX_DeviceDssMode) 0)\n+#define VL53LX_DEVICEDSSMODE__TARGET_RATE \\\n+\t((VL53LX_DeviceDssMode) 1)\n+#define VL53LX_DEVICEDSSMODE__REQUESTED_EFFFECTIVE_SPADS \\\n+\t((VL53LX_DeviceDssMode) 2)\n+#define VL53LX_DEVICEDSSMODE__BLOCK_SELECT \\\n+\t((VL53LX_DeviceDssMode) 3)\n+\n+typedef uint8_t VL53LX_DeviceTestMode;\n+\n+#define VL53LX_DEVICETESTMODE_NONE \\\n+\t((VL53LX_DeviceTestMode) 0x00)\n+#define VL53LX_DEVICETESTMODE_NVM_ZERO \\\n+\t((VL53LX_DeviceTestMode) 0x01)\n+#define VL53LX_DEVICETESTMODE_NVM_COPY \\\n+\t((VL53LX_DeviceTestMode) 0x02)\n+#define VL53LX_DEVICETESTMODE_PATCH \\\n+\t((VL53LX_DeviceTestMode) 0x03)\n+#define VL53LX_DEVICETESTMODE_DCR \\\n+\t((VL53LX_DeviceTestMode) 0x04)\n+#define VL53LX_DEVICETESTMODE_LCR_VCSEL_OFF \\\n+\t((VL53LX_DeviceTestMode) 0x05)\n+#define VL53LX_DEVICETESTMODE_LCR_VCSEL_ON \\\n+\t((VL53LX_DeviceTestMode) 0x06)\n+#define VL53LX_DEVICETESTMODE_SPOT_CENTRE_LOCATE \\\n+\t((VL53LX_DeviceTestMode) 0x07)\n+#define VL53LX_DEVICETESTMODE_REF_SPAD_CHAR_WITH_PRE_VHV \\\n+\t((VL53LX_DeviceTestMode) 0x08)\n+#define VL53LX_DEVICETESTMODE_REF_SPAD_CHAR_ONLY \\\n+\t((VL53LX_DeviceTestMode) 0x09)\n+\n+#define VL53LX_SEQUENCE_VHV_EN\t\t\t\t\t\t    0x01\n+#define VL53LX_SEQUENCE_PHASECAL_EN                     0x02\n+#define VL53LX_SEQUENCE_REFERENCE_PHASE_EN              0x04\n+#define VL53LX_SEQUENCE_DSS1_EN                         0x08\n+#define VL53LX_SEQUENCE_DSS2_EN                         0x10\n+#define VL53LX_SEQUENCE_MM1_EN                          0x20\n+#define VL53LX_SEQUENCE_MM2_EN                          0x40\n+#define VL53LX_SEQUENCE_RANGE_EN                        0x80\n+\n+#define VL53LX_INTERRUPT_CONFIG_LEVEL_LOW               0x00\n+#define VL53LX_INTERRUPT_CONFIG_LEVEL_HIGH              0x01\n+#define VL53LX_INTERRUPT_CONFIG_OUT_OF_WINDOW           0x02\n+#define VL53LX_INTERRUPT_CONFIG_IN_WINDOW               0x03\n+#define VL53LX_INTERRUPT_CONFIG_NEW_SAMPLE_READY        0x20\n+\n+#define VL53LX_CLEAR_RANGE_INT                          0x01\n+#define VL53LX_CLEAR_ERROR_INT                          0x02\n+\n+#define VL53LX_DEVICESCHEDULERMODE_PSEUDO_SOLO  0x00\n+#define VL53LX_DEVICESCHEDULERMODE_STREAMING    0x01\n+#define VL53LX_DEVICESCHEDULERMODE_HISTOGRAM    0x02\n+\n+#define VL53LX_DEVICEREADOUTMODE_SINGLE_SD        (0x00 << 2)\n+#define VL53LX_DEVICEREADOUTMODE_DUAL_SD          (0x01 << 2)\n+#define VL53LX_DEVICEREADOUTMODE_SPLIT_READOUT    (0x02 << 2)\n+#define VL53LX_DEVICEREADOUTMODE_SPLIT_MANUAL     (0x03 << 2)\n+\n+#define VL53LX_TUNINGPARM_VERSION \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 0))\n+#define VL53LX_TUNINGPARM_KEY_TABLE_VERSION \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 1))\n+#define VL53LX_TUNINGPARM_LLD_VERSION \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 2))\n+#define VL53LX_TUNINGPARM_HIST_ALGO_SELECT \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 3))\n+#define VL53LX_TUNINGPARM_HIST_TARGET_ORDER \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 4))\n+#define VL53LX_TUNINGPARM_HIST_FILTER_WOI_0 \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 5))\n+#define VL53LX_TUNINGPARM_HIST_FILTER_WOI_1 \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 6))\n+#define VL53LX_TUNINGPARM_HIST_AMB_EST_METHOD \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 7))\n+#define VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_0 \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 8))\n+#define VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_1 \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 9))\n+#define VL53LX_TUNINGPARM_HIST_MIN_AMB_THRESH_EVENTS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 10))\n+#define VL53LX_TUNINGPARM_HIST_AMB_EVENTS_SCALER \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 11))\n+#define VL53LX_TUNINGPARM_HIST_NOISE_THRESHOLD \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 12))\n+#define VL53LX_TUNINGPARM_HIST_SIGNAL_TOTAL_EVENTS_LIMIT \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 13))\n+#define VL53LX_TUNINGPARM_HIST_SIGMA_EST_REF_MM \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 14))\n+#define VL53LX_TUNINGPARM_HIST_SIGMA_THRESH_MM \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 15))\n+#define VL53LX_TUNINGPARM_HIST_GAIN_FACTOR \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 16))\n+#define VL53LX_TUNINGPARM_CONSISTENCY_HIST_PHASE_TOLERANCE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 17))\n+#define VL53LX_TUNINGPARM_CONSISTENCY_HIST_MIN_MAX_TOLERANCE_MM \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 18))\n+#define VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 19))\n+#define VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA_MIN_SPAD_LIMIT \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 20))\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_LONG_RANGE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 21))\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_MED_RANGE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 22))\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_SHORT_RANGE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 23))\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_LONG_RANGE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 24))\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_MED_RANGE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 25))\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_SHORT_RANGE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 26))\n+#define VL53LX_TUNINGPARM_XTALK_DETECT_MIN_VALID_RANGE_MM \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 27))\n+#define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RANGE_MM \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 28))\n+#define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_SIGMA_MM \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 29))\n+#define VL53LX_TUNINGPARM_XTALK_DETECT_MIN_MAX_TOLERANCE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 30))\n+#define VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RATE_KCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 31))\n+#define VL53LX_TUNINGPARM_XTALK_DETECT_EVENT_SIGMA \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 32))\n+#define VL53LX_TUNINGPARM_HIST_XTALK_MARGIN_KCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 33))\n+#define VL53LX_TUNINGPARM_CONSISTENCY_LITE_PHASE_TOLERANCE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 34))\n+#define VL53LX_TUNINGPARM_PHASECAL_TARGET \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 35))\n+#define VL53LX_TUNINGPARM_LITE_CAL_REPEAT_RATE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 36))\n+#define VL53LX_TUNINGPARM_LITE_RANGING_GAIN_FACTOR \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 37))\n+#define VL53LX_TUNINGPARM_LITE_MIN_CLIP_MM \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 38))\n+#define VL53LX_TUNINGPARM_LITE_LONG_SIGMA_THRESH_MM \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 39))\n+#define VL53LX_TUNINGPARM_LITE_MED_SIGMA_THRESH_MM \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 40))\n+#define VL53LX_TUNINGPARM_LITE_SHORT_SIGMA_THRESH_MM \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 41))\n+#define VL53LX_TUNINGPARM_LITE_LONG_MIN_COUNT_RATE_RTN_MCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 42))\n+#define VL53LX_TUNINGPARM_LITE_MED_MIN_COUNT_RATE_RTN_MCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 43))\n+#define VL53LX_TUNINGPARM_LITE_SHORT_MIN_COUNT_RATE_RTN_MCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 44))\n+#define VL53LX_TUNINGPARM_LITE_SIGMA_EST_PULSE_WIDTH \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 45))\n+#define VL53LX_TUNINGPARM_LITE_SIGMA_EST_AMB_WIDTH_NS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 46))\n+#define VL53LX_TUNINGPARM_LITE_SIGMA_REF_MM \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 47))\n+#define VL53LX_TUNINGPARM_LITE_RIT_MULT \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 48))\n+#define VL53LX_TUNINGPARM_LITE_SEED_CONFIG \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 49))\n+#define VL53LX_TUNINGPARM_LITE_QUANTIFIER \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 50))\n+#define VL53LX_TUNINGPARM_LITE_FIRST_ORDER_SELECT \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 51))\n+#define VL53LX_TUNINGPARM_LITE_XTALK_MARGIN_KCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 52))\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_LONG_RANGE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 53))\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_MED_RANGE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 54))\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_SHORT_RANGE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 55))\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_LONG_RANGE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 56))\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_MED_RANGE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 57))\n+#define VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_SHORT_RANGE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 58))\n+#define VL53LX_TUNINGPARM_TIMED_SEED_CONFIG \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 59))\n+#define VL53LX_TUNINGPARM_DMAX_CFG_SIGNAL_THRESH_SIGMA \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 60))\n+#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_0 \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 61))\n+#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_1 \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 62))\n+#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_2 \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 63))\n+#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_3 \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 64))\n+#define VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_4 \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 65))\n+#define VL53LX_TUNINGPARM_VHV_LOOPBOUND \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 66))\n+#define VL53LX_TUNINGPARM_REFSPADCHAR_DEVICE_TEST_MODE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 67))\n+#define VL53LX_TUNINGPARM_REFSPADCHAR_VCSEL_PERIOD \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 68))\n+#define VL53LX_TUNINGPARM_REFSPADCHAR_PHASECAL_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 69))\n+#define VL53LX_TUNINGPARM_REFSPADCHAR_TARGET_COUNT_RATE_MCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 70))\n+#define VL53LX_TUNINGPARM_REFSPADCHAR_MIN_COUNTRATE_LIMIT_MCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 71))\n+#define VL53LX_TUNINGPARM_REFSPADCHAR_MAX_COUNTRATE_LIMIT_MCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 72))\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_NUM_OF_SAMPLES \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 73))\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_MIN_FILTER_THRESH_MM \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 74))\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_FILTER_THRESH_MM \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 75))\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_RATE_MCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 76))\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_PHASECAL_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 77))\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_VALID_RATE_KCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 78))\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_SIGMA_THRESHOLD_MM \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 79))\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 80))\n+#define VL53LX_TUNINGPARM_XTALK_EXTRACT_BIN_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 81))\n+#define VL53LX_TUNINGPARM_OFFSET_CAL_DSS_RATE_MCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 82))\n+#define VL53LX_TUNINGPARM_OFFSET_CAL_PHASECAL_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 83))\n+#define VL53LX_TUNINGPARM_OFFSET_CAL_MM_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 84))\n+#define VL53LX_TUNINGPARM_OFFSET_CAL_RANGE_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 85))\n+#define VL53LX_TUNINGPARM_OFFSET_CAL_PRE_SAMPLES \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 86))\n+#define VL53LX_TUNINGPARM_OFFSET_CAL_MM1_SAMPLES \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 87))\n+#define VL53LX_TUNINGPARM_OFFSET_CAL_MM2_SAMPLES \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 88))\n+#define VL53LX_TUNINGPARM_ZONE_CAL_DSS_RATE_MCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 89))\n+#define VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 90))\n+#define VL53LX_TUNINGPARM_ZONE_CAL_DSS_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 91))\n+#define VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_NUM_SAMPLES \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 92))\n+#define VL53LX_TUNINGPARM_ZONE_CAL_RANGE_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 93))\n+#define VL53LX_TUNINGPARM_ZONE_CAL_ZONE_NUM_SAMPLES \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 94))\n+#define VL53LX_TUNINGPARM_SPADMAP_VCSEL_PERIOD \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 95))\n+#define VL53LX_TUNINGPARM_SPADMAP_VCSEL_START \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 96))\n+#define VL53LX_TUNINGPARM_SPADMAP_RATE_LIMIT_MCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 97))\n+#define VL53LX_TUNINGPARM_LITE_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 98))\n+#define VL53LX_TUNINGPARM_RANGING_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 99))\n+#define VL53LX_TUNINGPARM_MZ_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 100))\n+#define VL53LX_TUNINGPARM_TIMED_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 101))\n+#define VL53LX_TUNINGPARM_LITE_PHASECAL_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 102))\n+#define VL53LX_TUNINGPARM_RANGING_LONG_PHASECAL_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 103))\n+#define VL53LX_TUNINGPARM_RANGING_MED_PHASECAL_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 104))\n+#define VL53LX_TUNINGPARM_RANGING_SHORT_PHASECAL_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 105))\n+#define VL53LX_TUNINGPARM_MZ_LONG_PHASECAL_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 106))\n+#define VL53LX_TUNINGPARM_MZ_MED_PHASECAL_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 107))\n+#define VL53LX_TUNINGPARM_MZ_SHORT_PHASECAL_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 108))\n+#define VL53LX_TUNINGPARM_TIMED_PHASECAL_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 109))\n+#define VL53LX_TUNINGPARM_LITE_MM_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 110))\n+#define VL53LX_TUNINGPARM_RANGING_MM_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 111))\n+#define VL53LX_TUNINGPARM_MZ_MM_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 112))\n+#define VL53LX_TUNINGPARM_TIMED_MM_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 113))\n+#define VL53LX_TUNINGPARM_LITE_RANGE_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 114))\n+#define VL53LX_TUNINGPARM_RANGING_RANGE_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 115))\n+#define VL53LX_TUNINGPARM_MZ_RANGE_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 116))\n+#define VL53LX_TUNINGPARM_TIMED_RANGE_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 117))\n+#define VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_MARGIN \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 118))\n+#define VL53LX_TUNINGPARM_DYNXTALK_NOISE_MARGIN \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 119))\n+#define VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 120))\n+#define VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT_HI \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 121))\n+#define VL53LX_TUNINGPARM_DYNXTALK_SAMPLE_LIMIT \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 122))\n+#define VL53LX_TUNINGPARM_DYNXTALK_SINGLE_XTALK_DELTA \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 123))\n+#define VL53LX_TUNINGPARM_DYNXTALK_AVERAGED_XTALK_DELTA \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 124))\n+#define VL53LX_TUNINGPARM_DYNXTALK_CLIP_LIMIT \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 125))\n+#define VL53LX_TUNINGPARM_DYNXTALK_SCALER_CALC_METHOD \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 126))\n+#define VL53LX_TUNINGPARM_DYNXTALK_XGRADIENT_SCALER \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 127))\n+#define VL53LX_TUNINGPARM_DYNXTALK_YGRADIENT_SCALER \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 128))\n+#define VL53LX_TUNINGPARM_DYNXTALK_USER_SCALER_SET \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 129))\n+#define VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_COR_SINGLE_APPLY \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 130))\n+#define VL53LX_TUNINGPARM_DYNXTALK_XTALK_AMB_THRESHOLD \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 131))\n+#define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_AMB_THRESHOLD_KCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 132))\n+#define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_SAMPLE_LIMIT \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 133))\n+#define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_XTALK_OFFSET_KCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 134))\n+#define VL53LX_TUNINGPARM_DYNXTALK_NODETECT_MIN_RANGE_MM \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 135))\n+#define VL53LX_TUNINGPARM_LOWPOWERAUTO_VHV_LOOP_BOUND \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 136))\n+#define VL53LX_TUNINGPARM_LOWPOWERAUTO_MM_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 137))\n+#define VL53LX_TUNINGPARM_LOWPOWERAUTO_RANGE_CONFIG_TIMEOUT_US \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 138))\n+#define VL53LX_TUNINGPARM_VERY_SHORT_DSS_RATE_MCPS \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 139))\n+#define VL53LX_TUNINGPARM_PHASECAL_PATCH_POWER \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 140))\n+#define VL53LX_TUNINGPARM_HIST_MERGE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 141))\n+#define VL53LX_TUNINGPARM_RESET_MERGE_THRESHOLD \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 142))\n+#define VL53LX_TUNINGPARM_HIST_MERGE_MAX_SIZE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 143))\n+#define VL53LX_TUNINGPARM_DYNXTALK_MAX_SMUDGE_FACTOR \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 144))\n+#define VL53LX_TUNINGPARM_UWR_ENABLE \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 145))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_1_MIN \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 146))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_1_MAX \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 147))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_2_MIN \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 148))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_2_MAX \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 149))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_3_MIN \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 150))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_3_MAX \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 151))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_4_MIN \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 152))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_4_MAX \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 153))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_5_MIN \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 154))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_5_MAX \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 155))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_1_RANGEA \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 156))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_1_RANGEB \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 157))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_2_RANGEA \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 158))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_2_RANGEB \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 159))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_3_RANGEA \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 160))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_3_RANGEB \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 161))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_4_RANGEA \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 162))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_4_RANGEB \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 163))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_5_RANGEA \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 164))\n+#define VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_5_RANGEB \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 165))\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_1_MIN \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 166))\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_1_MAX \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 167))\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_2_MIN \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 168))\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_2_MAX \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 169))\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_3_MIN \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 170))\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_3_MAX \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 171))\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_4_MIN \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 172))\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_4_MAX \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 173))\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_5_MIN \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 174))\n+#define VL53LX_TUNINGPARM_UWR_LONG_ZONE_5_MAX \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 175))\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_1_RANGEA \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 176))\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_1_RANGEB \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 177))\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_2_RANGEA \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 178))\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_2_RANGEB \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 179))\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_3_RANGEA \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 180))\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_3_RANGEB \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 181))\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_4_RANGEA \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 182))\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_4_RANGEB \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 183))\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_5_RANGEA \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 184))\n+#define VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_5_RANGEB \\\n+((VL53LX_TuningParms) (VL53LX_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS + 185))\n+\n+enum VL53LX_Tuning_t {\n+\tVL53LX_TUNING_VERSION = 0,\n+\tVL53LX_TUNING_PROXY_MIN,\n+\tVL53LX_TUNING_SINGLE_TARGET_XTALK_TARGET_DISTANCE_MM,\n+\tVL53LX_TUNING_SINGLE_TARGET_XTALK_SAMPLE_NUMBER,\n+\tVL53LX_TUNING_MIN_AMBIENT_DMAX_VALID,\n+\tVL53LX_TUNING_MAX_SIMPLE_OFFSET_CALIBRATION_SAMPLE_NUMBER,\n+\tVL53LX_TUNING_XTALK_FULL_ROI_TARGET_DISTANCE_MM,\n+\tVL53LX_TUNING_SIMPLE_OFFSET_CALIBRATION_REPEAT,\n+\tVL53LX_TUNING_XTALK_FULL_ROI_BIN_SUM_MARGIN,\n+\tVL53LX_TUNING_XTALK_FULL_ROI_DEFAULT_OFFSET,\n+\tVL53LX_TUNING_ZERO_DISTANCE_OFFSET_NON_LINEAR_FACTOR,\n+\tVL53LX_TUNING_MAX_TUNABLE_KEY\n+};\n+\n+#define TUNING_VERSION\t0x0007\n+#define TUNING_PROXY_MIN -30\n+#define TUNING_SINGLE_TARGET_XTALK_TARGET_DISTANCE_MM 600\n+#define TUNING_SINGLE_TARGET_XTALK_SAMPLE_NUMBER 50\n+#define TUNING_MIN_AMBIENT_DMAX_VALID 8\n+#ifdef SMALL_FOOTPRINT\n+#define TUNING_MAX_SIMPLE_OFFSET_CALIBRATION_SAMPLE_NUMBER 50\n+#else\n+#define TUNING_MAX_SIMPLE_OFFSET_CALIBRATION_SAMPLE_NUMBER 10\n+#endif\n+#define TUNING_XTALK_FULL_ROI_TARGET_DISTANCE_MM 600\n+#ifdef SMALL_FOOTPRINT\n+#define TUNING_SIMPLE_OFFSET_CALIBRATION_REPEAT 1\n+#else\n+#define TUNING_SIMPLE_OFFSET_CALIBRATION_REPEAT 3\n+#endif\n+#define TUNING_ZERO_DISTANCE_OFFSET_NON_LINEAR_FACTOR_DEFAULT 9\n+#define TUNING_XTALK_FULL_ROI_BIN_SUM_MARGIN 24\n+#define TUNING_XTALK_FULL_ROI_DEFAULT_OFFSET 50\n+\n+#ifdef STMVL53LX_DEBUG_I2C\n+#define i2c_debug(fmt, ...) printk(fmt, ##__VA_ARGS__)\n+#else\n+#define i2c_debug(fmt, ...) ((void)0)\n+#endif\n+\n+#if STMVL53LX_LOG_POLL_TIMING\n+#define poll_timing_log(ptv) printk(\"poll in %d us\\n\", tv_elapsed_us(ptv))\n+#else\n+#define poll_timing_log(...) ((void)0)\n+#endif\n+\n+#define IMPLEMENT_PARAMETER_INTEGER(sysfs_name, info_name)\\\n+static ssize_t stmvl53lx_show_##sysfs_name(struct device *dev, \\\n+\t\t\t\tstruct device_attribute *attr, char *buf) \\\n+{ \\\n+\tstruct stmvl53lx_data *data = dev_get_drvdata(dev); \\\n+\tint param; \\\n+\\\n+\tmutex_lock(&data->work_mutex); \\\n+\tparam = data->sysfs_name; \\\n+\tmutex_unlock(&data->work_mutex);; \\\n+\\\n+\treturn scnprintf(buf, PAGE_SIZE, \"%d\\n\", param); \\\n+} \\\n+\\\n+static ssize_t stmvl53lx_store_##sysfs_name(struct device *dev, \\\n+\t\t\t\t\tstruct device_attribute *attr, \\\n+\t\t\t\t\tconst char *buf, size_t count) \\\n+{ \\\n+\tstruct stmvl53lx_data *data = dev_get_drvdata(dev); \\\n+\tint rc = 0; \\\n+\tint param; \\\n+\\\n+\tmutex_lock(&data->work_mutex); \\\n+\\\n+\tif (kstrtoint(buf, 0, &param)) { \\\n+\t\tvl53lx_errmsg(\"invalid syntax in %s\", buf); \\\n+\t\trc = -EINVAL; \\\n+\t} else \\\n+\t\trc = stmvl53lx_set_##sysfs_name(data, param); \\\n+\\\n+\tmutex_unlock(&data->work_mutex); \\\n+\\\n+\treturn rc ? rc : count; \\\n+} \\\n+\\\n+static int ctrl_param_##sysfs_name(struct stmvl53lx_data *data, \\\n+\t\tstruct stmvl53lx_parameter *param) \\\n+{ \\\n+\tint rc = 0; \\\n+\\\n+\tif (param->is_read) { \\\n+\t\tparam->value = data->sysfs_name; \\\n+\t\tparam->status = 0; \\\n+\t\tvl53lx_dbgmsg(\"get \" info_name \" %d\", param->value); \\\n+\t\trc = 0; \\\n+\t} else { \\\n+\t\trc = stmvl53lx_set_##sysfs_name(data, param->value); \\\n+\t\tvl53lx_dbgmsg(\"rc %d req %d now %d\", rc, \\\n+\t\t\t\tparam->value, data->sysfs_name); \\\n+\t} \\\n+\\\n+\treturn rc; \\\n+}\n+\n+typedef struct {\n+\tuint32_t   VL53LX_p_016;\n+\tuint32_t   VL53LX_p_017;\n+\tuint16_t   VL53LX_p_011;\n+\tuint8_t    range_status;\n+} VL53LX_object_data_t;\n+\n+typedef struct {\n+\tVL53LX_DeviceState     cfg_device_state;\n+\tVL53LX_DeviceState     rd_device_state;\n+\tuint8_t                zone_id;\n+\tuint8_t                stream_count;\n+\tuint8_t                max_objects;\n+\tuint8_t                active_objects;\n+\tVL53LX_object_data_t   VL53LX_p_003[VL53LX_MAX_RANGE_RESULTS];\n+\tVL53LX_object_data_t   xmonitor;\n+} VL53LX_zone_objects_t;\n+\n+typedef struct {\n+\tuint32_t     ll_revision;\n+\tuint8_t      ll_major;\n+\tuint8_t      ll_minor;\n+\tuint8_t      ll_build;\n+} VL53LX_ll_version_t;\n+\n+typedef struct {\n+\tVL53LX_DeviceState   cfg_device_state;\n+\tuint8_t   cfg_stream_count;\n+\tuint8_t   cfg_internal_stream_count;\n+\tuint8_t   cfg_internal_stream_count_val;\n+\tuint8_t   cfg_gph_id;\n+\tuint8_t   cfg_timing_status;\n+\tuint8_t   cfg_zone_id;\n+\tVL53LX_DeviceState   rd_device_state;\n+\tuint8_t   rd_stream_count;\n+\tuint8_t   rd_internal_stream_count;\n+\tuint8_t   rd_internal_stream_count_val;\n+\tuint8_t   rd_gph_id;\n+\tuint8_t   rd_timing_status;\n+\tuint8_t   rd_zone_id;\n+} VL53LX_ll_driver_state_t;\n+\n+typedef struct {\n+\tVL53LX_GPIO_Interrupt_Mode\tintr_mode_distance;\n+\tVL53LX_GPIO_Interrupt_Mode\tintr_mode_rate;\n+\tuint8_t\t\t\t\tintr_new_measure_ready;\n+\tuint8_t\t\t\t\tintr_no_target;\n+\tuint8_t\t\t\t\tintr_combined_mode;\n+\tuint16_t\t\t\tthreshold_distance_high;\n+\tuint16_t\t\t\tthreshold_distance_low;\n+\tuint16_t\t\t\tthreshold_rate_high;\n+\tuint16_t\t\t\tthreshold_rate_low;\n+} VL53LX_GPIO_interrupt_config_t;\n+\n+typedef struct {\n+\tuint16_t  tp_tuning_parm_version;\n+\tuint16_t  tp_tuning_parm_key_table_version;\n+\tuint16_t  tp_tuning_parm_lld_version;\n+\tuint8_t   tp_init_phase_rtn_lite_long;\n+\tuint8_t   tp_init_phase_rtn_lite_med;\n+\tuint8_t   tp_init_phase_rtn_lite_short;\n+\tuint8_t   tp_init_phase_ref_lite_long;\n+\tuint8_t   tp_init_phase_ref_lite_med;\n+\tuint8_t   tp_init_phase_ref_lite_short;\n+\tuint8_t   tp_init_phase_rtn_hist_long;\n+\tuint8_t   tp_init_phase_rtn_hist_med;\n+\tuint8_t   tp_init_phase_rtn_hist_short;\n+\tuint8_t   tp_init_phase_ref_hist_long;\n+\tuint8_t   tp_init_phase_ref_hist_med;\n+\tuint8_t   tp_init_phase_ref_hist_short;\n+\tuint8_t   tp_consistency_lite_phase_tolerance;\n+\tuint8_t   tp_phasecal_target;\n+\tuint16_t  tp_cal_repeat_rate;\n+\tuint8_t   tp_lite_min_clip;\n+\tuint16_t  tp_lite_long_sigma_thresh_mm;\n+\tuint16_t  tp_lite_med_sigma_thresh_mm;\n+\tuint16_t  tp_lite_short_sigma_thresh_mm;\n+\tuint16_t  tp_lite_long_min_count_rate_rtn_mcps;\n+\tuint16_t  tp_lite_med_min_count_rate_rtn_mcps;\n+\tuint16_t  tp_lite_short_min_count_rate_rtn_mcps;\n+\tuint8_t   tp_lite_sigma_est_pulse_width_ns;\n+\tuint8_t   tp_lite_sigma_est_amb_width_ns;\n+\tuint8_t   tp_lite_sigma_ref_mm;\n+\tuint8_t   tp_lite_seed_cfg;\n+\tuint8_t   tp_timed_seed_cfg;\n+\tuint8_t   tp_lite_quantifier;\n+\tuint8_t   tp_lite_first_order_select;\n+\tuint16_t  tp_dss_target_lite_mcps;\n+\tuint16_t  tp_dss_target_histo_mcps;\n+\tuint16_t  tp_dss_target_histo_mz_mcps;\n+\tuint16_t  tp_dss_target_timed_mcps;\n+\tuint16_t  tp_dss_target_very_short_mcps;\n+\tuint32_t  tp_phasecal_timeout_lite_us;\n+\tuint32_t  tp_phasecal_timeout_hist_long_us;\n+\tuint32_t  tp_phasecal_timeout_hist_med_us;\n+\tuint32_t  tp_phasecal_timeout_hist_short_us;\n+\tuint32_t  tp_phasecal_timeout_mz_long_us;\n+\tuint32_t  tp_phasecal_timeout_mz_med_us;\n+\tuint32_t  tp_phasecal_timeout_mz_short_us;\n+\tuint32_t  tp_phasecal_timeout_timed_us;\n+\tuint32_t  tp_mm_timeout_lite_us;\n+\tuint32_t  tp_mm_timeout_histo_us;\n+\tuint32_t  tp_mm_timeout_mz_us;\n+\tuint32_t  tp_mm_timeout_timed_us;\n+\tuint32_t  tp_mm_timeout_lpa_us;\n+\tuint32_t  tp_range_timeout_lite_us;\n+\tuint32_t  tp_range_timeout_histo_us;\n+\tuint32_t  tp_range_timeout_mz_us;\n+\tuint32_t  tp_range_timeout_timed_us;\n+\tuint32_t  tp_range_timeout_lpa_us;\n+\tuint32_t tp_phasecal_patch_power;\n+\tuint8_t tp_hist_merge;\n+\tuint32_t tp_reset_merge_threshold;\n+\tuint8_t tp_hist_merge_max_size;\n+\tuint8_t tp_uwr_enable;\n+\tint16_t tp_uwr_med_z_1_min;\n+\tint16_t tp_uwr_med_z_1_max;\n+\tint16_t tp_uwr_med_z_2_min;\n+\tint16_t tp_uwr_med_z_2_max;\n+\tint16_t tp_uwr_med_z_3_min;\n+\tint16_t tp_uwr_med_z_3_max;\n+\tint16_t tp_uwr_med_z_4_min;\n+\tint16_t tp_uwr_med_z_4_max;\n+\tint16_t tp_uwr_med_z_5_min;\n+\tint16_t tp_uwr_med_z_5_max;\n+\tint16_t tp_uwr_med_corr_z_1_rangea;\n+\tint16_t tp_uwr_med_corr_z_1_rangeb;\n+\tint16_t tp_uwr_med_corr_z_2_rangea;\n+\tint16_t tp_uwr_med_corr_z_2_rangeb;\n+\tint16_t tp_uwr_med_corr_z_3_rangea;\n+\tint16_t tp_uwr_med_corr_z_3_rangeb;\n+\tint16_t tp_uwr_med_corr_z_4_rangea;\n+\tint16_t tp_uwr_med_corr_z_4_rangeb;\n+\tint16_t tp_uwr_med_corr_z_5_rangea;\n+\tint16_t tp_uwr_med_corr_z_5_rangeb;\n+\tint16_t tp_uwr_lng_z_1_min;\n+\tint16_t tp_uwr_lng_z_1_max;\n+\tint16_t tp_uwr_lng_z_2_min;\n+\tint16_t tp_uwr_lng_z_2_max;\n+\tint16_t tp_uwr_lng_z_3_min;\n+\tint16_t tp_uwr_lng_z_3_max;\n+\tint16_t tp_uwr_lng_z_4_min;\n+\tint16_t tp_uwr_lng_z_4_max;\n+\tint16_t tp_uwr_lng_z_5_min;\n+\tint16_t tp_uwr_lng_z_5_max;\n+\tint16_t tp_uwr_lng_corr_z_1_rangea;\n+\tint16_t tp_uwr_lng_corr_z_1_rangeb;\n+\tint16_t tp_uwr_lng_corr_z_2_rangea;\n+\tint16_t tp_uwr_lng_corr_z_2_rangeb;\n+\tint16_t tp_uwr_lng_corr_z_3_rangea;\n+\tint16_t tp_uwr_lng_corr_z_3_rangeb;\n+\tint16_t tp_uwr_lng_corr_z_4_rangea;\n+\tint16_t tp_uwr_lng_corr_z_4_rangeb;\n+\tint16_t tp_uwr_lng_corr_z_5_rangea;\n+\tint16_t tp_uwr_lng_corr_z_5_rangeb;\n+} VL53LX_tuning_parm_storage_t;\n+\n+typedef struct {\n+\tuint8_t    device_test_mode;\n+\tuint8_t    VL53LX_p_005;\n+\tuint32_t   timeout_us;\n+\tuint16_t   target_count_rate_mcps;\n+\tuint16_t   min_count_rate_limit_mcps;\n+\tuint16_t   max_count_rate_limit_mcps;\n+} VL53LX_refspadchar_config_t;\n+\n+typedef struct {\n+\tVL53LX_DeviceSscArray  array_select;\n+\tuint8_t    VL53LX_p_005;\n+\tuint8_t    vcsel_start;\n+\tuint8_t    vcsel_width;\n+\tuint32_t   timeout_us;\n+\tuint16_t   rate_limit_mcps;\n+} VL53LX_ssc_config_t;\n+\n+typedef struct {\n+\tVL53LX_HistAlgoSelect  hist_algo_select;\n+\tVL53LX_HistTargetOrder hist_target_order;\n+\tuint8_t   filter_woi0;\n+\tuint8_t   filter_woi1;\n+\tVL53LX_HistAmbEstMethod hist_amb_est_method;\n+\tuint8_t   ambient_thresh_sigma0;\n+\tuint8_t   ambient_thresh_sigma1;\n+\tuint16_t  ambient_thresh_events_scaler;\n+\tint32_t   min_ambient_thresh_events;\n+\tuint16_t  noise_threshold;\n+\tint32_t   signal_total_events_limit;\n+\tuint8_t\t  sigma_estimator__sigma_ref_mm;\n+\tuint16_t  sigma_thresh;\n+\tint16_t   range_offset_mm;\n+\tuint16_t  gain_factor;\n+\tuint8_t   valid_phase_low;\n+\tuint8_t   valid_phase_high;\n+\tuint8_t   algo__consistency_check__phase_tolerance;\n+\tuint8_t   algo__consistency_check__event_sigma;\n+\tuint16_t  algo__consistency_check__event_min_spad_count;\n+\tuint16_t  algo__consistency_check__min_max_tolerance;\n+\tuint8_t   algo__crosstalk_compensation_enable;\n+\tuint32_t  algo__crosstalk_compensation_plane_offset_kcps;\n+\tint16_t   algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\tint16_t   algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\tint16_t   algo__crosstalk_detect_min_valid_range_mm;\n+\tint16_t   algo__crosstalk_detect_max_valid_range_mm;\n+\tuint16_t  algo__crosstalk_detect_max_valid_rate_kcps;\n+\tuint16_t  algo__crosstalk_detect_max_sigma_mm;\n+\tuint8_t   algo__crosstalk_detect_event_sigma;\n+\tuint16_t  algo__crosstalk_detect_min_max_tolerance;\n+} VL53LX_hist_post_process_config_t;\n+\n+typedef struct {\n+\tuint8_t   signal_thresh_sigma;\n+\tuint8_t   ambient_thresh_sigma;\n+\tint32_t   min_ambient_thresh_events;\n+\tint32_t   signal_total_events_limit;\n+\tuint16_t  target_reflectance_for_dmax_calc[VL53LX_MAX_AMBIENT_DMAX_VALUES];\n+\tuint16_t  max_effective_spads;\n+\tuint16_t  dss_config__target_total_rate_mcps;\n+\tuint8_t   dss_config__aperture_attenuation;\n+} VL53LX_hist_gen3_dmax_config_t;\n+\n+typedef struct {\n+\tuint16_t  dss_config__target_total_rate_mcps;\n+\tuint32_t  phasecal_config_timeout_us;\n+\tuint32_t  mm_config_timeout_us;\n+\tuint32_t  range_config_timeout_us;\n+\tuint8_t   num_of_samples;\n+\tint16_t   algo__crosstalk_extract_min_valid_range_mm;\n+\tint16_t   algo__crosstalk_extract_max_valid_range_mm;\n+\tuint16_t  algo__crosstalk_extract_max_valid_rate_kcps;\n+\tuint16_t  algo__crosstalk_extract_max_sigma_mm;\n+} VL53LX_xtalkextract_config_t;\n+\n+typedef struct {\n+\tuint32_t  algo__crosstalk_compensation_plane_offset_kcps;\n+\tint16_t   algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\tint16_t   algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\tuint32_t  nvm_default__crosstalk_compensation_plane_offset_kcps;\n+\tint16_t   nvm_default__crosstalk_compensation_x_plane_gradient_kcps;\n+\tint16_t   nvm_default__crosstalk_compensation_y_plane_gradient_kcps;\n+\tuint8_t   global_crosstalk_compensation_enable;\n+\tint16_t   histogram_mode_crosstalk_margin_kcps;\n+\tint16_t   lite_mode_crosstalk_margin_kcps;\n+\tuint8_t   crosstalk_range_ignore_threshold_mult;\n+\tuint16_t  crosstalk_range_ignore_threshold_rate_mcps;\n+\tint16_t   algo__crosstalk_detect_min_valid_range_mm;\n+\tint16_t   algo__crosstalk_detect_max_valid_range_mm;\n+\tuint16_t  algo__crosstalk_detect_max_valid_rate_kcps;\n+\tuint16_t  algo__crosstalk_detect_max_sigma_mm;\n+} VL53LX_xtalk_config_t;\n+\n+typedef struct {\n+\tuint16_t  dss_config__target_total_rate_mcps;\n+\tuint32_t  phasecal_config_timeout_us;\n+\tuint32_t  range_config_timeout_us;\n+\tuint32_t  mm_config_timeout_us;\n+\tuint8_t   pre_num_of_samples;\n+\tuint8_t   mm1_num_of_samples;\n+\tuint8_t   mm2_num_of_samples;\n+} VL53LX_offsetcal_config_t;\n+\n+typedef struct {\n+\tuint16_t   dss_config__target_total_rate_mcps;\n+\tuint32_t   phasecal_config_timeout_us;\n+\tuint32_t   mm_config_timeout_us;\n+\tuint32_t   range_config_timeout_us;\n+\tuint16_t   phasecal_num_of_samples;\n+\tuint16_t   zone_num_of_samples;\n+} VL53LX_zonecal_config_t;\n+\n+typedef struct {\n+\tuint8_t   global_config__spad_enables_ref_0;\n+\tuint8_t   global_config__spad_enables_ref_1;\n+\tuint8_t   global_config__spad_enables_ref_2;\n+\tuint8_t   global_config__spad_enables_ref_3;\n+\tuint8_t   global_config__spad_enables_ref_4;\n+\tuint8_t   global_config__spad_enables_ref_5;\n+\tuint8_t   global_config__ref_en_start_select;\n+\tuint8_t   ref_spad_man__num_requested_ref_spads;\n+\tuint8_t   ref_spad_man__ref_location;\n+\tuint16_t  algo__crosstalk_compensation_plane_offset_kcps;\n+\tint16_t   algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\tint16_t   algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\tuint16_t  ref_spad_char__total_rate_target_mcps;\n+\tint16_t   algo__part_to_part_range_offset_mm;\n+\tint16_t   mm_config__inner_offset_mm;\n+\tint16_t   mm_config__outer_offset_mm;\n+} VL53LX_customer_nvm_managed_t;\n+\n+typedef struct {\n+\tint16_t     cal_distance_mm;\n+\tuint16_t    cal_reflectance_pc;\n+\tuint16_t    max_samples;\n+\tuint16_t    width;\n+\tuint16_t    height;\n+\tuint16_t    peak_rate_mcps[VL53LX_NVM_PEAK_RATE_MAP_SAMPLES];\n+} VL53LX_cal_peak_rate_map_t;\n+\n+typedef struct {\n+\tuint16_t  result__mm_inner_actual_effective_spads;\n+\tuint16_t  result__mm_outer_actual_effective_spads;\n+\tuint16_t  result__mm_inner_peak_signal_count_rtn_mcps;\n+\tuint16_t  result__mm_outer_peak_signal_count_rtn_mcps;\n+} VL53LX_additional_offset_cal_data_t;\n+\n+typedef struct {\n+\tuint16_t  ref__actual_effective_spads;\n+\tuint16_t  ref__peak_signal_count_rate_mcps;\n+\tuint16_t  ref__distance_mm;\n+\tuint16_t   ref_reflectance_pc;\n+\tuint16_t   coverglass_transmission;\n+} VL53LX_dmax_calibration_data_t;\n+\n+typedef struct {\n+\tuint16_t   standard_ranging_gain_factor;\n+\tuint16_t   histogram_ranging_gain_factor;\n+} VL53LX_gain_calibration_data_t;\n+\n+typedef struct {\n+\tuint8_t   x_centre;\n+\tuint8_t   y_centre;\n+\tuint8_t   width;\n+\tuint8_t   height;\n+} VL53LX_user_zone_t;\n+\n+typedef struct {\n+\tuint8_t   x_centre;\n+\tuint8_t   y_centre;\n+} VL53LX_optical_centre_t;\n+\n+typedef struct {\n+\tuint8_t histogram_config__spad_array_selection;\n+\tuint8_t histogram_config__low_amb_even_bin_0_1;\n+\tuint8_t histogram_config__low_amb_even_bin_2_3;\n+\tuint8_t histogram_config__low_amb_even_bin_4_5;\n+\tuint8_t histogram_config__low_amb_odd_bin_0_1;\n+\tuint8_t histogram_config__low_amb_odd_bin_2_3;\n+\tuint8_t histogram_config__low_amb_odd_bin_4_5;\n+\tuint8_t histogram_config__mid_amb_even_bin_0_1;\n+\tuint8_t histogram_config__mid_amb_even_bin_2_3;\n+\tuint8_t histogram_config__mid_amb_even_bin_4_5;\n+\tuint8_t histogram_config__mid_amb_odd_bin_0_1;\n+\tuint8_t histogram_config__mid_amb_odd_bin_2;\n+\tuint8_t histogram_config__mid_amb_odd_bin_3_4;\n+\tuint8_t histogram_config__mid_amb_odd_bin_5;\n+\tuint8_t histogram_config__user_bin_offset;\n+\tuint8_t histogram_config__high_amb_even_bin_0_1;\n+\tuint8_t histogram_config__high_amb_even_bin_2_3;\n+\tuint8_t histogram_config__high_amb_even_bin_4_5;\n+\tuint8_t histogram_config__high_amb_odd_bin_0_1;\n+\tuint8_t histogram_config__high_amb_odd_bin_2_3;\n+\tuint8_t histogram_config__high_amb_odd_bin_4_5;\n+\tuint16_t histogram_config__amb_thresh_low;\n+\tuint16_t histogram_config__amb_thresh_high;\n+} VL53LX_histogram_config_t;\n+\n+typedef struct {\n+\tuint8_t             max_zones;\n+\tuint8_t             active_zones;\n+\tVL53LX_histogram_config_t multizone_hist_cfg;\n+\tVL53LX_user_zone_t user_zones[VL53LX_MAX_USER_ZONES];\n+\tuint8_t bin_config[VL53LX_MAX_USER_ZONES];\n+} VL53LX_zone_config_t;\n+\n+typedef struct {\n+\tuint8_t   i2c_slave__device_address;\n+\tuint8_t   ana_config__vhv_ref_sel_vddpix;\n+\tuint8_t   ana_config__vhv_ref_sel_vquench;\n+\tuint8_t   ana_config__reg_avdd1v2_sel;\n+\tuint8_t   ana_config__fast_osc__trim;\n+\tuint16_t  osc_measured__fast_osc__frequency;\n+\tuint8_t   vhv_config__timeout_macrop_loop_bound;\n+\tuint8_t   vhv_config__count_thresh;\n+\tuint8_t   vhv_config__offset;\n+\tuint8_t   vhv_config__init;\n+} VL53LX_static_nvm_managed_t;\n+\n+typedef struct {\n+\tuint32_t  VL53LX_p_037;\n+\tuint8_t   VL53LX_p_063;\n+\tuint8_t   VL53LX_p_064;\n+\tuint16_t   VL53LX_p_065;\n+\tuint16_t   VL53LX_p_066;\n+\tuint16_t   VL53LX_p_067;\n+\tuint16_t   VL53LX_p_038;\n+\tuint32_t   VL53LX_p_009;\n+\tuint32_t   VL53LX_p_033;\n+\tuint16_t   VL53LX_p_034;\n+\tuint16_t   VL53LX_p_004;\n+\tuint32_t   VL53LX_p_028;\n+\tuint32_t   VL53LX_p_035;\n+\tint16_t    VL53LX_p_036;\n+\tint16_t    VL53LX_p_022;\n+} VL53LX_hist_gen3_dmax_private_data_t;\n+\n+typedef struct {\n+\tuint16_t  dss_config__target_total_rate_mcps;\n+\tuint8_t   debug__ctrl;\n+\tuint8_t   test_mode__ctrl;\n+\tuint8_t   clk_gating__ctrl;\n+\tuint8_t   nvm_bist__ctrl;\n+\tuint8_t   nvm_bist__num_nvm_words;\n+\tuint8_t   nvm_bist__start_address;\n+\tuint8_t   host_if__status;\n+\tuint8_t   pad_i2c_hv__config;\n+\tuint8_t   pad_i2c_hv__extsup_config;\n+\tuint8_t   gpio_hv_pad__ctrl;\n+\tuint8_t   gpio_hv_mux__ctrl;\n+\tuint8_t   gpio__tio_hv_status;\n+\tuint8_t   gpio__fio_hv_status;\n+\tuint8_t   ana_config__spad_sel_pswidth;\n+\tuint8_t   ana_config__vcsel_pulse_width_offset;\n+\tuint8_t   ana_config__fast_osc__config_ctrl;\n+\tuint8_t   sigma_estimator__effective_pulse_width_ns;\n+\tuint8_t   sigma_estimator__effective_ambient_width_ns;\n+\tuint8_t   sigma_estimator__sigma_ref_mm;\n+\tuint8_t   algo__crosstalk_compensation_valid_height_mm;\n+\tuint8_t   spare_host_config__static_config_spare_0;\n+\tuint8_t   spare_host_config__static_config_spare_1;\n+\tuint16_t  algo__range_ignore_threshold_mcps;\n+\tuint8_t   algo__range_ignore_valid_height_mm;\n+\tuint8_t   algo__range_min_clip;\n+\tuint8_t   algo__consistency_check__tolerance;\n+\tuint8_t   spare_host_config__static_config_spare_2;\n+\tuint8_t   sd_config__reset_stages_msb;\n+\tuint8_t   sd_config__reset_stages_lsb;\n+} VL53LX_static_config_t;\n+\n+typedef struct {\n+\tuint8_t   gph_config__stream_count_update_value;\n+\tuint8_t   global_config__stream_divider;\n+\tuint8_t   system__interrupt_config_gpio;\n+\tuint8_t   cal_config__vcsel_start;\n+\tuint16_t  cal_config__repeat_rate;\n+\tuint8_t   global_config__vcsel_width;\n+\tuint8_t   phasecal_config__timeout_macrop;\n+\tuint8_t   phasecal_config__target;\n+\tuint8_t   phasecal_config__override;\n+\tuint8_t   dss_config__roi_mode_control;\n+\tuint16_t  system__thresh_rate_high;\n+\tuint16_t  system__thresh_rate_low;\n+\tuint16_t  dss_config__manual_effective_spads_select;\n+\tuint8_t   dss_config__manual_block_select;\n+\tuint8_t   dss_config__aperture_attenuation;\n+\tuint8_t   dss_config__max_spads_limit;\n+\tuint8_t   dss_config__min_spads_limit;\n+} VL53LX_general_config_t;\n+\n+typedef struct {\n+\tuint8_t   mm_config__timeout_macrop_a_hi;\n+\tuint8_t   mm_config__timeout_macrop_a_lo;\n+\tuint8_t   mm_config__timeout_macrop_b_hi;\n+\tuint8_t   mm_config__timeout_macrop_b_lo;\n+\tuint8_t   range_config__timeout_macrop_a_hi;\n+\tuint8_t   range_config__timeout_macrop_a_lo;\n+\tuint8_t   range_config__vcsel_period_a;\n+\tuint8_t   range_config__timeout_macrop_b_hi;\n+\tuint8_t   range_config__timeout_macrop_b_lo;\n+\tuint8_t   range_config__vcsel_period_b;\n+\tuint16_t  range_config__sigma_thresh;\n+\tuint16_t  range_config__min_count_rate_rtn_limit_mcps;\n+\tuint8_t   range_config__valid_phase_low;\n+\tuint8_t   range_config__valid_phase_high;\n+\tuint32_t  system__intermeasurement_period;\n+\tuint8_t   system__fractional_enable;\n+} VL53LX_timing_config_t;\n+\n+typedef struct {\n+\tuint8_t   system__grouped_parameter_hold_0;\n+\tuint16_t  system__thresh_high;\n+\tuint16_t  system__thresh_low;\n+\tuint8_t   system__enable_xtalk_per_quadrant;\n+\tuint8_t   system__seed_config;\n+\tuint8_t   sd_config__woi_sd0;\n+\tuint8_t   sd_config__woi_sd1;\n+\tuint8_t   sd_config__initial_phase_sd0;\n+\tuint8_t   sd_config__initial_phase_sd1;\n+\tuint8_t   system__grouped_parameter_hold_1;\n+\tuint8_t   sd_config__first_order_select;\n+\tuint8_t   sd_config__quantifier;\n+\tuint8_t   roi_config__user_roi_centre_spad;\n+\tuint8_t   roi_config__user_roi_requested_global_xy_size;\n+\tuint8_t   system__sequence_config;\n+\tuint8_t   system__grouped_parameter_hold;\n+} VL53LX_dynamic_config_t;\n+\n+typedef struct {\n+\tuint8_t   power_management__go1_power_force;\n+\tuint8_t   system__stream_count_ctrl;\n+\tuint8_t   firmware__enable;\n+\tuint8_t   system__interrupt_clear;\n+\tuint8_t   system__mode_start;\n+} VL53LX_system_control_t;\n+\n+typedef struct {\n+\tuint8_t   result__interrupt_status;\n+\tuint8_t   result__range_status;\n+\tuint8_t   result__report_status;\n+\tuint8_t   result__stream_count;\n+\tuint16_t  result__dss_actual_effective_spads_sd0;\n+\tuint16_t  result__peak_signal_count_rate_mcps_sd0;\n+\tuint16_t  result__ambient_count_rate_mcps_sd0;\n+\tuint16_t  result__sigma_sd0;\n+\tuint16_t  result__phase_sd0;\n+\tuint16_t  result__final_crosstalk_corrected_range_mm_sd0;\n+\tuint16_t  result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0;\n+\tuint16_t  result__mm_inner_actual_effective_spads_sd0;\n+\tuint16_t  result__mm_outer_actual_effective_spads_sd0;\n+\tuint16_t  result__avg_signal_count_rate_mcps_sd0;\n+\tuint16_t  result__dss_actual_effective_spads_sd1;\n+\tuint16_t  result__peak_signal_count_rate_mcps_sd1;\n+\tuint16_t  result__ambient_count_rate_mcps_sd1;\n+\tuint16_t  result__sigma_sd1;\n+\tuint16_t  result__phase_sd1;\n+\tuint16_t  result__final_crosstalk_corrected_range_mm_sd1;\n+\tuint16_t  result__spare_0_sd1;\n+\tuint16_t  result__spare_1_sd1;\n+\tuint16_t  result__spare_2_sd1;\n+\tuint8_t   result__spare_3_sd1;\n+\tuint8_t   result__thresh_info;\n+} VL53LX_system_results_t;\n+\n+typedef struct {\n+\tuint8_t   identification__model_id;\n+\tuint8_t   identification__module_type;\n+\tuint8_t   identification__revision_id;\n+\tuint16_t  identification__module_id;\n+\tuint8_t   ana_config__fast_osc__trim_max;\n+\tuint8_t   ana_config__fast_osc__freq_set;\n+\tuint8_t   ana_config__vcsel_trim;\n+\tuint8_t   ana_config__vcsel_selion;\n+\tuint8_t   ana_config__vcsel_selion_max;\n+\tuint8_t   protected_laser_safety__lock_bit;\n+\tuint8_t   laser_safety__key;\n+\tuint8_t   laser_safety__key_ro;\n+\tuint8_t   laser_safety__clip;\n+\tuint8_t   laser_safety__mult;\n+\tuint8_t   global_config__spad_enables_rtn_0;\n+\tuint8_t   global_config__spad_enables_rtn_1;\n+\tuint8_t   global_config__spad_enables_rtn_2;\n+\tuint8_t   global_config__spad_enables_rtn_3;\n+\tuint8_t   global_config__spad_enables_rtn_4;\n+\tuint8_t   global_config__spad_enables_rtn_5;\n+\tuint8_t   global_config__spad_enables_rtn_6;\n+\tuint8_t   global_config__spad_enables_rtn_7;\n+\tuint8_t   global_config__spad_enables_rtn_8;\n+\tuint8_t   global_config__spad_enables_rtn_9;\n+\tuint8_t   global_config__spad_enables_rtn_10;\n+\tuint8_t   global_config__spad_enables_rtn_11;\n+\tuint8_t   global_config__spad_enables_rtn_12;\n+\tuint8_t   global_config__spad_enables_rtn_13;\n+\tuint8_t   global_config__spad_enables_rtn_14;\n+\tuint8_t   global_config__spad_enables_rtn_15;\n+\tuint8_t   global_config__spad_enables_rtn_16;\n+\tuint8_t   global_config__spad_enables_rtn_17;\n+\tuint8_t   global_config__spad_enables_rtn_18;\n+\tuint8_t   global_config__spad_enables_rtn_19;\n+\tuint8_t   global_config__spad_enables_rtn_20;\n+\tuint8_t   global_config__spad_enables_rtn_21;\n+\tuint8_t   global_config__spad_enables_rtn_22;\n+\tuint8_t   global_config__spad_enables_rtn_23;\n+\tuint8_t   global_config__spad_enables_rtn_24;\n+\tuint8_t   global_config__spad_enables_rtn_25;\n+\tuint8_t   global_config__spad_enables_rtn_26;\n+\tuint8_t   global_config__spad_enables_rtn_27;\n+\tuint8_t   global_config__spad_enables_rtn_28;\n+\tuint8_t   global_config__spad_enables_rtn_29;\n+\tuint8_t   global_config__spad_enables_rtn_30;\n+\tuint8_t   global_config__spad_enables_rtn_31;\n+\tuint8_t   roi_config__mode_roi_centre_spad;\n+\tuint8_t   roi_config__mode_roi_xy_size;\n+} VL53LX_nvm_copy_data_t;\n+\n+typedef struct {\n+\tVL53LX_DeviceState     cfg_device_state;\n+\tVL53LX_DeviceState     rd_device_state;\n+\tuint8_t  zone_id;\n+\tuint32_t time_stamp;\n+\tuint8_t  VL53LX_p_019;\n+\tuint8_t  VL53LX_p_020;\n+\tuint8_t  VL53LX_p_021;\n+\tuint8_t  number_of_ambient_bins;\n+\tuint8_t  bin_seq[VL53LX_MAX_BIN_SEQUENCE_LENGTH];\n+\tuint8_t  bin_rep[VL53LX_MAX_BIN_SEQUENCE_LENGTH];\n+\tint32_t  bin_data[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tuint8_t  result__interrupt_status;\n+\tuint8_t  result__range_status;\n+\tuint8_t  result__report_status;\n+\tuint8_t  result__stream_count;\n+\tuint16_t result__dss_actual_effective_spads;\n+\tuint16_t phasecal_result__reference_phase;\n+\tuint8_t  phasecal_result__vcsel_start;\n+\tuint8_t  cal_config__vcsel_start;\n+\tuint16_t vcsel_width;\n+\tuint8_t  VL53LX_p_005;\n+\tuint16_t VL53LX_p_015;\n+\tuint32_t  total_periods_elapsed;\n+\tuint32_t peak_duration_us;\n+\tuint32_t woi_duration_us;\n+\tint32_t  min_bin_value;\n+\tint32_t  max_bin_value;\n+\tuint16_t zero_distance_phase;\n+\tuint8_t  number_of_ambient_samples;\n+\tint32_t  ambient_events_sum;\n+\tint32_t  VL53LX_p_028;\n+\tuint8_t  roi_config__user_roi_centre_spad;\n+\tuint8_t  roi_config__user_roi_requested_global_xy_size;\n+} VL53LX_histogram_bin_data_t;\n+\n+typedef struct {\n+\tuint8_t  zone_id;\n+\tuint32_t time_stamp;\n+\tuint8_t  VL53LX_p_019;\n+\tuint8_t  VL53LX_p_020;\n+\tuint8_t  VL53LX_p_021;\n+\tuint32_t bin_data[VL53LX_XTALK_HISTO_BINS];\n+\tuint16_t phasecal_result__reference_phase;\n+\tuint8_t  phasecal_result__vcsel_start;\n+\tuint8_t  cal_config__vcsel_start;\n+\tuint16_t vcsel_width;\n+\tuint16_t VL53LX_p_015;\n+\tuint16_t zero_distance_phase;\n+} VL53LX_xtalk_histogram_shape_t;\n+\n+typedef struct {\n+\tVL53LX_xtalk_histogram_shape_t  xtalk_shape;\n+\tVL53LX_histogram_bin_data_t     xtalk_hist_removed;\n+} VL53LX_xtalk_histogram_data_t;\n+\n+typedef struct {\n+\tuint8_t    no_of_samples;\n+\tuint32_t   rate_per_spad_kcps_sum;\n+\tuint32_t   rate_per_spad_kcps_avg;\n+\tint32_t    signal_total_events_sum;\n+\tint32_t    signal_total_events_avg;\n+\tuint32_t   sigma_mm_sum;\n+\tuint32_t   sigma_mm_avg;\n+\tuint32_t   median_phase_sum;\n+\tuint32_t   median_phase_avg;\n+} VL53LX_xtalk_range_data_t;\n+\n+typedef struct {\n+\tVL53LX_Error                cal_status;\n+\tuint8_t                     num_of_samples_status;\n+\tuint8_t                     zero_samples_status;\n+\tuint8_t                     max_sigma_status;\n+\tuint8_t                     max_results;\n+\tuint8_t                     active_results;\n+\tVL53LX_xtalk_range_data_t VL53LX_p_003[VL53LX_MAX_XTALK_RANGE_RESULTS];\n+\tVL53LX_histogram_bin_data_t central_histogram_sum;\n+\tVL53LX_histogram_bin_data_t central_histogram_avg;\n+\tuint8_t central_histogram__window_start;\n+\tuint8_t central_histogram__window_end;\n+\tVL53LX_histogram_bin_data_t histogram_avg_1[VL53LX_MAX_XTALK_RANGE_RESULTS];\n+\tVL53LX_histogram_bin_data_t histogram_avg_2[VL53LX_MAX_XTALK_RANGE_RESULTS];\n+\tVL53LX_histogram_bin_data_t xtalk_avg[VL53LX_MAX_XTALK_RANGE_RESULTS];\n+} VL53LX_xtalk_range_results_t;\n+\n+typedef struct {\n+\tuint32_t  algo__crosstalk_compensation_plane_offset_kcps;\n+\tint16_t   algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\tint16_t   algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\tuint32_t  algo__xtalk_cpo_HistoMerge_kcps[VL53LX_BIN_REC_SIZE];\n+} VL53LX_xtalk_calibration_results_t;\n+\n+typedef struct {\n+\tuint32_t   sample_count;\n+\tuint32_t   pll_period_mm;\n+\tuint32_t   peak_duration_us_sum;\n+\tuint32_t   effective_spad_count_sum;\n+\tuint32_t   zero_distance_phase_sum;\n+\tuint32_t   zero_distance_phase_avg;\n+\tint32_t    event_scaler_sum;\n+\tint32_t    event_scaler_avg;\n+\tint32_t   signal_events_sum;\n+\tuint32_t  xtalk_rate_kcps_per_spad;\n+\tint32_t   xtalk_start_phase;\n+\tint32_t   xtalk_end_phase;\n+\tint32_t   xtalk_width_phase;\n+\tint32_t   target_start_phase;\n+\tint32_t   target_end_phase;\n+\tint32_t   target_width_phase;\n+\tint32_t   effective_width;\n+\tint32_t   event_scaler;\n+\tuint8_t   VL53LX_p_012;\n+\tuint8_t   VL53LX_p_013;\n+\tuint8_t   target_start;\n+\tint32_t   max_shape_value;\n+\tint32_t   bin_data_sums[VL53LX_XTALK_HISTO_BINS];\n+} VL53LX_hist_xtalk_extract_data_t;\n+\n+typedef struct {\n+\tuint8_t    preset_mode;\n+\tuint8_t    dss_config__roi_mode_control;\n+\tuint16_t   dss_config__manual_effective_spads_select;\n+\tuint8_t    no_of_samples;\n+\tuint32_t   effective_spads;\n+\tuint32_t   peak_rate_mcps;\n+\tuint32_t   VL53LX_p_002;\n+\tint32_t    median_range_mm;\n+\tint32_t    range_mm_offset;\n+} VL53LX_offset_range_data_t;\n+\n+typedef struct {\n+\tint16_t      cal_distance_mm;\n+\tuint16_t     cal_reflectance_pc;\n+\tVL53LX_Error cal_status;\n+\tuint8_t      cal_report;\n+\tuint8_t      max_results;\n+\tuint8_t      active_results;\n+\tVL53LX_offset_range_data_t VL53LX_p_003[VL53LX_MAX_OFFSET_RANGE_RESULTS];\n+} VL53LX_offset_range_results_t;\n+\n+typedef struct {\n+\tuint32_t  result_core__ambient_window_events_sd0;\n+\tuint32_t  result_core__ranging_total_events_sd0;\n+\tint32_t   result_core__signal_total_events_sd0;\n+\tuint32_t  result_core__total_periods_elapsed_sd0;\n+\tuint32_t  result_core__ambient_window_events_sd1;\n+\tuint32_t  result_core__ranging_total_events_sd1;\n+\tint32_t   result_core__signal_total_events_sd1;\n+\tuint32_t  result_core__total_periods_elapsed_sd1;\n+\tuint8_t   result_core__spare_0;\n+} VL53LX_core_results_t;\n+\n+typedef struct {\n+\n+\tuint16_t  result__actual_effective_rtn_spads;\n+\tuint8_t   ref_spad_array__num_requested_ref_spads;\n+\tuint8_t   ref_spad_array__ref_location;\n+\tuint16_t  result__peak_signal_count_rate_rtn_mcps;\n+\tuint16_t  result__ambient_count_rate_rtn_mcps;\n+\tuint16_t  result__peak_signal_count_rate_ref_mcps;\n+\tuint16_t  result__ambient_count_rate_ref_mcps;\n+\tuint16_t  measured_distance_mm;\n+\tuint16_t  measured_distance_stdev_mm;\n+} VL53LX_decoded_nvm_fmt_range_data_t;\n+\n+typedef struct {\n+\tuint16_t  phasecal_result__reference_phase;\n+\tuint8_t   phasecal_result__vcsel_start;\n+\tuint8_t   ref_spad_char_result__num_actual_ref_spads;\n+\tuint8_t   ref_spad_char_result__ref_location;\n+\tuint8_t   vhv_result__coldboot_status;\n+\tuint8_t   vhv_result__search_result;\n+\tuint8_t   vhv_result__latest_setting;\n+\tuint16_t  result__osc_calibrate_val;\n+\tuint8_t   ana_config__powerdown_go1;\n+\tuint8_t   ana_config__ref_bg_ctrl;\n+\tuint8_t   ana_config__regdvdd1v2_ctrl;\n+\tuint8_t   ana_config__osc_slow_ctrl;\n+\tuint8_t   test_mode__status;\n+\tuint8_t   firmware__system_status;\n+\tuint8_t   firmware__mode_status;\n+\tuint8_t   firmware__secondary_mode_status;\n+\tuint16_t  firmware__cal_repeat_rate_counter;\n+\tuint16_t  gph__system__thresh_high;\n+\tuint16_t  gph__system__thresh_low;\n+\tuint8_t   gph__system__enable_xtalk_per_quadrant;\n+\tuint8_t   gph__spare_0;\n+\tuint8_t   gph__sd_config__woi_sd0;\n+\tuint8_t   gph__sd_config__woi_sd1;\n+\tuint8_t   gph__sd_config__initial_phase_sd0;\n+\tuint8_t   gph__sd_config__initial_phase_sd1;\n+\tuint8_t   gph__sd_config__first_order_select;\n+\tuint8_t   gph__sd_config__quantifier;\n+\tuint8_t   gph__roi_config__user_roi_centre_spad;\n+\tuint8_t   gph__roi_config__user_roi_requested_global_xy_size;\n+\tuint8_t   gph__system__sequence_config;\n+\tuint8_t   gph__gph_id;\n+\tuint8_t   system__interrupt_set;\n+\tuint8_t   interrupt_manager__enables;\n+\tuint8_t   interrupt_manager__clear;\n+\tuint8_t   interrupt_manager__status;\n+\tuint8_t   mcu_to_host_bank__wr_access_en;\n+\tuint8_t   power_management__go1_reset_status;\n+\tuint8_t   pad_startup_mode__value_ro;\n+\tuint8_t   pad_startup_mode__value_ctrl;\n+\tuint32_t  pll_period_us;\n+\tuint32_t  interrupt_scheduler__data_out;\n+\tuint8_t   nvm_bist__complete;\n+\tuint8_t   nvm_bist__status;\n+} VL53LX_debug_results_t;\n+\n+typedef struct {\n+\tuint8_t\tsmudge_corr_enabled;\n+\tuint8_t\tsmudge_corr_apply_enabled;\n+\tuint8_t\tsmudge_corr_single_apply;\n+\tuint16_t\tsmudge_margin;\n+\tuint32_t\tnoise_margin;\n+\tuint32_t\tuser_xtalk_offset_limit;\n+\tuint8_t\tuser_xtalk_offset_limit_hi;\n+\tuint32_t\tsample_limit;\n+\tuint32_t\tsingle_xtalk_delta;\n+\tuint32_t\taveraged_xtalk_delta;\n+\tuint32_t\tsmudge_corr_clip_limit;\n+\tuint32_t\tsmudge_corr_ambient_threshold;\n+\tuint8_t\tscaler_calc_method;\n+\tint16_t\tx_gradient_scaler;\n+\tint16_t\ty_gradient_scaler;\n+\tuint8_t\tuser_scaler_set;\n+\tuint32_t nodetect_ambient_threshold;\n+\tuint32_t nodetect_sample_limit;\n+\tuint32_t nodetect_xtalk_offset;\n+\tuint16_t nodetect_min_range_mm;\n+\tuint32_t max_smudge_factor;\n+} VL53LX_smudge_corrector_config_t;\n+\n+typedef struct {\n+\tuint32_t\tcurrent_samples;\n+\tuint32_t\trequired_samples;\n+\tuint64_t\taccumulator;\n+\tuint32_t\tnodetect_counter;\n+} VL53LX_smudge_corrector_internals_t;\n+\n+typedef struct {\n+\tuint8_t\t\tvhv_loop_bound;\n+\tuint8_t\t\tis_low_power_auto_mode;\n+\tuint8_t\t\tlow_power_auto_range_count;\n+\tuint8_t\t\tsaved_interrupt_config;\n+\tuint8_t\t\tsaved_vhv_init;\n+\tuint8_t\t\tsaved_vhv_timeout;\n+\tuint8_t\t\tfirst_run_phasecal_result;\n+\tuint32_t\tdss__total_rate_per_spad_mcps;\n+\tuint16_t\tdss__required_spads;\n+} VL53LX_low_power_auto_data_t;\n+\n+typedef struct {\n+\tint16_t   short_a_offset_mm;\n+\tint16_t   short_b_offset_mm;\n+\tint16_t   medium_a_offset_mm;\n+\tint16_t   medium_b_offset_mm;\n+\tint16_t   long_a_offset_mm;\n+\tint16_t   long_b_offset_mm;\n+} VL53LX_per_vcsel_period_offset_cal_data_t;\n+\n+typedef struct {\n+\tuint8_t   wait_method;\n+\tVL53LX_DevicePresetModes        preset_mode;\n+\tVL53LX_DeviceZonePreset         zone_preset;\n+\tVL53LX_DeviceMeasurementModes   measurement_mode;\n+\tVL53LX_OffsetCalibrationMode    offset_calibration_mode;\n+\tVL53LX_OffsetCorrectionMode     offset_correction_mode;\n+\tVL53LX_DeviceDmaxMode           dmax_mode;\n+\tuint32_t  phasecal_config_timeout_us;\n+\tuint32_t  mm_config_timeout_us;\n+\tuint32_t  range_config_timeout_us;\n+\tuint32_t  inter_measurement_period_ms;\n+\tuint16_t  dss_config__target_total_rate_mcps;\n+\tuint32_t  fw_ready_poll_duration_ms;\n+\tuint8_t   fw_ready;\n+\tuint8_t   debug_mode;\n+\tVL53LX_ll_version_t                 version;\n+\tVL53LX_ll_driver_state_t            ll_state;\n+\tVL53LX_GPIO_interrupt_config_t\t    gpio_interrupt_config;\n+\tVL53LX_customer_nvm_managed_t       customer;\n+\tVL53LX_cal_peak_rate_map_t          cal_peak_rate_map;\n+\tVL53LX_additional_offset_cal_data_t add_off_cal_data;\n+\tVL53LX_dmax_calibration_data_t      fmt_dmax_cal;\n+\tVL53LX_dmax_calibration_data_t      cust_dmax_cal;\n+\tVL53LX_gain_calibration_data_t      gain_cal;\n+\tVL53LX_user_zone_t                  mm_roi;\n+\tVL53LX_optical_centre_t             optical_centre;\n+\tVL53LX_zone_config_t                zone_cfg;\n+\tVL53LX_tuning_parm_storage_t        tuning_parms;\n+\tuint8_t rtn_good_spads[VL53LX_RTN_SPAD_BUFFER_SIZE];\n+\tVL53LX_refspadchar_config_t         refspadchar;\n+\tVL53LX_ssc_config_t                 ssc_cfg;\n+\tVL53LX_hist_post_process_config_t   histpostprocess;\n+\tVL53LX_hist_gen3_dmax_config_t      dmax_cfg;\n+\tVL53LX_xtalkextract_config_t        xtalk_extract_cfg;\n+\tVL53LX_xtalk_config_t               xtalk_cfg;\n+\tVL53LX_offsetcal_config_t           offsetcal_cfg;\n+\tVL53LX_zonecal_config_t             zonecal_cfg;\n+\tVL53LX_static_nvm_managed_t         stat_nvm;\n+\tVL53LX_histogram_config_t           hist_cfg;\n+\tVL53LX_static_config_t              stat_cfg;\n+\tVL53LX_general_config_t             gen_cfg;\n+\tVL53LX_timing_config_t              tim_cfg;\n+\tVL53LX_dynamic_config_t             dyn_cfg;\n+\tVL53LX_system_control_t             sys_ctrl;\n+\tVL53LX_system_results_t             sys_results;\n+\tVL53LX_nvm_copy_data_t              nvm_copy_data;\n+\tVL53LX_histogram_bin_data_t         hist_data;\n+\tVL53LX_histogram_bin_data_t         hist_xtalk;\n+\tVL53LX_xtalk_histogram_data_t       xtalk_shapes;\n+\tVL53LX_xtalk_range_results_t        xtalk_results;\n+\tVL53LX_xtalk_calibration_results_t  xtalk_cal;\n+\tVL53LX_hist_xtalk_extract_data_t    xtalk_extract;\n+\tVL53LX_offset_range_results_t       offset_results;\n+\tVL53LX_core_results_t               core_results;\n+\tVL53LX_debug_results_t              dbg_results;\n+\tVL53LX_smudge_corrector_config_t\tsmudge_correct_config;\n+\tVL53LX_smudge_corrector_internals_t smudge_corrector_internals;\n+\tVL53LX_low_power_auto_data_t\t\tlow_power_auto_data;\n+\tuint8_t  wArea1[1536];\n+\tuint8_t  wArea2[512];\n+\tVL53LX_per_vcsel_period_offset_cal_data_t per_vcsel_cal_data;\n+\tuint8_t bin_rec_pos;\n+\tuint8_t pos_before_next_recom;\n+\tint32_t  multi_bins_rec[VL53LX_BIN_REC_SIZE][VL53LX_TIMING_CONF_A_B_SIZE][VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tint16_t PreviousRangeMilliMeter[VL53LX_MAX_RANGE_RESULTS];\n+\tuint8_t PreviousRangeStatus[VL53LX_MAX_RANGE_RESULTS];\n+\tuint8_t PreviousExtendedRange[VL53LX_MAX_RANGE_RESULTS];\n+\tuint8_t PreviousRangeActiveResults;\n+\tuint8_t PreviousStreamCount;\n+} VL53LX_LLDriverData_t;\n+\n+typedef struct {\n+\tuint8_t      expected_stream_count;\n+\tuint8_t      expected_gph_id;\n+\tuint8_t      dss_mode;\n+\tuint16_t     dss_requested_effective_spad_count;\n+\tuint8_t      seed_cfg;\n+\tuint8_t      initial_phase_seed;\n+\tuint8_t  roi_config__user_roi_centre_spad;\n+\tuint8_t  roi_config__user_roi_requested_global_xy_size;\n+} VL53LX_zone_private_dyn_cfg_t;\n+\n+typedef struct {\n+\tuint8_t                     max_zones;\n+\tuint8_t                     active_zones;\n+\tVL53LX_zone_private_dyn_cfg_t VL53LX_p_003[VL53LX_MAX_USER_ZONES];\n+} VL53LX_zone_private_dyn_cfgs_t;\n+\n+typedef struct {\n+\tuint8_t  range_id;\n+\tuint32_t time_stamp;\n+\tuint8_t  VL53LX_p_012;\n+\tuint8_t  VL53LX_p_019;\n+\tuint8_t  VL53LX_p_023;\n+\tuint8_t  VL53LX_p_024;\n+\tuint8_t  VL53LX_p_013;\n+\tuint8_t  VL53LX_p_025;\n+\tuint16_t   width;\n+\tuint8_t    VL53LX_p_029;\n+\tuint16_t   fast_osc_frequency;\n+\tuint16_t   zero_distance_phase;\n+\tuint16_t   VL53LX_p_004;\n+\tuint32_t   total_periods_elapsed;\n+\tuint32_t   peak_duration_us;\n+\tuint32_t   woi_duration_us;\n+\tuint32_t   VL53LX_p_016;\n+\tuint32_t   VL53LX_p_017;\n+\tint32_t    VL53LX_p_010;\n+\tuint16_t    peak_signal_count_rate_mcps;\n+\tuint16_t    avg_signal_count_rate_mcps;\n+\tuint16_t    ambient_count_rate_mcps;\n+\tuint16_t    total_rate_per_spad_mcps;\n+\tuint32_t    VL53LX_p_009;\n+\tuint16_t   VL53LX_p_002;\n+\tuint16_t   VL53LX_p_026;\n+\tuint16_t   VL53LX_p_011;\n+\tuint16_t   VL53LX_p_027;\n+\tint16_t    min_range_mm;\n+\tint16_t    median_range_mm;\n+\tint16_t    max_range_mm;\n+\tuint8_t    range_status;\n+} VL53LX_range_data_t;\n+\n+typedef struct {\n+\tuint8_t\tsmudge_corr_valid;\n+\tuint8_t\tsmudge_corr_clipped;\n+\tuint8_t\tsingle_xtalk_delta_flag;\n+\tuint8_t\taveraged_xtalk_delta_flag;\n+\tuint8_t\tsample_limit_exceeded_flag;\n+\tuint8_t gradient_zero_flag;\n+\tuint8_t new_xtalk_applied_flag;\n+\tuint32_t  algo__crosstalk_compensation_plane_offset_kcps;\n+\tint16_t   algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\tint16_t   algo__crosstalk_compensation_y_plane_gradient_kcps;\n+} VL53LX_smudge_corrector_data_t;\n+\n+typedef struct {\n+\tVL53LX_DeviceState     cfg_device_state;\n+\tVL53LX_DeviceState     rd_device_state;\n+\tuint8_t                zone_id;\n+\tuint8_t                stream_count;\n+\tint16_t                VL53LX_p_022[VL53LX_MAX_AMBIENT_DMAX_VALUES];\n+\tint16_t                wrap_dmax_mm;\n+\tuint8_t                device_status;\n+\tuint8_t                max_results;\n+\tuint8_t                active_results;\n+\tVL53LX_range_data_t    VL53LX_p_003[VL53LX_MAX_RANGE_RESULTS];\n+\tVL53LX_range_data_t    xmonitor;\n+\tVL53LX_smudge_corrector_data_t smudge_corrector_data;\n+} VL53LX_range_results_t;\n+\n+typedef struct {\n+\tuint8_t                max_zones;\n+\tuint8_t                active_zones;\n+\tVL53LX_zone_objects_t VL53LX_p_003[VL53LX_MAX_USER_ZONES];\n+} VL53LX_zone_results_t;\n+\n+typedef struct {\n+\tVL53LX_DeviceState     rd_device_state;\n+\tuint8_t  number_of_ambient_bins;\n+\tuint16_t result__dss_actual_effective_spads;\n+\tuint8_t  VL53LX_p_005;\n+\tuint32_t total_periods_elapsed;\n+\tint32_t  ambient_events_sum;\n+} VL53LX_zone_hist_info_t;\n+\n+typedef struct {\n+\tuint8_t                     max_zones;\n+\tuint8_t                     active_zones;\n+\tVL53LX_zone_hist_info_t     VL53LX_p_003[VL53LX_MAX_USER_ZONES];\n+} VL53LX_zone_histograms_t;\n+\n+typedef struct {\n+\tuint32_t   no_of_samples;\n+\tuint32_t   effective_spads;\n+\tuint32_t   peak_rate_mcps;\n+\tuint32_t   VL53LX_p_011;\n+\tuint32_t   VL53LX_p_002;\n+\tint32_t    median_range_mm;\n+\tint32_t    range_mm_offset;\n+} VL53LX_zone_calibration_data_t;\n+\n+typedef struct {\n+\tuint32_t                         struct_version;\n+\tVL53LX_DevicePresetModes         preset_mode;\n+\tVL53LX_DeviceZonePreset          zone_preset;\n+\tint16_t                          cal_distance_mm;\n+\tuint16_t                         cal_reflectance_pc;\n+\tuint16_t                         phasecal_result__reference_phase;\n+\tuint16_t                         zero_distance_phase;\n+\tVL53LX_Error                     cal_status;\n+\tuint8_t                          max_zones;\n+\tuint8_t                          active_zones;\n+\tVL53LX_zone_calibration_data_t   VL53LX_p_003[VL53LX_MAX_USER_ZONES];\n+} VL53LX_zone_calibration_results_t;\n+\n+typedef struct {\n+\tVL53LX_range_results_t             range_results;\n+\tVL53LX_zone_private_dyn_cfgs_t     zone_dyn_cfgs;\n+\tVL53LX_zone_results_t              zone_results;\n+\tVL53LX_zone_histograms_t           zone_hists;\n+\tVL53LX_zone_calibration_results_t  zone_cal;\n+} VL53LX_LLDriverResults_t;\n+\n+typedef struct {\n+\tVL53LX_DistanceModes DistanceMode;\n+\tuint32_t MeasurementTimingBudgetMicroSeconds;\n+} VL53LX_DeviceParameters_t;\n+\n+typedef struct {\n+\tVL53LX_LLDriverData_t   LLData;\n+\tVL53LX_LLDriverResults_t llresults;\n+\tVL53LX_DeviceParameters_t CurrentParameters;\n+} VL53LX_DevData_t;\n+\n+typedef struct {\n+\tuint8_t   global_config__spad_enables_ref_0;\n+\tuint8_t   global_config__spad_enables_ref_1;\n+\tuint8_t   global_config__spad_enables_ref_2;\n+\tuint8_t   global_config__spad_enables_ref_3;\n+\tuint8_t   global_config__spad_enables_ref_4;\n+\tuint8_t   global_config__spad_enables_ref_5;\n+\tuint8_t   global_config__ref_en_start_select;\n+\tuint8_t   ref_spad_man__num_requested_ref_spads;\n+\tuint8_t   ref_spad_man__ref_location;\n+\tuint32_t  algo__crosstalk_compensation_plane_offset_kcps;\n+\tint16_t   algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\tint16_t   algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\tuint16_t  ref_spad_char__total_rate_target_mcps;\n+\tint16_t   algo__part_to_part_range_offset_mm;\n+\tint16_t   mm_config__inner_offset_mm;\n+\tint16_t   mm_config__outer_offset_mm;\n+} VL53LX_CustomerNvmManaged_t;\n+\n+typedef struct {\n+\tuint32_t                             struct_version;\n+\tVL53LX_CustomerNvmManaged_t          customer;\n+\tVL53LX_additional_offset_cal_data_t  add_off_cal_data;\n+\tVL53LX_optical_centre_t              optical_centre;\n+\tVL53LX_xtalk_histogram_data_t        xtalkhisto;\n+\tVL53LX_gain_calibration_data_t       gain_cal;\n+\tVL53LX_cal_peak_rate_map_t           cal_peak_rate_map;\n+\tVL53LX_per_vcsel_period_offset_cal_data_t per_vcsel_cal_data;\n+\tuint32_t  algo__xtalk_cpo_HistoMerge_kcps[VL53LX_BIN_REC_SIZE];\n+} VL53LX_CalibrationData_t;\n+\n+struct stmvl53lx_ioctl_calibration_data_t {\n+\tint32_t is_read;\n+\tVL53LX_CalibrationData_t data;\n+};\n+\n+struct stmvl53lx_ioctl_perform_calibration_t {\n+\tuint32_t calibration_type;\n+\tuint32_t param1;\n+\tuint32_t param2;\n+\tuint32_t param3;\n+};\n+\n+typedef struct {\n+\tuint8_t ProductType;\n+\tuint8_t ProductRevisionMajor;\n+\tuint8_t ProductRevisionMinor;\n+} VL53LX_DeviceInfo_t;\n+\n+typedef struct {\n+\tint16_t RangeMaxMilliMeter;\n+\tint16_t RangeMinMilliMeter;\n+\tFixPoint1616_t SignalRateRtnMegaCps;\n+\tFixPoint1616_t AmbientRateRtnMegaCps;\n+\tFixPoint1616_t SigmaMilliMeter;\n+\tint16_t RangeMilliMeter;\n+\tuint8_t RangeStatus;\n+\tuint8_t ExtendedRange;\n+} VL53LX_TargetRangeData_t;\n+\n+typedef struct {\n+\tuint32_t TimeStamp;\n+\tuint8_t StreamCount;\n+\tuint8_t NumberOfObjectsFound;\n+\tVL53LX_TargetRangeData_t RangeData[VL53LX_MAX_RANGE_RESULTS];\n+\tuint8_t HasXtalkValueChanged;\n+\tuint16_t EffectiveSpadRtnCount;\n+} VL53LX_MultiRangingData_t;\n+\n+typedef struct {\n+\tVL53LX_DevicePresetModes        preset_mode;\n+\tVL53LX_DeviceZonePreset         zone_preset;\n+\tVL53LX_DeviceMeasurementModes   measurement_mode;\n+\tVL53LX_OffsetCalibrationMode    offset_calibration_mode;\n+\tVL53LX_OffsetCorrectionMode     offset_correction_mode;\n+\tVL53LX_DeviceDmaxMode           dmax_mode;\n+\tuint32_t  phasecal_config_timeout_us;\n+\tuint32_t  mm_config_timeout_us;\n+\tuint32_t  range_config_timeout_us;\n+\tuint32_t  inter_measurement_period_ms;\n+\tuint16_t  dss_config__target_total_rate_mcps;\n+\tVL53LX_histogram_bin_data_t    VL53LX_p_006;\n+} VL53LX_additional_data_t;\n+\n+typedef VL53LX_additional_data_t VL53LX_AdditionalData_t;\n+\n+struct stmvl53lx_data_with_additional {\n+\tVL53LX_MultiRangingData_t data;\n+\tVL53LX_AdditionalData_t additional_data;\n+};\n+\n+typedef struct {\n+\n+\tuint32_t                             struct_version;\n+\tVL53LX_customer_nvm_managed_t        customer;\n+\tVL53LX_dmax_calibration_data_t       fmt_dmax_cal;\n+\tVL53LX_dmax_calibration_data_t       cust_dmax_cal;\n+\tVL53LX_additional_offset_cal_data_t  add_off_cal_data;\n+\tVL53LX_optical_centre_t              optical_centre;\n+\tVL53LX_xtalk_histogram_data_t        xtalkhisto;\n+\tVL53LX_gain_calibration_data_t       gain_cal;\n+\tVL53LX_cal_peak_rate_map_t           cal_peak_rate_map;\n+\tVL53LX_per_vcsel_period_offset_cal_data_t per_vcsel_cal_data;\n+} VL53LX_calibration_data_t;\n+\n+typedef struct {\n+\tuint8_t  VL53LX_p_019;\n+\tuint8_t  VL53LX_p_020;\n+\tuint8_t  VL53LX_p_021;\n+\tuint8_t  VL53LX_p_029;\n+\tint32_t  VL53LX_p_016;\n+\tint32_t   VL53LX_p_043[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tint32_t   VL53LX_p_068[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tuint8_t   VL53LX_p_040[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tint32_t   VL53LX_p_018[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tuint16_t  VL53LX_p_014[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tuint16_t  VL53LX_p_008[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\n+} VL53LX_hist_gen1_algo_private_data_t;\n+\n+typedef struct {\n+\tuint8_t  VL53LX_p_019;\n+\tuint8_t  VL53LX_p_020;\n+\tuint8_t  VL53LX_p_021;\n+\tuint16_t VL53LX_p_015;\n+\tuint8_t  VL53LX_p_005;\n+\tuint8_t  VL53LX_p_029;\n+\tint32_t  VL53LX_p_028;\n+\tint32_t  VL53LX_p_016;\n+\tint32_t   VL53LX_p_007[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tint32_t   VL53LX_p_032[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tint32_t   VL53LX_p_001[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tint32_t   VL53LX_p_018[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tint32_t   VL53LX_p_055[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tint32_t   VL53LX_p_053[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tint32_t   VL53LX_p_054[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+} VL53LX_hist_gen2_algo_filtered_data_t;\n+\n+typedef struct {\n+\tuint8_t  VL53LX_p_019;\n+\tuint8_t  VL53LX_p_020;\n+\tuint8_t  VL53LX_p_021;\n+\tint32_t  VL53LX_p_031;\n+\tuint8_t   VL53LX_p_069[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tuint8_t   VL53LX_p_070[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tuint32_t  VL53LX_p_014[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tuint16_t  VL53LX_p_008[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tuint8_t   VL53LX_p_040[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+} VL53LX_hist_gen2_algo_detection_data_t;\n+\n+typedef struct {\n+\tuint8_t  VL53LX_p_012;\n+\tuint8_t  VL53LX_p_019;\n+\tuint8_t  VL53LX_p_023;\n+\tuint8_t  VL53LX_p_024;\n+\tuint8_t  VL53LX_p_013;\n+\tuint8_t  VL53LX_p_025;\n+\tuint8_t  VL53LX_p_051;\n+\tint32_t  VL53LX_p_016;\n+\tint32_t  VL53LX_p_017;\n+\tint32_t  VL53LX_p_010;\n+\tuint32_t VL53LX_p_026;\n+\tuint32_t VL53LX_p_011;\n+\tuint32_t VL53LX_p_027;\n+\tuint16_t VL53LX_p_002;\n+} VL53LX_hist_pulse_data_t;\n+\n+typedef struct {\n+\tuint8_t  VL53LX_p_019;\n+\tuint8_t  VL53LX_p_020;\n+\tuint8_t  VL53LX_p_021;\n+\tuint8_t  VL53LX_p_030;\n+\tuint8_t  VL53LX_p_039;\n+\tint32_t  VL53LX_p_028;\n+\tint32_t  VL53LX_p_031;\n+\tuint8_t  VL53LX_p_040[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tuint8_t  VL53LX_p_041[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tuint8_t  VL53LX_p_042[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tint32_t  VL53LX_p_052[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tint32_t  VL53LX_p_043[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tint32_t  VL53LX_p_018[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tuint8_t  VL53LX_p_044;\n+\tuint8_t  VL53LX_p_045;\n+\tuint8_t  VL53LX_p_046;\n+\tVL53LX_hist_pulse_data_t  VL53LX_p_003[VL53LX_D_001];\n+\tVL53LX_histogram_bin_data_t   VL53LX_p_006;\n+\tVL53LX_histogram_bin_data_t   VL53LX_p_047;\n+\tVL53LX_histogram_bin_data_t   VL53LX_p_048;\n+\tVL53LX_histogram_bin_data_t   VL53LX_p_049;\n+\tVL53LX_histogram_bin_data_t   VL53LX_p_050;\n+} VL53LX_hist_gen3_algo_private_data_t;\n+\n+typedef struct {\n+\tuint8_t  VL53LX_p_019;\n+\tuint8_t  VL53LX_p_020;\n+\tuint8_t  VL53LX_p_021;\n+\tint32_t   VL53LX_p_007[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tint32_t   VL53LX_p_032[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tint32_t   VL53LX_p_001[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tint32_t   VL53LX_p_053[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tint32_t   VL53LX_p_054[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+\tuint8_t  VL53LX_p_040[VL53LX_HISTOGRAM_BUFFER_SIZE];\n+} VL53LX_hist_gen4_algo_filtered_data_t;\n+\n+struct st_timeval {\n+\ttime64_t tv_sec;\n+\tlong tv_usec;\n+};\n+\n+struct stmvl53lx_data {\n+\tint id;\n+\tchar name[64];\n+\tVL53LX_DevData_t stdev;\n+\tvoid *client_object;\n+\tbool is_device_remove;\n+\tstruct mutex work_mutex;\n+\tstruct delayed_work\tdwork;\n+\tstruct input_dev *input_dev_ps;\n+\tstruct miscdevice miscdev;\n+\tint is_first_irq;\n+\tint is_first_start_done;\n+\tint poll_mode;\n+\tint poll_delay_ms;\n+\tint enable_sensor;\n+\tstruct st_timeval start_tv;\n+\tint enable_debug;\n+\tbool allow_hidden_start_stop;\n+\tint32_t timing_budget;\n+\tint distance_mode;\n+\tint crosstalk_enable;\n+\tint output_mode;\n+\tbool force_device_on_en;\n+\tVL53LX_Error last_error;\n+\tint offset_correction_mode;\n+\tint smudge_correction_mode;\n+\tFixPoint1616_t optical_offset_x;\n+\tFixPoint1616_t optical_offset_y;\n+\tbool is_xtalk_value_changed;\n+\tbool is_calibrating;\n+\tstruct range_t {\n+\t\tuint32_t\tcnt;\n+\t\tuint32_t\tintr;\n+\t\tint\tpoll_cnt;\n+\t\tuint32_t\terr_cnt;\n+\t\tuint32_t\terr_tot;\n+\t\tstruct st_timeval start_tv;\n+\t\tstruct st_timeval comp_tv;\n+\t\tVL53LX_MultiRangingData_t multi_range_data;\n+\t\tVL53LX_MultiRangingData_t tmp_range_data;\n+\t\tVL53LX_AdditionalData_t additional_data;\n+\t} meas;\n+\tuint32_t flushCount;\n+\tint flush_todo_counter;\n+\tstruct list_head simple_data_reader_list;\n+\tstruct list_head mz_data_reader_list;\n+\twait_queue_head_t waiter_for_data;\n+\tbool is_data_valid;\n+\tbool is_delay_allowed;\n+\tint reset_state;\n+\tVL53LX_UserRoi_t roi_cfg;\n+};\n+\n+struct i2c_data {\n+\tstruct i2c_client *client;\n+\tstruct stmvl53lx_data *vl53lx_data;\n+\tstruct kref ref;\n+\tstruct regulator *vdd;\n+\tint pwren_gpio;\n+\tint xsdn_gpio;\n+\tint intr_gpio;\n+\tint boot_reg;\n+\tstruct i2d_data_flags_t {\n+\t\tunsigned pwr_owned:1;\n+\t\tunsigned xsdn_owned:1;\n+\t\tunsigned intr_owned:1;\n+\t\tunsigned intr_started:1;\n+\t} io_flag;\n+\tint irq;\n+\tstruct msgtctrl_t {\n+\t\tunsigned unhandled_irq_vec:1;\n+\t} msg_flag;\n+};\n+\n+struct stmvl53lx_waiters {\n+\tstruct list_head list;\n+\tpid_t pid;\n+};\n+\n+struct stmvl53lx_data *stmvl53lx_dev_table[STMVL53LX_CFG_MAX_DEV];\n+\n+struct stmvl53lx_module_fn_t {\n+\tint (*init)(void);\n+\tvoid (*deinit)(void *data);\n+\tint (*power_up)(void *data);\n+\tint (*power_down)(void *data);\n+\tint (*reset_release)(void *data);\n+\tint (*reset_hold)(void *data);\n+\tint (*start_intr)(void *object, int *poll_mode);\n+\tvoid (*clean_up)(void);\n+\tvoid *(*get)(void *object);\n+\tvoid (*put)(void *object);\n+};\n+\n+static int32_t BDTable[VL53LX_TUNING_MAX_TUNABLE_KEY] = {\n+\t\tTUNING_VERSION,\n+\t\tTUNING_PROXY_MIN,\n+\t\tTUNING_SINGLE_TARGET_XTALK_TARGET_DISTANCE_MM,\n+\t\tTUNING_SINGLE_TARGET_XTALK_SAMPLE_NUMBER,\n+\t\tTUNING_MIN_AMBIENT_DMAX_VALID,\n+\t\tTUNING_MAX_SIMPLE_OFFSET_CALIBRATION_SAMPLE_NUMBER,\n+\t\tTUNING_XTALK_FULL_ROI_TARGET_DISTANCE_MM,\n+\t\tTUNING_SIMPLE_OFFSET_CALIBRATION_REPEAT,\n+\t\tTUNING_XTALK_FULL_ROI_BIN_SUM_MARGIN,\n+\t\tTUNING_XTALK_FULL_ROI_DEFAULT_OFFSET,\n+\t\tTUNING_ZERO_DISTANCE_OFFSET_NON_LINEAR_FACTOR_DEFAULT\n+};\n+\n+static struct i2c_client *stm_test_i2c_client;\n+\n+static const int tunings[][2] = {\n+};\n+\n+int stmvl53lx_enable_debug = 1;\n+\n+static int force_device;\n+static int adapter_nb = -1;\n+static int xsdn_gpio_nb = -1;\n+static int pwren_gpio_nb = -1;\n+static int intr_gpio_nb = -1;\n+static int i2c_addr_nb = STMVL53LX_SLAVE_ADDR;\n+\n+static bool force_device_on_en_default = true;\n+\n+module_param(force_device_on_en_default, bool, 0444);\n+MODULE_PARM_DESC(force_device_on_en_default, \"select whether force_device_on_en is true or false by default\");\n+\n+module_param(force_device, int, 0000);\n+MODULE_PARM_DESC(force_device, \"force device insertion at module init\");\n+\n+module_param(adapter_nb, int, 0000);\n+MODULE_PARM_DESC(adapter_nb, \"i2c adapter to use\");\n+\n+module_param(i2c_addr_nb, int, 0000);\n+MODULE_PARM_DESC(i2c_addr_nb, \"desired i2c device address on adapter \");\n+\n+module_param(xsdn_gpio_nb, int, 0000);\n+MODULE_PARM_DESC(xsdn_gpio_nb, \"select gpio numer to use for vl53lx reset\");\n+\n+module_param(pwren_gpio_nb, int, 0000);\n+MODULE_PARM_DESC(pwren_gpio_nb, \"select gpio numer to use for vl53lx power\");\n+\n+module_param(intr_gpio_nb, int, 0000);\n+MODULE_PARM_DESC(intr_gpio_nb, \"select gpio numer to use for vl53lx interrupt\");\n+static DEFINE_MUTEX(dev_addr_change_mutex);\n+static DEFINE_MUTEX(dev_table_mutex);\n+\n+static struct stmvl53lx_module_fn_t stmvl53lx_module_func_tbl;\n+static int _ctrl_stop(struct stmvl53lx_data *data);\n+static int reset_hold(struct stmvl53lx_data *data);\n+static void stmvl53lx_insert_flush_events_lock(struct stmvl53lx_data *data);\n+VL53LX_Error VL53LX_GetCalibrationData(VL53LX_DEV Dev, VL53LX_CalibrationData_t *pCalibrationData);\n+VL53LX_Error VL53LX_get_device_results(VL53LX_DEV Dev, VL53LX_DeviceResultsLevel device_results_level, VL53LX_range_results_t *prange_results);\n+VL53LX_Error VL53LX_poll_for_range_completion(VL53LX_DEV Dev, uint32_t timeout_ms);\n+VL53LX_Error VL53LX_preset_mode_histogram_short_range(\n+\tVL53LX_hist_post_process_config_t  *phistpostprocess,\n+\tVL53LX_static_config_t             *pstatic,\n+\tVL53LX_histogram_config_t          *phistogram,\n+\tVL53LX_general_config_t            *pgeneral,\n+\tVL53LX_timing_config_t             *ptiming,\n+\tVL53LX_dynamic_config_t            *pdynamic,\n+\tVL53LX_system_control_t            *psystem,\n+\tVL53LX_tuning_parm_storage_t       *ptuning_parms,\n+\tVL53LX_zone_config_t               *pzone_cfg);\n+static VL53LX_Error SetMeasurementData(VL53LX_DEV Dev, VL53LX_range_results_t *presults, VL53LX_MultiRangingData_t *pMultiRangingData);\n+void stmvl53lx_put(void *object);\n+void st_gettimeofday(struct st_timeval *tv);\n+VL53LX_Error VL53LX_WaitUs(VL53LX_DEV pdev, int32_t wait_us);\n+VL53LX_Error VL53LX_WaitMs(VL53LX_DEV pdev, int32_t wait_ms);\n+VL53LX_Error VL53LX_WaitValueMaskEx(VL53LX_DEV pdev, uint32_t timeout_ms, uint16_t index, uint8_t value, uint8_t mask, uint32_t poll_delay_ms);\n+void VL53LX_init_ll_driver_state(VL53LX_DEV Dev, VL53LX_DeviceState device_state);\n+VL53LX_Error VL53LX_poll_for_boot_completion(VL53LX_DEV Dev, uint32_t timeout_ms);\n+VL53LX_Error VL53LX_WaitDeviceBooted(VL53LX_DEV Dev);\n+uint32_t VL53LX_calc_pll_period_us(uint16_t fast_osc_frequency);\n+uint8_t VL53LX_decode_vcsel_period(uint8_t vcsel_period_reg);\n+uint32_t VL53LX_calc_macro_period_us(uint16_t fast_osc_frequency, uint8_t VL53LX_p_005);\n+uint32_t VL53LX_calc_timeout_us(uint32_t timeout_mclks, uint32_t macro_period_us);\n+uint32_t VL53LX_decode_timeout(uint16_t encoded_timeout);\n+uint32_t VL53LX_calc_decoded_timeout_us(\n+\tuint16_t timeout_encoded,\n+\tuint32_t macro_period_us);\n+VL53LX_Error VL53LX_get_timeouts_us(VL53LX_DEV Dev, uint32_t *pphasecal_config_timeout_us, uint32_t *pmm_config_timeout_us, uint32_t *prange_config_timeout_us);\n+uint32_t VL53LX_calc_timeout_mclks(uint32_t timeout_us, uint32_t macro_period_us);\n+uint16_t VL53LX_encode_timeout(uint32_t timeout_mclks);\n+uint16_t VL53LX_calc_encoded_timeout(uint32_t timeout_us, uint32_t macro_period_us);\n+VL53LX_Error VL53LX_calc_timeout_register_values(uint32_t phasecal_config_timeout_us, uint32_t mm_config_timeout_us, uint32_t range_config_timeout_us, uint16_t fast_osc_frequency, VL53LX_general_config_t *pgeneral, VL53LX_timing_config_t  *ptiming);\n+VL53LX_Error VL53LX_set_timeouts_us(VL53LX_DEV Dev, uint32_t phasecal_config_timeout_us, uint32_t mm_config_timeout_us, uint32_t range_config_timeout_us);\n+VL53LX_Error VL53LX_SetMeasurementTimingBudgetMicroSeconds(VL53LX_DEV Dev, uint32_t MeasurementTimingBudgetMicroSeconds);\n+VL53LX_Error VL53LX_i2c_encode_system_control(VL53LX_system_control_t *pdata, uint16_t buf_size, uint8_t *pbuffer);\n+VL53LX_Error VL53LX_WriteMulti(VL53LX_DEV pdev, uint16_t index, uint8_t *pdata, uint32_t count);\n+VL53LX_Error VL53LX_ReadMulti(VL53LX_DEV pdev, uint16_t index, uint8_t *pdata, uint32_t count);\n+VL53LX_Error VL53LX_RdByte(VL53LX_DEV pdev, uint16_t index, uint8_t *pdata);\n+VL53LX_Error VL53LX_WrByte(VL53LX_DEV pdev, uint16_t index, uint8_t data);\n+VL53LX_Error VL53LX_RdWord(VL53LX_DEV pdev, uint16_t index, uint16_t *pdata);\n+VL53LX_Error VL53LX_WrWord(VL53LX_DEV pdev, uint16_t index, uint16_t data);\n+VL53LX_Error VL53LX_WrDWord(VL53LX_DEV pdev, uint16_t index, uint32_t data);\n+VL53LX_Error VL53LX_RdDWord(VL53LX_DEV pdev, uint16_t index, uint32_t *pdata);\n+VL53LX_Error VL53LX_set_system_control(VL53LX_DEV Dev, VL53LX_system_control_t *pdata);\n+void V53L1_init_zone_results_structure(uint8_t active_zones, VL53LX_zone_results_t *pdata);\n+void V53L1_init_zone_dss_configs(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_low_power_auto_data_stop_range(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_stop_range(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_set_powerforce_register(VL53LX_DEV Dev, uint8_t value);\n+VL53LX_Error VL53LX_disable_powerforce(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_unload_patch(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_StopMeasurement(VL53LX_DEV Dev);\n+void VL53LX_i2c_encode_uint16_t(uint16_t ip_value, uint16_t count, uint8_t *pbuffer);\n+uint16_t VL53LX_i2c_decode_uint16_t(uint16_t count, uint8_t *pbuffer);\n+void VL53LX_i2c_encode_int16_t(int16_t ip_value, uint16_t count, uint8_t *pbuffer);\n+int16_t VL53LX_i2c_decode_int16_t(uint16_t count, uint8_t *pbuffer);\n+uint32_t VL53LX_i2c_decode_with_mask(uint16_t count, uint8_t *pbuffer, uint32_t bit_mask, uint32_t down_shift, uint32_t offset);\n+void VL53LX_i2c_encode_int32_t(int32_t ip_value, uint16_t count, uint8_t *pbuffer);\n+int32_t VL53LX_i2c_decode_int32_t(uint16_t count, uint8_t *pbuffer);\n+VL53LX_Error VL53LX_i2c_encode_customer_nvm_managed(VL53LX_customer_nvm_managed_t *pdata, uint16_t buf_size, uint8_t *pbuffer);\n+VL53LX_Error VL53LX_set_customer_nvm_managed(VL53LX_DEV Dev, VL53LX_customer_nvm_managed_t *pdata);\n+VL53LX_Error VL53LX_disable_xtalk_compensation(VL53LX_DEV Dev);\n+uint32_t VL53LX_calc_crosstalk_plane_offset_with_margin(uint32_t plane_offset_kcps, int16_t margin_offset_kcps);\n+uint16_t VL53LX_calc_range_ignore_threshold(uint32_t central_rate, int16_t x_gradient, int16_t y_gradient, uint8_t rate_mult);\n+VL53LX_Error VL53LX_enable_xtalk_compensation(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_SetXTalkCompensationEnable(VL53LX_DEV Dev, uint8_t XTalkCompensationEnable);\n+VL53LX_Error VL53LX_get_preset_mode_timing_cfg(VL53LX_DEV Dev, VL53LX_DevicePresetModes device_preset_mode, uint16_t *pdss_config__target_total_rate_mcps, uint32_t *pphasecal_config_timeout_us, uint32_t *pmm_config_timeout_us, uint32_t  *prange_config_timeout_us);\n+VL53LX_Error VL53LX_preset_mode_standard_ranging(\n+\tVL53LX_static_config_t    *pstatic,\n+\tVL53LX_histogram_config_t *phistogram,\n+\tVL53LX_general_config_t   *pgeneral,\n+\tVL53LX_timing_config_t    *ptiming,\n+\tVL53LX_dynamic_config_t   *pdynamic,\n+\tVL53LX_system_control_t   *psystem,\n+\tVL53LX_tuning_parm_storage_t *ptuning_parms,\n+\tVL53LX_zone_config_t      *pzone_cfg);\n+void VL53LX_init_histogram_config_structure(\n+\tuint8_t   even_bin0,\n+\tuint8_t   even_bin1,\n+\tuint8_t   even_bin2,\n+\tuint8_t   even_bin3,\n+\tuint8_t   even_bin4,\n+\tuint8_t   even_bin5,\n+\tuint8_t   odd_bin0,\n+\tuint8_t   odd_bin1,\n+\tuint8_t   odd_bin2,\n+\tuint8_t   odd_bin3,\n+\tuint8_t   odd_bin4,\n+\tuint8_t   odd_bin5,\n+\tVL53LX_histogram_config_t  *pdata);\n+void VL53LX_init_histogram_multizone_config_structure(\n+\tuint8_t   even_bin0,\n+\tuint8_t   even_bin1,\n+\tuint8_t   even_bin2,\n+\tuint8_t   even_bin3,\n+\tuint8_t   even_bin4,\n+\tuint8_t   even_bin5,\n+\tuint8_t   odd_bin0,\n+\tuint8_t   odd_bin1,\n+\tuint8_t   odd_bin2,\n+\tuint8_t   odd_bin3,\n+\tuint8_t   odd_bin4,\n+\tuint8_t   odd_bin5,\n+\tVL53LX_histogram_config_t  *pdata);\n+void VL53LX_copy_hist_cfg_to_static_cfg(\n+\tVL53LX_histogram_config_t *phistogram,\n+\tVL53LX_static_config_t    *pstatic,\n+\tVL53LX_general_config_t   *pgeneral,\n+\tVL53LX_timing_config_t    *ptiming,\n+\tVL53LX_dynamic_config_t   *pdynamic);\n+VL53LX_Error VL53LX_preset_mode_histogram_ranging(\n+\tVL53LX_hist_post_process_config_t  *phistpostprocess,\n+\tVL53LX_static_config_t             *pstatic,\n+\tVL53LX_histogram_config_t          *phistogram,\n+\tVL53LX_general_config_t            *pgeneral,\n+\tVL53LX_timing_config_t             *ptiming,\n+\tVL53LX_dynamic_config_t            *pdynamic,\n+\tVL53LX_system_control_t            *psystem,\n+\tVL53LX_tuning_parm_storage_t       *ptuning_parms,\n+\tVL53LX_zone_config_t               *pzone_cfg);\n+VL53LX_Error VL53LX_preset_mode_histogram_long_range(\n+\tVL53LX_hist_post_process_config_t  *phistpostprocess,\n+\tVL53LX_static_config_t             *pstatic,\n+\tVL53LX_histogram_config_t          *phistogram,\n+\tVL53LX_general_config_t            *pgeneral,\n+\tVL53LX_timing_config_t             *ptiming,\n+\tVL53LX_dynamic_config_t            *pdynamic,\n+\tVL53LX_system_control_t            *psystem,\n+\tVL53LX_tuning_parm_storage_t       *ptuning_parms,\n+\tVL53LX_zone_config_t               *pzone_cfg);\n+VL53LX_Error VL53LX_set_inter_measurement_period_ms(VL53LX_DEV Dev, uint32_t inter_measurement_period_ms);\n+VL53LX_Error VL53LX_preset_mode_histogram_medium_range(\n+\tVL53LX_hist_post_process_config_t  *phistpostprocess,\n+\tVL53LX_static_config_t             *pstatic,\n+\tVL53LX_histogram_config_t          *phistogram,\n+\tVL53LX_general_config_t            *pgeneral,\n+\tVL53LX_timing_config_t             *ptiming,\n+\tVL53LX_dynamic_config_t            *pdynamic,\n+\tVL53LX_system_control_t            *psystem,\n+\tVL53LX_tuning_parm_storage_t       *ptuning_parms,\n+\tVL53LX_zone_config_t               *pzone_cfg);\n+VL53LX_Error VL53LX_set_preset_mode(VL53LX_DEV Dev, VL53LX_DevicePresetModes device_preset_mode, uint16_t dss_config__target_total_rate_mcps, uint32_t phasecal_config_timeout_us, uint32_t mm_config_timeout_us, uint32_t range_config_timeout_us, uint32_t inter_measurement_period_ms);\n+VL53LX_Error VL53LX_SetDistanceMode(VL53LX_DEV Dev, VL53LX_DistanceModes DistanceMode);\n+VL53LX_Error VL53LX_set_offset_correction_mode(VL53LX_DEV Dev, VL53LX_OffsetCorrectionMode offset_cor_mode);\n+VL53LX_Error VL53LX_SetOffsetCorrectionMode(VL53LX_DEV Dev, VL53LX_OffsetCorrectionModes OffsetCorrectionMode);\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_disable(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_apply_disable(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_single_apply_disable(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_enable(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_apply_enable(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_single_apply_enable(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_SmudgeCorrectionEnable(VL53LX_DEV Dev, VL53LX_SmudgeCorrectionModes Mode);\n+VL53LX_Error VL53LX_init_zone_config_histogram_bins(VL53LX_zone_config_t *pdata);\n+VL53LX_Error VL53LX_set_zone_config(VL53LX_DEV Dev, VL53LX_zone_config_t *pzone_cfg);\n+VL53LX_Error VL53LX_SetUserROI(VL53LX_DEV Dev, VL53LX_UserRoi_t *pRoi);\n+VL53LX_Error VL53LX_enable_powerforce(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_get_tuning_parm(VL53LX_DEV Dev, VL53LX_TuningParms tuning_parm_key, int32_t *ptuning_parm_value);\n+VL53LX_Error VL53LX_load_patch(VL53LX_DEV Dev);\n+void VL53LX_encode_row_col(uint8_t row, uint8_t col, uint8_t *pspad_number);\n+void VL53LX_encode_zone_size(uint8_t width, uint8_t height, uint8_t *pencoded_xy_size);\n+VL53LX_Error VL53LX_set_user_zone(VL53LX_DEV Dev, VL53LX_user_zone_t *puser_zone);\n+VL53LX_Error VL53LX_set_zone_dss_config(VL53LX_DEV Dev, VL53LX_zone_private_dyn_cfg_t *pzone_dyn_cfg);\n+VL53LX_Error VL53LX_save_cfg_data(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_i2c_encode_static_nvm_managed(VL53LX_static_nvm_managed_t *pdata, uint16_t buf_size, uint8_t *pbuffer);\n+VL53LX_Error VL53LX_i2c_decode_static_nvm_managed(uint16_t buf_size, uint8_t *pbuffer, VL53LX_static_nvm_managed_t *pdata);\n+VL53LX_Error VL53LX_i2c_encode_static_config(VL53LX_static_config_t *pdata, uint16_t buf_size, uint8_t *pbuffer);\n+VL53LX_Error VL53LX_i2c_encode_general_config(VL53LX_general_config_t *pdata, uint16_t buf_size, uint8_t *pbuffer);\n+void VL53LX_i2c_encode_uint32_t(uint32_t ip_value, uint16_t count, uint8_t *pbuffer);\n+uint32_t VL53LX_i2c_decode_uint32_t(uint16_t count, uint8_t *pbuffer);\n+VL53LX_Error VL53LX_i2c_encode_timing_config(VL53LX_timing_config_t *pdata, uint16_t buf_size, uint8_t *pbuffer);\n+VL53LX_Error VL53LX_i2c_encode_dynamic_config(VL53LX_dynamic_config_t *pdata, uint16_t buf_size, uint8_t *pbuffer);\n+VL53LX_Error VL53LX_update_internal_stream_counters(VL53LX_DEV Dev, uint8_t external_stream_count, uint8_t *pinternal_stream_count, uint8_t *pinternal_stream_count_val);\n+VL53LX_Error VL53LX_update_ll_driver_rd_state(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_update_ll_driver_cfg_state(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_init_and_start_range(VL53LX_DEV Dev, uint8_t measurement_mode, VL53LX_DeviceConfigLevel device_config_level);\n+VL53LX_Error VL53LX_StartMeasurement(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_WaitMeasurementDataReady(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_is_new_data_ready(VL53LX_DEV Dev, uint8_t *pready);\n+VL53LX_Error VL53LX_GetMeasurementDataReady(VL53LX_DEV Dev, uint8_t *pMeasurementDataReady);\n+long stmvl53lx_tv_dif(struct st_timeval *pstart_tv, struct st_timeval *pstop_tv);\n+VL53LX_Error VL53LX_GetMultiRangingData(VL53LX_DEV Dev, VL53LX_MultiRangingData_t *pMultiRangingData);\n+VL53LX_Error VL53LX_get_histogram_debug_data(VL53LX_DEV Dev, VL53LX_histogram_bin_data_t *pdata);\n+VL53LX_Error VL53LX_get_additional_data(VL53LX_DEV Dev, VL53LX_additional_data_t *pdata);\n+VL53LX_Error VL53LX_GetAdditionalData(VL53LX_DEV Dev, VL53LX_AdditionalData_t *pAdditionalData);\n+VL53LX_Error VL53LX_clear_interrupt_and_enable_next_range(VL53LX_DEV Dev, uint8_t measurement_mode);\n+VL53LX_Error VL53LX_ClearInterruptAndStartMeasurement(VL53LX_DEV Dev);\n+int stmvl53lx_intr_handler(struct stmvl53lx_data *data);\n+VL53LX_Error VL53LX_set_tuning_parm(VL53LX_DEV Dev, VL53LX_TuningParms tuning_parm_key, int32_t tuning_parm_value);\n+VL53LX_Error VL53LX_SetTuningParameter(VL53LX_DEV Dev, uint16_t TuningParameterId, int32_t TuningParameterValue);\n+VL53LX_Error VL53LX_GetTuningParameter(VL53LX_DEV Dev, uint16_t TuningParameterId, int32_t *pTuningParameterValue);\n+VL53LX_Error VL53LX_set_part_to_part_data(VL53LX_DEV Dev, VL53LX_calibration_data_t *pcal_data);\n+VL53LX_Error VL53LX_get_current_xtalk_settings(VL53LX_DEV Dev, VL53LX_xtalk_calibration_results_t *pxtalk);\n+VL53LX_Error VL53LX_set_current_xtalk_settings(VL53LX_DEV Dev, VL53LX_xtalk_calibration_results_t *pxtalk);\n+VL53LX_Error VL53LX_SetCalibrationData(VL53LX_DEV Dev, VL53LX_CalibrationData_t *pCalibrationData);\n+VL53LX_Error VL53LX_get_part_to_part_data(VL53LX_DEV Dev, VL53LX_calibration_data_t *pcal_data);\n+void VL53LX_init_version(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_get_static_nvm_managed(VL53LX_DEV Dev, VL53LX_static_nvm_managed_t *pdata);\n+VL53LX_Error VL53LX_i2c_decode_customer_nvm_managed(uint16_t buf_size, uint8_t *pbuffer, VL53LX_customer_nvm_managed_t *pdata);\n+VL53LX_Error VL53LX_get_customer_nvm_managed(VL53LX_DEV Dev, VL53LX_customer_nvm_managed_t *pdata);\n+VL53LX_Error VL53LX_i2c_decode_nvm_copy_data(uint16_t buf_size, uint8_t *pbuffer, VL53LX_nvm_copy_data_t *pdata);\n+VL53LX_Error VL53LX_get_nvm_copy_data(VL53LX_DEV Dev, VL53LX_nvm_copy_data_t *pdata);\n+void VL53LX_copy_rtn_good_spads_to_buffer(VL53LX_nvm_copy_data_t *pdata, uint8_t *pbuffer);\n+VL53LX_Error VL53LX_set_firmware_enable_register(VL53LX_DEV Dev, uint8_t value);\n+VL53LX_Error VL53LX_disable_firmware(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_nvm_enable(VL53LX_DEV Dev, uint16_t nvm_ctrl_pulse_width, int32_t nvm_power_up_delay_us);\n+VL53LX_Error VL53LX_nvm_read(VL53LX_DEV Dev, uint8_t start_address, uint8_t count, uint8_t *pdata);\n+VL53LX_Error VL53LX_enable_firmware(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_nvm_disable(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_read_nvm_raw_data(VL53LX_DEV Dev, uint8_t start_address, uint8_t count, uint8_t *pnvm_raw_data);\n+VL53LX_Error VL53LX_nvm_decode_optical_centre(uint16_t buf_size, uint8_t *pbuffer, VL53LX_optical_centre_t *pdata);\n+VL53LX_Error VL53LX_read_nvm_optical_centre(VL53LX_DEV Dev, VL53LX_optical_centre_t *pcentre);\n+VL53LX_Error VL53LX_nvm_decode_cal_peak_rate_map(uint16_t buf_size, uint8_t *pbuffer, VL53LX_cal_peak_rate_map_t *pdata);\n+VL53LX_Error VL53LX_read_nvm_cal_peak_rate_map(VL53LX_DEV Dev, VL53LX_cal_peak_rate_map_t *pcal_data);\n+VL53LX_Error VL53LX_nvm_decode_additional_offset_cal_data(uint16_t buf_size, uint8_t *pbuffer, VL53LX_additional_offset_cal_data_t *pdata);\n+VL53LX_Error VL53LX_read_nvm_additional_offset_cal_data(VL53LX_DEV Dev, VL53LX_additional_offset_cal_data_t *pcal_data);\n+void VL53LX_spad_number_to_byte_bit_index(uint8_t spad_number, uint8_t *pbyte_index, uint8_t *pbit_index, uint8_t *pbit_mask);\n+uint8_t VL53LX_is_aperture_location(uint8_t row, uint8_t col);\n+void VL53LX_decode_row_col(uint8_t spad_number, uint8_t *prow, uint8_t *pcol);\n+void VL53LX_decode_zone_size(uint8_t encoded_xy_size, uint8_t *pwidth, uint8_t *pheight);\n+void VL53LX_decode_zone_limits(uint8_t encoded_xy_centre, uint8_t encoded_xy_size, int16_t *px_ll, int16_t *py_ll, int16_t *px_ur, int16_t *py_ur);\n+void VL53LX_calc_mm_effective_spads(\n+\tuint8_t     encoded_mm_roi_centre,\n+\tuint8_t     encoded_mm_roi_size,\n+\tuint8_t     encoded_zone_centre,\n+\tuint8_t     encoded_zone_size,\n+\tuint8_t    *pgood_spads,\n+\tuint16_t    aperture_attenuation,\n+\tuint16_t   *pmm_inner_effective_spads,\n+\tuint16_t   *pmm_outer_effective_spads);\n+VL53LX_Error VL53LX_nvm_decode_fmt_range_results_data(uint16_t buf_size, uint8_t *pbuffer, VL53LX_decoded_nvm_fmt_range_data_t *pdata);\n+VL53LX_Error VL53LX_read_nvm_fmt_range_results_data(VL53LX_DEV Dev, uint16_t range_results_select, VL53LX_decoded_nvm_fmt_range_data_t *prange_data);\n+VL53LX_Error VL53LX_get_mode_mitigation_roi(VL53LX_DEV Dev, VL53LX_user_zone_t *pmm_roi);\n+VL53LX_Error VL53LX_read_p2p_data(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_init_refspadchar_config_struct(VL53LX_refspadchar_config_t *pdata);\n+VL53LX_Error VL53LX_init_ssc_config_struct(VL53LX_ssc_config_t *pdata);\n+VL53LX_Error VL53LX_init_xtalk_config_struct(VL53LX_customer_nvm_managed_t *pnvm, VL53LX_xtalk_config_t *pdata);\n+VL53LX_Error VL53LX_init_xtalk_extract_config_struct(VL53LX_xtalkextract_config_t *pdata);\n+VL53LX_Error VL53LX_init_offset_cal_config_struct(VL53LX_offsetcal_config_t *pdata);\n+VL53LX_Error VL53LX_init_zone_cal_config_struct(VL53LX_zonecal_config_t *pdata);\n+VL53LX_Error VL53LX_init_hist_post_process_config_struct(uint8_t xtalk_compensation_enable, VL53LX_hist_post_process_config_t *pdata);\n+VL53LX_Error VL53LX_init_hist_gen3_dmax_config_struct(VL53LX_hist_gen3_dmax_config_t *pdata);\n+VL53LX_Error VL53LX_init_tuning_parm_storage_struct(VL53LX_tuning_parm_storage_t *pdata);\n+void VL53LX_init_histogram_bin_data_struct(int32_t bin_value, uint16_t VL53LX_p_021, VL53LX_histogram_bin_data_t *pdata);\n+void VL53LX_init_xtalk_bin_data_struct(uint32_t bin_value, uint16_t VL53LX_p_021, VL53LX_xtalk_histogram_shape_t *pdata);\n+VL53LX_Error VL53LX_xtalk_cal_data_init(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_output_init(VL53LX_LLDriverResults_t *pres);\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_data_init(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_low_power_auto_data_init(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_data_init(VL53LX_DEV Dev, uint8_t read_p2p_data);\n+VL53LX_Error VL53LX_set_dmax_mode(VL53LX_DEV Dev, VL53LX_DeviceDmaxMode dmax_mode);\n+VL53LX_Error VL53LX_DataInit(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_get_zone_config(VL53LX_DEV Dev, VL53LX_zone_config_t *pzone_cfg);\n+VL53LX_Error VL53LX_GetUserROI(VL53LX_DEV Dev, VL53LX_UserRoi_t *pRoi);\n+VL53LX_Error VL53LX_GetDeviceInfo(VL53LX_DEV Dev, VL53LX_DeviceInfo_t *pVL53LX_DeviceInfo);\n+VL53LX_Error VL53LX_GetOpticalCenter(VL53LX_DEV Dev, FixPoint1616_t *pOpticalCenterX, FixPoint1616_t *pOpticalCenterY);\n+void VL53LX_hist_get_bin_sequence_config(VL53LX_DEV Dev, VL53LX_histogram_bin_data_t *pdata);\n+uint32_t VL53LX_duration_maths(uint32_t pll_period_us, uint32_t vcsel_parm_pclks, uint32_t window_vclks, uint32_t elapsed_mclks);\n+void VL53LX_hist_calc_zero_distance_phase(VL53LX_histogram_bin_data_t *pdata);\n+void VL53LX_hist_estimate_ambient_from_ambient_bins(VL53LX_histogram_bin_data_t *pdata);\n+VL53LX_Error VL53LX_get_histogram_bin_data(VL53LX_DEV Dev, VL53LX_histogram_bin_data_t *pdata);\n+VL53LX_Error VL53LX_hist_copy_and_scale_ambient_info(VL53LX_zone_hist_info_t *pidata, VL53LX_histogram_bin_data_t *podata);\n+VL53LX_Error VL53LX_compute_histo_merge_nb(VL53LX_DEV Dev, uint8_t *histo_merge_nb);\n+void VL53LX_hist_combine_mm1_mm2_offsets(\n+\tint16_t                               mm1_offset_mm,\n+\tint16_t                               mm2_offset_mm,\n+\tuint8_t                               encoded_mm_roi_centre,\n+\tuint8_t                               encoded_mm_roi_size,\n+\tuint8_t                               encoded_zone_centre,\n+\tuint8_t                               encoded_zone_size,\n+\tVL53LX_additional_offset_cal_data_t  *pcal_data,\n+\tuint8_t                              *pgood_spads,\n+\tuint16_t                              aperture_attenuation,\n+\tint16_t                               *prange_offset_mm);\n+void VL53LX_calc_max_effective_spads(uint8_t encoded_zone_centre, uint8_t encoded_zone_size, uint8_t *pgood_spads, uint16_t aperture_attenuation, uint16_t *pmax_effective_spads);\n+VL53LX_Error VL53LX_get_dmax_calibration_data(VL53LX_DEV Dev, VL53LX_DeviceDmaxMode dmax_mode, VL53LX_dmax_calibration_data_t *pdmax_cal);\n+VL53LX_Error VL53LX_f_031(VL53LX_histogram_bin_data_t *pidata, VL53LX_histogram_bin_data_t *podata);\n+VL53LX_Error VL53LX_f_032(uint32_t mean_offset, int16_t xgradient, int16_t ygradient, int8_t centre_offset_x, int8_t centre_offset_y, uint16_t roi_effective_spads, uint8_t roi_centre_spad, uint8_t roi_xy_size, uint32_t *xtalk_rate_kcps);\n+VL53LX_Error VL53LX_f_033(VL53LX_histogram_bin_data_t *phist_data, VL53LX_xtalk_histogram_shape_t *pxtalk_data, uint32_t xtalk_rate_kcps, VL53LX_histogram_bin_data_t *pxtalkcount_data);\n+void VL53LX_copy_xtalk_bin_data_to_histogram_data_struct(VL53LX_xtalk_histogram_shape_t *pxtalk, VL53LX_histogram_bin_data_t *phist);\n+void VL53LX_f_003(VL53LX_hist_gen3_algo_private_data_t *palgo);\n+void VL53LX_hist_find_min_max_bin_values(VL53LX_histogram_bin_data_t *pdata);\n+uint32_t VL53LX_isqrt(uint32_t num);\n+void VL53LX_hist_estimate_ambient_from_thresholded_bins(int32_t ambient_threshold_sigma, VL53LX_histogram_bin_data_t *pdata);\n+void VL53LX_hist_remove_ambient_bins(VL53LX_histogram_bin_data_t *pdata);\n+int8_t VL53LX_f_030(VL53LX_histogram_bin_data_t *pdata1, VL53LX_histogram_bin_data_t *pdata2);\n+void VL53LX_f_005(VL53LX_histogram_bin_data_t *pxtalk, VL53LX_histogram_bin_data_t *pbins, VL53LX_histogram_bin_data_t *pxtalk_realigned);\n+uint16_t VL53LX_rate_maths(int32_t VL53LX_p_018, uint32_t time_us);\n+uint32_t VL53LX_events_per_spad_maths(int32_t VL53LX_p_010, uint16_t num_spads, uint32_t duration);\n+uint32_t VL53LX_f_002(uint32_t events_threshold, uint32_t ref_signal_events, uint32_t ref_distance_mm, uint32_t signal_thresh_sigma);\n+VL53LX_Error VL53LX_f_001(\n+\tuint16_t                              target_reflectance,\n+\tVL53LX_dmax_calibration_data_t\t     *pcal,\n+\tVL53LX_hist_gen3_dmax_config_t\t     *pcfg,\n+\tVL53LX_histogram_bin_data_t          *pbins,\n+\tVL53LX_hist_gen3_dmax_private_data_t *pdata,\n+\tint16_t                              *pambient_dmax_mm);\n+VL53LX_Error VL53LX_f_006(\n+\tuint16_t ambient_threshold_events_scaler,\n+\tint32_t ambient_threshold_sigma,\n+\tint32_t min_ambient_threshold_events,\n+\tuint8_t algo__crosstalk_compensation_enable,\n+\tVL53LX_histogram_bin_data_t *pbins,\n+\tVL53LX_histogram_bin_data_t *pxtalk,\n+\tVL53LX_hist_gen3_algo_private_data_t *palgo);\n+VL53LX_Error VL53LX_f_007(VL53LX_hist_gen3_algo_private_data_t *palgo);\n+VL53LX_Error VL53LX_f_008(VL53LX_hist_gen3_algo_private_data_t *palgo);\n+VL53LX_Error VL53LX_f_009(VL53LX_hist_gen3_algo_private_data_t *palgo);\n+VL53LX_Error VL53LX_f_010(uint8_t pulse_no, VL53LX_histogram_bin_data_t *pbins, VL53LX_hist_gen3_algo_private_data_t *palgo);\n+VL53LX_Error VL53LX_f_011(\n+\tuint8_t                                pulse_no,\n+\tVL53LX_histogram_bin_data_t           *pbins,\n+\tVL53LX_hist_gen3_algo_private_data_t  *palgo,\n+\tint32_t                                pad_value,\n+\tVL53LX_histogram_bin_data_t           *ppulse);\n+VL53LX_Error VL53LX_f_014(\n+\tuint8_t                       bin,\n+\tuint8_t                       sigma_estimator__sigma_ref_mm,\n+\tuint8_t                       VL53LX_p_030,\n+\tuint8_t                       VL53LX_p_051,\n+\tuint8_t                       crosstalk_compensation_enable,\n+\tVL53LX_histogram_bin_data_t  *phist_data_ap,\n+\tVL53LX_histogram_bin_data_t  *phist_data_zp,\n+\tVL53LX_histogram_bin_data_t  *pxtalk_hist,\n+\tuint16_t                     *psigma_est);\n+VL53LX_Error VL53LX_f_015(uint8_t pulse_no, uint8_t clip_events, VL53LX_histogram_bin_data_t *pbins, VL53LX_hist_gen3_algo_private_data_t *palgo);\n+VL53LX_Error VL53LX_f_016(VL53LX_HistTargetOrder target_order, VL53LX_hist_gen3_algo_private_data_t *palgo);\n+void VL53LX_f_017(\n+\tuint8_t                      range_id,\n+\tuint8_t                      valid_phase_low,\n+\tuint8_t                      valid_phase_high,\n+\tuint16_t                     sigma_thres,\n+\tVL53LX_histogram_bin_data_t *pbins,\n+\tVL53LX_hist_pulse_data_t    *ppulse,\n+\tVL53LX_range_data_t         *pdata);\n+VL53LX_Error VL53LX_f_018(\n+\tuint16_t           vcsel_width,\n+\tuint16_t           fast_osc_frequency,\n+\tuint32_t           total_periods_elapsed,\n+\tuint16_t           VL53LX_p_004,\n+\tVL53LX_range_data_t  *pdata,\n+\tuint8_t histo_merge_nb);\n+void VL53LX_f_019(uint16_t gain_factor, int16_t range_offset_mm, VL53LX_range_data_t *pdata);\n+VL53LX_Error VL53LX_f_020(int16_t VL53LX_p_019, int16_t VL53LX_p_024, uint8_t VL53LX_p_030, uint8_t clip_events, VL53LX_histogram_bin_data_t *pbins, uint32_t *pphase);\n+void VL53LX_f_022(uint8_t VL53LX_p_032, uint8_t filter_woi, VL53LX_histogram_bin_data_t *pbins, int32_t *pa, int32_t *pb, int32_t *pc);\n+VL53LX_Error VL53LX_f_023(\n+\tuint8_t\t sigma_estimator__sigma_ref_mm,\n+\tuint32_t VL53LX_p_007,\n+\tuint32_t VL53LX_p_032,\n+\tuint32_t VL53LX_p_001,\n+\tuint32_t a_zp,\n+\tuint32_t c_zp,\n+\tuint32_t bx,\n+\tuint32_t ax_zp,\n+\tuint32_t cx_zp,\n+\tuint32_t VL53LX_p_028,\n+\tuint16_t fast_osc_frequency,\n+\tuint16_t *psigma_est);\n+VL53LX_Error VL53LX_f_025(\n+\tVL53LX_dmax_calibration_data_t         *pdmax_cal,\n+\tVL53LX_hist_gen3_dmax_config_t         *pdmax_cfg,\n+\tVL53LX_hist_post_process_config_t      *ppost_cfg,\n+\tVL53LX_histogram_bin_data_t            *pbins_input,\n+\tVL53LX_histogram_bin_data_t            *pxtalk,\n+\tVL53LX_hist_gen3_algo_private_data_t   *palgo3,\n+\tVL53LX_hist_gen4_algo_filtered_data_t  *pfiltered,\n+\tVL53LX_hist_gen3_dmax_private_data_t   *pdmax_algo,\n+\tVL53LX_range_results_t                 *presults,\n+\tuint8_t                                histo_merge_nb);\n+VL53LX_Error VL53LX_f_026(\n+\tuint8_t                                pulse_no,\n+\tVL53LX_histogram_bin_data_t           *ppulse,\n+\tVL53LX_hist_gen3_algo_private_data_t  *palgo3,\n+\tVL53LX_hist_gen4_algo_filtered_data_t *pfiltered);\n+VL53LX_Error VL53LX_f_027(uint8_t pulse_no, uint16_t noise_threshold, VL53LX_hist_gen4_algo_filtered_data_t *pfiltered, VL53LX_hist_gen3_algo_private_data_t *palgo3);\n+VL53LX_Error VL53LX_f_028(\n+\tuint8_t   bin,\n+\tint32_t   VL53LX_p_007,\n+\tint32_t   VL53LX_p_032,\n+\tint32_t   VL53LX_p_001,\n+\tint32_t   ax,\n+\tint32_t   bx,\n+\tint32_t   cx,\n+\tint32_t   VL53LX_p_028,\n+\tuint8_t   VL53LX_p_030,\n+\tuint32_t *pmean_phase);\n+uint32_t VL53LX_calc_pll_period_mm(uint16_t fast_osc_frequency);\n+int32_t VL53LX_range_maths(\n+\tuint16_t  fast_osc_frequency,\n+\tuint16_t  VL53LX_p_014,\n+\tuint16_t  zero_distance_phase,\n+\tuint8_t   fractional_bits,\n+\tint32_t   gain_factor,\n+\tint32_t   range_offset_mm);\n+uint16_t VL53LX_rate_per_spad_maths(uint32_t frac_bits, uint32_t peak_count_rate, uint16_t num_spads, uint32_t max_output_value);\n+VL53LX_Error VL53LX_hist_process_data(\n+\tVL53LX_dmax_calibration_data_t     *pdmax_cal,\n+\tVL53LX_hist_gen3_dmax_config_t     *pdmax_cfg,\n+\tVL53LX_hist_post_process_config_t  *ppost_cfg,\n+\tVL53LX_histogram_bin_data_t        *pbins_input,\n+\tVL53LX_xtalk_histogram_data_t      *pxtalk_shape,\n+\tuint8_t                            *pArea1,\n+\tuint8_t                            *pArea2,\n+\tVL53LX_range_results_t             *presults,\n+\tuint8_t                            *HistMergeNumber);\n+VL53LX_Error VL53LX_hist_wrap_dmax(VL53LX_hist_post_process_config_t *phistpostprocess, VL53LX_histogram_bin_data_t *pcurrent, int16_t *pwrap_dmax_mm);\n+VL53LX_Error VL53LX_ipp_hist_process_data(\n+\tVL53LX_DEV                         Dev,\n+\tVL53LX_dmax_calibration_data_t    *pdmax_cal,\n+\tVL53LX_hist_gen3_dmax_config_t    *pdmax_cfg,\n+\tVL53LX_hist_post_process_config_t *ppost_cfg,\n+\tVL53LX_histogram_bin_data_t       *pbins,\n+\tVL53LX_xtalk_histogram_data_t     *pxtalk,\n+\tuint8_t                           *pArea1,\n+\tuint8_t                           *pArea2,\n+\tuint8_t                           *phisto_merge_nb,\n+\tVL53LX_range_results_t            *presults);\n+VL53LX_Error VL53LX_hist_events_consistency_check(\n+\tuint8_t                      event_sigma,\n+\tuint16_t                     min_effective_spad_count,\n+\tVL53LX_zone_hist_info_t     *phist_prev,\n+\tVL53LX_object_data_t        *prange_prev,\n+\tVL53LX_range_data_t         *prange_curr,\n+\tint32_t                     *pevents_tolerance,\n+\tint32_t                     *pevents_delta,\n+\tVL53LX_DeviceError          *prange_status);\n+VL53LX_Error VL53LX_hist_phase_consistency_check(VL53LX_DEV Dev, VL53LX_zone_hist_info_t *phist_prev, VL53LX_zone_objects_t *prange_prev, VL53LX_range_results_t *prange_curr);\n+VL53LX_Error VL53LX_hist_merged_pulse_check(int16_t min_max_tolerance_mm, VL53LX_range_data_t *pdata, VL53LX_DeviceError *prange_status);\n+VL53LX_Error VL53LX_hist_xmonitor_consistency_check(VL53LX_DEV Dev, VL53LX_zone_hist_info_t *phist_prev, VL53LX_zone_objects_t *prange_prev, VL53LX_range_data_t *prange_curr);\n+void VL53LX_init_system_results(VL53LX_system_results_t *pdata);\n+void VL53LX_hist_copy_results_to_sys_and_core(\n+\tVL53LX_histogram_bin_data_t      *pbins,\n+\tVL53LX_range_results_t           *phist,\n+\tVL53LX_system_results_t          *psys,\n+\tVL53LX_core_results_t            *pcore);\n+VL53LX_Error VL53LX_dynamic_zone_update(VL53LX_DEV Dev, VL53LX_range_results_t *presults);\n+void VL53LX_copy_hist_bins_to_static_cfg(VL53LX_histogram_config_t *phistogram, VL53LX_static_config_t *pstatic, VL53LX_timing_config_t *ptiming);\n+VL53LX_Error VL53LX_multizone_hist_bins_update(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_calc_required_samples(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_calc_new_xtalk(\n+\tVL53LX_DEV\t\t\t\tDev,\n+\tuint32_t\t\t\t\txtalk_offset_out,\n+\tVL53LX_smudge_corrector_config_t\t*pconfig,\n+\tVL53LX_smudge_corrector_data_t\t\t*pout,\n+\tuint8_t\t\t\t\t\tadd_smudge,\n+\tuint8_t\t\t\t\t\tsoft_update\n+\t);\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_corrector(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_i2c_decode_debug_results(uint16_t buf_size, uint8_t *pbuffer, VL53LX_debug_results_t *pdata);\n+VL53LX_Error VL53LX_i2c_decode_core_results(uint16_t buf_size, uint8_t *pbuffer, VL53LX_core_results_t *pdata);\n+VL53LX_Error VL53LX_i2c_decode_system_results(uint16_t buf_size, uint8_t *pbuffer, VL53LX_system_results_t *pdata);\n+VL53LX_Error VL53LX_get_measurement_results(VL53LX_DEV Dev, VL53LX_DeviceResultsLevel device_results_level);\n+void VL53LX_copy_sys_and_core_results_to_range_results(int32_t gain_factor, VL53LX_system_results_t *psys, VL53LX_core_results_t *pcore, VL53LX_range_results_t *presults);\n+VL53LX_Error VL53LX_low_power_auto_setup_manual_calibration(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_low_power_auto_update_DSS(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_check_ll_driver_rd_state(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_set_ref_spad_char_config(\n+\tVL53LX_DEV    Dev,\n+\tuint8_t       vcsel_period_a,\n+\tuint32_t      phasecal_timeout_us,\n+\tuint16_t      total_rate_target_mcps,\n+\tuint16_t      max_count_rate_rtn_limit_mcps,\n+\tuint16_t      min_count_rate_rtn_limit_mcps,\n+\tuint16_t      fast_osc_frequency);\n+VL53LX_Error VL53LX_start_test(VL53LX_DEV Dev, uint8_t test_mode__ctrl);\n+VL53LX_Error VL53LX_wait_for_test_completion(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_clear_interrupt(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_run_device_test(VL53LX_DEV Dev, VL53LX_DeviceTestMode device_test_mode);\n+VL53LX_Error VL53LX_run_ref_spad_char(VL53LX_DEV Dev, VL53LX_Error *pcal_status);\n+VL53LX_Error VL53LX_PerformRefSpadManagement(VL53LX_DEV Dev);\n+void VL53LX_hist_xtalk_extract_data_init(VL53LX_hist_xtalk_extract_data_t *pxtalk_data);\n+VL53LX_Error VL53LX_wait_for_range_completion(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_hist_xtalk_extract_calc_window(\n+\tint16_t                             target_distance_mm,\n+\tuint16_t                            target_width_oversize,\n+\tVL53LX_histogram_bin_data_t        *phist_bins,\n+\tVL53LX_hist_xtalk_extract_data_t   *pxtalk_data);\n+VL53LX_Error VL53LX_hist_xtalk_extract_calc_event_sums(VL53LX_histogram_bin_data_t *phist_bins, VL53LX_hist_xtalk_extract_data_t *pxtalk_data);\n+VL53LX_Error VL53LX_hist_xtalk_extract_update(\n+\tint16_t                             target_distance_mm,\n+\tuint16_t                            target_width_oversize,\n+\tVL53LX_histogram_bin_data_t        *phist_bins,\n+\tVL53LX_hist_xtalk_extract_data_t   *pxtalk_data);\n+VL53LX_Error VL53LX_hist_xtalk_extract_calc_rate_per_spad(VL53LX_hist_xtalk_extract_data_t *pxtalk_data);\n+VL53LX_Error VL53LX_hist_xtalk_extract_calc_shape(VL53LX_hist_xtalk_extract_data_t *pxtalk_data, VL53LX_xtalk_histogram_shape_t *pxtalk_shape);\n+VL53LX_Error VL53LX_hist_xtalk_extract_fini(\n+\tVL53LX_histogram_bin_data_t        *phist_bins,\n+\tVL53LX_hist_xtalk_extract_data_t   *pxtalk_data,\n+\tVL53LX_xtalk_calibration_results_t *pxtalk_cal,\n+\tVL53LX_xtalk_histogram_shape_t     *pxtalk_shape);\n+VL53LX_Error VL53LX_run_hist_xtalk_extraction(VL53LX_DEV Dev, int16_t cal_distance_mm, VL53LX_Error *pcal_status);\n+VL53LX_Error VL53LX_PerformXTalkCalibration(VL53LX_DEV Dev);\n+VL53LX_Error VL53LX_PerformOffsetSimpleCalibration(VL53LX_DEV Dev, int32_t CalDistanceMilliMeter);\n+VL53LX_Error VL53LX_GetDistanceMode(VL53LX_DEV Dev, VL53LX_DistanceModes *pDistanceMode);\n+VL53LX_Error VL53LX_PerformOffsetPerVcselCalibration(VL53LX_DEV Dev, int32_t CalDistanceMilliMeter);\n+VL53LX_Error VL53LX_PerformOffsetZeroDistanceCalibration(VL53LX_DEV Dev);\n+int stmvl53lx_setup(struct stmvl53lx_data *data);\n+void stmvl53lx_cleanup(struct stmvl53lx_data *data);\n+void stmvl53lx_pm_suspend_stop(struct stmvl53lx_data *data);\n+int stmvl53lx_init_i2c(void);\n+void stmvl53lx_exit_i2c(void *i2c_object);\n+int stmvl53lx_power_up_i2c(void *object);\n+int stmvl53lx_power_down_i2c(void *i2c_object);\n+int stmvl53lx_reset_release_i2c(void *i2c_object);\n+int stmvl53lx_reset_hold_i2c(void *i2c_object);\n+void stmvl53lx_clean_up_i2c(void);\n+int stmvl53lx_start_intr(void *object, int *poll_mode);\n+void *stmvl53lx_get(void *object);\n+\n+void st_gettimeofday(struct st_timeval *tv)\n+{\n+\tstruct timespec64 now;\n+\n+\tktime_get_real_ts64(&now);\n+\ttv->tv_sec = now.tv_sec;\n+\ttv->tv_usec = now.tv_nsec/1000;\n+}\n+\n+#if STMVL53LX_LOG_CCI_TIMING\n+static uint32_t tv_elapsed_us(struct st_timeval *tv)\n+{\n+\tstruct st_timeval now;\n+\n+\tst_gettimeofday(&now);\n+\treturn (now.tv_sec - tv->tv_sec) * 1000000 + (now.tv_usec - tv->tv_usec);\n+}\n+\n+#define\tcci_access_var struct st_timeval cci_log_start_tv\n+#define cci_access_start() st_gettimeofday(&cci_log_start_tv)\n+#define cci_access_over(fmt, ...) printk(\"cci_timing %d us\" fmt \"\\n\", tv_elapsed_us(&cci_log_start_tv), ##__VA_ARGS__)\n+#else\n+#define cci_access_var\n+#define cci_access_start(...) ((void)0)\n+#define cci_access_over(...) ((void)0)\n+#endif\n+\n+static int get_xsdn(struct device *dev, struct i2c_data *i2c_data)\n+{\n+\tint rc = 0;\n+\n+\ti2c_data->io_flag.xsdn_owned = 0;\n+\tif (i2c_data->xsdn_gpio == -1) {\n+\t\tvl53lx_errmsg(\"reset gpio is required\");\n+\t\trc = -ENODEV;\n+\t\tgoto no_gpio;\n+\t}\n+\n+\tvl53lx_dbgmsg(\"request xsdn_gpio %d\", i2c_data->xsdn_gpio);\n+\trc = gpio_request(i2c_data->xsdn_gpio, \"vl53lx_xsdn\");\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"fail to acquire xsdn %d\", rc);\n+\t\tgoto request_failed;\n+\t}\n+\n+\trc = gpio_direction_output(i2c_data->xsdn_gpio, 0);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"fail to configure xsdn as output %d\", rc);\n+\t\tgoto direction_failed;\n+\t}\n+\ti2c_data->io_flag.xsdn_owned = 1;\n+\n+\treturn rc;\n+\n+direction_failed:\n+\tgpio_free(i2c_data->xsdn_gpio);\n+\n+request_failed:\n+no_gpio:\n+\treturn rc;\n+}\n+\n+static void put_xsdn(struct i2c_data *i2c_data)\n+{\n+\tif (i2c_data->io_flag.xsdn_owned) {\n+\t\tvl53lx_dbgmsg(\"release xsdn_gpio %d\", i2c_data->xsdn_gpio);\n+\t\tgpio_free(i2c_data->xsdn_gpio);\n+\t\ti2c_data->io_flag.xsdn_owned = 0;\n+\t}\n+\ti2c_data->xsdn_gpio = -1;\n+}\n+\n+static int get_pwren(struct device *dev, struct i2c_data *i2c_data)\n+{\n+\tint rc = 0;\n+\n+\ti2c_data->io_flag.pwr_owned = 0;\n+\tif (i2c_data->pwren_gpio == -1) {\n+\t\tvl53lx_wanrmsg(\"pwren gpio disable\");\n+\t\tgoto no_gpio;\n+\t}\n+\n+\tvl53lx_dbgmsg(\"request pwren_gpio %d\", i2c_data->pwren_gpio);\n+\trc = gpio_request(i2c_data->pwren_gpio, \"vl53lx_pwren\");\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"fail to acquire pwren %d\", rc);\n+\t\tgoto request_failed;\n+\t}\n+\n+\trc = gpio_direction_output(i2c_data->pwren_gpio, 0);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"fail to configure pwren as output %d\", rc);\n+\t\tgoto direction_failed;\n+\t}\n+\ti2c_data->io_flag.pwr_owned = 1;\n+\n+\treturn rc;\n+\n+direction_failed:\n+\tgpio_free(i2c_data->xsdn_gpio);\n+\n+request_failed:\n+no_gpio:\n+\treturn rc;\n+}\n+\n+static void put_pwren(struct i2c_data *i2c_data)\n+{\n+\tif (i2c_data->io_flag.pwr_owned) {\n+\t\tvl53lx_dbgmsg(\"release xsdn_gpio %d\", i2c_data->xsdn_gpio);\n+\t\tgpio_free(i2c_data->pwren_gpio);\n+\t\ti2c_data->io_flag.pwr_owned = 0;\n+\t}\n+\ti2c_data->pwren_gpio = -1;\n+}\n+\n+static int get_intr(struct device *dev, struct i2c_data *i2c_data)\n+{\n+\tint rc = 0;\n+\n+\ti2c_data->io_flag.intr_owned = 0;\n+\tif (i2c_data->intr_gpio == -1) {\n+\t\tvl53lx_wanrmsg(\"no interrupt gpio\");\n+\t\tgoto no_gpio;\n+\t}\n+\n+\tvl53lx_dbgmsg(\"request intr_gpio %d\", i2c_data->intr_gpio);\n+\trc = gpio_request(i2c_data->intr_gpio, \"vl53lx_intr\");\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"fail to acquire intr %d\", rc);\n+\t\tgoto request_failed;\n+\t}\n+\n+\trc = gpio_direction_input(i2c_data->intr_gpio);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"fail to configure intr as input %d\", rc);\n+\t\tgoto direction_failed;\n+\t}\n+\n+\ti2c_data->irq = gpio_to_irq(i2c_data->intr_gpio);\n+\tif (i2c_data->irq < 0) {\n+\t\tvl53lx_errmsg(\"fail to map GPIO: %d to interrupt:%d\\n\", i2c_data->intr_gpio, i2c_data->irq);\n+\t\tgoto irq_failed;\n+\t}\n+\ti2c_data->io_flag.intr_owned = 1;\n+\n+\treturn rc;\n+\n+irq_failed:\n+direction_failed:\n+\tgpio_free(i2c_data->intr_gpio);\n+\n+request_failed:\n+no_gpio:\n+\treturn rc;\n+}\n+\n+static void put_intr(struct i2c_data *i2c_data)\n+{\n+\tif (i2c_data->io_flag.intr_owned) {\n+\t\tif (i2c_data->io_flag.intr_started) {\n+\t\t\tfree_irq(i2c_data->irq, i2c_data);\n+\t\t\ti2c_data->io_flag.intr_started = 0;\n+\t\t}\n+\t\tvl53lx_dbgmsg(\"release intr_gpio %d\", i2c_data->intr_gpio);\n+\t\tgpio_free(i2c_data->intr_gpio);\n+\t\ti2c_data->io_flag.intr_owned = 0;\n+\t}\n+\ti2c_data->intr_gpio = -1;\n+}\n+\n+static int handle_i2c_address_device_change_lock(struct i2c_data *data)\n+{\n+\tstruct i2c_client *client = (struct i2c_client *) data->client;\n+\tuint8_t buffer[3];\n+\tstruct i2c_msg msg;\n+\tint rc = 0;\n+\n+\tvl53lx_dbgmsg(\"change device i2c address from 0x%02x to 0x%02x\", data->boot_reg, client->addr);\n+\n+\tusleep_range(VL53LX_FIRMWARE_BOOT_TIME_US, VL53LX_FIRMWARE_BOOT_TIME_US + 1);\n+\n+\tbuffer[0] = (VL53LX_I2C_SLAVE__DEVICE_ADDRESS >> 8) & 0xFF;\n+\tbuffer[1] = (VL53LX_I2C_SLAVE__DEVICE_ADDRESS >> 0) & 0xFF;\n+\tbuffer[2] = client->addr;\n+\tmsg.addr = data->boot_reg;\n+\tmsg.flags = client->flags;\n+\tmsg.buf = buffer;\n+\tmsg.len = 3;\n+\tif (i2c_transfer(client->adapter, &msg, 1) != 1) {\n+\t\trc = -ENXIO;\n+\t\tvl53lx_errmsg(\"Fail to change i2c address to 0x%02x\", client->addr);\n+\t}\n+\n+\treturn rc;\n+}\n+\n+static int release_reset(struct i2c_data *data)\n+{\n+\tstruct i2c_client *client = (struct i2c_client *) data->client;\n+\tint rc = 0;\n+\tbool is_address_change = client->addr != data->boot_reg;\n+\n+\tif (is_address_change)\n+\t\tmutex_lock(&dev_addr_change_mutex);\n+\n+\tgpio_set_value(data->xsdn_gpio, 1);\n+\tif (is_address_change) {\n+\t\trc = handle_i2c_address_device_change_lock(data);\n+\t\tif (rc)\n+\t\t\tgpio_set_value(data->xsdn_gpio, 0);\n+\t}\n+\n+\tif (is_address_change)\n+\t\tmutex_unlock(&dev_addr_change_mutex);\n+\n+\treturn rc;\n+}\n+\n+VL53LX_Error VL53LX_WaitUs(VL53LX_DEV pdev, int32_t wait_us)\n+{\n+\tstruct stmvl53lx_data *data;\n+\n+\tdata = (struct stmvl53lx_data *)container_of(pdev, struct stmvl53lx_data, stdev);\n+\n+\tif (!data->is_delay_allowed)\n+\t\treturn VL53LX_ERROR_PLATFORM_SPECIFIC_START;\n+\n+\tif (wait_us < 10)\n+\t\tudelay(wait_us);\n+\telse if (wait_us < 20000)\n+\t\tusleep_range(wait_us, wait_us + 1);\n+\telse\n+\t\tmsleep(wait_us / 1000);\n+\n+\treturn VL53LX_ERROR_NONE;\n+}\n+\n+VL53LX_Error VL53LX_WaitMs(VL53LX_DEV pdev, int32_t wait_ms)\n+{\n+\treturn VL53LX_WaitUs(pdev, wait_ms * 1000);\n+}\n+\n+static int cci_write(struct stmvl53lx_data *dev, int index, uint8_t *data, uint16_t len)\n+{\n+\tuint8_t buffer[STMVL53LX_MAX_CCI_XFER_SZ + 2];\n+\tstruct i2c_msg msg;\n+\tstruct i2c_data *i2c_client_obj = (struct i2c_data *)dev->client_object;\n+\tstruct i2c_client *client = (struct i2c_client *)i2c_client_obj->client;\n+\tint rc;\n+\n+\tcci_access_var;\n+\tif (len > STMVL53LX_MAX_CCI_XFER_SZ || len == 0) {\n+\t\tvl53lx_errmsg(\"invalid len %d\\n\", len);\n+\t\treturn -1;\n+\t}\n+\tcci_access_start();\n+\tbuffer[0] = (index >> 8) & 0xFF;\n+\tbuffer[1] = (index >> 0) & 0xFF;\n+\tmemcpy(buffer + 2, data, len);\n+\tmsg.addr = client->addr;\n+\tmsg.flags = client->flags;\n+\tmsg.buf = buffer;\n+\tmsg.len = len + 2;\n+\n+\trc = i2c_transfer(client->adapter, &msg, 1);\n+\tif (rc != 1) {\n+\t\tvl53lx_errmsg(\"wr i2c_transfer err:%d, index 0x%x len %d\\n\", rc, index, len);\n+\t}\n+\tcci_access_over(\"rd status %d long %d \", rc != 1, len);\n+\treturn rc != 1;\n+}\n+\n+static int cci_read(struct stmvl53lx_data *dev, int index, uint8_t *data, uint16_t len)\n+{\n+\tuint8_t buffer[2];\n+\tstruct i2c_msg msg[2];\n+\tstruct i2c_data *i2c_client_obj = (struct i2c_data *)dev->client_object;\n+\tstruct i2c_client *client = (struct i2c_client *)i2c_client_obj->client;\n+\tint rc;\n+\n+\tcci_access_var;\n+\tif (len > STMVL53LX_MAX_CCI_XFER_SZ || len == 0) {\n+\t\tvl53lx_errmsg(\"invalid len %d\\n\", len);\n+\t\treturn -1;\n+\t}\n+\tcci_access_start();\n+\n+\tbuffer[0] = (index >> 8) & 0xFF;\n+\tbuffer[1] = (index >> 0) & 0xFF;\n+\n+\tmsg[0].addr = client->addr;\n+\tmsg[0].flags = client->flags;\n+\tmsg[0].buf = buffer;\n+\tmsg[0].len = 2;\n+\n+\tmsg[1].addr = client->addr;\n+\tmsg[1].flags = I2C_M_RD | client->flags;\n+\tmsg[1].buf = data;\n+\tmsg[1].len = len;\n+\n+\trc = i2c_transfer(client->adapter, msg, 2);\n+\tif (rc != 2) {\n+\t\tpr_err(\"%s: i2c_transfer :%d, @%x index 0x%x len %d\\n\", __func__, rc, client->addr, index, len);\n+\t}\n+\tcci_access_over(\" wr len %d status %d\", rc != 2, len);\n+\treturn rc != 2;\n+}\n+\n+static uint32_t tv_elapsed_ms(struct st_timeval *tv)\n+{\n+\tstruct st_timeval now;\n+\n+\tst_gettimeofday(&now);\n+\treturn (now.tv_sec - tv->tv_sec) * 1000 + (now.tv_usec - tv->tv_usec) / 1000;\n+}\n+\n+static int is_time_over(struct st_timeval *tv, uint32_t msec)\n+{\n+\treturn tv_elapsed_ms(tv) >= msec;\n+}\n+\n+VL53LX_Error VL53LX_WaitValueMaskEx(VL53LX_DEV pdev, uint32_t timeout_ms, uint16_t index, uint8_t value, uint8_t mask, uint32_t poll_delay_ms)\n+{\n+\tstruct st_timeval start_tv;\n+\tstruct stmvl53lx_data *dev;\n+\tint rc, time_over;\n+\tuint8_t rd_val;\n+\n+\tdev = (struct stmvl53lx_data *)container_of(pdev, struct stmvl53lx_data, stdev);\n+\n+\tst_gettimeofday(&start_tv);\n+\tdo {\n+\t\trc = cci_read(dev, index, &rd_val, 1);\n+\t\tif (rc)\n+\t\t\treturn VL53LX_ERROR_CONTROL_INTERFACE;\n+\t\tif ((rd_val & mask) == value) {\n+\t\t\tpoll_timing_log(&start_tv);\n+\t\t\treturn VL53LX_ERROR_NONE;\n+\t\t}\n+\t\tvl53lx_dbgmsg(\"poll @%x %x & %d != %x\", index, rd_val, mask, value);\n+\t\ttime_over = is_time_over(&start_tv, timeout_ms);\n+\t\tif (!time_over)\n+\t\t\tmsleep(poll_delay_ms);\n+\t} while (!time_over);\n+\tvl53lx_errmsg(\"time over %d ms\", timeout_ms);\n+\treturn VL53LX_ERROR_TIME_OUT;\n+}\n+\n+void VL53LX_init_ll_driver_state(VL53LX_DEV Dev, VL53LX_DeviceState device_state)\n+{\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_ll_driver_state_t *pstate = &(pdev->ll_state);\n+\n+\tpstate->cfg_device_state  = device_state;\n+\tpstate->cfg_stream_count  = 0;\n+\tpstate->cfg_gph_id        = VL53LX_GROUPEDPARAMETERHOLD_ID_MASK;\n+\tpstate->cfg_timing_status = 0;\n+\tpstate->cfg_zone_id       = 0;\n+\n+\tpstate->rd_device_state   = device_state;\n+\tpstate->rd_stream_count   = 0;\n+\tpstate->rd_gph_id         = VL53LX_GROUPEDPARAMETERHOLD_ID_MASK;\n+\tpstate->rd_timing_status  = 0;\n+\tpstate->rd_zone_id        = 0;\n+}\n+\n+VL53LX_Error VL53LX_poll_for_boot_completion(VL53LX_DEV Dev, uint32_t timeout_ms)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tstatus = VL53LX_WaitUs(Dev, VL53LX_FIRMWARE_BOOT_TIME_US);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WaitValueMaskEx(Dev, timeout_ms, VL53LX_FIRMWARE__SYSTEM_STATUS, 0x01, 0x01, VL53LX_POLLING_DELAY_MS);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tVL53LX_init_ll_driver_state(Dev, VL53LX_DEVICESTATE_SW_STANDBY);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_WaitDeviceBooted(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\n+\tStatus = VL53LX_poll_for_boot_completion(Dev, VL53LX_BOOT_COMPLETION_POLLING_TIMEOUT_MS);\n+\n+\treturn Status;\n+}\n+\n+static int stmvl53lx_input_setup(struct stmvl53lx_data *data)\n+{\n+\tint rc = 0;\n+\tstruct input_dev *idev;\n+\tidev = input_allocate_device();\n+\tif (idev == NULL) {\n+\t\trc = -ENOMEM;\n+\t\tvl53lx_errmsg(\"%d error:%d\\n\", __LINE__, rc);\n+\t\tgoto exit_err;\n+\t}\n+\n+\tset_bit(EV_ABS, idev->evbit);\n+\n+\tinput_set_abs_params(idev, ABS_DISTANCE, 0, 0xff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_HAT0X, 0, 0xffffffff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_HAT0Y, 0, 0xffffffff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_HAT1X, 0, 0xffffffff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_HAT1Y, 0, 0xffffffff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_HAT2X, 0, 0xffffffff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_HAT2Y, 0, 0xffffffff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_HAT3X, 0, 0xffffffff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_HAT3Y, 0, 0xffffffff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_WHEEL, 0, 0xffffffff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_TILT_Y, 0, 0xffffffff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_BRAKE, 0, 0xffffffff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_TILT_X, 0, 0xffffffff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_TOOL_WIDTH, 0, 0xffffffff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_THROTTLE, 0, 0xffffffff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_RUDDER, 0, 0xffffffff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_MISC, 0, 0xffffffff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_VOLUME, 0, 0xffffffff, 0, 0);\n+\tinput_set_abs_params(idev, ABS_GAS, 0, 0xffffffff, 0, 0);\n+\n+\tidev->name = \"STM VL53LX proximity sensor\";\n+\trc = input_register_device(idev);\n+\tif (rc) {\n+\t\trc = -ENOMEM;\n+\t\tvl53lx_errmsg(\"%d error:%d\\n\", __LINE__, rc);\n+\t\tgoto exit_free_dev_ps;\n+\t}\n+\tinput_set_drvdata(idev, data);\n+\tdata->input_dev_ps = idev;\n+\treturn 0;\n+\n+exit_free_dev_ps:\n+\tinput_free_device(data->input_dev_ps);\n+exit_err:\n+\treturn rc;\n+}\n+\n+uint32_t VL53LX_calc_pll_period_us(uint16_t fast_osc_frequency)\n+{\n+\tuint32_t pll_period_us = 0;\n+\n+\tif (fast_osc_frequency > 0)\n+\t\tpll_period_us = (0x01 << 30) / fast_osc_frequency;\n+\treturn pll_period_us;\n+}\n+\n+uint8_t VL53LX_decode_vcsel_period(uint8_t vcsel_period_reg)\n+{\n+\tuint8_t VL53LX_p_030 = 0;\n+\n+\tVL53LX_p_030 = (vcsel_period_reg + 1) << 1;\n+\treturn VL53LX_p_030;\n+}\n+\n+\n+uint32_t VL53LX_calc_macro_period_us(uint16_t fast_osc_frequency, uint8_t VL53LX_p_005)\n+{\n+\tuint32_t  pll_period_us        = 0;\n+\tuint8_t   VL53LX_p_030   = 0;\n+\tuint32_t  macro_period_us      = 0;\n+\n+\tpll_period_us = VL53LX_calc_pll_period_us(fast_osc_frequency);\n+\n+\tVL53LX_p_030 = VL53LX_decode_vcsel_period(VL53LX_p_005);\n+\n+\tmacro_period_us = (uint32_t)VL53LX_MACRO_PERIOD_VCSEL_PERIODS * pll_period_us;\n+\tmacro_period_us = macro_period_us >> 6;\n+\n+\tmacro_period_us = macro_period_us * (uint32_t)VL53LX_p_030;\n+\tmacro_period_us = macro_period_us >> 6;\n+\n+\treturn macro_period_us;\n+}\n+\n+uint32_t VL53LX_calc_timeout_us(uint32_t timeout_mclks, uint32_t macro_period_us)\n+{\n+\tuint32_t timeout_us     = 0;\n+\tuint64_t tmp            = 0;\n+\n+\n+\ttmp  = (uint64_t)timeout_mclks * (uint64_t)macro_period_us;\n+\ttmp += 0x00800;\n+\ttmp  = tmp >> 12;\n+\n+\ttimeout_us = (uint32_t)tmp;\n+\n+\treturn timeout_us;\n+}\n+\n+uint32_t VL53LX_decode_timeout(uint16_t encoded_timeout)\n+{\n+\tuint32_t timeout_macro_clks = 0;\n+\n+\ttimeout_macro_clks = ((uint32_t) (encoded_timeout & 0x00FF) << (uint32_t) ((encoded_timeout & 0xFF00) >> 8)) + 1;\n+\n+\treturn timeout_macro_clks;\n+}\n+\n+uint32_t VL53LX_calc_decoded_timeout_us(\n+\tuint16_t timeout_encoded,\n+\tuint32_t macro_period_us)\n+{\n+\tuint32_t timeout_mclks  = 0;\n+\tuint32_t timeout_us     = 0;\n+\n+\ttimeout_mclks = VL53LX_decode_timeout(timeout_encoded);\n+\n+\ttimeout_us = VL53LX_calc_timeout_us(timeout_mclks, macro_period_us);\n+\n+\treturn timeout_us;\n+}\n+\n+VL53LX_Error VL53LX_get_timeouts_us(VL53LX_DEV Dev, uint32_t *pphasecal_config_timeout_us, uint32_t *pmm_config_timeout_us, uint32_t *prange_config_timeout_us)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tuint32_t  macro_period_us = 0;\n+\tuint16_t  timeout_encoded = 0;\n+\n+\tif (pdev->stat_nvm.osc_measured__fast_osc__frequency == 0)\n+\t\tstatus = VL53LX_ERROR_DIVISION_BY_ZERO;\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tmacro_period_us = VL53LX_calc_macro_period_us(pdev->stat_nvm.osc_measured__fast_osc__frequency, pdev->tim_cfg.range_config__vcsel_period_a);\n+\n+\t\t*pphasecal_config_timeout_us = VL53LX_calc_timeout_us((uint32_t)pdev->gen_cfg.phasecal_config__timeout_macrop, macro_period_us);\n+\n+\t\ttimeout_encoded = (uint16_t)pdev->tim_cfg.mm_config__timeout_macrop_a_hi;\n+\t\ttimeout_encoded = (timeout_encoded << 8) + (uint16_t)pdev->tim_cfg.mm_config__timeout_macrop_a_lo;\n+\n+\t\t*pmm_config_timeout_us = VL53LX_calc_decoded_timeout_us(timeout_encoded, macro_period_us);\n+\n+\t\ttimeout_encoded = (uint16_t)pdev->tim_cfg.range_config__timeout_macrop_a_hi;\n+\t\ttimeout_encoded = (timeout_encoded << 8) + (uint16_t)pdev->tim_cfg.range_config__timeout_macrop_a_lo;\n+\n+\t\t*prange_config_timeout_us = VL53LX_calc_decoded_timeout_us(timeout_encoded, macro_period_us);\n+\n+\t\tpdev->phasecal_config_timeout_us = *pphasecal_config_timeout_us;\n+\t\tpdev->mm_config_timeout_us       = *pmm_config_timeout_us;\n+\t\tpdev->range_config_timeout_us    = *prange_config_timeout_us;\n+\n+\t}\n+\n+\treturn status;\n+}\n+\n+uint32_t VL53LX_calc_timeout_mclks(uint32_t timeout_us, uint32_t macro_period_us)\n+{\n+\tuint32_t timeout_mclks   = 0;\n+\n+\tif (macro_period_us == 0)\n+\t\ttimeout_mclks = 0;\n+\telse\n+\t\ttimeout_mclks = ((timeout_us << 12) + (macro_period_us>>1)) / macro_period_us;\n+\n+\treturn timeout_mclks;\n+}\n+\n+uint16_t VL53LX_encode_timeout(uint32_t timeout_mclks)\n+{\n+\tuint16_t encoded_timeout = 0;\n+\tuint32_t ls_byte = 0;\n+\tuint16_t ms_byte = 0;\n+\n+\tif (timeout_mclks > 0) {\n+\t\tls_byte = timeout_mclks - 1;\n+\t\twhile ((ls_byte & 0xFFFFFF00) > 0) {\n+\t\t\tls_byte = ls_byte >> 1;\n+\t\t\tms_byte++;\n+\t\t}\n+\t\tencoded_timeout = (ms_byte << 8) + (uint16_t) (ls_byte & 0x000000FF);\n+\t}\n+\treturn encoded_timeout;\n+}\n+\n+\n+uint16_t VL53LX_calc_encoded_timeout(uint32_t timeout_us, uint32_t macro_period_us)\n+{\n+\tuint32_t timeout_mclks   = 0;\n+\tuint16_t timeout_encoded = 0;\n+\n+\ttimeout_mclks = VL53LX_calc_timeout_mclks(timeout_us, macro_period_us);\n+\n+\ttimeout_encoded = VL53LX_encode_timeout(timeout_mclks);\n+\n+\treturn timeout_encoded;\n+}\n+\n+VL53LX_Error VL53LX_calc_timeout_register_values(uint32_t phasecal_config_timeout_us, uint32_t mm_config_timeout_us, uint32_t range_config_timeout_us, uint16_t fast_osc_frequency, VL53LX_general_config_t *pgeneral, VL53LX_timing_config_t  *ptiming)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tuint32_t macro_period_us    = 0;\n+\tuint32_t timeout_mclks      = 0;\n+\tuint16_t timeout_encoded    = 0;\n+\n+\tif (fast_osc_frequency == 0) {\n+\t\tstatus = VL53LX_ERROR_DIVISION_BY_ZERO;\n+\t} else {\n+\t\tmacro_period_us = VL53LX_calc_macro_period_us(fast_osc_frequency, ptiming->range_config__vcsel_period_a);\n+\n+\t\ttimeout_mclks = VL53LX_calc_timeout_mclks(phasecal_config_timeout_us, macro_period_us);\n+\n+\t\tif (timeout_mclks > 0xFF)\n+\t\t\ttimeout_mclks = 0xFF;\n+\n+\t\tpgeneral->phasecal_config__timeout_macrop = (uint8_t)timeout_mclks;\n+\n+\t\ttimeout_encoded = VL53LX_calc_encoded_timeout(mm_config_timeout_us, macro_period_us);\n+\n+\t\tptiming->mm_config__timeout_macrop_a_hi = (uint8_t)((timeout_encoded & 0xFF00) >> 8);\n+\t\tptiming->mm_config__timeout_macrop_a_lo = (uint8_t) (timeout_encoded & 0x00FF);\n+\n+\t\ttimeout_encoded = VL53LX_calc_encoded_timeout(range_config_timeout_us, macro_period_us);\n+\n+\t\tptiming->range_config__timeout_macrop_a_hi = (uint8_t)((timeout_encoded & 0xFF00) >> 8);\n+\t\tptiming->range_config__timeout_macrop_a_lo = (uint8_t) (timeout_encoded & 0x00FF);\n+\n+\t\tmacro_period_us = VL53LX_calc_macro_period_us(fast_osc_frequency, ptiming->range_config__vcsel_period_b);\n+\n+\t\ttimeout_encoded = VL53LX_calc_encoded_timeout(mm_config_timeout_us, macro_period_us);\n+\n+\t\tptiming->mm_config__timeout_macrop_b_hi = (uint8_t)((timeout_encoded & 0xFF00) >> 8);\n+\t\tptiming->mm_config__timeout_macrop_b_lo = (uint8_t) (timeout_encoded & 0x00FF);\n+\n+\t\ttimeout_encoded = VL53LX_calc_encoded_timeout(range_config_timeout_us, macro_period_us);\n+\n+\t\tptiming->range_config__timeout_macrop_b_hi = (uint8_t)((timeout_encoded & 0xFF00) >> 8);\n+\t\tptiming->range_config__timeout_macrop_b_lo = (uint8_t) (timeout_encoded & 0x00FF);\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_set_timeouts_us(VL53LX_DEV Dev, uint32_t phasecal_config_timeout_us, uint32_t mm_config_timeout_us, uint32_t range_config_timeout_us)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tif (pdev->stat_nvm.osc_measured__fast_osc__frequency == 0)\n+\t\tstatus = VL53LX_ERROR_DIVISION_BY_ZERO;\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tpdev->phasecal_config_timeout_us = phasecal_config_timeout_us;\n+\t\tpdev->mm_config_timeout_us       = mm_config_timeout_us;\n+\t\tpdev->range_config_timeout_us    = range_config_timeout_us;\n+\n+\t\tstatus = VL53LX_calc_timeout_register_values(phasecal_config_timeout_us, mm_config_timeout_us, range_config_timeout_us, pdev->stat_nvm.osc_measured__fast_osc__frequency, &(pdev->gen_cfg), &(pdev->tim_cfg));\n+\t}\n+\treturn status;\n+}\n+\n+static int IsL4(VL53LX_DEV Dev)\n+{\n+\tint devL4 = 0;\n+\tVL53LX_LLDriverData_t *pDev;\n+\tpDev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tif ((pDev->nvm_copy_data.identification__module_type == 0xAA) && (pDev->nvm_copy_data.identification__model_id == 0xEB))\n+\t\tdevL4 = 1;\n+\treturn devL4;\n+}\n+\n+VL53LX_Error VL53LX_SetMeasurementTimingBudgetMicroSeconds(VL53LX_DEV Dev, uint32_t MeasurementTimingBudgetMicroSeconds)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tuint32_t TimingGuard;\n+\tuint32_t divisor;\n+\tuint32_t TimingBudget = 0;\n+\tuint32_t MmTimeoutUs = 0;\n+\tuint32_t PhaseCalTimeoutUs = 0;\n+\tuint32_t FDAMaxTimingBudgetUs = FDA_MAX_TIMING_BUDGET_US;\n+\n+\tif (MeasurementTimingBudgetMicroSeconds > 10000000)\n+\t\tStatus = VL53LX_ERROR_INVALID_PARAMS;\n+\n+\tif (Status == VL53LX_ERROR_NONE)\n+\t\tStatus = VL53LX_get_timeouts_us(Dev, &PhaseCalTimeoutUs, &MmTimeoutUs, &TimingBudget);\n+\n+\tTimingGuard = 1700;\n+\tdivisor = 6;\n+\n+\tif (IsL4(Dev))\n+\t\tFDAMaxTimingBudgetUs = L4_FDA_MAX_TIMING_BUDGET_US;\n+\n+\tif (MeasurementTimingBudgetMicroSeconds <= TimingGuard)\n+\t\tStatus = VL53LX_ERROR_INVALID_PARAMS;\n+\telse {\n+\t\tTimingBudget = (MeasurementTimingBudgetMicroSeconds - TimingGuard);\n+\t}\n+\n+\tif (Status == VL53LX_ERROR_NONE) {\n+\t\tif (TimingBudget > FDAMaxTimingBudgetUs)\n+\t\t\tStatus = VL53LX_ERROR_INVALID_PARAMS;\n+\t\telse {\n+\t\t\tTimingBudget /= divisor;\n+\t\t\tStatus = VL53LX_set_timeouts_us(Dev, PhaseCalTimeoutUs, MmTimeoutUs, TimingBudget);\n+\t\t}\n+\t\tif (Status == VL53LX_ERROR_NONE)\n+\t\t\tVL53LXDevDataSet(Dev, LLData.range_config_timeout_us, TimingBudget);\n+\t}\n+\tif (Status == VL53LX_ERROR_NONE) {\n+\t\tVL53LXDevDataSet(Dev, CurrentParameters.MeasurementTimingBudgetMicroSeconds, MeasurementTimingBudgetMicroSeconds);\n+\t}\n+\treturn Status;\n+}\n+\n+static int store_last_error(struct stmvl53lx_data *data, int rc)\n+{\n+\tdata->last_error = rc;\n+\n+\treturn -EIO;\n+}\n+\n+VL53LX_Error VL53LX_i2c_encode_system_control(VL53LX_system_control_t *pdata, uint16_t buf_size, uint8_t *pbuffer)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (buf_size < VL53LX_SYSTEM_CONTROL_I2C_SIZE_BYTES)\n+\t\treturn VL53LX_ERROR_COMMS_BUFFER_TOO_SMALL;\n+\n+\t*(pbuffer + 0) = pdata->power_management__go1_power_force & 0x1;\n+\t*(pbuffer + 1) = pdata->system__stream_count_ctrl & 0x1;\n+\t*(pbuffer + 2) = pdata->firmware__enable & 0x1;\n+\t*(pbuffer + 3) = pdata->system__interrupt_clear & 0x3;\n+\t*(pbuffer + 4) = pdata->system__mode_start;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_WriteMulti(VL53LX_DEV pdev, uint16_t index, uint8_t *pdata, uint32_t count)\n+{\n+\tuint32_t chunk_size = WRITE_MULTIPLE_CHUNK_MAX;\n+\tVL53LX_Error status;\n+\tuint32_t i;\n+\tuint16_t hostaddr = index;\n+\tstruct stmvl53lx_data *dev;\n+\n+\tdev = (struct stmvl53lx_data *)container_of(pdev, struct stmvl53lx_data, stdev);\n+\n+\tfor (i = 0; i < count; i += chunk_size) {\n+\t\tstatus = (cci_write(dev, hostaddr, &pdata[i],  min(chunk_size, (count - i))) ? VL53LX_ERROR_CONTROL_INTERFACE : VL53LX_ERROR_NONE);\n+\t\tif (status != VL53LX_ERROR_NONE)\n+\t\t\tbreak;\n+\t\thostaddr += chunk_size;\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_ReadMulti(VL53LX_DEV pdev, uint16_t index, uint8_t *pdata, uint32_t count)\n+{\n+\tstruct stmvl53lx_data *dev;\n+\n+\tdev = (struct stmvl53lx_data *)container_of(pdev, struct stmvl53lx_data, stdev);\n+\n+\treturn cci_read(dev, index, pdata, count) ? VL53LX_ERROR_CONTROL_INTERFACE : VL53LX_ERROR_NONE;\n+}\n+\n+VL53LX_Error VL53LX_RdByte(VL53LX_DEV pdev, uint16_t index, uint8_t *pdata)\n+{\n+\tstruct stmvl53lx_data *dev;\n+\tdev = (struct stmvl53lx_data *)container_of(pdev, struct stmvl53lx_data, stdev);\n+\n+\treturn cci_read(dev, index, pdata, 1) ? VL53LX_ERROR_CONTROL_INTERFACE : VL53LX_ERROR_NONE;\n+}\n+\n+VL53LX_Error VL53LX_WrByte(VL53LX_DEV pdev, uint16_t index, uint8_t data)\n+{\n+\tstruct stmvl53lx_data *dev;\n+\tdev = (struct stmvl53lx_data *)container_of(pdev, struct stmvl53lx_data, stdev);\n+\n+\treturn cci_write(dev, index, &data, 1);\n+}\n+\n+VL53LX_Error VL53LX_RdWord(VL53LX_DEV pdev, uint16_t index, uint16_t *pdata)\n+{\n+\tVL53LX_Error status;\n+\tuint8_t buffer[2];\n+\n+\tstatus = VL53LX_ReadMulti(pdev, index, buffer, 2);\n+\n+\t*pdata = ((uint16_t) buffer[0] << 8) + (uint16_t) buffer[1];\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_WrWord(VL53LX_DEV pdev, uint16_t index, uint16_t data)\n+{\n+\tVL53LX_Error status;\n+\tuint8_t buffer[2];\n+\n+\n+\tbuffer[0] = (uint8_t) (data >> 8);\n+\tbuffer[1] = (uint8_t) (data & 0x00FF);\n+\ti2c_debug(\" @%x d= %x  => [ %x , %x ] \", index, data, buffer[0], buffer[1]);\n+\tstatus = VL53LX_WriteMulti(pdev, index, buffer, 2);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_WrDWord(VL53LX_DEV pdev, uint16_t index, uint32_t data)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tuint8_t buffer[4];\n+\n+\tbuffer[0] = (uint8_t) (data >> 24);\n+\tbuffer[1] = (uint8_t) ((data & 0x00FF0000) >> 16);\n+\tbuffer[2] = (uint8_t) ((data & 0x0000FF00) >> 8);\n+\tbuffer[3] = (uint8_t) (data & 0x000000FF);\n+\n+\tstatus = VL53LX_WriteMulti(pdev, index, buffer, 4);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_RdDWord(VL53LX_DEV pdev, uint16_t index, uint32_t *pdata)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tuint8_t buffer[4];\n+\n+\tstatus = VL53LX_ReadMulti(pdev, index, buffer, 4);\n+\n+\t*pdata = ((uint32_t) buffer[0] << 24) + ((uint32_t) buffer[1] << 16) + ((uint32_t) buffer[2] << 8) + (uint32_t) buffer[3];\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_set_system_control(VL53LX_DEV Dev, VL53LX_system_control_t *pdata)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tuint8_t comms_buffer[VL53LX_SYSTEM_CONTROL_I2C_SIZE_BYTES];\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_i2c_encode_system_control(pdata, VL53LX_SYSTEM_CONTROL_I2C_SIZE_BYTES, comms_buffer);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WriteMulti(Dev, VL53LX_POWER_MANAGEMENT__GO1_POWER_FORCE, comms_buffer, VL53LX_SYSTEM_CONTROL_I2C_SIZE_BYTES);\n+\n+\treturn status;\n+}\n+\n+void V53L1_init_zone_results_structure(uint8_t active_zones, VL53LX_zone_results_t *pdata)\n+{\n+\tuint8_t  z = 0;\n+\tVL53LX_zone_objects_t *pobjects;\n+\n+\tpdata->max_zones    = VL53LX_MAX_USER_ZONES;\n+\tpdata->active_zones = active_zones;\n+\n+\tfor (z = 0; z < pdata->max_zones; z++) {\n+\t\tpobjects = &(pdata->VL53LX_p_003[z]);\n+\t\tpobjects->cfg_device_state = VL53LX_DEVICESTATE_SW_STANDBY;\n+\t\tpobjects->rd_device_state  = VL53LX_DEVICESTATE_SW_STANDBY;\n+\t\tpobjects->max_objects      = VL53LX_MAX_RANGE_RESULTS;\n+\t\tpobjects->active_objects   = 0;\n+\t}\n+}\n+\n+void V53L1_init_zone_dss_configs(VL53LX_DEV Dev)\n+{\n+\tVL53LX_LLDriverResults_t *pres = VL53LXDevStructGetLLResultsHandle(Dev);\n+\tuint8_t  z = 0;\n+\tuint8_t max_zones    = VL53LX_MAX_USER_ZONES;\n+\tVL53LX_zone_private_dyn_cfgs_t *pdata = &(pres->zone_dyn_cfgs);\n+\n+\tfor (z = 0; z < max_zones; z++) {\n+\t\tpdata->VL53LX_p_003[z].dss_mode = VL53LX_DSS_CONTROL__MODE_TARGET_RATE;\n+\t\tpdata->VL53LX_p_003[z].dss_requested_effective_spad_count = 0;\n+\t}\n+}\n+\n+VL53LX_Error VL53LX_low_power_auto_data_stop_range(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpdev->low_power_auto_data.low_power_auto_range_count = 0xFF;\n+\n+\tpdev->low_power_auto_data.first_run_phasecal_result = 0;\n+\tpdev->low_power_auto_data.dss__total_rate_per_spad_mcps = 0;\n+\tpdev->low_power_auto_data.dss__required_spads = 0;\n+\n+\tif (pdev->low_power_auto_data.saved_vhv_init != 0)\n+\t\tpdev->stat_nvm.vhv_config__init = pdev->low_power_auto_data.saved_vhv_init;\n+\tif (pdev->low_power_auto_data.saved_vhv_timeout != 0)\n+\t\tpdev->stat_nvm.vhv_config__timeout_macrop_loop_bound = pdev->low_power_auto_data.saved_vhv_timeout;\n+\n+\tpdev->gen_cfg.phasecal_config__override = 0x00;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_stop_range(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_LLDriverResults_t *pres = VL53LXDevStructGetLLResultsHandle(Dev);\n+\n+\tpdev->sys_ctrl.system__mode_start = (pdev->sys_ctrl.system__mode_start & VL53LX_DEVICEMEASUREMENTMODE_STOP_MASK) | VL53LX_DEVICEMEASUREMENTMODE_ABORT;\n+\n+\tstatus = VL53LX_set_system_control(Dev, &pdev->sys_ctrl);\n+\n+\tpdev->sys_ctrl.system__mode_start = (pdev->sys_ctrl.system__mode_start & VL53LX_DEVICEMEASUREMENTMODE_STOP_MASK);\n+\n+\tVL53LX_init_ll_driver_state(Dev, VL53LX_DEVICESTATE_SW_STANDBY);\n+\n+\tV53L1_init_zone_results_structure(pdev->zone_cfg.active_zones+1, &(pres->zone_results));\n+\n+\tV53L1_init_zone_dss_configs(Dev);\n+\n+\tif (pdev->low_power_auto_data.is_low_power_auto_mode == 1)\n+\t\tVL53LX_low_power_auto_data_stop_range(Dev);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_set_powerforce_register(VL53LX_DEV Dev, uint8_t value)\n+{\n+\tVL53LX_Error status       = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpdev->sys_ctrl.power_management__go1_power_force = value;\n+\n+\tstatus = VL53LX_WrByte(Dev, VL53LX_POWER_MANAGEMENT__GO1_POWER_FORCE, pdev->sys_ctrl.power_management__go1_power_force);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_disable_powerforce(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tstatus = VL53LX_set_powerforce_register(Dev, 0x00);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_unload_patch(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WrByte(Dev, VL53LX_FIRMWARE__ENABLE, 0x00);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tVL53LX_disable_powerforce(Dev);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WrByte(Dev, VL53LX_PATCH__CTRL, 0x00);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WrByte(Dev, VL53LX_FIRMWARE__ENABLE, 0x01);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_StopMeasurement(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\n+\tStatus = VL53LX_stop_range(Dev);\n+\n+\tVL53LX_unload_patch(Dev);\n+\n+\treturn Status;\n+}\n+\n+static void empty_and_free_list(struct list_head *head)\n+{\n+\tstruct stmvl53lx_waiters *waiter;\n+\tstruct stmvl53lx_waiters *tmp;\n+\n+\tlist_for_each_entry_safe(waiter, tmp, head, list) {\n+\t\tlist_del(&waiter->list);\n+\t\tkfree(waiter);\n+\t}\n+}\n+\n+static void wake_up_data_waiters(struct stmvl53lx_data *data)\n+{\n+\tempty_and_free_list(&data->simple_data_reader_list);\n+\tempty_and_free_list(&data->mz_data_reader_list);\n+\twake_up(&data->waiter_for_data);\n+}\n+\n+static int stmvl53lx_stop(struct stmvl53lx_data *data)\n+{\n+\tint rc = 0;\n+\n+\trc = VL53LX_StopMeasurement(&data->stdev);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"VL53LX_StopMeasurement @%d fail %d\", __LINE__, rc);\n+\t\trc = store_last_error(data, rc);\n+\t}\n+\n+\treset_hold(data);\n+\tdata->enable_sensor = 0;\n+\tif (data->poll_mode) {\n+\t\tcancel_delayed_work(&data->dwork);\n+\t}\n+\n+\twake_up_data_waiters(data);\n+\treturn rc;\n+}\n+\n+void VL53LX_i2c_encode_uint16_t(uint16_t ip_value, uint16_t count, uint8_t *pbuffer)\n+{\n+\tuint16_t i    = 0;\n+\tuint16_t VL53LX_p_003 = 0;\n+\n+\tVL53LX_p_003 = ip_value;\n+\n+\tfor (i = 0; i < count; i++) {\n+\t\tpbuffer[count-i-1] = (uint8_t)(VL53LX_p_003 & 0x00FF);\n+\t\tVL53LX_p_003 = VL53LX_p_003 >> 8;\n+\t}\n+}\n+\n+uint16_t VL53LX_i2c_decode_uint16_t(uint16_t count, uint8_t *pbuffer)\n+{\n+\tuint16_t   value = 0x00;\n+\n+\twhile (count-- > 0)\n+\t\tvalue = (value << 8) | (uint16_t)*pbuffer++;\n+\n+\treturn value;\n+}\n+\n+void VL53LX_i2c_encode_int16_t(int16_t ip_value, uint16_t count, uint8_t *pbuffer)\n+{\n+\tuint16_t i = 0;\n+\tint16_t VL53LX_p_003 = 0;\n+\n+\tVL53LX_p_003 = ip_value;\n+\n+\tfor (i = 0; i < count; i++) {\n+\t\tpbuffer[count-i-1] = (uint8_t)(VL53LX_p_003 & 0x00FF);\n+\t\tVL53LX_p_003 = VL53LX_p_003 >> 8;\n+\t}\n+}\n+\n+int16_t VL53LX_i2c_decode_int16_t(uint16_t count, uint8_t *pbuffer)\n+{\n+\tint16_t    value = 0x00;\n+\n+\tif (*pbuffer >= 0x80)\n+\t\tvalue = 0xFFFF;\n+\n+\twhile (count-- > 0)\n+\t\tvalue = (value << 8) | (int16_t)*pbuffer++;\n+\n+\treturn value;\n+}\n+\n+uint32_t VL53LX_i2c_decode_with_mask(uint16_t count, uint8_t *pbuffer, uint32_t bit_mask, uint32_t down_shift, uint32_t offset)\n+{\n+\tuint32_t   value = 0x00;\n+\n+\twhile (count-- > 0)\n+\t\tvalue = (value << 8) | (uint32_t)*pbuffer++;\n+\n+\tvalue =  value & bit_mask;\n+\tif (down_shift > 0)\n+\t\tvalue = value >> down_shift;\n+\n+\tvalue = value + offset;\n+\n+\treturn value;\n+}\n+\n+\n+void VL53LX_i2c_encode_int32_t(int32_t ip_value, uint16_t count, uint8_t *pbuffer)\n+{\n+\tuint16_t   i    = 0;\n+\tint32_t    VL53LX_p_003 = 0;\n+\n+\tVL53LX_p_003 =  ip_value;\n+\n+\tfor (i = 0; i < count; i++) {\n+\t\tpbuffer[count-i-1] = (uint8_t)(VL53LX_p_003 & 0x00FF);\n+\t\tVL53LX_p_003 = VL53LX_p_003 >> 8;\n+\t}\n+}\n+\n+int32_t VL53LX_i2c_decode_int32_t(uint16_t count, uint8_t *pbuffer)\n+{\n+\tint32_t    value = 0x00;\n+\n+\tif (*pbuffer >= 0x80)\n+\t\tvalue = 0xFFFFFFFF;\n+\n+\twhile (count-- > 0)\n+\t\tvalue = (value << 8) | (int32_t)*pbuffer++;\n+\n+\treturn value;\n+}\n+\n+VL53LX_Error VL53LX_i2c_encode_customer_nvm_managed(VL53LX_customer_nvm_managed_t *pdata, uint16_t buf_size, uint8_t *pbuffer)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (buf_size < VL53LX_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES)\n+\t\treturn VL53LX_ERROR_COMMS_BUFFER_TOO_SMALL;\n+\n+\t*(pbuffer +   0) = pdata->global_config__spad_enables_ref_0;\n+\t*(pbuffer +   1) = pdata->global_config__spad_enables_ref_1;\n+\t*(pbuffer +   2) = pdata->global_config__spad_enables_ref_2;\n+\t*(pbuffer +   3) = pdata->global_config__spad_enables_ref_3;\n+\t*(pbuffer +   4) = pdata->global_config__spad_enables_ref_4;\n+\t*(pbuffer +   5) = pdata->global_config__spad_enables_ref_5 & 0xF;\n+\t*(pbuffer +   6) = pdata->global_config__ref_en_start_select;\n+\t*(pbuffer +   7) = pdata->ref_spad_man__num_requested_ref_spads & 0x3F;\n+\t*(pbuffer +   8) = pdata->ref_spad_man__ref_location & 0x3;\n+\tVL53LX_i2c_encode_uint16_t(pdata->algo__crosstalk_compensation_plane_offset_kcps, 2, pbuffer + 9);\n+\tVL53LX_i2c_encode_int16_t(pdata->algo__crosstalk_compensation_x_plane_gradient_kcps, 2, pbuffer + 11);\n+\tVL53LX_i2c_encode_int16_t(pdata->algo__crosstalk_compensation_y_plane_gradient_kcps, 2, pbuffer + 13);\n+\tVL53LX_i2c_encode_uint16_t(pdata->ref_spad_char__total_rate_target_mcps, 2, pbuffer + 15);\n+\tVL53LX_i2c_encode_int16_t(pdata->algo__part_to_part_range_offset_mm & 0x1FFF, 2, pbuffer + 17);\n+\tVL53LX_i2c_encode_int16_t(pdata->mm_config__inner_offset_mm, 2, pbuffer + 19);\n+\tVL53LX_i2c_encode_int16_t(pdata->mm_config__outer_offset_mm, 2, pbuffer + 21);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_set_customer_nvm_managed(VL53LX_DEV Dev, VL53LX_customer_nvm_managed_t *pdata)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tuint8_t comms_buffer[VL53LX_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES];\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_i2c_encode_customer_nvm_managed(pdata, VL53LX_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES, comms_buffer);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WriteMulti(Dev, VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_0, comms_buffer, VL53LX_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_disable_xtalk_compensation(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_hist_post_process_config_t *pHP = &(pdev->histpostprocess);\n+\tVL53LX_customer_nvm_managed_t *pN = &(pdev->customer);\n+\n+\tpN->algo__crosstalk_compensation_plane_offset_kcps = 0x00;\n+\tpN->algo__crosstalk_compensation_x_plane_gradient_kcps = 0x00;\n+\tpN->algo__crosstalk_compensation_y_plane_gradient_kcps = 0x00;\n+\tpdev->xtalk_cfg.global_crosstalk_compensation_enable = 0x00;\n+\tpHP->algo__crosstalk_compensation_enable = pdev->xtalk_cfg.global_crosstalk_compensation_enable;\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tpdev->xtalk_cfg.crosstalk_range_ignore_threshold_rate_mcps = 0x0000;\n+\t}\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tstatus = VL53LX_set_customer_nvm_managed(Dev, &(pdev->customer));\n+\t}\n+\treturn status;\n+}\n+\n+uint32_t VL53LX_calc_crosstalk_plane_offset_with_margin(uint32_t plane_offset_kcps, int16_t margin_offset_kcps)\n+{\n+\tuint32_t plane_offset_with_margin = 0;\n+\tint32_t  plane_offset_kcps_temp   = 0;\n+\n+\tplane_offset_kcps_temp = (int32_t)plane_offset_kcps + (int32_t)margin_offset_kcps;\n+\n+\tif (plane_offset_kcps_temp < 0)\n+\t\tplane_offset_kcps_temp = 0;\n+\telse\n+\t\tif (plane_offset_kcps_temp > 0x3FFFF)\n+\t\t\tplane_offset_kcps_temp = 0x3FFFF;\n+\n+\tplane_offset_with_margin = (uint32_t) plane_offset_kcps_temp;\n+\n+\treturn plane_offset_with_margin;\n+}\n+\n+uint16_t VL53LX_calc_range_ignore_threshold(uint32_t central_rate, int16_t x_gradient, int16_t y_gradient, uint8_t rate_mult)\n+{\n+\tint32_t    range_ignore_thresh_int  = 0;\n+\tuint16_t   range_ignore_thresh_kcps = 0;\n+\tint32_t    central_rate_int         = 0;\n+\tint16_t    x_gradient_int           = 0;\n+\tint16_t    y_gradient_int           = 0;\n+\n+\tcentral_rate_int = ((int32_t)central_rate * (1 << 4)) / (1000);\n+\n+\tif (x_gradient < 0)\n+\t\tx_gradient_int = x_gradient * -1;\n+\n+\tif (y_gradient < 0)\n+\t\ty_gradient_int = y_gradient * -1;\n+\n+\n+\trange_ignore_thresh_int = (8 * x_gradient_int * 4) + (8 * y_gradient_int * 4);\n+\trange_ignore_thresh_int = range_ignore_thresh_int / 1000;\n+\trange_ignore_thresh_int = range_ignore_thresh_int + central_rate_int;\n+\trange_ignore_thresh_int = (int32_t)rate_mult * range_ignore_thresh_int;\n+\trange_ignore_thresh_int = (range_ignore_thresh_int + (1<<4)) / (1<<5);\n+\n+\tif (range_ignore_thresh_int > 0xFFFF)\n+\t\trange_ignore_thresh_kcps = 0xFFFF;\n+\telse\n+\t\trange_ignore_thresh_kcps = (uint16_t)range_ignore_thresh_int;\n+\n+\treturn range_ignore_thresh_kcps;\n+}\n+\n+VL53LX_Error VL53LX_enable_xtalk_compensation(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tuint32_t tempu32;\n+\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_xtalk_config_t *pC = &(pdev->xtalk_cfg);\n+\tVL53LX_hist_post_process_config_t *pHP = &(pdev->histpostprocess);\n+\tVL53LX_customer_nvm_managed_t *pN = &(pdev->customer);\n+\n+\ttempu32 = VL53LX_calc_crosstalk_plane_offset_with_margin(pC->algo__crosstalk_compensation_plane_offset_kcps, pC->lite_mode_crosstalk_margin_kcps);\n+\tif (tempu32 > 0xFFFF)\n+\t\ttempu32 = 0xFFFF;\n+\n+\tpN->algo__crosstalk_compensation_plane_offset_kcps = (uint16_t)tempu32;\n+\tpN->algo__crosstalk_compensation_x_plane_gradient_kcps = pC->algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\tpN->algo__crosstalk_compensation_y_plane_gradient_kcps = pC->algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\tpHP->algo__crosstalk_compensation_plane_offset_kcps = VL53LX_calc_crosstalk_plane_offset_with_margin(pC->algo__crosstalk_compensation_plane_offset_kcps, pC->histogram_mode_crosstalk_margin_kcps);\n+\tpHP->algo__crosstalk_compensation_x_plane_gradient_kcps = pC->algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\tpHP->algo__crosstalk_compensation_y_plane_gradient_kcps = pC->algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\tpC->global_crosstalk_compensation_enable = 0x01;\n+\tpHP->algo__crosstalk_compensation_enable = pC->global_crosstalk_compensation_enable;\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tpC->crosstalk_range_ignore_threshold_rate_mcps =\n+\t\tVL53LX_calc_range_ignore_threshold(pC->algo__crosstalk_compensation_plane_offset_kcps, pC->algo__crosstalk_compensation_x_plane_gradient_kcps, pC->algo__crosstalk_compensation_y_plane_gradient_kcps, pC->crosstalk_range_ignore_threshold_mult);\n+\t}\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_set_customer_nvm_managed(Dev, &(pdev->customer));\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_SetXTalkCompensationEnable(VL53LX_DEV Dev, uint8_t XTalkCompensationEnable)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\n+\tif (XTalkCompensationEnable == 0)\n+\t\tStatus = VL53LX_disable_xtalk_compensation(Dev);\n+\telse\n+\t\tStatus = VL53LX_enable_xtalk_compensation(Dev);\n+\n+\treturn Status;\n+}\n+\n+static VL53LX_Error ComputeDevicePresetMode(VL53LX_DistanceModes DistanceMode, VL53LX_DevicePresetModes *pDevicePresetMode)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\n+\tuint8_t DistIdx;\n+\tVL53LX_DevicePresetModes RangingModes[3] = { VL53LX_DEVICEPRESETMODE_HISTOGRAM_SHORT_RANGE, VL53LX_DEVICEPRESETMODE_HISTOGRAM_MEDIUM_RANGE, VL53LX_DEVICEPRESETMODE_HISTOGRAM_LONG_RANGE};\n+\n+\tswitch (DistanceMode) {\n+\tcase VL53LX_DISTANCEMODE_SHORT:\n+\t\tDistIdx = 0;\n+\t\tbreak;\n+\tcase VL53LX_DISTANCEMODE_MEDIUM:\n+\t\tDistIdx = 1;\n+\t\tbreak;\n+\tdefault:\n+\t\tDistIdx = 2;\n+\t}\n+\t*pDevicePresetMode = RangingModes[DistIdx];\n+\treturn Status;\n+}\n+\n+VL53LX_Error VL53LX_get_preset_mode_timing_cfg(VL53LX_DEV Dev, VL53LX_DevicePresetModes device_preset_mode, uint16_t *pdss_config__target_total_rate_mcps, uint32_t *pphasecal_config_timeout_us, uint32_t *pmm_config_timeout_us, uint32_t  *prange_config_timeout_us)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tswitch (device_preset_mode) {\n+\tcase VL53LX_DEVICEPRESETMODE_HISTOGRAM_LONG_RANGE:\n+\t\t*pdss_config__target_total_rate_mcps = pdev->tuning_parms.tp_dss_target_histo_mcps;\n+\t\t*pphasecal_config_timeout_us = pdev->tuning_parms.tp_phasecal_timeout_hist_long_us;\n+\t\t*pmm_config_timeout_us = pdev->tuning_parms.tp_mm_timeout_histo_us;\n+\t\t*prange_config_timeout_us = pdev->tuning_parms.tp_range_timeout_histo_us;\n+\t\tbreak;\n+\tcase VL53LX_DEVICEPRESETMODE_HISTOGRAM_MEDIUM_RANGE:\n+\t\t*pdss_config__target_total_rate_mcps = pdev->tuning_parms.tp_dss_target_histo_mcps;\n+\t\t*pphasecal_config_timeout_us = pdev->tuning_parms.tp_phasecal_timeout_hist_med_us;\n+\t\t*pmm_config_timeout_us = pdev->tuning_parms.tp_mm_timeout_histo_us;\n+\t\t*prange_config_timeout_us = pdev->tuning_parms.tp_range_timeout_histo_us;\n+\t\tbreak;\n+\tcase VL53LX_DEVICEPRESETMODE_HISTOGRAM_SHORT_RANGE:\n+\t\t*pdss_config__target_total_rate_mcps = pdev->tuning_parms.tp_dss_target_histo_mcps;\n+\t\t*pphasecal_config_timeout_us = pdev->tuning_parms.tp_phasecal_timeout_hist_short_us;\n+\t\t*pmm_config_timeout_us = pdev->tuning_parms.tp_mm_timeout_histo_us;\n+\t\t*prange_config_timeout_us = pdev->tuning_parms.tp_range_timeout_histo_us;\n+\t\tbreak;\n+\tdefault:\n+\t\tstatus = VL53LX_ERROR_INVALID_PARAMS;\n+\t\tbreak;\n+\t}\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_preset_mode_standard_ranging(\n+\tVL53LX_static_config_t    *pstatic,\n+\tVL53LX_histogram_config_t *phistogram,\n+\tVL53LX_general_config_t   *pgeneral,\n+\tVL53LX_timing_config_t    *ptiming,\n+\tVL53LX_dynamic_config_t   *pdynamic,\n+\tVL53LX_system_control_t   *psystem,\n+\tVL53LX_tuning_parm_storage_t *ptuning_parms,\n+\tVL53LX_zone_config_t      *pzone_cfg)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tpstatic->dss_config__target_total_rate_mcps = 0x0A00;\n+\tpstatic->debug__ctrl = 0x00;\n+\tpstatic->test_mode__ctrl = 0x00;\n+\tpstatic->clk_gating__ctrl = 0x00;\n+\tpstatic->nvm_bist__ctrl = 0x00;\n+\tpstatic->nvm_bist__num_nvm_words = 0x00;\n+\tpstatic->nvm_bist__start_address = 0x00;\n+\tpstatic->host_if__status = 0x00;\n+\tpstatic->pad_i2c_hv__config = 0x00;\n+\tpstatic->pad_i2c_hv__extsup_config = 0x00;\n+\tpstatic->gpio_hv_pad__ctrl = 0x00;\n+\tpstatic->gpio_hv_mux__ctrl = VL53LX_DEVICEINTERRUPTPOLARITY_ACTIVE_LOW | VL53LX_DEVICEGPIOMODE_OUTPUT_RANGE_AND_ERROR_INTERRUPTS;\n+\tpstatic->gpio__tio_hv_status = 0x02;\n+\tpstatic->gpio__fio_hv_status = 0x00;\n+\tpstatic->ana_config__spad_sel_pswidth = 0x02;\n+\tpstatic->ana_config__vcsel_pulse_width_offset = 0x08;\n+\tpstatic->ana_config__fast_osc__config_ctrl = 0x00;\n+\tpstatic->sigma_estimator__effective_pulse_width_ns = ptuning_parms->tp_lite_sigma_est_pulse_width_ns;\n+\tpstatic->sigma_estimator__effective_ambient_width_ns = ptuning_parms->tp_lite_sigma_est_amb_width_ns;\n+\tpstatic->sigma_estimator__sigma_ref_mm = ptuning_parms->tp_lite_sigma_ref_mm;\n+\tpstatic->algo__crosstalk_compensation_valid_height_mm = 0x01;\n+\tpstatic->spare_host_config__static_config_spare_0 = 0x00;\n+\tpstatic->spare_host_config__static_config_spare_1 = 0x00;\n+\tpstatic->algo__range_ignore_threshold_mcps = 0x0000;\n+\tpstatic->algo__range_ignore_valid_height_mm = 0xff;\n+\tpstatic->algo__range_min_clip = ptuning_parms->tp_lite_min_clip;\n+\tpstatic->algo__consistency_check__tolerance = ptuning_parms->tp_consistency_lite_phase_tolerance;\n+\tpstatic->spare_host_config__static_config_spare_2 = 0x00;\n+\tpstatic->sd_config__reset_stages_msb = 0x00;\n+\tpstatic->sd_config__reset_stages_lsb = 0x00;\n+\tpgeneral->gph_config__stream_count_update_value = 0x00;\n+\tpgeneral->global_config__stream_divider = 0x00;\n+\tpgeneral->system__interrupt_config_gpio = VL53LX_INTERRUPT_CONFIG_NEW_SAMPLE_READY;\n+\tpgeneral->cal_config__vcsel_start = 0x0B;\n+\tpgeneral->cal_config__repeat_rate = ptuning_parms->tp_cal_repeat_rate;\n+\tpgeneral->global_config__vcsel_width = 0x02;\n+\tpgeneral->phasecal_config__timeout_macrop = 0x0D;\n+\tpgeneral->phasecal_config__target = ptuning_parms->tp_phasecal_target;\n+\tpgeneral->phasecal_config__override = 0x00;\n+\tpgeneral->dss_config__roi_mode_control = VL53LX_DEVICEDSSMODE__TARGET_RATE;\n+\tpgeneral->system__thresh_rate_high = 0x0000;\n+\tpgeneral->system__thresh_rate_low = 0x0000;\n+\tpgeneral->dss_config__manual_effective_spads_select = 0x8C00;\n+\tpgeneral->dss_config__manual_block_select = 0x00;\n+\tpgeneral->dss_config__aperture_attenuation = 0x38;\n+\tpgeneral->dss_config__max_spads_limit = 0xFF;\n+\tpgeneral->dss_config__min_spads_limit = 0x01;\n+\tptiming->mm_config__timeout_macrop_a_hi = 0x00;\n+\tptiming->mm_config__timeout_macrop_a_lo = 0x1a;\n+\tptiming->mm_config__timeout_macrop_b_hi = 0x00;\n+\tptiming->mm_config__timeout_macrop_b_lo = 0x20;\n+\tptiming->range_config__timeout_macrop_a_hi = 0x01;\n+\tptiming->range_config__timeout_macrop_a_lo = 0xCC;\n+\tptiming->range_config__vcsel_period_a = 0x0B;\n+\tptiming->range_config__timeout_macrop_b_hi = 0x01;\n+\tptiming->range_config__timeout_macrop_b_lo = 0xF5;\n+\tptiming->range_config__vcsel_period_b = 0x09;\n+\tptiming->range_config__sigma_thresh = ptuning_parms->tp_lite_med_sigma_thresh_mm;\n+\tptiming->range_config__min_count_rate_rtn_limit_mcps = ptuning_parms->tp_lite_med_min_count_rate_rtn_mcps;\n+\tptiming->range_config__valid_phase_low = 0x08;\n+\tptiming->range_config__valid_phase_high = 0x78;\n+\tptiming->system__intermeasurement_period = 0x00000000;\n+\tptiming->system__fractional_enable = 0x00;\n+\tphistogram->histogram_config__low_amb_even_bin_0_1 = 0x07;\n+\tphistogram->histogram_config__low_amb_even_bin_2_3 = 0x21;\n+\tphistogram->histogram_config__low_amb_even_bin_4_5 = 0x43;\n+\tphistogram->histogram_config__low_amb_odd_bin_0_1 = 0x10;\n+\tphistogram->histogram_config__low_amb_odd_bin_2_3 = 0x32;\n+\tphistogram->histogram_config__low_amb_odd_bin_4_5 = 0x54;\n+\tphistogram->histogram_config__mid_amb_even_bin_0_1 = 0x07;\n+\tphistogram->histogram_config__mid_amb_even_bin_2_3 = 0x21;\n+\tphistogram->histogram_config__mid_amb_even_bin_4_5 = 0x43;\n+\tphistogram->histogram_config__mid_amb_odd_bin_0_1 = 0x10;\n+\tphistogram->histogram_config__mid_amb_odd_bin_2 = 0x02;\n+\tphistogram->histogram_config__mid_amb_odd_bin_3_4 = 0x43;\n+\tphistogram->histogram_config__mid_amb_odd_bin_5 = 0x05;\n+\tphistogram->histogram_config__user_bin_offset = 0x00;\n+\tphistogram->histogram_config__high_amb_even_bin_0_1 = 0x07;\n+\tphistogram->histogram_config__high_amb_even_bin_2_3 = 0x21;\n+\tphistogram->histogram_config__high_amb_even_bin_4_5 = 0x43;\n+\tphistogram->histogram_config__high_amb_odd_bin_0_1 = 0x10;\n+\tphistogram->histogram_config__high_amb_odd_bin_2_3 = 0x32;\n+\tphistogram->histogram_config__high_amb_odd_bin_4_5 = 0x54;\n+\tphistogram->histogram_config__amb_thresh_low = 0xFFFF;\n+\tphistogram->histogram_config__amb_thresh_high = 0xFFFF;\n+\tphistogram->histogram_config__spad_array_selection = 0x00;\n+\tpzone_cfg->max_zones                     = VL53LX_MAX_USER_ZONES;\n+\tpzone_cfg->active_zones = 0x00;\n+\tpzone_cfg->user_zones[0].height = 0x0f;\n+\tpzone_cfg->user_zones[0].width = 0x0f;\n+\tpzone_cfg->user_zones[0].x_centre = 0x08;\n+\tpzone_cfg->user_zones[0].y_centre = 0x08;\n+\tpdynamic->system__grouped_parameter_hold_0 = 0x01;\n+\tpdynamic->system__thresh_high = 0x0000;\n+\tpdynamic->system__thresh_low = 0x0000;\n+\tpdynamic->system__enable_xtalk_per_quadrant = 0x00;\n+\tpdynamic->system__seed_config = ptuning_parms->tp_lite_seed_cfg;\n+\tpdynamic->sd_config__woi_sd0 = 0x0B;\n+\tpdynamic->sd_config__woi_sd1 = 0x09;\n+\tpdynamic->sd_config__initial_phase_sd0 = ptuning_parms->tp_init_phase_rtn_lite_med;\n+\tpdynamic->sd_config__initial_phase_sd1 = ptuning_parms->tp_init_phase_ref_lite_med;\n+\tpdynamic->system__grouped_parameter_hold_1 = 0x01;\n+\tpdynamic->sd_config__first_order_select = ptuning_parms->tp_lite_first_order_select;\n+\tpdynamic->sd_config__quantifier = ptuning_parms->tp_lite_quantifier;\n+\tpdynamic->roi_config__user_roi_centre_spad = 0xC7;\n+\tpdynamic->roi_config__user_roi_requested_global_xy_size = 0xFF;\n+\tpdynamic->system__sequence_config = VL53LX_SEQUENCE_VHV_EN | VL53LX_SEQUENCE_PHASECAL_EN | VL53LX_SEQUENCE_DSS1_EN | VL53LX_SEQUENCE_DSS2_EN | VL53LX_SEQUENCE_MM2_EN | VL53LX_SEQUENCE_RANGE_EN;\n+\tpdynamic->system__grouped_parameter_hold = 0x02;\n+\tpsystem->system__stream_count_ctrl = 0x00;\n+\tpsystem->firmware__enable = 0x01;\n+\tpsystem->system__interrupt_clear = VL53LX_CLEAR_RANGE_INT;\n+\tpsystem->system__mode_start = VL53LX_DEVICESCHEDULERMODE_STREAMING | VL53LX_DEVICEREADOUTMODE_SINGLE_SD | VL53LX_DEVICEMEASUREMENTMODE_BACKTOBACK;\n+\n+\treturn status;\n+}\n+\n+void VL53LX_init_histogram_config_structure(\n+\tuint8_t   even_bin0,\n+\tuint8_t   even_bin1,\n+\tuint8_t   even_bin2,\n+\tuint8_t   even_bin3,\n+\tuint8_t   even_bin4,\n+\tuint8_t   even_bin5,\n+\tuint8_t   odd_bin0,\n+\tuint8_t   odd_bin1,\n+\tuint8_t   odd_bin2,\n+\tuint8_t   odd_bin3,\n+\tuint8_t   odd_bin4,\n+\tuint8_t   odd_bin5,\n+\tVL53LX_histogram_config_t  *pdata)\n+{\n+\tpdata->histogram_config__low_amb_even_bin_0_1 = (even_bin1 << 4) + even_bin0;\n+\tpdata->histogram_config__low_amb_even_bin_2_3 = (even_bin3 << 4) + even_bin2;\n+\tpdata->histogram_config__low_amb_even_bin_4_5 = (even_bin5 << 4) + even_bin4;\n+\tpdata->histogram_config__low_amb_odd_bin_0_1 = (odd_bin1 << 4) + odd_bin0;\n+\tpdata->histogram_config__low_amb_odd_bin_2_3 = (odd_bin3 << 4) + odd_bin2;\n+\tpdata->histogram_config__low_amb_odd_bin_4_5 = (odd_bin5 << 4) + odd_bin4;\n+\tpdata->histogram_config__mid_amb_even_bin_0_1 = pdata->histogram_config__low_amb_even_bin_0_1;\n+\tpdata->histogram_config__mid_amb_even_bin_2_3 = pdata->histogram_config__low_amb_even_bin_2_3;\n+\tpdata->histogram_config__mid_amb_even_bin_4_5 = pdata->histogram_config__low_amb_even_bin_4_5;\n+\tpdata->histogram_config__mid_amb_odd_bin_0_1 = pdata->histogram_config__low_amb_odd_bin_0_1;\n+\tpdata->histogram_config__mid_amb_odd_bin_2 = odd_bin2;\n+\tpdata->histogram_config__mid_amb_odd_bin_3_4 = (odd_bin4 << 4) + odd_bin3;\n+\tpdata->histogram_config__mid_amb_odd_bin_5 = odd_bin5;\n+\tpdata->histogram_config__user_bin_offset = 0x00;\n+\tpdata->histogram_config__high_amb_even_bin_0_1 = pdata->histogram_config__low_amb_even_bin_0_1;\n+\tpdata->histogram_config__high_amb_even_bin_2_3 = pdata->histogram_config__low_amb_even_bin_2_3;\n+\tpdata->histogram_config__high_amb_even_bin_4_5 = pdata->histogram_config__low_amb_even_bin_4_5;\n+\tpdata->histogram_config__high_amb_odd_bin_0_1 = pdata->histogram_config__low_amb_odd_bin_0_1;\n+\tpdata->histogram_config__high_amb_odd_bin_2_3 = pdata->histogram_config__low_amb_odd_bin_2_3;\n+\tpdata->histogram_config__high_amb_odd_bin_4_5 = pdata->histogram_config__low_amb_odd_bin_4_5;\n+\tpdata->histogram_config__amb_thresh_low = 0xFFFF;\n+\tpdata->histogram_config__amb_thresh_high = 0xFFFF;\n+\tpdata->histogram_config__spad_array_selection = 0x00;\n+}\n+\n+void VL53LX_init_histogram_multizone_config_structure(\n+\tuint8_t   even_bin0,\n+\tuint8_t   even_bin1,\n+\tuint8_t   even_bin2,\n+\tuint8_t   even_bin3,\n+\tuint8_t   even_bin4,\n+\tuint8_t   even_bin5,\n+\tuint8_t   odd_bin0,\n+\tuint8_t   odd_bin1,\n+\tuint8_t   odd_bin2,\n+\tuint8_t   odd_bin3,\n+\tuint8_t   odd_bin4,\n+\tuint8_t   odd_bin5,\n+\tVL53LX_histogram_config_t  *pdata)\n+{\n+\tpdata->histogram_config__low_amb_even_bin_0_1 = (even_bin1 << 4) + even_bin0;\n+\tpdata->histogram_config__low_amb_even_bin_2_3 = (even_bin3 << 4) + even_bin2;\n+\tpdata->histogram_config__low_amb_even_bin_4_5 = (even_bin5 << 4) + even_bin4;\n+\tpdata->histogram_config__low_amb_odd_bin_0_1 = pdata->histogram_config__low_amb_even_bin_0_1;\n+\tpdata->histogram_config__low_amb_odd_bin_2_3 = pdata->histogram_config__low_amb_even_bin_2_3;\n+\tpdata->histogram_config__low_amb_odd_bin_4_5 = pdata->histogram_config__low_amb_even_bin_4_5;\n+\tpdata->histogram_config__mid_amb_even_bin_0_1 = pdata->histogram_config__low_amb_even_bin_0_1;\n+\tpdata->histogram_config__mid_amb_even_bin_2_3 = pdata->histogram_config__low_amb_even_bin_2_3;\n+\tpdata->histogram_config__mid_amb_even_bin_4_5 = pdata->histogram_config__low_amb_even_bin_4_5;\n+\tpdata->histogram_config__mid_amb_odd_bin_0_1 = pdata->histogram_config__low_amb_odd_bin_0_1;\n+\tpdata->histogram_config__mid_amb_odd_bin_2 = odd_bin2;\n+\tpdata->histogram_config__mid_amb_odd_bin_3_4 = (odd_bin4 << 4) + odd_bin3;\n+\tpdata->histogram_config__mid_amb_odd_bin_5 = odd_bin5;\n+\tpdata->histogram_config__user_bin_offset = 0x00;\n+\tpdata->histogram_config__high_amb_even_bin_0_1 = (odd_bin1 << 4) + odd_bin0;\n+\tpdata->histogram_config__high_amb_even_bin_2_3 = (odd_bin3 << 4) + odd_bin2;\n+\tpdata->histogram_config__high_amb_even_bin_4_5 = (odd_bin5 << 4) + odd_bin4;\n+\tpdata->histogram_config__high_amb_odd_bin_0_1 = pdata->histogram_config__high_amb_even_bin_0_1;\n+\tpdata->histogram_config__high_amb_odd_bin_2_3 = pdata->histogram_config__high_amb_even_bin_2_3;\n+\tpdata->histogram_config__high_amb_odd_bin_4_5 = pdata->histogram_config__high_amb_even_bin_4_5;\n+\tpdata->histogram_config__amb_thresh_low = 0xFFFF;\n+\tpdata->histogram_config__amb_thresh_high = 0xFFFF;\n+\tpdata->histogram_config__spad_array_selection = 0x00;\n+}\n+\n+void VL53LX_copy_hist_cfg_to_static_cfg(\n+\tVL53LX_histogram_config_t *phistogram,\n+\tVL53LX_static_config_t    *pstatic,\n+\tVL53LX_general_config_t   *pgeneral,\n+\tVL53LX_timing_config_t    *ptiming,\n+\tVL53LX_dynamic_config_t   *pdynamic)\n+{\n+\tSUPPRESS_UNUSED_WARNING(pgeneral);\n+\n+\tpstatic->sigma_estimator__effective_pulse_width_ns = phistogram->histogram_config__high_amb_even_bin_0_1;\n+\tpstatic->sigma_estimator__effective_ambient_width_ns = phistogram->histogram_config__high_amb_even_bin_2_3;\n+\tpstatic->sigma_estimator__sigma_ref_mm = phistogram->histogram_config__high_amb_even_bin_4_5;\n+\tpstatic->algo__crosstalk_compensation_valid_height_mm = phistogram->histogram_config__high_amb_odd_bin_0_1;\n+\tpstatic->spare_host_config__static_config_spare_0 = phistogram->histogram_config__high_amb_odd_bin_2_3;\n+\tpstatic->spare_host_config__static_config_spare_1 = phistogram->histogram_config__high_amb_odd_bin_4_5;\n+\tpstatic->algo__range_ignore_threshold_mcps = (((uint16_t)phistogram->histogram_config__mid_amb_even_bin_0_1) << 8) + (uint16_t)phistogram->histogram_config__mid_amb_even_bin_2_3;\n+\tpstatic->algo__range_ignore_valid_height_mm = phistogram->histogram_config__mid_amb_even_bin_4_5;\n+\tpstatic->algo__range_min_clip = phistogram->histogram_config__mid_amb_odd_bin_0_1;\n+\tpstatic->algo__consistency_check__tolerance = phistogram->histogram_config__mid_amb_odd_bin_2;\n+\tpstatic->spare_host_config__static_config_spare_2 = phistogram->histogram_config__mid_amb_odd_bin_3_4;\n+\tpstatic->sd_config__reset_stages_msb = phistogram->histogram_config__mid_amb_odd_bin_5;\n+\tpstatic->sd_config__reset_stages_lsb = phistogram->histogram_config__user_bin_offset;\n+\tptiming->range_config__sigma_thresh = (((uint16_t)phistogram->histogram_config__low_amb_even_bin_0_1) << 8) + (uint16_t)phistogram->histogram_config__low_amb_even_bin_2_3;\n+\tptiming->range_config__min_count_rate_rtn_limit_mcps = (((uint16_t)phistogram->histogram_config__low_amb_even_bin_4_5) << 8) + (uint16_t)phistogram->histogram_config__low_amb_odd_bin_0_1;\n+\tptiming->range_config__valid_phase_low = phistogram->histogram_config__low_amb_odd_bin_2_3;\n+\tptiming->range_config__valid_phase_high = phistogram->histogram_config__low_amb_odd_bin_4_5;\n+\tpdynamic->system__thresh_high = phistogram->histogram_config__amb_thresh_low;\n+\tpdynamic->system__thresh_low = phistogram->histogram_config__amb_thresh_high;\n+\tpdynamic->system__enable_xtalk_per_quadrant = phistogram->histogram_config__spad_array_selection;\n+}\n+\n+VL53LX_Error VL53LX_preset_mode_histogram_ranging(\n+\tVL53LX_hist_post_process_config_t  *phistpostprocess,\n+\tVL53LX_static_config_t             *pstatic,\n+\tVL53LX_histogram_config_t          *phistogram,\n+\tVL53LX_general_config_t            *pgeneral,\n+\tVL53LX_timing_config_t             *ptiming,\n+\tVL53LX_dynamic_config_t            *pdynamic,\n+\tVL53LX_system_control_t            *psystem,\n+\tVL53LX_tuning_parm_storage_t       *ptuning_parms,\n+\tVL53LX_zone_config_t               *pzone_cfg)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tstatus = VL53LX_preset_mode_standard_ranging(pstatic, phistogram, pgeneral, ptiming, pdynamic, psystem, ptuning_parms, pzone_cfg);\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tpstatic->dss_config__target_total_rate_mcps = 0x1400;\n+\t\tVL53LX_init_histogram_config_structure(7, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 5, phistogram);\n+\t\tVL53LX_init_histogram_multizone_config_structure(7, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 5, &(pzone_cfg->multizone_hist_cfg));\n+\t\tptiming->range_config__vcsel_period_a = 0x09;\n+\t\tptiming->range_config__vcsel_period_b = 0x0B;\n+\t\tpdynamic->sd_config__woi_sd0 = 0x09;\n+\t\tpdynamic->sd_config__woi_sd1 = 0x0B;\n+\t\tptiming->mm_config__timeout_macrop_a_hi = 0x00;\n+\t\tptiming->mm_config__timeout_macrop_a_lo = 0x20;\n+\t\tptiming->mm_config__timeout_macrop_b_hi = 0x00;\n+\t\tptiming->mm_config__timeout_macrop_b_lo = 0x1A;\n+\t\tptiming->range_config__timeout_macrop_a_hi = 0x00;\n+\t\tptiming->range_config__timeout_macrop_a_lo = 0x28;\n+\t\tptiming->range_config__timeout_macrop_b_hi = 0x00;\n+\t\tptiming->range_config__timeout_macrop_b_lo = 0x21;\n+\t\tpgeneral->phasecal_config__timeout_macrop = 0xF5;\n+\t\tphistpostprocess->valid_phase_low = 0x08;\n+\t\tphistpostprocess->valid_phase_high = 0x88;\n+\t\tVL53LX_copy_hist_cfg_to_static_cfg(phistogram, pstatic, pgeneral, ptiming, pdynamic);\n+\t\tpdynamic->system__sequence_config = VL53LX_SEQUENCE_VHV_EN | VL53LX_SEQUENCE_PHASECAL_EN | VL53LX_SEQUENCE_DSS1_EN | VL53LX_SEQUENCE_DSS2_EN | VL53LX_SEQUENCE_RANGE_EN;\n+\t\tpsystem->system__mode_start = VL53LX_DEVICESCHEDULERMODE_HISTOGRAM | VL53LX_DEVICEREADOUTMODE_DUAL_SD | VL53LX_DEVICEMEASUREMENTMODE_BACKTOBACK;\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_preset_mode_histogram_long_range(\n+\tVL53LX_hist_post_process_config_t  *phistpostprocess,\n+\tVL53LX_static_config_t             *pstatic,\n+\tVL53LX_histogram_config_t          *phistogram,\n+\tVL53LX_general_config_t            *pgeneral,\n+\tVL53LX_timing_config_t             *ptiming,\n+\tVL53LX_dynamic_config_t            *pdynamic,\n+\tVL53LX_system_control_t            *psystem,\n+\tVL53LX_tuning_parm_storage_t       *ptuning_parms,\n+\tVL53LX_zone_config_t               *pzone_cfg)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tstatus = VL53LX_preset_mode_histogram_ranging(phistpostprocess, pstatic, phistogram, pgeneral, ptiming, pdynamic, psystem, ptuning_parms, pzone_cfg);\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tVL53LX_init_histogram_config_structure(7, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 5, phistogram);\n+\t\tVL53LX_init_histogram_multizone_config_structure(7, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 5, &(pzone_cfg->multizone_hist_cfg));\n+\t\tVL53LX_copy_hist_cfg_to_static_cfg(phistogram, pstatic, pgeneral, ptiming, pdynamic);\n+\t\tptiming->range_config__vcsel_period_a = 0x09;\n+\t\tptiming->range_config__vcsel_period_b = 0x0b;\n+\t\tptiming->mm_config__timeout_macrop_a_hi = 0x00;\n+\t\tptiming->mm_config__timeout_macrop_a_lo = 0x21;\n+\t\tptiming->mm_config__timeout_macrop_b_hi = 0x00;\n+\t\tptiming->mm_config__timeout_macrop_b_lo = 0x1b;\n+\t\tptiming->range_config__timeout_macrop_a_hi = 0x00;\n+\t\tptiming->range_config__timeout_macrop_a_lo = 0x29;\n+\t\tptiming->range_config__timeout_macrop_b_hi = 0x00;\n+\t\tptiming->range_config__timeout_macrop_b_lo = 0x22;\n+\t\tpgeneral->cal_config__vcsel_start = 0x09;\n+\t\tpgeneral->phasecal_config__timeout_macrop = 0xF5;\n+\t\tpdynamic->sd_config__woi_sd0 = 0x09;\n+\t\tpdynamic->sd_config__woi_sd1 = 0x0B;\n+\t\tpdynamic->sd_config__initial_phase_sd0 = ptuning_parms->tp_init_phase_rtn_hist_long;\n+\t\tpdynamic->sd_config__initial_phase_sd1 = ptuning_parms->tp_init_phase_ref_hist_long;\n+\t\tphistpostprocess->valid_phase_low = 0x08;\n+\t\tphistpostprocess->valid_phase_high = 0x88;\n+\t\tpdynamic->system__sequence_config = VL53LX_SEQUENCE_VHV_EN | VL53LX_SEQUENCE_PHASECAL_EN | VL53LX_SEQUENCE_DSS1_EN | VL53LX_SEQUENCE_DSS2_EN | VL53LX_SEQUENCE_RANGE_EN;\n+\t\tpsystem->system__mode_start = VL53LX_DEVICESCHEDULERMODE_HISTOGRAM | VL53LX_DEVICEREADOUTMODE_DUAL_SD | VL53LX_DEVICEMEASUREMENTMODE_BACKTOBACK;\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_set_inter_measurement_period_ms(VL53LX_DEV Dev, uint32_t inter_measurement_period_ms)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tif (pdev->dbg_results.result__osc_calibrate_val == 0)\n+\t\tstatus = VL53LX_ERROR_DIVISION_BY_ZERO;\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tpdev->inter_measurement_period_ms = inter_measurement_period_ms;\n+\t\tpdev->tim_cfg.system__intermeasurement_period = inter_measurement_period_ms * (uint32_t)pdev->dbg_results.result__osc_calibrate_val;\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_preset_mode_histogram_medium_range(\n+\tVL53LX_hist_post_process_config_t  *phistpostprocess,\n+\tVL53LX_static_config_t             *pstatic,\n+\tVL53LX_histogram_config_t          *phistogram,\n+\tVL53LX_general_config_t            *pgeneral,\n+\tVL53LX_timing_config_t             *ptiming,\n+\tVL53LX_dynamic_config_t            *pdynamic,\n+\tVL53LX_system_control_t            *psystem,\n+\tVL53LX_tuning_parm_storage_t       *ptuning_parms,\n+\tVL53LX_zone_config_t               *pzone_cfg)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tstatus = VL53LX_preset_mode_histogram_ranging(phistpostprocess, pstatic, phistogram, pgeneral, ptiming, pdynamic, psystem, ptuning_parms, pzone_cfg);\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tVL53LX_init_histogram_config_structure(7, 0, 1, 1, 2, 2, 0, 1, 2, 1, 2, 3, phistogram);\n+\t\tVL53LX_init_histogram_multizone_config_structure(7, 0, 1, 1, 2, 2, 0, 1, 2, 1, 2, 3, &(pzone_cfg->multizone_hist_cfg));\n+\t\tVL53LX_copy_hist_cfg_to_static_cfg(phistogram, pstatic, pgeneral, ptiming, pdynamic);\n+\n+\t\tptiming->range_config__vcsel_period_a = 0x05;\n+\t\tptiming->range_config__vcsel_period_b = 0x07;\n+\n+\t\tptiming->mm_config__timeout_macrop_a_hi = 0x00;\n+\t\tptiming->mm_config__timeout_macrop_a_lo = 0x36;\n+\t\tptiming->mm_config__timeout_macrop_b_hi = 0x00;\n+\t\tptiming->mm_config__timeout_macrop_b_lo = 0x28;\n+\n+\t\tptiming->range_config__timeout_macrop_a_hi = 0x00;\n+\t\tptiming->range_config__timeout_macrop_a_lo = 0x44;\n+\t\tptiming->range_config__timeout_macrop_b_hi = 0x00;\n+\t\tptiming->range_config__timeout_macrop_b_lo = 0x33;\n+\n+\t\tpgeneral->cal_config__vcsel_start = 0x05;\n+\n+\t\tpgeneral->phasecal_config__timeout_macrop = 0xF5;\n+\n+\t\tpdynamic->sd_config__woi_sd0 = 0x05;\n+\t\tpdynamic->sd_config__woi_sd1 = 0x07;\n+\t\tpdynamic->sd_config__initial_phase_sd0            = ptuning_parms->tp_init_phase_rtn_hist_med;\n+\t\tpdynamic->sd_config__initial_phase_sd1            = ptuning_parms->tp_init_phase_ref_hist_med;\n+\n+\t\tphistpostprocess->valid_phase_low = 0x08;\n+\t\tphistpostprocess->valid_phase_high = 0x48;\n+\n+\t\tpdynamic->system__sequence_config = VL53LX_SEQUENCE_VHV_EN | VL53LX_SEQUENCE_PHASECAL_EN | VL53LX_SEQUENCE_DSS1_EN | VL53LX_SEQUENCE_DSS2_EN | VL53LX_SEQUENCE_RANGE_EN;\n+\n+\t\tpsystem->system__mode_start = VL53LX_DEVICESCHEDULERMODE_HISTOGRAM | VL53LX_DEVICEREADOUTMODE_DUAL_SD | VL53LX_DEVICEMEASUREMENTMODE_BACKTOBACK;\n+\t}\n+\treturn status;\n+}\n+\n+\n+VL53LX_Error VL53LX_set_preset_mode(VL53LX_DEV Dev, VL53LX_DevicePresetModes device_preset_mode, uint16_t dss_config__target_total_rate_mcps, uint32_t phasecal_config_timeout_us, uint32_t mm_config_timeout_us, uint32_t range_config_timeout_us, uint32_t inter_measurement_period_ms)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_LLDriverResults_t *pres = VL53LXDevStructGetLLResultsHandle(Dev);\n+\n+\tVL53LX_hist_post_process_config_t *phistpostprocess = &(pdev->histpostprocess);\n+\n+\tVL53LX_static_config_t        *pstatic       = &(pdev->stat_cfg);\n+\tVL53LX_histogram_config_t     *phistogram    = &(pdev->hist_cfg);\n+\tVL53LX_general_config_t       *pgeneral      = &(pdev->gen_cfg);\n+\tVL53LX_timing_config_t        *ptiming       = &(pdev->tim_cfg);\n+\tVL53LX_dynamic_config_t       *pdynamic      = &(pdev->dyn_cfg);\n+\tVL53LX_system_control_t       *psystem       = &(pdev->sys_ctrl);\n+\tVL53LX_zone_config_t          *pzone_cfg     = &(pdev->zone_cfg);\n+\tVL53LX_tuning_parm_storage_t  *ptuning_parms = &(pdev->tuning_parms);\n+\n+\tpdev->preset_mode                 = device_preset_mode;\n+\tpdev->mm_config_timeout_us        = mm_config_timeout_us;\n+\tpdev->range_config_timeout_us     = range_config_timeout_us;\n+\tpdev->inter_measurement_period_ms = inter_measurement_period_ms;\n+\n+\tVL53LX_init_ll_driver_state(Dev, VL53LX_DEVICESTATE_SW_STANDBY);\n+\n+\tswitch (device_preset_mode) {\n+\tcase VL53LX_DEVICEPRESETMODE_HISTOGRAM_LONG_RANGE:\n+\t\tstatus = VL53LX_preset_mode_histogram_long_range(phistpostprocess, pstatic, phistogram, pgeneral, ptiming, pdynamic, psystem, ptuning_parms, pzone_cfg);\n+\t\tbreak;\n+\tcase VL53LX_DEVICEPRESETMODE_HISTOGRAM_MEDIUM_RANGE:\n+\t\tstatus = VL53LX_preset_mode_histogram_medium_range(phistpostprocess, pstatic, phistogram, pgeneral, ptiming, pdynamic, psystem, ptuning_parms, pzone_cfg);\n+\t\tbreak;\n+\tcase VL53LX_DEVICEPRESETMODE_HISTOGRAM_SHORT_RANGE:\n+\t\tstatus = VL53LX_preset_mode_histogram_short_range(phistpostprocess, pstatic, phistogram, pgeneral, ptiming, pdynamic, psystem, ptuning_parms, pzone_cfg);\n+\t\tbreak;\n+\tdefault:\n+\t\tstatus = VL53LX_ERROR_INVALID_PARAMS;\n+\t\tbreak;\n+\t}\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tpstatic->dss_config__target_total_rate_mcps = dss_config__target_total_rate_mcps;\n+\t\tpdev->dss_config__target_total_rate_mcps = dss_config__target_total_rate_mcps;\n+\t}\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_set_timeouts_us(Dev, phasecal_config_timeout_us, mm_config_timeout_us, range_config_timeout_us);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_set_inter_measurement_period_ms(Dev, inter_measurement_period_ms);\n+\n+\tV53L1_init_zone_results_structure(pdev->zone_cfg.active_zones+1, &(pres->zone_results));\n+\n+\treturn status;\n+}\n+\n+\n+static VL53LX_Error SetPresetModeL3CX(VL53LX_DEV Dev, VL53LX_DistanceModes DistanceMode, uint32_t inter_measurement_period_ms)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tVL53LX_DevicePresetModes   device_preset_mode;\n+\tuint8_t measurement_mode;\n+\tuint16_t dss_config__target_total_rate_mcps = 0;\n+\tuint32_t phasecal_config_timeout_us = 0;\n+\tuint32_t mm_config_timeout_us = 0;\n+\tuint32_t lld_range_config_timeout_us = 0;\n+\n+\tmeasurement_mode  = VL53LX_DEVICEMEASUREMENTMODE_BACKTOBACK;\n+\n+\tStatus = ComputeDevicePresetMode(DistanceMode, &device_preset_mode);\n+\n+\tif (Status == VL53LX_ERROR_NONE)\n+\t\tStatus =  VL53LX_get_preset_mode_timing_cfg(Dev, device_preset_mode, &dss_config__target_total_rate_mcps, &phasecal_config_timeout_us, &mm_config_timeout_us, &lld_range_config_timeout_us);\n+\n+\tif (Status == VL53LX_ERROR_NONE)\n+\t\tStatus = VL53LX_set_preset_mode(Dev, device_preset_mode, dss_config__target_total_rate_mcps, phasecal_config_timeout_us, mm_config_timeout_us, lld_range_config_timeout_us, inter_measurement_period_ms);\n+\n+\tif (Status == VL53LX_ERROR_NONE)\n+\t\tVL53LXDevDataSet(Dev, LLData.measurement_mode, measurement_mode);\n+\n+\treturn Status;\n+}\n+\n+VL53LX_Error VL53LX_SetDistanceMode(VL53LX_DEV Dev, VL53LX_DistanceModes DistanceMode)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tuint32_t inter_measurement_period_ms;\n+\tuint32_t TimingBudget = 0;\n+\tuint32_t MmTimeoutUs = 0;\n+\tuint32_t PhaseCalTimeoutUs = 0;\n+\n+\tif ((DistanceMode != VL53LX_DISTANCEMODE_SHORT) && (DistanceMode != VL53LX_DISTANCEMODE_MEDIUM) && (DistanceMode != VL53LX_DISTANCEMODE_LONG))\n+\t\treturn VL53LX_ERROR_INVALID_PARAMS;\n+\n+\tif (IsL4(Dev) && (DistanceMode == VL53LX_DISTANCEMODE_SHORT))\n+\t\treturn VL53LX_ERROR_INVALID_PARAMS;\n+\n+\tinter_measurement_period_ms = VL53LXDevDataGet(Dev, LLData.inter_measurement_period_ms);\n+\n+\tif (Status == VL53LX_ERROR_NONE)\n+\t\tStatus = VL53LX_get_timeouts_us(Dev, &PhaseCalTimeoutUs, &MmTimeoutUs, &TimingBudget);\n+\n+\tif (Status == VL53LX_ERROR_NONE)\n+\t\tStatus = SetPresetModeL3CX(Dev, DistanceMode, inter_measurement_period_ms);\n+\n+\tif (Status == VL53LX_ERROR_NONE) {\n+\t\tVL53LXDevDataSet(Dev, CurrentParameters.DistanceMode, DistanceMode);\n+\t}\n+\n+\tif (Status == VL53LX_ERROR_NONE) {\n+\t\tStatus = VL53LX_set_timeouts_us(Dev, PhaseCalTimeoutUs, MmTimeoutUs, TimingBudget);\n+\n+\t\tif (Status == VL53LX_ERROR_NONE)\n+\t\t\tVL53LXDevDataSet(Dev, LLData.range_config_timeout_us, TimingBudget);\n+\t}\n+\treturn Status;\n+}\n+\n+VL53LX_Error VL53LX_set_offset_correction_mode(VL53LX_DEV Dev, VL53LX_OffsetCorrectionMode offset_cor_mode)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpdev->offset_correction_mode = offset_cor_mode;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_SetOffsetCorrectionMode(VL53LX_DEV Dev, VL53LX_OffsetCorrectionModes OffsetCorrectionMode)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tVL53LX_OffsetCorrectionMode offset_cor_mode;\n+\n+\tif (OffsetCorrectionMode == VL53LX_OFFSETCORRECTIONMODE_PERVCSEL)\n+\t\toffset_cor_mode = VL53LX_OFFSETCORRECTIONMODE__PER_VCSEL_OFFSETS;\n+\telse {\n+\t\toffset_cor_mode = VL53LX_OFFSETCORRECTIONMODE__MM1_MM2_OFFSETS;\n+\t\tif (OffsetCorrectionMode != VL53LX_OFFSETCORRECTIONMODE_STANDARD)\n+\t\t\tStatus = VL53LX_ERROR_INVALID_PARAMS;\n+\t}\n+\n+\tif (Status == VL53LX_ERROR_NONE)\n+\t\tStatus = VL53LX_set_offset_correction_mode(Dev, offset_cor_mode);\n+\n+\treturn Status;\n+}\n+\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_disable(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpdev->smudge_correct_config.smudge_corr_enabled = 0;\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_apply_disable(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpdev->smudge_correct_config.smudge_corr_apply_enabled = 0;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_single_apply_disable(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpdev->smudge_correct_config.smudge_corr_single_apply = 0;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_enable(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpdev->smudge_correct_config.smudge_corr_enabled = 1;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_apply_enable(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpdev->smudge_correct_config.smudge_corr_apply_enabled = 1;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_single_apply_enable(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpdev->smudge_correct_config.smudge_corr_single_apply = 1;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_SmudgeCorrectionEnable(VL53LX_DEV Dev, VL53LX_SmudgeCorrectionModes Mode)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tVL53LX_Error s1 = VL53LX_ERROR_NONE;\n+\tVL53LX_Error s2 = VL53LX_ERROR_NONE;\n+\tVL53LX_Error s3 = VL53LX_ERROR_NONE;\n+\n+\tswitch (Mode) {\n+\tcase VL53LX_SMUDGE_CORRECTION_NONE:\n+\t\ts1 = VL53LX_dynamic_xtalk_correction_disable(Dev);\n+\t\ts2 = VL53LX_dynamic_xtalk_correction_apply_disable(Dev);\n+\t\ts3 = VL53LX_dynamic_xtalk_correction_single_apply_disable(Dev);\n+\t\tbreak;\n+\tcase VL53LX_SMUDGE_CORRECTION_CONTINUOUS:\n+\t\ts1 = VL53LX_dynamic_xtalk_correction_enable(Dev);\n+\t\ts2 = VL53LX_dynamic_xtalk_correction_apply_enable(Dev);\n+\t\ts3 = VL53LX_dynamic_xtalk_correction_single_apply_disable(Dev);\n+\t\tbreak;\n+\tcase VL53LX_SMUDGE_CORRECTION_SINGLE:\n+\t\ts1 = VL53LX_dynamic_xtalk_correction_enable(Dev);\n+\t\ts2 = VL53LX_dynamic_xtalk_correction_apply_enable(Dev);\n+\t\ts3 = VL53LX_dynamic_xtalk_correction_single_apply_enable(Dev);\n+\t\tbreak;\n+\tcase VL53LX_SMUDGE_CORRECTION_DEBUG:\n+\t\ts1 = VL53LX_dynamic_xtalk_correction_enable(Dev);\n+\t\ts2 = VL53LX_dynamic_xtalk_correction_apply_disable(Dev);\n+\t\ts3 = VL53LX_dynamic_xtalk_correction_single_apply_disable(Dev);\n+\t\tbreak;\n+\tdefault:\n+\t\tStatus = VL53LX_ERROR_INVALID_PARAMS;\n+\t\tbreak;\n+\t}\n+\n+\tif (Status == VL53LX_ERROR_NONE) {\n+\t\tStatus = s1;\n+\t\tif (Status == VL53LX_ERROR_NONE)\n+\t\t\tStatus = s2;\n+\t\tif (Status == VL53LX_ERROR_NONE)\n+\t\t\tStatus = s3;\n+\t}\n+\treturn Status;\n+}\n+\n+static VL53LX_Error CheckValidRectRoi(VL53LX_UserRoi_t ROI)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\n+\tif ((ROI.TopLeftX > 15) || (ROI.TopLeftY > 15) || (ROI.BotRightX > 15) || (ROI.BotRightY > 15))\n+\t\tStatus = VL53LX_ERROR_INVALID_PARAMS;\n+\tif ((ROI.TopLeftX > ROI.BotRightX) || (ROI.TopLeftY < ROI.BotRightY))\n+\t\tStatus = VL53LX_ERROR_INVALID_PARAMS;\n+\n+\treturn Status;\n+}\n+\n+VL53LX_Error VL53LX_init_zone_config_histogram_bins(VL53LX_zone_config_t *pdata)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tuint8_t i;\n+\n+\tfor (i = 0; i < pdata->max_zones; i++)\n+\t\tpdata->bin_config[i] = VL53LX_ZONECONFIG_BINCONFIG__LOWAMB;\n+\n+\treturn status;\n+}\n+\n+\n+VL53LX_Error VL53LX_set_zone_config(VL53LX_DEV Dev, VL53LX_zone_config_t *pzone_cfg)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tmemcpy(&(pdev->zone_cfg.user_zones), &(pzone_cfg->user_zones), sizeof(pdev->zone_cfg.user_zones));\n+\n+\tpdev->zone_cfg.max_zones    = pzone_cfg->max_zones;\n+\tpdev->zone_cfg.active_zones = pzone_cfg->active_zones;\n+\n+\tstatus = VL53LX_init_zone_config_histogram_bins(&pdev->zone_cfg);\n+\n+\tif (pzone_cfg->active_zones == 0)\n+\t\tpdev->gen_cfg.global_config__stream_divider = 0;\n+\telse if (pzone_cfg->active_zones < VL53LX_MAX_USER_ZONES)\n+\t\tpdev->gen_cfg.global_config__stream_divider = pzone_cfg->active_zones + 1;\n+\telse\n+\t\tpdev->gen_cfg.global_config__stream_divider = VL53LX_MAX_USER_ZONES + 1;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_SetUserROI(VL53LX_DEV Dev, VL53LX_UserRoi_t *pRoi)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tVL53LX_zone_config_t  zone_cfg;\n+\tuint8_t x_centre, y_centre, width, height;\n+\n+\tStatus = CheckValidRectRoi(*pRoi);\n+\tif (Status != VL53LX_ERROR_NONE)\n+\t\treturn VL53LX_ERROR_INVALID_PARAMS;\n+\n+\tx_centre = (pRoi->BotRightX + pRoi->TopLeftX  + 1) / 2;\n+\ty_centre = (pRoi->TopLeftY  + pRoi->BotRightY + 1) / 2;\n+\twidth =    (pRoi->BotRightX - pRoi->TopLeftX);\n+\theight =   (pRoi->TopLeftY  - pRoi->BotRightY);\n+\tzone_cfg.max_zones = 1;\n+\tzone_cfg.active_zones = 0;\n+\tzone_cfg.user_zones[0].x_centre = x_centre;\n+\tzone_cfg.user_zones[0].y_centre = y_centre;\n+\tzone_cfg.user_zones[0].width = width;\n+\tzone_cfg.user_zones[0].height = height;\n+\tif ((width < 3) || (height < 3))\n+\t\tStatus = VL53LX_ERROR_INVALID_PARAMS;\n+\telse\n+\t\tStatus =  VL53LX_set_zone_config(Dev, &zone_cfg);\n+\n+\treturn Status;\n+}\n+\n+static int stmvl53lx_sendparams(struct stmvl53lx_data *data)\n+{\n+\tint rc = 0;\n+\n+\trc = VL53LX_SetXTalkCompensationEnable(&data->stdev, data->crosstalk_enable);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"VL53LX_SetXTalkCompensationEnable %d fail %d\", data->crosstalk_enable, rc);\n+\t\trc = store_last_error(data, rc);\n+\t\tgoto done;\n+\t}\n+\tvl53lx_dbgmsg(\"Xtalk enable @%d\\n\", data->crosstalk_enable);\n+\n+\trc = VL53LX_SetDistanceMode(&data->stdev, data->distance_mode);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"VL53LX_SetDistanceMode %d fail %d\", data->distance_mode, rc);\n+\t\trc = store_last_error(data, rc);\n+\t\tgoto done;\n+\t}\n+\tvl53lx_dbgmsg(\"distance mode @%d\\n\", data->distance_mode);\n+\n+\trc = VL53LX_SetMeasurementTimingBudgetMicroSeconds(&data->stdev, data->timing_budget);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"SetTimingBudget %d fail %d\", data->timing_budget, rc);\n+\t\trc = store_last_error(data, rc);\n+\t\tgoto done;\n+\t}\n+\tvl53lx_dbgmsg(\"timing budget @%d\\n\", data->timing_budget);\n+\n+\trc = VL53LX_SetOffsetCorrectionMode(&data->stdev, data->offset_correction_mode);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"offset correction mode %d fail %d\", data->offset_correction_mode, rc);\n+\t\trc = store_last_error(data, rc);\n+\t\tgoto done;\n+\t}\n+\tvl53lx_dbgmsg(\"offset correction mode @%d\\n\", data->offset_correction_mode);\n+\n+\trc =  VL53LX_SmudgeCorrectionEnable(&data->stdev, data->smudge_correction_mode);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"smudge correction mode %d fail %d\", data->smudge_correction_mode, rc);\n+\t\trc = store_last_error(data, rc);\n+\t\tgoto done;\n+\t}\n+\tvl53lx_dbgmsg(\"smudge correction mode @%d\\n\", data->smudge_correction_mode);\n+\n+\trc = VL53LX_SetUserROI(&data->stdev, &data->roi_cfg);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"VL53LX_SetUserROI fail %d\\n\", rc);\n+\t\trc = store_last_error(data, rc);\n+\t\tgoto done;\n+\t}\n+\tvl53lx_dbgmsg(\"ROI set TopLeft(%d %d) BottomRight(%d %d)\\n\", data->roi_cfg.TopLeftX, data->roi_cfg.TopLeftY, data->roi_cfg.BotRightX, data->roi_cfg.BotRightY);\n+\n+done:\n+\treturn rc;\n+}\n+\n+static void kill_mz_data(VL53LX_MultiRangingData_t *pdata)\n+{\n+\tint i;\n+\n+\tmemset(pdata, 0, sizeof(*pdata));\n+\tfor (i = 0; i < VL53LX_MAX_RANGE_RESULTS; i++)\n+\t\tpdata->RangeData[i].RangeStatus = VL53LX_RANGESTATUS_NONE;\n+}\n+\n+VL53LX_Error VL53LX_enable_powerforce(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tstatus = VL53LX_set_powerforce_register(Dev, 0x01);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_get_tuning_parm(VL53LX_DEV Dev, VL53LX_TuningParms tuning_parm_key, int32_t *ptuning_parm_value)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_hist_post_process_config_t *pHP = &(pdev->histpostprocess);\n+\tVL53LX_xtalkextract_config_t *pXC = &(pdev->xtalk_extract_cfg);\n+\n+\tswitch (tuning_parm_key) {\n+\tcase VL53LX_TUNINGPARM_VERSION:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_tuning_parm_version;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_KEY_TABLE_VERSION:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_tuning_parm_key_table_version;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LLD_VERSION:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_tuning_parm_lld_version;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_ALGO_SELECT:\n+\t\t*ptuning_parm_value = (int32_t)pHP->hist_algo_select;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_TARGET_ORDER:\n+\t\t*ptuning_parm_value = (int32_t)pHP->hist_target_order;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_FILTER_WOI_0:\n+\t\t*ptuning_parm_value = (int32_t)pHP->filter_woi0;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_FILTER_WOI_1:\n+\t\t*ptuning_parm_value = (int32_t)pHP->filter_woi1;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_AMB_EST_METHOD:\n+\t\t*ptuning_parm_value = (int32_t)pHP->hist_amb_est_method;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_0:\n+\t\t*ptuning_parm_value = (int32_t)pHP->ambient_thresh_sigma0;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_1:\n+\t\t*ptuning_parm_value = (int32_t)pHP->ambient_thresh_sigma1;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_MIN_AMB_THRESH_EVENTS:\n+\t\t*ptuning_parm_value = (int32_t)pHP->min_ambient_thresh_events;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_AMB_EVENTS_SCALER:\n+\t\t*ptuning_parm_value = (int32_t)pHP->ambient_thresh_events_scaler;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_NOISE_THRESHOLD:\n+\t\t*ptuning_parm_value = (int32_t)pHP->noise_threshold;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_SIGNAL_TOTAL_EVENTS_LIMIT:\n+\t\t*ptuning_parm_value = (int32_t)pHP->signal_total_events_limit;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_SIGMA_EST_REF_MM:\n+\t\t*ptuning_parm_value = (int32_t)pHP->sigma_estimator__sigma_ref_mm;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_SIGMA_THRESH_MM:\n+\t\t*ptuning_parm_value = (int32_t)pHP->sigma_thresh;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_GAIN_FACTOR:\n+\t\t*ptuning_parm_value = (int32_t)pdev->gain_cal.histogram_ranging_gain_factor;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_CONSISTENCY_HIST_PHASE_TOLERANCE:\n+\t\t*ptuning_parm_value = (int32_t)pHP->algo__consistency_check__phase_tolerance;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_CONSISTENCY_HIST_MIN_MAX_TOLERANCE_MM:\n+\t\t*ptuning_parm_value = (int32_t)pHP->algo__consistency_check__min_max_tolerance;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA:\n+\t\t*ptuning_parm_value = (int32_t)pHP->algo__consistency_check__event_sigma;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA_MIN_SPAD_LIMIT:\n+\t\t*ptuning_parm_value = (int32_t)pHP->algo__consistency_check__event_min_spad_count;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_LONG_RANGE:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_init_phase_rtn_hist_long;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_MED_RANGE:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_init_phase_rtn_hist_med;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_SHORT_RANGE:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_init_phase_rtn_hist_short;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_LONG_RANGE:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_init_phase_ref_hist_long;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_MED_RANGE:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_init_phase_ref_hist_med;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_SHORT_RANGE:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_init_phase_ref_hist_short;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_DETECT_MIN_VALID_RANGE_MM:\n+\t\t*ptuning_parm_value = (int32_t)(pdev->xtalk_cfg.algo__crosstalk_detect_min_valid_range_mm);\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RANGE_MM:\n+\t\t*ptuning_parm_value = (int32_t)(pdev->xtalk_cfg.algo__crosstalk_detect_max_valid_range_mm);\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_DETECT_MAX_SIGMA_MM:\n+\t\t*ptuning_parm_value = (int32_t)pdev->xtalk_cfg.algo__crosstalk_detect_max_sigma_mm;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_DETECT_MIN_MAX_TOLERANCE:\n+\t\t*ptuning_parm_value = (int32_t)pHP->algo__crosstalk_detect_min_max_tolerance;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RATE_KCPS:\n+\t\t*ptuning_parm_value = (int32_t)(pdev->xtalk_cfg.algo__crosstalk_detect_max_valid_rate_kcps);\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_DETECT_EVENT_SIGMA:\n+\t\t*ptuning_parm_value = (int32_t)pHP->algo__crosstalk_detect_event_sigma;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_XTALK_MARGIN_KCPS:\n+\t\t*ptuning_parm_value = (int32_t)pdev->xtalk_cfg.histogram_mode_crosstalk_margin_kcps;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_CONSISTENCY_LITE_PHASE_TOLERANCE:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_consistency_lite_phase_tolerance;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_PHASECAL_TARGET:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_phasecal_target;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_CAL_REPEAT_RATE:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_cal_repeat_rate;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_RANGING_GAIN_FACTOR:\n+\t\t*ptuning_parm_value = (int32_t)pdev->gain_cal.standard_ranging_gain_factor;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_MIN_CLIP_MM:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_lite_min_clip;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_LONG_SIGMA_THRESH_MM:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_lite_long_sigma_thresh_mm;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_MED_SIGMA_THRESH_MM:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_lite_med_sigma_thresh_mm;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_SHORT_SIGMA_THRESH_MM:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_lite_short_sigma_thresh_mm;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_LONG_MIN_COUNT_RATE_RTN_MCPS:\n+\t\t*ptuning_parm_value = (int32_t)(pdev->tuning_parms.tp_lite_long_min_count_rate_rtn_mcps);\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_MED_MIN_COUNT_RATE_RTN_MCPS:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_lite_med_min_count_rate_rtn_mcps;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_SHORT_MIN_COUNT_RATE_RTN_MCPS:\n+\t\t*ptuning_parm_value = (int32_t)(pdev->tuning_parms.tp_lite_short_min_count_rate_rtn_mcps);\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_SIGMA_EST_PULSE_WIDTH:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_lite_sigma_est_pulse_width_ns;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_SIGMA_EST_AMB_WIDTH_NS:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_lite_sigma_est_amb_width_ns;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_SIGMA_REF_MM:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_lite_sigma_ref_mm;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_RIT_MULT:\n+\t\t*ptuning_parm_value = (int32_t)pdev->xtalk_cfg.crosstalk_range_ignore_threshold_mult;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_SEED_CONFIG:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_lite_seed_cfg;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_QUANTIFIER:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_lite_quantifier;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_FIRST_ORDER_SELECT:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_lite_first_order_select;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_XTALK_MARGIN_KCPS:\n+\t\t*ptuning_parm_value = (int32_t)pdev->xtalk_cfg.lite_mode_crosstalk_margin_kcps;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_LONG_RANGE:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_init_phase_rtn_lite_long;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_MED_RANGE:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_init_phase_rtn_lite_med;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_SHORT_RANGE:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_init_phase_rtn_lite_short;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_LONG_RANGE:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_init_phase_ref_lite_long;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_MED_RANGE:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_init_phase_ref_lite_med;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_SHORT_RANGE:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_init_phase_ref_lite_short;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_TIMED_SEED_CONFIG:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_timed_seed_cfg;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DMAX_CFG_SIGNAL_THRESH_SIGMA:\n+\t\t*ptuning_parm_value = (int32_t)pdev->dmax_cfg.signal_thresh_sigma;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_0:\n+\t\t*ptuning_parm_value = (int32_t)pdev->dmax_cfg.target_reflectance_for_dmax_calc[0];\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_1:\n+\t\t*ptuning_parm_value = (int32_t)pdev->dmax_cfg.target_reflectance_for_dmax_calc[1];\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_2:\n+\t\t*ptuning_parm_value = (int32_t)pdev->dmax_cfg.target_reflectance_for_dmax_calc[2];\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_3:\n+\t\t*ptuning_parm_value = (int32_t)pdev->dmax_cfg.target_reflectance_for_dmax_calc[3];\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_4:\n+\t\t*ptuning_parm_value = (int32_t)pdev->dmax_cfg.target_reflectance_for_dmax_calc[4];\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_VHV_LOOPBOUND:\n+\t\t*ptuning_parm_value = (int32_t)pdev->stat_nvm.vhv_config__timeout_macrop_loop_bound;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_REFSPADCHAR_DEVICE_TEST_MODE:\n+\t\t*ptuning_parm_value = (int32_t)pdev->refspadchar.device_test_mode;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_REFSPADCHAR_VCSEL_PERIOD:\n+\t\t*ptuning_parm_value = (int32_t)pdev->refspadchar.VL53LX_p_005;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_REFSPADCHAR_PHASECAL_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->refspadchar.timeout_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_REFSPADCHAR_TARGET_COUNT_RATE_MCPS:\n+\t\t*ptuning_parm_value = (int32_t)pdev->refspadchar.target_count_rate_mcps;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_REFSPADCHAR_MIN_COUNTRATE_LIMIT_MCPS:\n+\t\t*ptuning_parm_value = (int32_t)pdev->refspadchar.min_count_rate_limit_mcps;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_REFSPADCHAR_MAX_COUNTRATE_LIMIT_MCPS:\n+\t\t*ptuning_parm_value = (int32_t)pdev->refspadchar.max_count_rate_limit_mcps;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_NUM_OF_SAMPLES:\n+\t\t*ptuning_parm_value = (int32_t)pXC->num_of_samples;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_MIN_FILTER_THRESH_MM:\n+\t\t*ptuning_parm_value = (int32_t)pXC->algo__crosstalk_extract_min_valid_range_mm;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_FILTER_THRESH_MM:\n+\t\t*ptuning_parm_value = (int32_t)pXC->algo__crosstalk_extract_max_valid_range_mm;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_RATE_MCPS:\n+\t\t*ptuning_parm_value = (int32_t)pXC->dss_config__target_total_rate_mcps;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_PHASECAL_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pXC->phasecal_config_timeout_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_VALID_RATE_KCPS:\n+\t\t*ptuning_parm_value = (int32_t)pXC->algo__crosstalk_extract_max_valid_rate_kcps;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_SIGMA_THRESHOLD_MM:\n+\t\t*ptuning_parm_value = (int32_t)pXC->algo__crosstalk_extract_max_sigma_mm;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pXC->mm_config_timeout_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_BIN_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pXC->range_config_timeout_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_OFFSET_CAL_DSS_RATE_MCPS:\n+\t\t*ptuning_parm_value = (int32_t)pdev->offsetcal_cfg.dss_config__target_total_rate_mcps;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_OFFSET_CAL_PHASECAL_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->offsetcal_cfg.phasecal_config_timeout_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_OFFSET_CAL_MM_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->offsetcal_cfg.mm_config_timeout_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_OFFSET_CAL_RANGE_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->offsetcal_cfg.range_config_timeout_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_OFFSET_CAL_PRE_SAMPLES:\n+\t\t*ptuning_parm_value = (int32_t)pdev->offsetcal_cfg.pre_num_of_samples;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_OFFSET_CAL_MM1_SAMPLES:\n+\t\t*ptuning_parm_value = (int32_t)pdev->offsetcal_cfg.mm1_num_of_samples;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_OFFSET_CAL_MM2_SAMPLES:\n+\t\t*ptuning_parm_value = (int32_t)pdev->offsetcal_cfg.mm2_num_of_samples;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_ZONE_CAL_DSS_RATE_MCPS:\n+\t\t*ptuning_parm_value = (int32_t)pdev->zonecal_cfg.dss_config__target_total_rate_mcps;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->zonecal_cfg.phasecal_config_timeout_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_ZONE_CAL_DSS_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->zonecal_cfg.mm_config_timeout_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_NUM_SAMPLES:\n+\t\t*ptuning_parm_value = (int32_t)pdev->zonecal_cfg.phasecal_num_of_samples;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_ZONE_CAL_RANGE_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->zonecal_cfg.range_config_timeout_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_ZONE_CAL_ZONE_NUM_SAMPLES:\n+\t\t*ptuning_parm_value = (int32_t)pdev->zonecal_cfg.zone_num_of_samples;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_SPADMAP_VCSEL_PERIOD:\n+\t\t*ptuning_parm_value = (int32_t)pdev->ssc_cfg.VL53LX_p_005;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_SPADMAP_VCSEL_START:\n+\t\t*ptuning_parm_value = (int32_t)pdev->ssc_cfg.vcsel_start;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_SPADMAP_RATE_LIMIT_MCPS:\n+\t\t*ptuning_parm_value = (int32_t)pdev->ssc_cfg.rate_limit_mcps;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_dss_target_lite_mcps;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_RANGING_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_dss_target_histo_mcps;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_MZ_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_dss_target_histo_mz_mcps;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_TIMED_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_dss_target_timed_mcps;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_PHASECAL_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_phasecal_timeout_lite_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_RANGING_LONG_PHASECAL_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_phasecal_timeout_hist_long_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_RANGING_MED_PHASECAL_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_phasecal_timeout_hist_med_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_RANGING_SHORT_PHASECAL_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_phasecal_timeout_hist_short_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_MZ_LONG_PHASECAL_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_phasecal_timeout_mz_long_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_MZ_MED_PHASECAL_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_phasecal_timeout_mz_med_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_MZ_SHORT_PHASECAL_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_phasecal_timeout_mz_short_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_TIMED_PHASECAL_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_phasecal_timeout_timed_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_MM_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_mm_timeout_lite_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_RANGING_MM_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_mm_timeout_histo_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_MZ_MM_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_mm_timeout_mz_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_TIMED_MM_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_mm_timeout_timed_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_RANGE_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_range_timeout_lite_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_RANGING_RANGE_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_range_timeout_histo_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_MZ_RANGE_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_range_timeout_mz_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_TIMED_RANGE_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_range_timeout_timed_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_MARGIN:\n+\t\t*ptuning_parm_value = (int32_t)pdev->smudge_correct_config.smudge_margin;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_NOISE_MARGIN:\n+\t\t*ptuning_parm_value = (int32_t)pdev->smudge_correct_config.noise_margin;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT:\n+\t\t*ptuning_parm_value = (int32_t)pdev->smudge_correct_config.user_xtalk_offset_limit;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT_HI:\n+\t\t*ptuning_parm_value = (int32_t)pdev->smudge_correct_config.user_xtalk_offset_limit_hi;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_SAMPLE_LIMIT:\n+\t\t*ptuning_parm_value = (int32_t)pdev->smudge_correct_config.sample_limit;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_SINGLE_XTALK_DELTA:\n+\t\t*ptuning_parm_value = (int32_t)pdev->smudge_correct_config.single_xtalk_delta;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_AVERAGED_XTALK_DELTA:\n+\t\t*ptuning_parm_value = (int32_t)pdev->smudge_correct_config.averaged_xtalk_delta;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_CLIP_LIMIT:\n+\t\t*ptuning_parm_value = (int32_t)pdev->smudge_correct_config.smudge_corr_clip_limit;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_SCALER_CALC_METHOD:\n+\t\t*ptuning_parm_value = (int32_t)pdev->smudge_correct_config.scaler_calc_method;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_XGRADIENT_SCALER:\n+\t\t*ptuning_parm_value = (int32_t)pdev->smudge_correct_config.x_gradient_scaler;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_YGRADIENT_SCALER:\n+\t\t*ptuning_parm_value = (int32_t)pdev->smudge_correct_config.y_gradient_scaler;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_USER_SCALER_SET:\n+\t\t*ptuning_parm_value = (int32_t)pdev->smudge_correct_config.user_scaler_set;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_COR_SINGLE_APPLY:\n+\t\t*ptuning_parm_value = (int32_t)pdev->smudge_correct_config.smudge_corr_single_apply;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_XTALK_AMB_THRESHOLD:\n+\t\t*ptuning_parm_value = (int32_t)(pdev->smudge_correct_config.smudge_corr_ambient_threshold);\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_NODETECT_AMB_THRESHOLD_KCPS:\n+\t\t*ptuning_parm_value = (int32_t)pdev->smudge_correct_config.nodetect_ambient_threshold;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_NODETECT_SAMPLE_LIMIT:\n+\t\t*ptuning_parm_value = (int32_t)pdev->smudge_correct_config.nodetect_sample_limit;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_NODETECT_XTALK_OFFSET_KCPS:\n+\t\t*ptuning_parm_value = (int32_t)pdev->smudge_correct_config.nodetect_xtalk_offset;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_NODETECT_MIN_RANGE_MM:\n+\t\t*ptuning_parm_value = (int32_t)pdev->smudge_correct_config.nodetect_min_range_mm;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LOWPOWERAUTO_VHV_LOOP_BOUND:\n+\t\t*ptuning_parm_value = (int32_t)pdev->low_power_auto_data.vhv_loop_bound;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LOWPOWERAUTO_MM_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_mm_timeout_lpa_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LOWPOWERAUTO_RANGE_CONFIG_TIMEOUT_US:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_range_timeout_lpa_us;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_VERY_SHORT_DSS_RATE_MCPS:\n+\t\t*ptuning_parm_value = (int32_t)pdev->tuning_parms.tp_dss_target_very_short_mcps;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_PHASECAL_PATCH_POWER:\n+\t\t*ptuning_parm_value = (int32_t) pdev->tuning_parms.tp_phasecal_patch_power;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_MERGE:\n+\t\t*ptuning_parm_value = (int32_t) pdev->tuning_parms.tp_hist_merge;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_RESET_MERGE_THRESHOLD:\n+\t\t*ptuning_parm_value = (int32_t) pdev->tuning_parms.tp_reset_merge_threshold;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_MERGE_MAX_SIZE:\n+\t\t*ptuning_parm_value = (int32_t) pdev->tuning_parms.tp_hist_merge_max_size;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_MAX_SMUDGE_FACTOR:\n+\t\t*ptuning_parm_value = pdev->smudge_correct_config.max_smudge_factor;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_ENABLE:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_enable;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_1_MIN:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_z_1_min;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_1_MAX:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_z_1_max;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_2_MIN:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_z_2_min;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_2_MAX:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_z_2_max;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_3_MIN:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_z_3_min;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_3_MAX:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_z_3_max;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_4_MIN:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_z_4_min;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_4_MAX:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_z_4_max;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_5_MIN:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_z_5_min;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_5_MAX:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_z_5_max;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_1_RANGEA:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_corr_z_1_rangea;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_1_RANGEB:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_corr_z_1_rangeb;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_2_RANGEA:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_corr_z_2_rangea;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_2_RANGEB:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_corr_z_2_rangeb;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_3_RANGEA:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_corr_z_3_rangea;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_3_RANGEB:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_corr_z_3_rangeb;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_4_RANGEA:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_corr_z_4_rangea;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_4_RANGEB:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_corr_z_4_rangeb;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_5_RANGEA:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_corr_z_5_rangea;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_5_RANGEB:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_med_corr_z_5_rangeb;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_1_MIN:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_z_1_min;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_1_MAX:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_z_1_max;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_2_MIN:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_z_2_min;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_2_MAX:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_z_2_max;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_3_MIN:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_z_3_min;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_3_MAX:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_z_3_max;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_4_MIN:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_z_4_min;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_4_MAX:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_z_4_max;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_5_MIN:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_z_5_min;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_5_MAX:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_z_5_max;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_1_RANGEA:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_corr_z_1_rangea;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_1_RANGEB:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_corr_z_1_rangeb;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_2_RANGEA:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_corr_z_2_rangea;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_2_RANGEB:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_corr_z_2_rangeb;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_3_RANGEA:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_corr_z_3_rangea;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_3_RANGEB:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_corr_z_3_rangeb;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_4_RANGEA:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_corr_z_4_rangea;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_4_RANGEB:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_corr_z_4_rangeb;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_5_RANGEA:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_corr_z_5_rangea;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_5_RANGEB:\n+\t\t*ptuning_parm_value = pdev->tuning_parms.tp_uwr_lng_corr_z_5_rangeb;\n+\t\tbreak;\n+\tdefault:\n+\t\t*ptuning_parm_value = 0x7FFFFFFF;\n+\t\tstatus = VL53LX_ERROR_INVALID_PARAMS;\n+\t\tbreak;\n+\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_load_patch(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tint32_t patch_tuning = 0;\n+\tuint8_t comms_buffer[256];\n+\tuint32_t patch_power;\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WrByte(Dev, VL53LX_FIRMWARE__ENABLE, 0x00);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tVL53LX_enable_powerforce(Dev);\n+\n+\tVL53LX_get_tuning_parm(Dev, VL53LX_TUNINGPARM_PHASECAL_PATCH_POWER, &patch_tuning);\n+\n+\tswitch (patch_tuning) {\n+\tcase 0:\n+\t\tpatch_power = 0x00;\n+\t\tbreak;\n+\tcase 1:\n+\t\tpatch_power = 0x10;\n+\t\tbreak;\n+\tcase 2:\n+\t\tpatch_power = 0x20;\n+\t\tbreak;\n+\tcase 3:\n+\t\tpatch_power = 0x40;\n+\t\tbreak;\n+\tdefault:\n+\t\tpatch_power = 0x00;\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tcomms_buffer[0] = 0x29;\n+\t\tcomms_buffer[1] = 0xC9;\n+\t\tcomms_buffer[2] = 0x0E;\n+\t\tcomms_buffer[3] = 0x40;\n+\t\tcomms_buffer[4] = 0x28;\n+\t\tcomms_buffer[5] = patch_power;\n+\t\tstatus = VL53LX_WriteMulti(Dev, VL53LX_PATCH__OFFSET_0, comms_buffer, 6);\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tcomms_buffer[0] = 0x03;\n+\t\tcomms_buffer[1] = 0x6D;\n+\t\tcomms_buffer[2] = 0x03;\n+\t\tcomms_buffer[3] = 0x6F;\n+\t\tcomms_buffer[4] = 0x07;\n+\t\tcomms_buffer[5] = 0x29;\n+\t\tstatus = VL53LX_WriteMulti(Dev, VL53LX_PATCH__ADDRESS_0, comms_buffer, 6);\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tcomms_buffer[0] = 0x00;\n+\t\tcomms_buffer[1] = 0x07;\n+\t\tstatus = VL53LX_WriteMulti(Dev, VL53LX_PATCH__JMP_ENABLES, comms_buffer, 2);\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tcomms_buffer[0] = 0x00;\n+\t\tcomms_buffer[1] = 0x07;\n+\t\tstatus = VL53LX_WriteMulti(Dev, VL53LX_PATCH__DATA_ENABLES, comms_buffer, 2);\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WrByte(Dev, VL53LX_PATCH__CTRL, 0x01);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WrByte(Dev, VL53LX_FIRMWARE__ENABLE, 0x01);\n+\n+\treturn status;\n+}\n+\n+void VL53LX_encode_row_col(uint8_t row, uint8_t col, uint8_t *pspad_number)\n+{\n+\tif (row > 7)\n+\t\t*pspad_number = 128 + (col << 3) + (15-row);\n+\telse\n+\t\t*pspad_number = ((15-col) << 3) + row;\n+}\n+\n+void VL53LX_encode_zone_size(uint8_t width, uint8_t height, uint8_t *pencoded_xy_size)\n+{\n+\t*pencoded_xy_size = (height << 4) + width;\n+}\n+\n+VL53LX_Error VL53LX_set_user_zone(VL53LX_DEV Dev, VL53LX_user_zone_t *puser_zone)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tVL53LX_encode_row_col(puser_zone->y_centre, puser_zone->x_centre, &(pdev->dyn_cfg.roi_config__user_roi_centre_spad));\n+\n+\tVL53LX_encode_zone_size(puser_zone->width, puser_zone->height, &(pdev->dyn_cfg.roi_config__user_roi_requested_global_xy_size));\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_set_zone_dss_config(VL53LX_DEV Dev, VL53LX_zone_private_dyn_cfg_t *pzone_dyn_cfg)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_ll_driver_state_t *pstate = &(pdev->ll_state);\n+\n+\tif (pstate->cfg_device_state == VL53LX_DEVICESTATE_RANGING_DSS_MANUAL) {\n+\t\tpdev->gen_cfg.dss_config__roi_mode_control = VL53LX_DSS_CONTROL__MODE_EFFSPADS;\n+\t\tpdev->gen_cfg.dss_config__manual_effective_spads_select = pzone_dyn_cfg->dss_requested_effective_spad_count;\n+\t} else {\n+\t\tpdev->gen_cfg.dss_config__roi_mode_control = VL53LX_DSS_CONTROL__MODE_TARGET_RATE;\n+\t}\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_save_cfg_data(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_LLDriverResults_t *pres = VL53LXDevStructGetLLResultsHandle(Dev);\n+\n+\tVL53LX_zone_private_dyn_cfg_t *pzone_dyn_cfg;\n+\tVL53LX_dynamic_config_t       *pdynamic = &(pdev->dyn_cfg);\n+\n+\tpzone_dyn_cfg = &(pres->zone_dyn_cfgs.VL53LX_p_003[pdev->ll_state.cfg_zone_id]);\n+\tpzone_dyn_cfg->expected_stream_count = pdev->ll_state.cfg_stream_count;\n+\tpzone_dyn_cfg->expected_gph_id = pdev->ll_state.cfg_gph_id;\n+\tpzone_dyn_cfg->roi_config__user_roi_centre_spad = pdynamic->roi_config__user_roi_centre_spad;\n+\tpzone_dyn_cfg->roi_config__user_roi_requested_global_xy_size = pdynamic->roi_config__user_roi_requested_global_xy_size;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_i2c_encode_static_nvm_managed(VL53LX_static_nvm_managed_t *pdata, uint16_t buf_size, uint8_t *pbuffer)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (buf_size < VL53LX_STATIC_NVM_MANAGED_I2C_SIZE_BYTES)\n+\t\treturn VL53LX_ERROR_COMMS_BUFFER_TOO_SMALL;\n+\n+\t*(pbuffer +   0) = pdata->i2c_slave__device_address & 0x7F;\n+\t*(pbuffer +   1) = pdata->ana_config__vhv_ref_sel_vddpix & 0xF;\n+\t*(pbuffer +   2) = pdata->ana_config__vhv_ref_sel_vquench & 0x7F;\n+\t*(pbuffer +   3) = pdata->ana_config__reg_avdd1v2_sel & 0x3;\n+\t*(pbuffer +   4) = pdata->ana_config__fast_osc__trim & 0x7F;\n+\tVL53LX_i2c_encode_uint16_t(pdata->osc_measured__fast_osc__frequency, 2, pbuffer +   5);\n+\t*(pbuffer +   7) = pdata->vhv_config__timeout_macrop_loop_bound;\n+\t*(pbuffer +   8) = pdata->vhv_config__count_thresh;\n+\t*(pbuffer +   9) = pdata->vhv_config__offset & 0x3F;\n+\t*(pbuffer +  10) = pdata->vhv_config__init;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_i2c_decode_static_nvm_managed(uint16_t buf_size, uint8_t *pbuffer, VL53LX_static_nvm_managed_t *pdata)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (buf_size < VL53LX_STATIC_NVM_MANAGED_I2C_SIZE_BYTES)\n+\t\treturn VL53LX_ERROR_COMMS_BUFFER_TOO_SMALL;\n+\n+\tpdata->i2c_slave__device_address =\n+\t\t(*(pbuffer +   0)) & 0x7F;\n+\tpdata->ana_config__vhv_ref_sel_vddpix =\n+\t\t(*(pbuffer +   1)) & 0xF;\n+\tpdata->ana_config__vhv_ref_sel_vquench =\n+\t\t(*(pbuffer +   2)) & 0x7F;\n+\tpdata->ana_config__reg_avdd1v2_sel =\n+\t\t(*(pbuffer +   3)) & 0x3;\n+\tpdata->ana_config__fast_osc__trim =\n+\t\t(*(pbuffer +   4)) & 0x7F;\n+\tpdata->osc_measured__fast_osc__frequency =\n+\t\t(VL53LX_i2c_decode_uint16_t(2, pbuffer +   5));\n+\tpdata->vhv_config__timeout_macrop_loop_bound =\n+\t\t(*(pbuffer +   7));\n+\tpdata->vhv_config__count_thresh =\n+\t\t(*(pbuffer +   8));\n+\tpdata->vhv_config__offset =\n+\t\t(*(pbuffer +   9)) & 0x3F;\n+\tpdata->vhv_config__init =\n+\t\t(*(pbuffer +  10));\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_i2c_encode_static_config(VL53LX_static_config_t *pdata, uint16_t buf_size, uint8_t *pbuffer)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (buf_size < VL53LX_STATIC_CONFIG_I2C_SIZE_BYTES)\n+\t\treturn VL53LX_ERROR_COMMS_BUFFER_TOO_SMALL;\n+\n+\tVL53LX_i2c_encode_uint16_t(pdata->dss_config__target_total_rate_mcps, 2, pbuffer + 0);\n+\t*(pbuffer +   2) = pdata->debug__ctrl & 0x1;\n+\t*(pbuffer +   3) = pdata->test_mode__ctrl & 0xF;\n+\t*(pbuffer +   4) = pdata->clk_gating__ctrl & 0xF;\n+\t*(pbuffer +   5) = pdata->nvm_bist__ctrl & 0x1F;\n+\t*(pbuffer +   6) = pdata->nvm_bist__num_nvm_words & 0x7F;\n+\t*(pbuffer +   7) = pdata->nvm_bist__start_address & 0x7F;\n+\t*(pbuffer +   8) = pdata->host_if__status & 0x1;\n+\t*(pbuffer +   9) = pdata->pad_i2c_hv__config;\n+\t*(pbuffer +  10) = pdata->pad_i2c_hv__extsup_config & 0x1;\n+\t*(pbuffer +  11) = pdata->gpio_hv_pad__ctrl & 0x3;\n+\t*(pbuffer +  12) = pdata->gpio_hv_mux__ctrl & 0x1F;\n+\t*(pbuffer +  13) = pdata->gpio__tio_hv_status & 0x3;\n+\t*(pbuffer +  14) = pdata->gpio__fio_hv_status & 0x3;\n+\t*(pbuffer +  15) = pdata->ana_config__spad_sel_pswidth & 0x7;\n+\t*(pbuffer +  16) = pdata->ana_config__vcsel_pulse_width_offset & 0x1F;\n+\t*(pbuffer +  17) = pdata->ana_config__fast_osc__config_ctrl & 0x1;\n+\t*(pbuffer +  18) = pdata->sigma_estimator__effective_pulse_width_ns;\n+\t*(pbuffer +  19) = pdata->sigma_estimator__effective_ambient_width_ns;\n+\t*(pbuffer +  20) = pdata->sigma_estimator__sigma_ref_mm;\n+\t*(pbuffer +  21) = pdata->algo__crosstalk_compensation_valid_height_mm;\n+\t*(pbuffer +  22) = pdata->spare_host_config__static_config_spare_0;\n+\t*(pbuffer +  23) = pdata->spare_host_config__static_config_spare_1;\n+\tVL53LX_i2c_encode_uint16_t(pdata->algo__range_ignore_threshold_mcps, 2, pbuffer + 24);\n+\t*(pbuffer +  26) = pdata->algo__range_ignore_valid_height_mm;\n+\t*(pbuffer +  27) = pdata->algo__range_min_clip;\n+\t*(pbuffer +  28) = pdata->algo__consistency_check__tolerance & 0xF;\n+\t*(pbuffer +  29) = pdata->spare_host_config__static_config_spare_2;\n+\t*(pbuffer +  30) = pdata->sd_config__reset_stages_msb & 0xF;\n+\t*(pbuffer +  31) = pdata->sd_config__reset_stages_lsb;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_i2c_encode_general_config(VL53LX_general_config_t *pdata, uint16_t buf_size, uint8_t *pbuffer)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (buf_size < VL53LX_GENERAL_CONFIG_I2C_SIZE_BYTES)\n+\t\treturn VL53LX_ERROR_COMMS_BUFFER_TOO_SMALL;\n+\n+\t*(pbuffer +   0) = pdata->gph_config__stream_count_update_value;\n+\t*(pbuffer +   1) = pdata->global_config__stream_divider;\n+\t*(pbuffer +   2) = pdata->system__interrupt_config_gpio;\n+\t*(pbuffer +   3) = pdata->cal_config__vcsel_start & 0x7F;\n+\tVL53LX_i2c_encode_uint16_t(pdata->cal_config__repeat_rate & 0xFFF, 2, pbuffer + 4);\n+\t*(pbuffer +   6) = pdata->global_config__vcsel_width & 0x7F;\n+\t*(pbuffer +   7) = pdata->phasecal_config__timeout_macrop;\n+\t*(pbuffer +   8) = pdata->phasecal_config__target;\n+\t*(pbuffer +   9) = pdata->phasecal_config__override & 0x1;\n+\t*(pbuffer +  11) = pdata->dss_config__roi_mode_control & 0x7;\n+\tVL53LX_i2c_encode_uint16_t(pdata->system__thresh_rate_high, 2, pbuffer + 12);\n+\tVL53LX_i2c_encode_uint16_t(pdata->system__thresh_rate_low, 2, pbuffer + 14);\n+\tVL53LX_i2c_encode_uint16_t(pdata->dss_config__manual_effective_spads_select, 2, pbuffer + 16);\n+\t*(pbuffer +  18) = pdata->dss_config__manual_block_select;\n+\t*(pbuffer +  19) = pdata->dss_config__aperture_attenuation;\n+\t*(pbuffer +  20) = pdata->dss_config__max_spads_limit;\n+\t*(pbuffer +  21) = pdata->dss_config__min_spads_limit;\n+\n+\treturn status;\n+}\n+\n+void VL53LX_i2c_encode_uint32_t(uint32_t ip_value, uint16_t count, uint8_t *pbuffer)\n+{\n+\tuint16_t   i    = 0;\n+\tuint32_t   VL53LX_p_003 = 0;\n+\n+\tVL53LX_p_003 =  ip_value;\n+\n+\tfor (i = 0; i < count; i++) {\n+\t\tpbuffer[count-i-1] = (uint8_t)(VL53LX_p_003 & 0x00FF);\n+\t\tVL53LX_p_003 = VL53LX_p_003 >> 8;\n+\t}\n+}\n+\n+uint32_t VL53LX_i2c_decode_uint32_t(uint16_t count, uint8_t *pbuffer)\n+{\n+\tuint32_t   value = 0x00;\n+\n+\twhile (count-- > 0)\n+\t\tvalue = (value << 8) | (uint32_t)*pbuffer++;\n+\n+\treturn value;\n+}\n+\n+VL53LX_Error VL53LX_i2c_encode_timing_config(VL53LX_timing_config_t *pdata, uint16_t buf_size, uint8_t *pbuffer)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (buf_size < VL53LX_TIMING_CONFIG_I2C_SIZE_BYTES)\n+\t\treturn VL53LX_ERROR_COMMS_BUFFER_TOO_SMALL;\n+\n+\t*(pbuffer +   0) = pdata->mm_config__timeout_macrop_a_hi & 0xF;\n+\t*(pbuffer +   1) = pdata->mm_config__timeout_macrop_a_lo;\n+\t*(pbuffer +   2) = pdata->mm_config__timeout_macrop_b_hi & 0xF;\n+\t*(pbuffer +   3) = pdata->mm_config__timeout_macrop_b_lo;\n+\t*(pbuffer +   4) = pdata->range_config__timeout_macrop_a_hi & 0xF;\n+\t*(pbuffer +   5) = pdata->range_config__timeout_macrop_a_lo;\n+\t*(pbuffer +   6) = pdata->range_config__vcsel_period_a & 0x3F;\n+\t*(pbuffer +   7) = pdata->range_config__timeout_macrop_b_hi & 0xF;\n+\t*(pbuffer +   8) = pdata->range_config__timeout_macrop_b_lo;\n+\t*(pbuffer +   9) = pdata->range_config__vcsel_period_b & 0x3F;\n+\tVL53LX_i2c_encode_uint16_t(pdata->range_config__sigma_thresh, 2, pbuffer + 10);\n+\tVL53LX_i2c_encode_uint16_t(pdata->range_config__min_count_rate_rtn_limit_mcps, 2, pbuffer + 12);\n+\t*(pbuffer +  14) = pdata->range_config__valid_phase_low;\n+\t*(pbuffer +  15) = pdata->range_config__valid_phase_high;\n+\tVL53LX_i2c_encode_uint32_t(pdata->system__intermeasurement_period, 4, pbuffer + 18);\n+\t*(pbuffer +  22) = pdata->system__fractional_enable & 0x1;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_i2c_encode_dynamic_config(VL53LX_dynamic_config_t *pdata, uint16_t buf_size, uint8_t *pbuffer)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (buf_size < VL53LX_DYNAMIC_CONFIG_I2C_SIZE_BYTES)\n+\t\treturn VL53LX_ERROR_COMMS_BUFFER_TOO_SMALL;\n+\n+\t*(pbuffer +   0) = pdata->system__grouped_parameter_hold_0 & 0x3;\n+\tVL53LX_i2c_encode_uint16_t(pdata->system__thresh_high, 2, pbuffer + 1);\n+\tVL53LX_i2c_encode_uint16_t(pdata->system__thresh_low, 2, pbuffer + 3);\n+\t*(pbuffer +   5) = pdata->system__enable_xtalk_per_quadrant & 0x1;\n+\t*(pbuffer +   6) = pdata->system__seed_config & 0x7;\n+\t*(pbuffer +   7) = pdata->sd_config__woi_sd0;\n+\t*(pbuffer +   8) = pdata->sd_config__woi_sd1;\n+\t*(pbuffer +   9) = pdata->sd_config__initial_phase_sd0 & 0x7F;\n+\t*(pbuffer +  10) = pdata->sd_config__initial_phase_sd1 & 0x7F;\n+\t*(pbuffer +  11) = pdata->system__grouped_parameter_hold_1 & 0x3;\n+\t*(pbuffer +  12) = pdata->sd_config__first_order_select & 0x3;\n+\t*(pbuffer +  13) = pdata->sd_config__quantifier & 0xF;\n+\t*(pbuffer +  14) = pdata->roi_config__user_roi_centre_spad;\n+\t*(pbuffer +  15) = pdata->roi_config__user_roi_requested_global_xy_size;\n+\t*(pbuffer +  16) = pdata->system__sequence_config;\n+\t*(pbuffer +  17) = pdata->system__grouped_parameter_hold & 0x3;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_update_internal_stream_counters(VL53LX_DEV Dev, uint8_t external_stream_count, uint8_t *pinternal_stream_count, uint8_t *pinternal_stream_count_val)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tuint8_t stream_divider;\n+\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tstream_divider = pdev->gen_cfg.global_config__stream_divider;\n+\n+\tif (stream_divider == 0) {\n+\t\t*pinternal_stream_count = external_stream_count;\n+\t} else if (*pinternal_stream_count_val == (stream_divider-1)) {\n+\t\tif (*pinternal_stream_count == 0xFF)\n+\t\t\t*pinternal_stream_count = 0x80;\n+\t\telse\n+\t\t\t*pinternal_stream_count = *pinternal_stream_count + 1;\n+\t\t*pinternal_stream_count_val = 0;\n+\n+\t} else {\n+\t\t*pinternal_stream_count_val = *pinternal_stream_count_val + 1;\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_update_ll_driver_rd_state(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error        status  = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_ll_driver_state_t *pstate = &(pdev->ll_state);\n+\n+\tif ((pdev->sys_ctrl.system__mode_start & VL53LX_DEVICEMEASUREMENTMODE_MODE_MASK) == 0x00) {\n+\t\tpstate->rd_device_state  = VL53LX_DEVICESTATE_SW_STANDBY;\n+\t\tpstate->rd_stream_count  = 0;\n+\t\tpstate->rd_internal_stream_count = 0;\n+\t\tpstate->rd_internal_stream_count_val = 0;\n+\t\tpstate->rd_gph_id = VL53LX_GROUPEDPARAMETERHOLD_ID_MASK;\n+\t\tpstate->rd_timing_status = 0;\n+\t\tpstate->rd_zone_id       = 0;\n+\n+\t} else {\n+\t\tif (pstate->rd_stream_count == 0xFF)\n+\t\t\tpstate->rd_stream_count = 0x80;\n+\t\telse\n+\t\t\tpstate->rd_stream_count++;\n+\n+\t\tstatus = VL53LX_update_internal_stream_counters(Dev, pstate->rd_stream_count, &(pstate->rd_internal_stream_count), &(pstate->rd_internal_stream_count_val));\n+\t\tpstate->rd_gph_id ^= VL53LX_GROUPEDPARAMETERHOLD_ID_MASK;\n+\t\tswitch (pstate->rd_device_state) {\n+\t\tcase VL53LX_DEVICESTATE_SW_STANDBY:\n+\t\t\tif ((pdev->dyn_cfg.system__grouped_parameter_hold & VL53LX_GROUPEDPARAMETERHOLD_ID_MASK) > 0) {\n+\t\t\t\tpstate->rd_device_state =\n+\t\t\t\tVL53LX_DEVICESTATE_RANGING_WAIT_GPH_SYNC;\n+\t\t\t} else {\n+\t\t\t\tif (pstate->rd_zone_id >= pdev->zone_cfg.active_zones)\n+\t\t\t\t\tpstate->rd_device_state = VL53LX_DEVICESTATE_RANGING_OUTPUT_DATA;\n+\t\t\t\telse\n+\t\t\t\t\tpstate->rd_device_state = VL53LX_DEVICESTATE_RANGING_GATHER_DATA;\n+\t\t\t}\n+\t\t\tpstate->rd_stream_count  = 0;\n+\t\t\tpstate->rd_internal_stream_count = 0;\n+\t\t\tpstate->rd_internal_stream_count_val = 0;\n+\t\t\tpstate->rd_timing_status = 0;\n+\t\t\tpstate->rd_zone_id       = 0;\n+\t\t\tbreak;\n+\t\tcase VL53LX_DEVICESTATE_RANGING_WAIT_GPH_SYNC:\n+\t\t\tpstate->rd_stream_count = 0;\n+\t\t\tpstate->rd_internal_stream_count = 0;\n+\t\t\tpstate->rd_internal_stream_count_val = 0;\n+\t\t\tpstate->rd_zone_id      = 0;\n+\t\t\tif (pstate->rd_zone_id >= pdev->zone_cfg.active_zones)\n+\t\t\t\tpstate->rd_device_state = VL53LX_DEVICESTATE_RANGING_OUTPUT_DATA;\n+\t\t\telse\n+\t\t\t\tpstate->rd_device_state = VL53LX_DEVICESTATE_RANGING_GATHER_DATA;\n+\t\t\tbreak;\n+\t\tcase VL53LX_DEVICESTATE_RANGING_GATHER_DATA:\n+\t\t\tpstate->rd_zone_id++;\n+\t\t\tif (pstate->rd_zone_id >= pdev->zone_cfg.active_zones)\n+\t\t\t\tpstate->rd_device_state = VL53LX_DEVICESTATE_RANGING_OUTPUT_DATA;\n+\t\t\telse\n+\t\t\t\tpstate->rd_device_state = VL53LX_DEVICESTATE_RANGING_GATHER_DATA;\n+\t\t\tbreak;\n+\t\tcase VL53LX_DEVICESTATE_RANGING_OUTPUT_DATA:\n+\t\t\tpstate->rd_zone_id        = 0;\n+\t\t\tpstate->rd_timing_status ^= 0x01;\n+\t\t\tif (pstate->rd_zone_id >= pdev->zone_cfg.active_zones)\n+\t\t\t\tpstate->rd_device_state = VL53LX_DEVICESTATE_RANGING_OUTPUT_DATA;\n+\t\t\telse\n+\t\t\t\tpstate->rd_device_state = VL53LX_DEVICESTATE_RANGING_GATHER_DATA;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tpstate->rd_device_state  = VL53LX_DEVICESTATE_SW_STANDBY;\n+\t\t\tpstate->rd_stream_count  = 0;\n+\t\t\tpstate->rd_internal_stream_count = 0;\n+\t\t\tpstate->rd_internal_stream_count_val = 0;\n+\t\t\tpstate->rd_gph_id = VL53LX_GROUPEDPARAMETERHOLD_ID_MASK;\n+\t\t\tpstate->rd_timing_status = 0;\n+\t\t\tpstate->rd_zone_id       = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_update_ll_driver_cfg_state(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error         status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t  *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_LLDriverResults_t  *pres = VL53LXDevStructGetLLResultsHandle(Dev);\n+\n+\tVL53LX_ll_driver_state_t *pstate = &(pdev->ll_state);\n+\tVL53LX_zone_private_dyn_cfgs_t *pZ = &(pres->zone_dyn_cfgs);\n+\n+\tuint8_t prev_cfg_zone_id;\n+\tuint8_t prev_cfg_gph_id;\n+\tuint8_t prev_cfg_stream_count;\n+\n+\tif ((pdev->sys_ctrl.system__mode_start & VL53LX_DEVICEMEASUREMENTMODE_MODE_MASK) == 0x00) {\n+\t\tpstate->cfg_device_state  = VL53LX_DEVICESTATE_SW_STANDBY;\n+\t\tpstate->cfg_stream_count  = 0;\n+\t\tpstate->cfg_internal_stream_count = 0;\n+\t\tpstate->cfg_internal_stream_count_val = 0;\n+\t\tpstate->cfg_gph_id = VL53LX_GROUPEDPARAMETERHOLD_ID_MASK;\n+\t\tpstate->cfg_timing_status = 0;\n+\t\tpstate->cfg_zone_id       = 0;\n+\t\tprev_cfg_zone_id          = 0;\n+\t\tprev_cfg_gph_id           = 0;\n+\t\tprev_cfg_stream_count     = 0;\n+\n+\t} else {\n+\t\tprev_cfg_gph_id           = pstate->cfg_gph_id;\n+\t\tprev_cfg_zone_id          = pstate->cfg_zone_id;\n+\t\tprev_cfg_stream_count     = pstate->cfg_stream_count;\n+\n+\t\tif (pstate->cfg_stream_count == 0xFF)\n+\t\t\tpstate->cfg_stream_count = 0x80;\n+\t\telse\n+\t\t\tpstate->cfg_stream_count++;\n+\n+\t\tstatus = VL53LX_update_internal_stream_counters(Dev, pstate->cfg_stream_count, &(pstate->cfg_internal_stream_count), &(pstate->cfg_internal_stream_count_val));\n+\n+\t\tpstate->cfg_gph_id ^= VL53LX_GROUPEDPARAMETERHOLD_ID_MASK;\n+\n+\t\tswitch (pstate->cfg_device_state) {\n+\t\tcase VL53LX_DEVICESTATE_SW_STANDBY:\n+\t\t\tpstate->cfg_zone_id = 1;\n+\t\t\tif (pstate->cfg_zone_id > pdev->zone_cfg.active_zones) {\n+\t\t\t\tpstate->cfg_zone_id = 0;\n+\t\t\t\tpstate->cfg_timing_status ^= 0x01;\n+\t\t\t}\n+\t\t\tpstate->cfg_stream_count = 1;\n+\n+\t\t\tif (pdev->gen_cfg.global_config__stream_divider == 0) {\n+\t\t\t\tpstate->cfg_internal_stream_count = 1;\n+\t\t\t\tpstate->cfg_internal_stream_count_val = 0;\n+\t\t\t} else {\n+\t\t\t\tpstate->cfg_internal_stream_count = 0;\n+\t\t\t\tpstate->cfg_internal_stream_count_val = 1;\n+\t\t\t}\n+\t\t\tpstate->cfg_device_state = VL53LX_DEVICESTATE_RANGING_DSS_AUTO;\n+\t\t\tbreak;\n+\t\tcase VL53LX_DEVICESTATE_RANGING_DSS_AUTO:\n+\t\t\tpstate->cfg_zone_id++;\n+\t\t\tif (pstate->cfg_zone_id > pdev->zone_cfg.active_zones) {\n+\t\t\t\tpstate->cfg_zone_id = 0;\n+\t\t\t\tpstate->cfg_timing_status ^= 0x01;\n+\n+\t\t\t\tif (pdev->zone_cfg.active_zones > 0) {\n+\t\t\t\t\tpstate->cfg_device_state =\n+\t\t\t\t\tVL53LX_DEVICESTATE_RANGING_DSS_MANUAL;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase VL53LX_DEVICESTATE_RANGING_DSS_MANUAL:\n+\t\t\tpstate->cfg_zone_id++;\n+\t\t\tif (pstate->cfg_zone_id > pdev->zone_cfg.active_zones) {\n+\t\t\t\tpstate->cfg_zone_id = 0;\n+\t\t\t\tpstate->cfg_timing_status ^= 0x01;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tpstate->cfg_device_state = VL53LX_DEVICESTATE_SW_STANDBY;\n+\t\t\tpstate->cfg_stream_count = 0;\n+\t\t\tpstate->cfg_internal_stream_count = 0;\n+\t\t\tpstate->cfg_internal_stream_count_val = 0;\n+\t\t\tpstate->cfg_gph_id = VL53LX_GROUPEDPARAMETERHOLD_ID_MASK;\n+\t\t\tpstate->cfg_timing_status = 0;\n+\t\t\tpstate->cfg_zone_id       = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tif (pdev->zone_cfg.active_zones == 0) {\n+\t\tpZ->VL53LX_p_003[prev_cfg_zone_id].expected_stream_count = prev_cfg_stream_count - 1;\n+\t\tpZ->VL53LX_p_003[pstate->rd_zone_id].expected_gph_id = prev_cfg_gph_id ^ VL53LX_GROUPEDPARAMETERHOLD_ID_MASK;\n+\t} else {\n+\t\tpZ->VL53LX_p_003[prev_cfg_zone_id].expected_stream_count = prev_cfg_stream_count;\n+\t\tpZ->VL53LX_p_003[prev_cfg_zone_id].expected_gph_id = prev_cfg_gph_id;\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_init_and_start_range(VL53LX_DEV Dev, uint8_t measurement_mode, VL53LX_DeviceConfigLevel device_config_level)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_LLDriverResults_t  *pres = VL53LXDevStructGetLLResultsHandle(Dev);\n+\n+\tuint8_t buffer[VL53LX_MAX_I2C_XFER_SIZE];\n+\n+\tVL53LX_static_nvm_managed_t   *pstatic_nvm   = &(pdev->stat_nvm);\n+\tVL53LX_customer_nvm_managed_t *pcustomer_nvm = &(pdev->customer);\n+\tVL53LX_static_config_t        *pstatic       = &(pdev->stat_cfg);\n+\tVL53LX_general_config_t       *pgeneral      = &(pdev->gen_cfg);\n+\tVL53LX_timing_config_t        *ptiming       = &(pdev->tim_cfg);\n+\tVL53LX_dynamic_config_t       *pdynamic      = &(pdev->dyn_cfg);\n+\tVL53LX_system_control_t       *psystem       = &(pdev->sys_ctrl);\n+\n+\tVL53LX_ll_driver_state_t  *pstate   = &(pdev->ll_state);\n+\tVL53LX_customer_nvm_managed_t *pN = &(pdev->customer);\n+\n+\tuint8_t  *pbuffer                   = &buffer[0];\n+\tuint16_t i                          = 0;\n+\tuint16_t i2c_index                  = 0;\n+\tuint16_t i2c_buffer_offset_bytes    = 0;\n+\tuint16_t i2c_buffer_size_bytes      = 0;\n+\n+\tpdev->measurement_mode = measurement_mode;\n+\n+\tpsystem->system__mode_start = (psystem->system__mode_start & VL53LX_DEVICEMEASUREMENTMODE_STOP_MASK) | measurement_mode;\n+\n+\tstatus = VL53LX_set_user_zone(Dev, &(pdev->zone_cfg.user_zones[pdev->ll_state.cfg_zone_id]));\n+\tif (pdev->zone_cfg.active_zones > 0) {\n+\t\tstatus = VL53LX_set_zone_dss_config(Dev, &(pres->zone_dyn_cfgs.VL53LX_p_003[pdev->ll_state.cfg_zone_id]));\n+\t}\n+\n+\tif (((pdev->sys_ctrl.system__mode_start & VL53LX_DEVICESCHEDULERMODE_HISTOGRAM) == 0x00) && (pdev->xtalk_cfg.global_crosstalk_compensation_enable == 0x01)) {\n+\t\tpdev->stat_cfg.algo__range_ignore_threshold_mcps = pdev->xtalk_cfg.crosstalk_range_ignore_threshold_rate_mcps;\n+\t}\n+\n+\tif (pdev->low_power_auto_data.low_power_auto_range_count == 0xFF)\n+\t\tpdev->low_power_auto_data.low_power_auto_range_count = 0x0;\n+\n+\tif ((pdev->low_power_auto_data.is_low_power_auto_mode == 1) && (pdev->low_power_auto_data.low_power_auto_range_count == 0)) {\n+\t\tpdev->low_power_auto_data.saved_interrupt_config = pdev->gen_cfg.system__interrupt_config_gpio;\n+\t\tpdev->gen_cfg.system__interrupt_config_gpio = 1 << 5;\n+\t\tif ((pdev->dyn_cfg.system__sequence_config & (VL53LX_SEQUENCE_MM1_EN | VL53LX_SEQUENCE_MM2_EN)) == 0x0) {\n+\t\t\tpN->algo__part_to_part_range_offset_mm = (pN->mm_config__outer_offset_mm << 2);\n+\t\t} else {\n+\t\t\tpN->algo__part_to_part_range_offset_mm = 0x0;\n+\t\t}\n+\t\tif (device_config_level < VL53LX_DEVICECONFIGLEVEL_CUSTOMER_ONWARDS) {\n+\t\t\tdevice_config_level = VL53LX_DEVICECONFIGLEVEL_CUSTOMER_ONWARDS;\n+\t\t}\n+\t}\n+\n+\tif ((pdev->low_power_auto_data.is_low_power_auto_mode == 1) && (pdev->low_power_auto_data.low_power_auto_range_count == 1)) {\n+\t\tpdev->gen_cfg.system__interrupt_config_gpio = pdev->low_power_auto_data.saved_interrupt_config;\n+\t\tdevice_config_level = VL53LX_DEVICECONFIGLEVEL_FULL;\n+\t}\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_save_cfg_data(Dev);\n+\n+\tswitch (device_config_level) {\n+\tcase VL53LX_DEVICECONFIGLEVEL_FULL:\n+\t\ti2c_index = VL53LX_STATIC_NVM_MANAGED_I2C_INDEX;\n+\t\tbreak;\n+\tcase VL53LX_DEVICECONFIGLEVEL_CUSTOMER_ONWARDS:\n+\t\ti2c_index = VL53LX_CUSTOMER_NVM_MANAGED_I2C_INDEX;\n+\t\tbreak;\n+\tcase VL53LX_DEVICECONFIGLEVEL_STATIC_ONWARDS:\n+\t\ti2c_index = VL53LX_STATIC_CONFIG_I2C_INDEX;\n+\t\tbreak;\n+\tcase VL53LX_DEVICECONFIGLEVEL_GENERAL_ONWARDS:\n+\t\ti2c_index = VL53LX_GENERAL_CONFIG_I2C_INDEX;\n+\t\tbreak;\n+\tcase VL53LX_DEVICECONFIGLEVEL_TIMING_ONWARDS:\n+\t\ti2c_index = VL53LX_TIMING_CONFIG_I2C_INDEX;\n+\t\tbreak;\n+\tcase VL53LX_DEVICECONFIGLEVEL_DYNAMIC_ONWARDS:\n+\t\ti2c_index = VL53LX_DYNAMIC_CONFIG_I2C_INDEX;\n+\t\tbreak;\n+\tdefault:\n+\t\ti2c_index = VL53LX_SYSTEM_CONTROL_I2C_INDEX;\n+\t\tbreak;\n+\t}\n+\ti2c_buffer_size_bytes = (VL53LX_SYSTEM_CONTROL_I2C_INDEX + VL53LX_SYSTEM_CONTROL_I2C_SIZE_BYTES) - i2c_index;\n+\n+\tpbuffer = &buffer[0];\n+\tfor (i = 0; i < i2c_buffer_size_bytes; i++)\n+\t\t*pbuffer++ = 0;\n+\n+\tif (device_config_level >= VL53LX_DEVICECONFIGLEVEL_FULL && status == VL53LX_ERROR_NONE) {\n+\t\ti2c_buffer_offset_bytes = VL53LX_STATIC_NVM_MANAGED_I2C_INDEX - i2c_index;\n+\t\tstatus = VL53LX_i2c_encode_static_nvm_managed(pstatic_nvm, VL53LX_STATIC_NVM_MANAGED_I2C_SIZE_BYTES, &buffer[i2c_buffer_offset_bytes]);\n+\t}\n+\tif (device_config_level >= VL53LX_DEVICECONFIGLEVEL_CUSTOMER_ONWARDS && status == VL53LX_ERROR_NONE) {\n+\t\ti2c_buffer_offset_bytes = VL53LX_CUSTOMER_NVM_MANAGED_I2C_INDEX - i2c_index;\n+\t\tstatus = VL53LX_i2c_encode_customer_nvm_managed(pcustomer_nvm, VL53LX_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES, &buffer[i2c_buffer_offset_bytes]);\n+\t}\n+\tif (device_config_level >= VL53LX_DEVICECONFIGLEVEL_STATIC_ONWARDS && status == VL53LX_ERROR_NONE) {\n+\t\ti2c_buffer_offset_bytes = VL53LX_STATIC_CONFIG_I2C_INDEX - i2c_index;\n+\t\tstatus = VL53LX_i2c_encode_static_config(pstatic, VL53LX_STATIC_CONFIG_I2C_SIZE_BYTES, &buffer[i2c_buffer_offset_bytes]);\n+\t}\n+\tif (device_config_level >= VL53LX_DEVICECONFIGLEVEL_GENERAL_ONWARDS && status == VL53LX_ERROR_NONE) {\n+\t\ti2c_buffer_offset_bytes = VL53LX_GENERAL_CONFIG_I2C_INDEX - i2c_index;\n+\t\tstatus = VL53LX_i2c_encode_general_config(pgeneral, VL53LX_GENERAL_CONFIG_I2C_SIZE_BYTES, &buffer[i2c_buffer_offset_bytes]);\n+\t}\n+\tif (device_config_level >= VL53LX_DEVICECONFIGLEVEL_TIMING_ONWARDS && status == VL53LX_ERROR_NONE) {\n+\t\ti2c_buffer_offset_bytes = VL53LX_TIMING_CONFIG_I2C_INDEX - i2c_index;\n+\t\tstatus = VL53LX_i2c_encode_timing_config(ptiming, VL53LX_TIMING_CONFIG_I2C_SIZE_BYTES, &buffer[i2c_buffer_offset_bytes]);\n+\t}\n+\tif (device_config_level >= VL53LX_DEVICECONFIGLEVEL_DYNAMIC_ONWARDS && status == VL53LX_ERROR_NONE) {\n+\t\ti2c_buffer_offset_bytes = VL53LX_DYNAMIC_CONFIG_I2C_INDEX - i2c_index;\n+\t\tif ((psystem->system__mode_start & VL53LX_DEVICEMEASUREMENTMODE_BACKTOBACK) == VL53LX_DEVICEMEASUREMENTMODE_BACKTOBACK) {\n+\t\t\tpdynamic->system__grouped_parameter_hold_0 = pstate->cfg_gph_id | 0x01;\n+\t\t\tpdynamic->system__grouped_parameter_hold_1 = pstate->cfg_gph_id | 0x01;\n+\t\t\tpdynamic->system__grouped_parameter_hold   = pstate->cfg_gph_id;\n+\t\t}\n+\t\tstatus = VL53LX_i2c_encode_dynamic_config(pdynamic, VL53LX_DYNAMIC_CONFIG_I2C_SIZE_BYTES, &buffer[i2c_buffer_offset_bytes]);\n+\t}\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\ti2c_buffer_offset_bytes = VL53LX_SYSTEM_CONTROL_I2C_INDEX - i2c_index;\n+\t\tstatus = VL53LX_i2c_encode_system_control(psystem, VL53LX_SYSTEM_CONTROL_I2C_SIZE_BYTES, &buffer[i2c_buffer_offset_bytes]);\n+\t}\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tstatus = VL53LX_WriteMulti(Dev, i2c_index, buffer, (uint32_t)i2c_buffer_size_bytes);\n+\t}\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_update_ll_driver_rd_state(Dev);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_update_ll_driver_cfg_state(Dev);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_StartMeasurement(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tuint8_t DeviceMeasurementMode;\n+\tuint8_t i;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tVL53LX_load_patch(Dev);\n+\tfor (i = 0; i < VL53LX_MAX_RANGE_RESULTS; i++) {\n+\t\tpdev->PreviousRangeMilliMeter[i] = 0;\n+\t\tpdev->PreviousRangeStatus[i] = 255;\n+\t\tpdev->PreviousExtendedRange[i] = 0;\n+\t}\n+\tpdev->PreviousStreamCount = 0;\n+\tpdev->PreviousRangeActiveResults = 0;\n+\n+\tDeviceMeasurementMode = VL53LXDevDataGet(Dev, LLData.measurement_mode);\n+\n+\tif (Status == VL53LX_ERROR_NONE)\n+\t\tStatus = VL53LX_init_and_start_range(Dev, DeviceMeasurementMode, VL53LX_DEVICECONFIGLEVEL_FULL);\n+\n+\treturn Status;\n+}\n+\n+VL53LX_Error VL53LX_WaitMeasurementDataReady(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\n+\tStatus = VL53LX_poll_for_range_completion(Dev, VL53LX_RANGE_COMPLETION_POLLING_TIMEOUT_MS);\n+\n+\treturn Status;\n+}\n+\n+VL53LX_Error VL53LX_is_new_data_ready(VL53LX_DEV Dev, uint8_t *pready)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tuint8_t  gpio__mux_active_high_hv = 0;\n+\tuint8_t  gpio__tio_hv_status      = 0;\n+\tuint8_t  interrupt_ready          = 0;\n+\n+\tgpio__mux_active_high_hv = pdev->stat_cfg.gpio_hv_mux__ctrl & VL53LX_DEVICEINTERRUPTLEVEL_ACTIVE_MASK;\n+\n+\tif (gpio__mux_active_high_hv == VL53LX_DEVICEINTERRUPTLEVEL_ACTIVE_HIGH)\n+\t\tinterrupt_ready = 0x01;\n+\telse\n+\t\tinterrupt_ready = 0x00;\n+\n+\tstatus = VL53LX_RdByte(Dev, VL53LX_GPIO__TIO_HV_STATUS, &gpio__tio_hv_status);\n+\n+\tif ((gpio__tio_hv_status & 0x01) == interrupt_ready)\n+\t\t*pready = 0x01;\n+\telse\n+\t\t*pready = 0x00;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_GetMeasurementDataReady(VL53LX_DEV Dev, uint8_t *pMeasurementDataReady)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\n+\tStatus = VL53LX_is_new_data_ready(Dev, pMeasurementDataReady);\n+\n+\treturn Status;\n+}\n+\n+long stmvl53lx_tv_dif(struct st_timeval *pstart_tv, struct st_timeval *pstop_tv)\n+{\n+\tlong total_sec, total_usec;\n+\n+\ttotal_sec = pstop_tv->tv_sec - pstart_tv->tv_sec;\n+\ttotal_usec = (pstop_tv->tv_usec - pstart_tv->tv_usec);\n+\n+\treturn total_sec*1000000+total_usec;\n+}\n+\n+VL53LX_Error VL53LX_GetMultiRangingData(VL53LX_DEV Dev, VL53LX_MultiRangingData_t *pMultiRangingData)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_range_results_t *presults = (VL53LX_range_results_t *) pdev->wArea1;\n+\n+\tmemset(pMultiRangingData, 0xFF, sizeof(VL53LX_MultiRangingData_t));\n+\n+\tStatus = VL53LX_get_device_results(Dev, VL53LX_DEVICERESULTSLEVEL_FULL, presults);\n+\tStatus = SetMeasurementData(Dev, presults, pMultiRangingData);\n+\n+\treturn Status;\n+}\n+\n+VL53LX_Error VL53LX_get_histogram_debug_data(VL53LX_DEV Dev, VL53LX_histogram_bin_data_t *pdata)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tmemcpy(pdata, &(pdev->hist_data), sizeof(VL53LX_histogram_bin_data_t));\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_get_additional_data(VL53LX_DEV Dev, VL53LX_additional_data_t *pdata)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpdata->preset_mode             = pdev->preset_mode;\n+\tpdata->zone_preset             = pdev->zone_preset;\n+\tpdata->measurement_mode        = pdev->measurement_mode;\n+\tpdata->offset_calibration_mode = pdev->offset_calibration_mode;\n+\tpdata->offset_correction_mode  = pdev->offset_correction_mode;\n+\tpdata->dmax_mode               = pdev->dmax_mode;\n+\n+\tpdata->phasecal_config_timeout_us  = pdev->phasecal_config_timeout_us;\n+\tpdata->mm_config_timeout_us        = pdev->mm_config_timeout_us;\n+\tpdata->range_config_timeout_us     = pdev->range_config_timeout_us;\n+\tpdata->inter_measurement_period_ms = pdev->inter_measurement_period_ms;\n+\tpdata->dss_config__target_total_rate_mcps = pdev->dss_config__target_total_rate_mcps;\n+\n+\tstatus = VL53LX_get_histogram_debug_data(Dev, &(pdata->VL53LX_p_006));\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_GetAdditionalData(VL53LX_DEV Dev, VL53LX_AdditionalData_t *pAdditionalData)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\n+\tStatus = VL53LX_get_additional_data(Dev, pAdditionalData);\n+\n+\treturn Status;\n+}\n+\n+static void detect_xtalk_value_change(struct stmvl53lx_data *data, VL53LX_MultiRangingData_t *meas)\n+{\n+\tdata->is_xtalk_value_changed = meas->HasXtalkValueChanged ? true : data->is_xtalk_value_changed;\n+}\n+\n+static void stmvl53lx_input_push_data_multiobject(struct stmvl53lx_data *data)\n+{\n+\tVL53LX_MultiRangingData_t *mmeas = &data->meas.multi_range_data;\n+\tint i;\n+\tint rc = 0;\n+\tVL53LX_TargetRangeData_t *meas_array[4];\n+\tVL53LX_CalibrationData_t calibration_data;\n+\tstruct st_timeval tv;\n+\tstruct input_dev *input = data->input_dev_ps;\n+\n+\tst_gettimeofday(&tv);\n+\n+\tfor (i = 0; i < 4; i++)\n+\t\tmeas_array[i] = &mmeas->RangeData[i];\n+\n+\trc = VL53LX_GetCalibrationData(&data->stdev, &calibration_data);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"%d error:%d\\n\", __LINE__, rc);\n+\t\treturn;\n+\t}\n+\n+\tinput_report_abs(input, ABS_HAT0X, tv.tv_sec);\n+\tvl53lx_dbgmsg(\"ABS_HAT0X : %ld, %zu\\n\", tv.tv_sec, sizeof(tv.tv_sec));\n+\n+\tinput_report_abs(input, ABS_HAT0Y, tv.tv_usec);\n+\tvl53lx_dbgmsg(\"ABS_HAT0Y : %ld\\n\", tv.tv_usec);\n+\n+\tinput_report_abs(input, ABS_WHEEL, meas_array[0]->AmbientRateRtnMegaCps);\n+\tvl53lx_dbgmsg(\"ABS_WHEEL : AmbRate = %d\\n\", meas_array[0]->AmbientRateRtnMegaCps);\n+\n+\tinput_report_abs(input, ABS_TILT_X, (mmeas->HasXtalkValueChanged << 16) | (mmeas->StreamCount << 8) | ((mmeas->NumberOfObjectsFound & 0x3) << 6));\n+\tvl53lx_dbgmsg(\"ABS_TILT_X :(%d):(%d):(%d)\\n\\n\", mmeas->HasXtalkValueChanged, mmeas->StreamCount, mmeas->NumberOfObjectsFound);\n+\n+\tinput_report_abs(input, ABS_TILT_Y,   0);\n+\tinput_report_abs(input, ABS_TOOL_WIDTH, calibration_data.customer.algo__crosstalk_compensation_plane_offset_kcps);\n+\n+\tvl53lx_dbgmsg(\"ABS_TOOL_WIDTH Xtalk = %d\\n\", calibration_data.customer.algo__crosstalk_compensation_plane_offset_kcps);\n+\tinput_report_abs(input, ABS_BRAKE, mmeas->EffectiveSpadRtnCount << 16 | ((meas_array[1]->RangeStatus) << 8) | meas_array[0]->RangeStatus);\n+\tvl53lx_dbgmsg(\"ABS_BRAKE : (%d):(%d):(%d)\\n\", mmeas->EffectiveSpadRtnCount, meas_array[1]->RangeStatus, meas_array[0]->RangeStatus);\n+\tvl53lx_dbgmsg(\"ABS_BRAKE : 0x%X\\n\", (mmeas->EffectiveSpadRtnCount & 0xFFFF) << 16 | ((meas_array[1]->RangeStatus) << 8) | meas_array[0]->RangeStatus);\n+\n+\tif (mmeas->NumberOfObjectsFound == 0) {\n+\t\tinput_sync(input);\n+\t\treturn;\n+\t}\n+\n+\tinput_report_abs(input, ABS_HAT1X, meas_array[0]->RangeMilliMeter << 16 | (meas_array[0]->SigmaMilliMeter/65536));\n+\tvl53lx_dbgmsg(\"ABS_HAT1X : 0x%X(%d:%d)\\n\",\n+\t\t\tmeas_array[0]->RangeMilliMeter << 16\n+\t\t\t| (meas_array[0]->SigmaMilliMeter/65536),\n+\t\t\tmeas_array[0]->RangeMilliMeter,\n+\t\t\t(meas_array[0]->SigmaMilliMeter/65536));\n+\n+\tinput_report_abs(input, ABS_HAT1Y, meas_array[0]->RangeMinMilliMeter << 16 | meas_array[0]->RangeMaxMilliMeter);\n+\tvl53lx_dbgmsg(\"ABS_HAT1Y : 0x%X(%d:%d)\\n\",\n+\t\t\tmeas_array[0]->RangeMinMilliMeter << 16\n+\t\t\t| meas_array[0]->RangeMaxMilliMeter,\n+\t\t\tmeas_array[0]->RangeMinMilliMeter,\n+\t\t\tmeas_array[0]->RangeMaxMilliMeter);\n+\n+\tif (mmeas->NumberOfObjectsFound > 1) {\n+\t\tinput_report_abs(input, ABS_HAT2X, meas_array[1]->RangeMilliMeter << 16 | (meas_array[1]->SigmaMilliMeter/65536));\n+\t\tvl53lx_dbgmsg(\"ABS_HAT2X : 0x%x(%d:%d)\\n\",\n+\t\t\t\tmeas_array[1]->RangeMilliMeter << 16\n+\t\t\t\t| (meas_array[1]->SigmaMilliMeter/65536),\n+\t\t\t\tmeas_array[1]->RangeMilliMeter,\n+\t\t\t\t(meas_array[1]->SigmaMilliMeter/65536));\n+\n+\t\tinput_report_abs(input, ABS_HAT2Y, meas_array[1]->RangeMinMilliMeter << 16 | meas_array[1]->RangeMaxMilliMeter);\n+\t\tvl53lx_dbgmsg(\"ABS_HAT1Y : 0x%X(%d:%d)\\n\",\n+\t\t\t\tmeas_array[1]->RangeMinMilliMeter << 16\n+\t\t\t\t| meas_array[1]->RangeMaxMilliMeter,\n+\t\t\t\tmeas_array[1]->RangeMinMilliMeter,\n+\t\t\t\tmeas_array[1]->RangeMaxMilliMeter);\n+\t}\n+\tinput_report_abs(input, ABS_HAT3X, meas_array[0]->SignalRateRtnMegaCps);\n+\tvl53lx_dbgmsg(\"ABS_HAT3X : SignalRateRtnMegaCps_0(%d)\\n\", meas_array[0]->SignalRateRtnMegaCps);\n+\tif (mmeas->NumberOfObjectsFound > 1) {\n+\t\tinput_report_abs(input, ABS_HAT3Y, meas_array[1]->SignalRateRtnMegaCps);\n+\t\tvl53lx_dbgmsg(\"ABS_HAT3Y : SignalRateRtnMegaCps_1(%d)\\n\", meas_array[1]->SignalRateRtnMegaCps);\n+\t}\n+\tinput_report_abs(input, ABS_MISC, 0);\n+\tinput_sync(input);\n+}\n+\n+static void stmvl53lx_input_push_data(struct stmvl53lx_data *data)\n+{\n+\tstmvl53lx_input_push_data_multiobject(data);\n+}\n+\n+static void stmvl53lx_on_newdata_event(struct stmvl53lx_data *data)\n+{\n+\tint rc = 0;\n+\tVL53LX_MultiRangingData_t *pmrange;\n+\tVL53LX_MultiRangingData_t *tmprange;\n+\tVL53LX_TargetRangeData_t RangeData[VL53LX_MAX_RANGE_RESULTS];\n+\tlong ts_msec;\n+\tint i;\n+\tstruct input_dev *input = data->input_dev_ps;\n+\n+\tst_gettimeofday(&data->meas.comp_tv);\n+\tts_msec = stmvl53lx_tv_dif(&data->start_tv, &data->meas.comp_tv)/1000;\n+\n+\tpmrange = &data->meas.multi_range_data;\n+\ttmprange = &data->meas.tmp_range_data;\n+\n+\tfor (i = 0; i < VL53LX_MAX_RANGE_RESULTS; i++)\n+\t\tmemcpy(&RangeData[i], &pmrange->RangeData[i], sizeof(VL53LX_TargetRangeData_t));\n+\n+\tdata->meas.intr++;\n+\n+\trc = VL53LX_GetMultiRangingData(&data->stdev, &data->meas.tmp_range_data);\n+\n+\tif (tmprange->NumberOfObjectsFound == 0)\n+\t\ttmprange->RangeData[0].RangeStatus = VL53LX_RANGESTATUS_NONE;\n+\n+\tmemcpy(pmrange, tmprange, sizeof(VL53LX_MultiRangingData_t));\n+\n+\tif (!rc)\n+\t\trc = VL53LX_GetAdditionalData(&data->stdev, &data->meas.additional_data);\n+\tdetect_xtalk_value_change(data, pmrange);\n+\n+\tif (data->enable_sensor == 0) {\n+\t\tvl53lx_dbgmsg(\"at meas #%d we got stopped\\n\", data->meas.cnt);\n+\t\treturn;\n+\t}\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"VL53LX_GetRangingMeasurementData @%d %d\", __LINE__, rc);\n+\t\tdata->meas.err_cnt++;\n+\t\tdata->meas.err_tot++;\n+\t\tif (data->meas.err_cnt > stvm531_get_max_meas_err(data) ||\n+\t\t\tdata->meas.err_tot > stvm531_get_max_stream_err(data)) {\n+\t\t\tvl53lx_errmsg(\"on #%d %d err %d tot stop\", data->meas.cnt, data->meas.err_cnt, data->meas.err_tot);\n+\t\t\t_ctrl_stop(data);\n+\t\t\tinput_report_abs(input, ABS_MISC, ABNORMAL_STOP_3);\n+\t\t\tinput_sync(input);\n+\t\t}\n+\t\treturn;\n+\t}\n+\n+\tpmrange->TimeStamp = ts_msec;\n+\tfor (i = 1; i < pmrange->NumberOfObjectsFound; i++)\n+\t\tpmrange->TimeStamp = ts_msec;\n+\n+\tdata->meas.cnt++;\n+\tvl53lx_dbgmsg(\"#%3d %2d poll ts %5d status=%d obj cnt=%d\\n\",\n+\t\tdata->meas.cnt,\n+\t\tdata->meas.poll_cnt,\n+\t\tpmrange->TimeStamp,\n+\t\tpmrange->RangeData[0].RangeStatus,\n+\t\tpmrange->NumberOfObjectsFound);\n+\n+\tdata->is_data_valid = true;\n+\n+\twake_up_data_waiters(data);\n+\n+\tstmvl53lx_input_push_data(data);\n+\tstmvl53lx_insert_flush_events_lock(data);\n+\n+\tdata->meas.start_tv = data->meas.comp_tv;\n+\tdata->meas.poll_cnt = 0;\n+\tdata->meas.err_cnt = 0;\n+}\n+\n+VL53LX_Error VL53LX_clear_interrupt_and_enable_next_range(VL53LX_DEV Dev, uint8_t measurement_mode)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_init_and_start_range(Dev, measurement_mode, VL53LX_DEVICECONFIGLEVEL_GENERAL_ONWARDS);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_ClearInterruptAndStartMeasurement(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tuint8_t DeviceMeasurementMode;\n+\n+\tDeviceMeasurementMode = VL53LXDevDataGet(Dev, LLData.measurement_mode);\n+\n+\tStatus = VL53LX_clear_interrupt_and_enable_next_range(Dev, DeviceMeasurementMode);\n+\treturn Status;\n+}\n+\n+static int stmvl53lx_intr_process(struct stmvl53lx_data *data)\n+{\n+\tuint8_t data_rdy;\n+\tint rc = 0;\n+\tstruct st_timeval tv_now;\n+\tstruct input_dev *input = data->input_dev_ps;\n+\n+\tif (!data->enable_sensor)\n+\t\tgoto done;\n+\n+\tdata->meas.poll_cnt++;\n+\trc = VL53LX_GetMeasurementDataReady(&data->stdev, &data_rdy);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"GetMeasurementDataReady @%d %d, fail\\n\", __LINE__, rc);\n+\t\tgoto stop_io;\n+\t}\n+\n+\tif (!data_rdy) {\n+\t\tlong poll_us;\n+\n+\t\tst_gettimeofday(&tv_now);\n+\t\tpoll_us = stmvl53lx_tv_dif(&data->meas.start_tv, &tv_now);\n+\t\tif (poll_us > data->timing_budget*4) {\n+\t\t\tvl53lx_errmsg(\"we're polling %ld ms too long\\n\", poll_us/1000);\n+\t\t\tgoto stop_io;\n+\t\t}\n+\t\twork_dbg(\"intr with no data rdy\");\n+\t\tgoto done;\n+\t}\n+\n+\tif (data->is_first_irq)\n+\t\tdata->is_first_irq = false;\n+\telse\n+\t\tstmvl53lx_on_newdata_event(data);\n+\n+\tif (data->enable_sensor) {\n+\t\twork_dbg(\"intr clr\");\n+\t\tdata->is_delay_allowed = data->allow_hidden_start_stop;\n+\t\trc = VL53LX_ClearInterruptAndStartMeasurement(&data->stdev);\n+\t\tdata->is_delay_allowed = 0;\n+\t\tif (rc) {\n+\t\t\tvl53lx_errmsg(\"Cltr intr restart fail %d\\n\", rc);\n+\t\t\tgoto stop_io;\n+\t\t}\n+\t}\n+done:\n+\treturn rc;\n+stop_io:\n+\tvl53lx_errmsg(\"GetDatardy fail stop\\n\");\n+\t_ctrl_stop(data);\n+\tinput_report_abs(input, ABS_MISC, ABNORMAL_STOP_1);\n+\tinput_sync(input);\n+\treturn rc;\n+}\n+\n+int stmvl53lx_intr_handler(struct stmvl53lx_data *data)\n+{\n+\tint rc = 0;\n+\n+\tmutex_lock(&data->work_mutex);\n+\tif (data->enable_sensor) {\n+\t\trc = stmvl53lx_intr_process(data);\n+\t} else {\n+\t\tvl53lx_dbgmsg(\"got intr but not on (dummy or calibration)\\n\");\n+\t\trc = 0;\n+\t}\n+\n+\tmutex_unlock(&data->work_mutex);\n+\treturn rc;\n+}\n+\n+static irqreturn_t stmvl53lx_irq_handler_i2c(int vec, void *info)\n+{\n+\tstruct i2c_data *i2c_data = (struct i2c_data *)info;\n+\n+\tif (i2c_data->irq == vec) {\n+\t\tmodi2c_dbg(\"irq\");\n+\t\tstmvl53lx_intr_handler(i2c_data->vl53lx_data);\n+\t\tmodi2c_dbg(\"over\");\n+\t} else {\n+\t\tif (!i2c_data->msg_flag.unhandled_irq_vec) {\n+\t\t\tmodi2c_warn(\"unmatching vec %d != %d\\n\", vec, i2c_data->irq);\n+\t\t\ti2c_data->msg_flag.unhandled_irq_vec = 1;\n+\t\t}\n+\t}\n+\treturn IRQ_HANDLED;\n+}\n+\n+static void memory_release(struct kref *kref)\n+{\n+\tstruct i2c_data *data = container_of(kref, struct i2c_data, ref);\n+\n+\tvl53lx_dbgmsg(\"Enter\\n\");\n+\tkfree(data->vl53lx_data);\n+\tkfree(data);\n+\tvl53lx_dbgmsg(\"End\\n\");\n+}\n+\n+static int reset_release(struct stmvl53lx_data *data)\n+{\n+\tint rc = 0;\n+\n+\tif (!data->reset_state)\n+\t\treturn 0;\n+\n+\trc = stmvl53lx_module_func_tbl.reset_release(data->client_object);\n+\tif (rc)\n+\t\tvl53lx_errmsg(\"reset release fail rc=%d\\n\", rc);\n+\telse\n+\t\tdata->reset_state = 0;\n+\n+\treturn rc;\n+}\n+\n+static int stmvl53lx_start(struct stmvl53lx_data *data)\n+{\n+\tint rc = 0;\n+\n+\tdata->is_first_irq = true;\n+\tdata->is_data_valid = false;\n+\tdata->is_xtalk_value_changed = false;\n+\n+\trc = reset_release(data);\n+\tif (rc)\n+\t\tgoto done;\n+\n+\trc = stmvl53lx_sendparams(data);\n+\tif (rc)\n+\t\tgoto done;\n+\n+\tst_gettimeofday(&data->start_tv);\n+\tdata->meas.start_tv = data->start_tv;\n+\tkill_mz_data(&data->meas.multi_range_data);\n+\n+\tdata->allow_hidden_start_stop = false;\n+\n+\trc = VL53LX_StartMeasurement(&data->stdev);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"VL53LX_StartMeasurement @%d fail %d\", __LINE__, rc);\n+\t\trc = store_last_error(data, rc);\n+\t\tgoto done;\n+\t}\n+\n+\tdata->meas.cnt = 0;\n+\tdata->meas.err_cnt = 0;\n+\tdata->meas.err_tot = 0;\n+\tdata->meas.poll_cnt = 0;\n+\tdata->meas.intr = 0;\n+\tdata->enable_sensor = 1;\n+\tif (data->poll_mode) {\n+\t\tschedule_delayed_work(&data->dwork, msecs_to_jiffies(data->poll_delay_ms));\n+\t}\n+\n+done:\n+\tdata->is_first_start_done = true;\n+\treturn rc;\n+}\n+\n+static int ctrl_start(struct stmvl53lx_data *data)\n+{\n+\tint rc = 0;\n+\n+\tmutex_lock(&data->work_mutex);\n+\n+\tif (data->is_device_remove) {\n+\t\trc = -ENODEV;\n+\t\tgoto done;\n+\t}\n+\n+\tvl53lx_dbgmsg(\" state = %d\\n\", data->enable_sensor);\n+\tif (data->enable_sensor == 0 && !data->is_calibrating) {\n+\t\trc = stmvl53lx_start(data);\n+\t} else {\n+\t\trc = -EBUSY;\n+\t}\n+\tvl53lx_dbgmsg(\" final state = %d\\n\", data->enable_sensor);\n+done:\n+\tmutex_unlock(&data->work_mutex);\n+\treturn rc;\n+}\n+\n+static void stmvl53lx_insert_flush_events_lock(struct stmvl53lx_data *data)\n+{\n+\twhile (data->flush_todo_counter) {\n+\t\tdata->flushCount++;\n+\t\tinput_report_abs(data->input_dev_ps, ABS_GAS, data->flushCount);\n+\t\tinput_sync(data->input_dev_ps);\n+\t\tvl53lx_dbgmsg(\"Sensor HAL Flush Count = %u\\n\", data->flushCount);\n+\t\tdata->flush_todo_counter--;\n+\t}\n+}\n+\n+static int _ctrl_stop(struct stmvl53lx_data *data)\n+{\n+\tint rc = 0;\n+\n+\tvl53lx_dbgmsg(\"enter state = %d\\n\", data->enable_sensor);\n+\tdata->is_data_valid = true;\n+\tif (data->enable_sensor == 1) {\n+\t\trc = stmvl53lx_stop(data);\n+\t} else {\n+\t\tvl53lx_dbgmsg(\"already off did nothing\\n\");\n+\t\trc = 0;\n+\t}\n+\tstmvl53lx_insert_flush_events_lock(data);\n+\tvl53lx_dbgmsg(\"\tfinal state = %d\\n\", data->enable_sensor);\n+\n+\treturn rc;\n+}\n+\n+static int ctrl_stop(struct stmvl53lx_data *data)\n+{\n+\tint rc = 0;\n+\n+\tmutex_lock(&data->work_mutex);\n+\n+\tif (data->is_device_remove) {\n+\t\trc = -ENODEV;\n+\t\tgoto done;\n+\t}\n+\tif (data->enable_sensor)\n+\t\trc = _ctrl_stop(data);\n+\telse\n+\t\trc = -EBUSY;\n+done:\n+\tmutex_unlock(&data->work_mutex);\n+\treturn rc;\n+}\n+\n+static int ctrl_reg_access(struct stmvl53lx_data *data, void *p)\n+{\n+\tstruct stmvl53lx_register reg;\n+\tsize_t total_byte;\n+\tint rc = 0;\n+\n+\tif (data->is_device_remove)\n+\t\treturn -ENODEV;\n+\n+\ttotal_byte = offsetof(struct stmvl53lx_register, data.b);\n+\tif (copy_from_user(&reg, p, total_byte)) {\n+\t\tvl53lx_errmsg(\"%d, fail\\n\", __LINE__);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tif (reg.cnt > STMVL53LX_MAX_CCI_XFER_SZ) {\n+\t\tvl53lx_errmsg(\"reg len %d > size limit\\n\", reg.cnt);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\ttotal_byte = offsetof(struct stmvl53lx_register, data.bytes[reg.cnt]);\n+\tif (!reg.is_read) {\n+\t\tif (copy_from_user(&reg, p, total_byte)) {\n+\t\t\tvl53lx_errmsg(\" data cpy fail\\n\");\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\t}\n+\n+\tif (!reg.is_read) {\n+\t\trc = VL53LX_WriteMulti(&data->stdev, (uint16_t)reg.index, reg.data.bytes, reg.cnt);\n+\t\treg.status = rc;\n+\t\ttotal_byte = offsetof(struct stmvl53lx_register, data.b);\n+\t\tvl53lx_dbgmsg(\"wr %x %d bytes statu %d\\n\", reg.index, reg.cnt, rc);\n+\t\tif (rc)\n+\t\t\trc = store_last_error(data, rc);\n+\t} else {\n+\t\trc = VL53LX_ReadMulti(&data->stdev, (uint16_t)reg.index, reg.data.bytes, reg.cnt);\n+\t\treg.status = rc;\n+\t\tvl53lx_dbgmsg(\"rd %x %d bytes status %d\\n\", reg.index, reg.cnt, rc);\n+\t\tif (rc) {\n+\t\t\ttotal_byte = offsetof(struct stmvl53lx_register, data.b);\n+\t\t\trc = store_last_error(data, rc);\n+\t\t}\n+\t}\n+\n+\tif (copy_to_user(p, &reg, total_byte)) {\n+\t\tvl53lx_errmsg(\"%d, fail\\n\", __LINE__);\n+\t\treturn -EFAULT;\n+\t}\n+\treturn rc;\n+}\n+\n+static int reset_hold(struct stmvl53lx_data *data)\n+{\n+\tint rc = 0;\n+\n+\tif (data->reset_state)\n+\t\treturn 0;\n+\n+\tif (data->force_device_on_en)\n+\t\treturn 0;\n+\n+\trc = stmvl53lx_module_func_tbl.reset_hold(data->client_object);\n+\tif (!rc)\n+\t\tdata->reset_state = 1;\n+\n+\treturn rc;\n+}\n+\n+static ssize_t stmvl53lx_show_enable_ps_sensor(struct device *dev, struct device_attribute *attr, char *buf)\n+{\n+\tstruct stmvl53lx_data *data = dev_get_drvdata(dev);\n+\treturn snprintf(buf, 5, \"%d\\n\", data->enable_sensor);\n+}\n+\n+static ssize_t stmvl53lx_store_enable_ps_sensor(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)\n+{\n+\tint rc = 0;\n+\tunsigned long val;\n+\tstruct stmvl53lx_data *data = dev_get_drvdata(dev);\n+\n+\trc = kstrtoul(buf, 10, &val);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"enable sensor syntax in %s\\n\", buf);\n+\t\treturn -EINVAL;\n+\t}\n+\tif (val == 1) {\n+\t\trc = ctrl_start(data);\n+\t} else if (val == 0) {\n+\t\trc = ctrl_stop(data);\n+\t} else {\n+\t\tvl53lx_dbgmsg(\"Unclog Input sub-system\\n\");\n+\t\tinput_report_abs(data->input_dev_ps, ABS_HAT0X, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_HAT0Y, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_HAT1X, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_HAT1Y, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_HAT2X, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_HAT2Y, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_HAT3X, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_HAT3Y, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_WHEEL, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_BRAKE, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_GAS, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_TILT_X, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_TILT_Y, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_TOOL_WIDTH, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_DISTANCE, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_THROTTLE, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_RUDDER, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_MISC, -1);\n+\t\tinput_report_abs(data->input_dev_ps, ABS_VOLUME, -1);\n+\t\tinput_sync(data->input_dev_ps);\n+\t\tvl53lx_dbgmsg(\"Unclog the input sub-system\\n\");\n+\t\trc = 0;\n+\t}\n+\tvl53lx_dbgmsg(\"End\\n\");\n+\treturn rc ? rc : count;\n+}\n+\n+static DEVICE_ATTR(enable_ps_sensor, 0664, stmvl53lx_show_enable_ps_sensor, stmvl53lx_store_enable_ps_sensor);\n+\n+static int stmvl53lx_set_poll_delay_ms(struct stmvl53lx_data *data, int delay)\n+{\n+\tint rc = 0;\n+\n+\tif (delay <= 0)\n+\t\trc = -EINVAL;\n+\telse\n+\t\tdata->poll_delay_ms = delay;\n+\n+\treturn rc;\n+}\n+\n+IMPLEMENT_PARAMETER_INTEGER(poll_delay_ms, \"poll delay ms\")\n+\n+static DEVICE_ATTR(set_delay_ms, 0660, stmvl53lx_show_poll_delay_ms, stmvl53lx_store_poll_delay_ms);\n+\n+static int stmvl53lx_set_timing_budget(struct stmvl53lx_data *data, int timing)\n+{\n+\tint rc = 0;\n+\n+\tif (timing <= 0) {\n+\t\tvl53lx_errmsg(\"invalid timing valid %d\\n\", timing);\n+\t\trc = -EINVAL;\n+\t} else if (data->enable_sensor) {\n+\t\trc = VL53LX_SetMeasurementTimingBudgetMicroSeconds(&data->stdev,\n+\t\t\ttiming);\n+\t\tif (rc) {\n+\t\t\tvl53lx_errmsg(\"SetTimingBudget %d fail %d\", timing, rc);\n+\t\t\trc = store_last_error(data, rc);\n+\t\t} else\n+\t\t\tdata->timing_budget = timing;\n+\t} else\n+\t\tdata->timing_budget = timing;\n+\n+\treturn rc;\n+}\n+\n+IMPLEMENT_PARAMETER_INTEGER(timing_budget, \"timing budget\")\n+\n+static DEVICE_ATTR(timing_budget, 0660, stmvl53lx_show_timing_budget, stmvl53lx_store_timing_budget);\n+\n+static ssize_t stmvl53lx_show_roi(struct device *dev, struct device_attribute *attr, char *buf)\n+{\n+\tint n;\n+\tstruct stmvl53lx_data *data = dev_get_drvdata(dev);\n+\n+\tmutex_lock(&data->work_mutex);\n+\tn = scnprintf(buf, PAGE_SIZE, \"%d %d %d %d\\n\", data->roi_cfg.TopLeftX, data->roi_cfg.TopLeftY, data->roi_cfg.BotRightX, data->roi_cfg.BotRightY);\n+\tmutex_unlock(&data->work_mutex);\n+\treturn n;\n+}\n+\n+static ssize_t stmvl53lx_store_roi(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)\n+{\n+\tint rc;\n+\tint n;\n+\tint tlx, tly, brx, bry;\n+\tstruct stmvl53lx_data *data = dev_get_drvdata(dev);\n+\n+\tmutex_lock(&data->work_mutex);\n+\tif (data->enable_sensor) {\n+\t\tvl53lx_errmsg(\"ERROR can't set roi while ranging\");\n+\t\trc = -EBUSY;\n+\t} else {\n+\t\tn = sscanf(buf, \"%d %d %d %d\", &tlx, &tly, &brx, &bry);\n+\t\tif (n == 4) {\n+\t\t\tdata->roi_cfg.TopLeftX = tlx;\n+\t\t\tdata->roi_cfg.TopLeftY = tly;\n+\t\t\tdata->roi_cfg.BotRightX = brx;\n+\t\t\tdata->roi_cfg.BotRightY = bry;\n+\t\t\trc = count;\n+\t\t\tvl53lx_dbgmsg(\"ROI %2d %2d %2d %2d\\n\", (int)data->roi_cfg.TopLeftX, (int)data->roi_cfg.TopLeftY, (int)data->roi_cfg.BotRightX, (int)data->roi_cfg.BotRightY);\n+\t\t} else {\n+\t\t\tvl53lx_errmsg(\"wrong roi syntax %s \", buf);\n+\t\t\trc = -EINVAL;\n+\t\t}\n+\t}\n+\tmutex_unlock(&data->work_mutex);\n+\tvl53lx_dbgmsg(\"ret %d count %d\\n\", rc, (int)count);\n+\n+\treturn rc;\n+}\n+\n+static DEVICE_ATTR(roi, 0660, stmvl53lx_show_roi, stmvl53lx_store_roi);\n+\n+static int stmvl53lx_set_distance_mode(struct stmvl53lx_data *data,\n+\tint distance_mode)\n+{\n+\tint rc = 0;\n+\n+\tif (data->enable_sensor) {\n+\t\tvl53lx_errmsg(\"can't change distance mode while ranging\\n\");\n+\t\trc = -EBUSY;\n+\t} else {\n+\t\tswitch (distance_mode) {\n+\t\tcase VL53LX_DISTANCEMODE_SHORT:\n+\t\tcase VL53LX_DISTANCEMODE_MEDIUM:\n+\t\tcase VL53LX_DISTANCEMODE_LONG:\n+\t\t\tdata->distance_mode = distance_mode;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tvl53lx_errmsg(\"invalid distance mode %d\\n\",\n+\t\t\t\tdistance_mode);\n+\t\t\trc = -EINVAL;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn rc;\n+}\n+\n+IMPLEMENT_PARAMETER_INTEGER(distance_mode, \"distance mode\")\n+\n+static DEVICE_ATTR(distance_mode, 0660, stmvl53lx_show_distance_mode, stmvl53lx_store_distance_mode);\n+\n+static int stmvl53lx_set_crosstalk_enable(struct stmvl53lx_data *data,\n+\tint crosstalk_enable)\n+{\n+\tint rc = 0;\n+\n+\tif (data->enable_sensor) {\n+\t\tvl53lx_errmsg(\"can't change crosstalk enable while ranging\\n\");\n+\t\trc = -EBUSY;\n+\t} else if (crosstalk_enable == 0 || crosstalk_enable == 1) {\n+\t\tdata->crosstalk_enable = crosstalk_enable;\n+\t} else {\n+\t\tvl53lx_errmsg(\"invalid crosstalk enable %d\\n\",\n+\t\t\tcrosstalk_enable);\n+\t\trc = -EINVAL;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+IMPLEMENT_PARAMETER_INTEGER(crosstalk_enable, \"crosstalk enable\")\n+\n+static DEVICE_ATTR(crosstalk_enable, 0660, stmvl53lx_show_crosstalk_enable, stmvl53lx_store_crosstalk_enable);\n+\n+static int stmvl53lx_set_force_device_on_en(struct stmvl53lx_data *data,\n+\tint force_device_on_en)\n+{\n+\tint rc = 0;\n+\n+\tif (force_device_on_en != 0 && force_device_on_en != 1) {\n+\t\tvl53lx_errmsg(\"invalid force_device_on_en mode %d\\n\",\n+\t\t\tforce_device_on_en);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tdata->force_device_on_en = force_device_on_en;\n+\n+\t/* don't update reset if sensor is enable */\n+\tif (data->enable_sensor)\n+\t\treturn 0;\n+\n+\t/* ok update reset according force_device_on_en value */\n+\tif (force_device_on_en)\n+\t\trc = reset_release(data);\n+\telse\n+\t\trc = reset_hold(data);\n+\n+\treturn rc;\n+}\n+\n+IMPLEMENT_PARAMETER_INTEGER(force_device_on_en, \"force device on enable\")\n+\n+\n+static DEVICE_ATTR(force_device_on_enable, 0660, stmvl53lx_show_force_device_on_en, stmvl53lx_store_force_device_on_en);\n+\n+static int stmvl53lx_set_offset_correction_mode(struct stmvl53lx_data *data,\n+\tint offset_correction_mode)\n+{\n+\tint rc = 0;\n+\n+\tif (data->enable_sensor) {\n+\t\tvl53lx_errmsg(\n+\t\t\t\"can't change offset correction mode while ranging\\n\");\n+\t\trc = -EBUSY;\n+\t} else {\n+\t\tswitch (offset_correction_mode) {\n+\t\tcase VL53LX_OFFSETCORRECTIONMODE_STANDARD:\n+\t\tcase VL53LX_OFFSETCORRECTIONMODE_PERVCSEL:\n+\t\t\tdata->offset_correction_mode = offset_correction_mode;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tvl53lx_errmsg(\"invalid offset correction mode %d\\n\",\n+\t\t\t\toffset_correction_mode);\n+\t\t\trc = -EINVAL;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn rc;\n+}\n+\n+IMPLEMENT_PARAMETER_INTEGER(offset_correction_mode, \"offset correction mode\")\n+\n+static DEVICE_ATTR(offset_correction_mode, 0660, stmvl53lx_show_offset_correction_mode, stmvl53lx_store_offset_correction_mode);\n+\n+static ssize_t stmvl53lx_do_flush(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)\n+{\n+\tstruct stmvl53lx_data *data = dev_get_drvdata(dev);\n+\n+\tmutex_lock(&data->work_mutex);\n+\n+\tdata->flush_todo_counter++;\n+\tif (data->enable_sensor == 0)\n+\t\tstmvl53lx_insert_flush_events_lock(data);\n+\n+\tmutex_unlock(&data->work_mutex);\n+\n+\treturn count;\n+}\n+\n+static DEVICE_ATTR(do_flush, 0660, NULL, stmvl53lx_do_flush);\n+\n+static ssize_t stmvl53lx_show_enable_debug(struct device *dev, struct device_attribute *attr, char *buf)\n+{\n+\treturn scnprintf(buf, PAGE_SIZE, \"%d\\n\", stmvl53lx_enable_debug);\n+}\n+\n+static ssize_t stmvl53lx_store_enable_debug(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)\n+{\n+\tint enable_debug;\n+\tint rc = 0;\n+\n+\tif (kstrtoint(buf, 0, &enable_debug)) {\n+\t\tvl53lx_errmsg(\"invalid syntax in %s\", buf);\n+\t\trc = -EINVAL;\n+\t} else\n+\t\tstmvl53lx_enable_debug = enable_debug;\n+\n+\treturn rc ? rc : count;\n+}\n+\n+static DEVICE_ATTR(enable_debug, 0660, stmvl53lx_show_enable_debug, stmvl53lx_store_enable_debug);\n+\n+static ssize_t stmvl53lx_show_last_error_config(struct device *dev, struct device_attribute *attr, char *buf)\n+{\n+\tstruct stmvl53lx_data *data = dev_get_drvdata(dev);\n+\treturn scnprintf(buf, PAGE_SIZE, \"%d\\n\", data->last_error);\n+}\n+\n+static DEVICE_ATTR(last_error, 0440, stmvl53lx_show_last_error_config, NULL);\n+\n+static ssize_t display_FixPoint1616(char *buf, size_t size, FixPoint1616_t fix)\n+{\n+\tuint32_t msb = fix >> 16;\n+\tuint32_t lsb = fix & 0xffff;\n+\n+\tlsb = (lsb * 1000000ULL + 32768) / 65536;\n+\n+\treturn scnprintf(buf, size, \"%d.%06d\", msb, (uint32_t) lsb);\n+}\n+\n+static ssize_t stmvl53lx_show_optical_center_config(struct device *dev, struct device_attribute *attr, char *buf)\n+{\n+\tstruct stmvl53lx_data *data = dev_get_drvdata(dev);\n+\tssize_t res = 0;\n+\n+\tres += display_FixPoint1616(&buf[res], PAGE_SIZE - res, data->optical_offset_x);\n+\tres += scnprintf(&buf[res], PAGE_SIZE - res, \" \");\n+\tres += display_FixPoint1616(&buf[res], PAGE_SIZE - res, data->optical_offset_y);\n+\tres += scnprintf(&buf[res], PAGE_SIZE - res, \"\\n\");\n+\treturn res;\n+}\n+\n+static DEVICE_ATTR(optical_center, 0440, stmvl53lx_show_optical_center_config, NULL);\n+\n+VL53LX_Error VL53LX_set_tuning_parm(VL53LX_DEV Dev, VL53LX_TuningParms tuning_parm_key, int32_t tuning_parm_value)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_hist_post_process_config_t *pHP = &(pdev->histpostprocess);\n+\tVL53LX_xtalkextract_config_t *pXC = &(pdev->xtalk_extract_cfg);\n+\n+\tswitch (tuning_parm_key) {\n+\tcase VL53LX_TUNINGPARM_VERSION:\n+\t\tpdev->tuning_parms.tp_tuning_parm_version = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_KEY_TABLE_VERSION:\n+\t\tpdev->tuning_parms.tp_tuning_parm_key_table_version = (uint16_t)tuning_parm_value;\n+\t\tif ((uint16_t)tuning_parm_value != VL53LX_TUNINGPARM_KEY_TABLE_VERSION_DEFAULT)\n+\t\t\tstatus = VL53LX_ERROR_TUNING_PARM_KEY_MISMATCH;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LLD_VERSION:\n+\t\tpdev->tuning_parms.tp_tuning_parm_lld_version = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_ALGO_SELECT:\n+\t\tpHP->hist_algo_select = (VL53LX_HistAlgoSelect)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_TARGET_ORDER:\n+\t\tpHP->hist_target_order = (VL53LX_HistTargetOrder)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_FILTER_WOI_0:\n+\t\tpHP->filter_woi0 = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_FILTER_WOI_1:\n+\t\tpHP->filter_woi1 = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_AMB_EST_METHOD:\n+\t\tpHP->hist_amb_est_method = (VL53LX_HistAmbEstMethod)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_0:\n+\t\tpHP->ambient_thresh_sigma0 = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_1:\n+\t\tpHP->ambient_thresh_sigma1 = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_MIN_AMB_THRESH_EVENTS:\n+\t\tpHP->min_ambient_thresh_events = (int32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_AMB_EVENTS_SCALER:\n+\t\tpHP->ambient_thresh_events_scaler = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_NOISE_THRESHOLD:\n+\t\tpHP->noise_threshold = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_SIGNAL_TOTAL_EVENTS_LIMIT:\n+\t\tpHP->signal_total_events_limit = (int32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_SIGMA_EST_REF_MM:\n+\t\tpHP->sigma_estimator__sigma_ref_mm = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_SIGMA_THRESH_MM:\n+\t\tpHP->sigma_thresh = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_GAIN_FACTOR:\n+\t\tpdev->gain_cal.histogram_ranging_gain_factor = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_CONSISTENCY_HIST_PHASE_TOLERANCE:\n+\t\tpHP->algo__consistency_check__phase_tolerance = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_CONSISTENCY_HIST_MIN_MAX_TOLERANCE_MM:\n+\t\tpHP->algo__consistency_check__min_max_tolerance = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA:\n+\t\tpHP->algo__consistency_check__event_sigma = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA_MIN_SPAD_LIMIT:\n+\t\tpHP->algo__consistency_check__event_min_spad_count = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_LONG_RANGE:\n+\t\tpdev->tuning_parms.tp_init_phase_rtn_hist_long = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_MED_RANGE:\n+\t\tpdev->tuning_parms.tp_init_phase_rtn_hist_med = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_SHORT_RANGE:\n+\t\tpdev->tuning_parms.tp_init_phase_rtn_hist_short = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_LONG_RANGE:\n+\t\tpdev->tuning_parms.tp_init_phase_ref_hist_long = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_MED_RANGE:\n+\t\tpdev->tuning_parms.tp_init_phase_ref_hist_med = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_SHORT_RANGE:\n+\t\tpdev->tuning_parms.tp_init_phase_ref_hist_short = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_DETECT_MIN_VALID_RANGE_MM:\n+\t\tpdev->xtalk_cfg.algo__crosstalk_detect_min_valid_range_mm = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RANGE_MM:\n+\t\tpdev->xtalk_cfg.algo__crosstalk_detect_max_valid_range_mm = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_DETECT_MAX_SIGMA_MM:\n+\t\tpdev->xtalk_cfg.algo__crosstalk_detect_max_sigma_mm = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_DETECT_MIN_MAX_TOLERANCE:\n+\t\tpHP->algo__crosstalk_detect_min_max_tolerance = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RATE_KCPS:\n+\t\tpdev->xtalk_cfg.algo__crosstalk_detect_max_valid_rate_kcps = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_DETECT_EVENT_SIGMA:\n+\t\tpHP->algo__crosstalk_detect_event_sigma = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_XTALK_MARGIN_KCPS:\n+\t\tpdev->xtalk_cfg.histogram_mode_crosstalk_margin_kcps = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_CONSISTENCY_LITE_PHASE_TOLERANCE:\n+\t\tpdev->tuning_parms.tp_consistency_lite_phase_tolerance = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_PHASECAL_TARGET:\n+\t\tpdev->tuning_parms.tp_phasecal_target = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_CAL_REPEAT_RATE:\n+\t\tpdev->tuning_parms.tp_cal_repeat_rate = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_RANGING_GAIN_FACTOR:\n+\t\tpdev->gain_cal.standard_ranging_gain_factor = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_MIN_CLIP_MM:\n+\t\tpdev->tuning_parms.tp_lite_min_clip = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_LONG_SIGMA_THRESH_MM:\n+\t\tpdev->tuning_parms.tp_lite_long_sigma_thresh_mm = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_MED_SIGMA_THRESH_MM:\n+\t\tpdev->tuning_parms.tp_lite_med_sigma_thresh_mm = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_SHORT_SIGMA_THRESH_MM:\n+\t\tpdev->tuning_parms.tp_lite_short_sigma_thresh_mm = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_LONG_MIN_COUNT_RATE_RTN_MCPS:\n+\t\tpdev->tuning_parms.tp_lite_long_min_count_rate_rtn_mcps = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_MED_MIN_COUNT_RATE_RTN_MCPS:\n+\t\tpdev->tuning_parms.tp_lite_med_min_count_rate_rtn_mcps = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_SHORT_MIN_COUNT_RATE_RTN_MCPS:\n+\t\tpdev->tuning_parms.tp_lite_short_min_count_rate_rtn_mcps = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_SIGMA_EST_PULSE_WIDTH:\n+\t\tpdev->tuning_parms.tp_lite_sigma_est_pulse_width_ns = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_SIGMA_EST_AMB_WIDTH_NS:\n+\t\tpdev->tuning_parms.tp_lite_sigma_est_amb_width_ns = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_SIGMA_REF_MM:\n+\t\tpdev->tuning_parms.tp_lite_sigma_ref_mm = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_RIT_MULT:\n+\t\tpdev->xtalk_cfg.crosstalk_range_ignore_threshold_mult = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_SEED_CONFIG:\n+\t\tpdev->tuning_parms.tp_lite_seed_cfg = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_QUANTIFIER:\n+\t\tpdev->tuning_parms.tp_lite_quantifier = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_FIRST_ORDER_SELECT:\n+\t\tpdev->tuning_parms.tp_lite_first_order_select = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_XTALK_MARGIN_KCPS:\n+\t\tpdev->xtalk_cfg.lite_mode_crosstalk_margin_kcps = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_LONG_RANGE:\n+\t\tpdev->tuning_parms.tp_init_phase_rtn_lite_long = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_MED_RANGE:\n+\t\tpdev->tuning_parms.tp_init_phase_rtn_lite_med = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_SHORT_RANGE:\n+\t\tpdev->tuning_parms.tp_init_phase_rtn_lite_short = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_LONG_RANGE:\n+\t\tpdev->tuning_parms.tp_init_phase_ref_lite_long = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_MED_RANGE:\n+\t\tpdev->tuning_parms.tp_init_phase_ref_lite_med = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_SHORT_RANGE:\n+\t\tpdev->tuning_parms.tp_init_phase_ref_lite_short = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_TIMED_SEED_CONFIG:\n+\t\tpdev->tuning_parms.tp_timed_seed_cfg = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DMAX_CFG_SIGNAL_THRESH_SIGMA:\n+\t\tpdev->dmax_cfg.signal_thresh_sigma = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_0:\n+\t\tpdev->dmax_cfg.target_reflectance_for_dmax_calc[0] = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_1:\n+\t\tpdev->dmax_cfg.target_reflectance_for_dmax_calc[1] = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_2:\n+\t\tpdev->dmax_cfg.target_reflectance_for_dmax_calc[2] = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_3:\n+\t\tpdev->dmax_cfg.target_reflectance_for_dmax_calc[3] = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_4:\n+\t\tpdev->dmax_cfg.target_reflectance_for_dmax_calc[4] = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_VHV_LOOPBOUND:\n+\t\tpdev->stat_nvm.vhv_config__timeout_macrop_loop_bound = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_REFSPADCHAR_DEVICE_TEST_MODE:\n+\t\tpdev->refspadchar.device_test_mode = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_REFSPADCHAR_VCSEL_PERIOD:\n+\t\tpdev->refspadchar.VL53LX_p_005 = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_REFSPADCHAR_PHASECAL_TIMEOUT_US:\n+\t\tpdev->refspadchar.timeout_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_REFSPADCHAR_TARGET_COUNT_RATE_MCPS:\n+\t\tpdev->refspadchar.target_count_rate_mcps = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_REFSPADCHAR_MIN_COUNTRATE_LIMIT_MCPS:\n+\t\tpdev->refspadchar.min_count_rate_limit_mcps = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_REFSPADCHAR_MAX_COUNTRATE_LIMIT_MCPS:\n+\t\tpdev->refspadchar.max_count_rate_limit_mcps = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_NUM_OF_SAMPLES:\n+\t\tpXC->num_of_samples = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_MIN_FILTER_THRESH_MM:\n+\t\tpXC->algo__crosstalk_extract_min_valid_range_mm = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_FILTER_THRESH_MM:\n+\t\tpXC->algo__crosstalk_extract_max_valid_range_mm = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_RATE_MCPS:\n+\t\tpXC->dss_config__target_total_rate_mcps = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_PHASECAL_TIMEOUT_US:\n+\t\tpXC->phasecal_config_timeout_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_VALID_RATE_KCPS:\n+\t\t pXC->algo__crosstalk_extract_max_valid_rate_kcps = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_SIGMA_THRESHOLD_MM:\n+\t\tpXC->algo__crosstalk_extract_max_sigma_mm = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_TIMEOUT_US:\n+\t\tpXC->mm_config_timeout_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_XTALK_EXTRACT_BIN_TIMEOUT_US:\n+\t\tpXC->range_config_timeout_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_OFFSET_CAL_DSS_RATE_MCPS:\n+\t\tpdev->offsetcal_cfg.dss_config__target_total_rate_mcps = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_OFFSET_CAL_PHASECAL_TIMEOUT_US:\n+\t\tpdev->offsetcal_cfg.phasecal_config_timeout_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_OFFSET_CAL_MM_TIMEOUT_US:\n+\t\tpdev->offsetcal_cfg.mm_config_timeout_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_OFFSET_CAL_RANGE_TIMEOUT_US:\n+\t\tpdev->offsetcal_cfg.range_config_timeout_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_OFFSET_CAL_PRE_SAMPLES:\n+\t\tpdev->offsetcal_cfg.pre_num_of_samples = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_OFFSET_CAL_MM1_SAMPLES:\n+\t\tpdev->offsetcal_cfg.mm1_num_of_samples = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_OFFSET_CAL_MM2_SAMPLES:\n+\t\tpdev->offsetcal_cfg.mm2_num_of_samples = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_ZONE_CAL_DSS_RATE_MCPS:\n+\t\tpdev->zonecal_cfg.dss_config__target_total_rate_mcps = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_TIMEOUT_US:\n+\t\tpdev->zonecal_cfg.phasecal_config_timeout_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_ZONE_CAL_DSS_TIMEOUT_US:\n+\t\tpdev->zonecal_cfg.mm_config_timeout_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_NUM_SAMPLES:\n+\t\tpdev->zonecal_cfg.phasecal_num_of_samples = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_ZONE_CAL_RANGE_TIMEOUT_US:\n+\t\tpdev->zonecal_cfg.range_config_timeout_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_ZONE_CAL_ZONE_NUM_SAMPLES:\n+\t\tpdev->zonecal_cfg.zone_num_of_samples = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_SPADMAP_VCSEL_PERIOD:\n+\t\tpdev->ssc_cfg.VL53LX_p_005 = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_SPADMAP_VCSEL_START:\n+\t\tpdev->ssc_cfg.vcsel_start = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_SPADMAP_RATE_LIMIT_MCPS:\n+\t\tpdev->ssc_cfg.rate_limit_mcps = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS:\n+\t\tpdev->tuning_parms.tp_dss_target_lite_mcps = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_RANGING_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS:\n+\t\tpdev->tuning_parms.tp_dss_target_histo_mcps = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_MZ_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS:\n+\t\tpdev->tuning_parms.tp_dss_target_histo_mz_mcps = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_TIMED_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS:\n+\t\tpdev->tuning_parms.tp_dss_target_timed_mcps = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_PHASECAL_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_phasecal_timeout_lite_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_RANGING_LONG_PHASECAL_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_phasecal_timeout_hist_long_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_RANGING_MED_PHASECAL_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_phasecal_timeout_hist_med_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_RANGING_SHORT_PHASECAL_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_phasecal_timeout_hist_short_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_MZ_LONG_PHASECAL_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_phasecal_timeout_mz_long_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_MZ_MED_PHASECAL_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_phasecal_timeout_mz_med_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_MZ_SHORT_PHASECAL_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_phasecal_timeout_mz_short_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_TIMED_PHASECAL_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_phasecal_timeout_timed_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_MM_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_mm_timeout_lite_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_RANGING_MM_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_mm_timeout_histo_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_MZ_MM_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_mm_timeout_mz_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_TIMED_MM_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_mm_timeout_timed_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LITE_RANGE_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_range_timeout_lite_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_RANGING_RANGE_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_range_timeout_histo_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_MZ_RANGE_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_range_timeout_mz_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_TIMED_RANGE_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_range_timeout_timed_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_MARGIN:\n+\t\tpdev->smudge_correct_config.smudge_margin = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_NOISE_MARGIN:\n+\t\tpdev->smudge_correct_config.noise_margin = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT:\n+\t\tpdev->smudge_correct_config.user_xtalk_offset_limit = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT_HI:\n+\t\tpdev->smudge_correct_config.user_xtalk_offset_limit_hi = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_SAMPLE_LIMIT:\n+\t\tpdev->smudge_correct_config.sample_limit = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_SINGLE_XTALK_DELTA:\n+\t\tpdev->smudge_correct_config.single_xtalk_delta = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_AVERAGED_XTALK_DELTA:\n+\t\tpdev->smudge_correct_config.averaged_xtalk_delta = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_CLIP_LIMIT:\n+\t\tpdev->smudge_correct_config.smudge_corr_clip_limit = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_SCALER_CALC_METHOD:\n+\t\tpdev->smudge_correct_config.scaler_calc_method = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_XGRADIENT_SCALER:\n+\t\tpdev->smudge_correct_config.x_gradient_scaler = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_YGRADIENT_SCALER:\n+\t\tpdev->smudge_correct_config.y_gradient_scaler = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_USER_SCALER_SET:\n+\t\tpdev->smudge_correct_config.user_scaler_set = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_COR_SINGLE_APPLY:\n+\t\tpdev->smudge_correct_config.smudge_corr_single_apply = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_XTALK_AMB_THRESHOLD:\n+\t\tpdev->smudge_correct_config.smudge_corr_ambient_threshold = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_NODETECT_AMB_THRESHOLD_KCPS:\n+\t\tpdev->smudge_correct_config.nodetect_ambient_threshold = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_NODETECT_SAMPLE_LIMIT:\n+\t\tpdev->smudge_correct_config.nodetect_sample_limit = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_NODETECT_XTALK_OFFSET_KCPS:\n+\t\tpdev->smudge_correct_config.nodetect_xtalk_offset = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_NODETECT_MIN_RANGE_MM:\n+\t\tpdev->smudge_correct_config.nodetect_min_range_mm = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LOWPOWERAUTO_VHV_LOOP_BOUND:\n+\t\tpdev->low_power_auto_data.vhv_loop_bound = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LOWPOWERAUTO_MM_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_mm_timeout_lpa_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_LOWPOWERAUTO_RANGE_CONFIG_TIMEOUT_US:\n+\t\tpdev->tuning_parms.tp_range_timeout_lpa_us = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_VERY_SHORT_DSS_RATE_MCPS:\n+\t\tpdev->tuning_parms.tp_dss_target_very_short_mcps = (uint16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_PHASECAL_PATCH_POWER:\n+\t\tpdev->tuning_parms.tp_phasecal_patch_power = (uint16_t) tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_MERGE:\n+\t\tpdev->tuning_parms.tp_hist_merge = (uint16_t) tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_RESET_MERGE_THRESHOLD:\n+\t\tpdev->tuning_parms.tp_reset_merge_threshold = (uint16_t) tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_HIST_MERGE_MAX_SIZE:\n+\t\tpdev->tuning_parms.tp_hist_merge_max_size = (uint16_t) tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_DYNXTALK_MAX_SMUDGE_FACTOR:\n+\t\tpdev->smudge_correct_config.max_smudge_factor = (uint32_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_ENABLE:\n+\t\tpdev->tuning_parms.tp_uwr_enable = (uint8_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_1_MIN:\n+\t\tpdev->tuning_parms.tp_uwr_med_z_1_min = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_1_MAX:\n+\t\tpdev->tuning_parms.tp_uwr_med_z_1_max = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_2_MIN:\n+\t\tpdev->tuning_parms.tp_uwr_med_z_2_min = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_2_MAX:\n+\t\tpdev->tuning_parms.tp_uwr_med_z_2_max = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_3_MIN:\n+\t\tpdev->tuning_parms.tp_uwr_med_z_3_min = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_3_MAX:\n+\t\tpdev->tuning_parms.tp_uwr_med_z_3_max = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_4_MIN:\n+\t\tpdev->tuning_parms.tp_uwr_med_z_4_min = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_4_MAX:\n+\t\tpdev->tuning_parms.tp_uwr_med_z_4_max = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_5_MIN:\n+\t\tpdev->tuning_parms.tp_uwr_med_z_5_min = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_5_MAX:\n+\t\tpdev->tuning_parms.tp_uwr_med_z_5_max = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_1_RANGEA:\n+\t\tpdev->tuning_parms.tp_uwr_med_corr_z_1_rangea = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_1_RANGEB:\n+\t\tpdev->tuning_parms.tp_uwr_med_corr_z_1_rangeb = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_2_RANGEA:\n+\t\tpdev->tuning_parms.tp_uwr_med_corr_z_2_rangea = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_2_RANGEB:\n+\t\tpdev->tuning_parms.tp_uwr_med_corr_z_2_rangeb = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_3_RANGEA:\n+\t\tpdev->tuning_parms.tp_uwr_med_corr_z_3_rangea = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_3_RANGEB:\n+\t\tpdev->tuning_parms.tp_uwr_med_corr_z_3_rangeb = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_4_RANGEA:\n+\t\tpdev->tuning_parms.tp_uwr_med_corr_z_4_rangea = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_4_RANGEB:\n+\t\tpdev->tuning_parms.tp_uwr_med_corr_z_4_rangeb = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_5_RANGEA:\n+\t\tpdev->tuning_parms.tp_uwr_med_corr_z_5_rangea = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_5_RANGEB:\n+\t\tpdev->tuning_parms.tp_uwr_med_corr_z_5_rangeb = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_1_MIN:\n+\t\tpdev->tuning_parms.tp_uwr_lng_z_1_min = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_1_MAX:\n+\t\tpdev->tuning_parms.tp_uwr_lng_z_1_max = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_2_MIN:\n+\t\tpdev->tuning_parms.tp_uwr_lng_z_2_min = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_2_MAX:\n+\t\tpdev->tuning_parms.tp_uwr_lng_z_2_max = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_3_MIN:\n+\t\tpdev->tuning_parms.tp_uwr_lng_z_3_min = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_3_MAX:\n+\t\tpdev->tuning_parms.tp_uwr_lng_z_3_max = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_4_MIN:\n+\t\tpdev->tuning_parms.tp_uwr_lng_z_4_min = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_4_MAX:\n+\t\tpdev->tuning_parms.tp_uwr_lng_z_4_max = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_5_MIN:\n+\t\tpdev->tuning_parms.tp_uwr_lng_z_5_min = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_ZONE_5_MAX:\n+\t\tpdev->tuning_parms.tp_uwr_lng_z_5_max = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_1_RANGEA:\n+\t\tpdev->tuning_parms.tp_uwr_lng_corr_z_1_rangea = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_1_RANGEB:\n+\t\tpdev->tuning_parms.tp_uwr_lng_corr_z_1_rangeb = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_2_RANGEA:\n+\t\tpdev->tuning_parms.tp_uwr_lng_corr_z_2_rangea = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_2_RANGEB:\n+\t\tpdev->tuning_parms.tp_uwr_lng_corr_z_2_rangeb = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_3_RANGEA:\n+\t\tpdev->tuning_parms.tp_uwr_lng_corr_z_3_rangea = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_3_RANGEB:\n+\t\tpdev->tuning_parms.tp_uwr_lng_corr_z_3_rangeb = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_4_RANGEA:\n+\t\tpdev->tuning_parms.tp_uwr_lng_corr_z_4_rangea = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_4_RANGEB:\n+\t\tpdev->tuning_parms.tp_uwr_lng_corr_z_4_rangeb = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_5_RANGEA:\n+\t\tpdev->tuning_parms.tp_uwr_lng_corr_z_5_rangea = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tcase VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_5_RANGEB:\n+\t\tpdev->tuning_parms.tp_uwr_lng_corr_z_5_rangeb = (int16_t)tuning_parm_value;\n+\t\tbreak;\n+\tdefault:\n+\t\tstatus = VL53LX_ERROR_INVALID_PARAMS;\n+\t\tbreak;\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_SetTuningParameter(VL53LX_DEV Dev, uint16_t TuningParameterId, int32_t TuningParameterValue)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\n+\tif (TuningParameterId == VL53LX_TUNINGPARM_DYNXTALK_NODETECT_XTALK_OFFSET_KCPS)\n+\t\treturn VL53LX_ERROR_INVALID_PARAMS;\n+\n+\tif (TuningParameterId >= 32768)\n+\t\tStatus = VL53LX_set_tuning_parm(Dev, TuningParameterId, TuningParameterValue);\n+\telse {\n+\t\tif (TuningParameterId < VL53LX_TUNING_MAX_TUNABLE_KEY)\n+\t\t\tBDTable[TuningParameterId] = TuningParameterValue;\n+\t\telse\n+\t\t\tStatus = VL53LX_ERROR_INVALID_PARAMS;\n+\t}\n+\n+\treturn Status;\n+}\n+\n+static int stmvl53lx_set_tuning(struct stmvl53lx_data *data, int key, int value)\n+{\n+\tint rc = 0;\n+\n+\tif (data->enable_sensor) {\n+\t\tvl53lx_errmsg(\"can't change tuning params while ranging\\n\");\n+\t\treturn -EBUSY;\n+\t}\n+\n+\tif (data->is_calibrating) {\n+\t\tvl53lx_errmsg(\"can't change tuning params while calibrating\\n\");\n+\t\treturn -EBUSY;\n+\t}\n+\n+\tif (key & ~0xffff)\n+\t\treturn -EINVAL;\n+\n+\tvl53lx_dbgmsg(\"trying to set %d with key %d\", value, key);\n+\n+\trc = VL53LX_SetTuningParameter(&data->stdev, key, value);\n+\tif (rc)\n+\t\trc = store_last_error(data, rc);\n+\n+\treturn rc;\n+}\n+\n+static ssize_t stmvl53lx_store_tuning(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)\n+{\n+\tstruct stmvl53lx_data *data = dev_get_drvdata(dev);\n+\tint key;\n+\tint value;\n+\tint n;\n+\tint rc = 0;\n+\n+\tmutex_lock(&data->work_mutex);\n+\n+\tn = sscanf(buf, \"%d %d\", &key, &value);\n+\tif (n != 2) {\n+\t\trc = -EINVAL;\n+\t\tgoto error;\n+\t}\n+\trc = stmvl53lx_set_tuning(data, key, value);\n+\tif (rc)\n+\t\tgoto error;\n+\n+\tmutex_unlock(&data->work_mutex);\n+\n+\treturn count;\n+\n+error:\n+\tmutex_unlock(&data->work_mutex);\n+\treturn rc;\n+}\n+\n+static DEVICE_ATTR(tuning, 0220, NULL, stmvl53lx_store_tuning);\n+\n+VL53LX_Error VL53LX_GetTuningParameter(VL53LX_DEV Dev, uint16_t TuningParameterId, int32_t *pTuningParameterValue)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\n+\tif (TuningParameterId >= 32768)\n+\t\tStatus = VL53LX_get_tuning_parm(Dev, TuningParameterId, pTuningParameterValue);\n+\telse {\n+\t\tif (TuningParameterId < VL53LX_TUNING_MAX_TUNABLE_KEY)\n+\t\t\t*pTuningParameterValue = BDTable[TuningParameterId];\n+\t\telse\n+\t\t\tStatus = VL53LX_ERROR_INVALID_PARAMS;\n+\t}\n+\n+\treturn Status;\n+}\n+\n+static int stmvl53lx_display_tuning_key(struct stmvl53lx_data *data, char *buf, int *pos, int key)\n+{\n+\tint rc = 0;\n+\tint value = 0;\n+\tint sz;\n+\n+\trc = VL53LX_GetTuningParameter(&data->stdev, key, &value);\n+\tif (rc)\n+\t\treturn 0;\n+\n+\tsz = snprintf(&buf[*pos], PAGE_SIZE - *pos, \"%d %d\\n\", key, value);\n+\tif (sz >= PAGE_SIZE - *pos)\n+\t\treturn -ENOSPC;\n+\n+\t*pos += sz;\n+\n+\treturn 0;\n+}\n+\n+static ssize_t stmvl53lx_show_tuning_status(struct device *dev, struct device_attribute *attr, char *buf)\n+{\n+\tconst int max_tuning_key = 65535;\n+\tstruct stmvl53lx_data *data = dev_get_drvdata(dev);\n+\tint rc = 0;\n+\tint i;\n+\tint pos = 0;\n+\n+\tmutex_lock(&data->work_mutex);\n+\n+\tfor (i = 0; i < max_tuning_key; ++i) {\n+\t\trc = stmvl53lx_display_tuning_key(data, buf, &pos, i);\n+\t\tif (rc)\n+\t\t\tbreak;\n+\t}\n+\n+\tmutex_unlock(&data->work_mutex);\n+\n+\treturn rc ? rc : pos;\n+}\n+\n+static DEVICE_ATTR(tuning_status, 0440, stmvl53lx_show_tuning_status, NULL);\n+\n+static int stmvl53lx_set_smudge_correction_mode(struct stmvl53lx_data *data,\n+\tint smudge_correction_mode)\n+{\n+\tint rc = 0;\n+\n+\tif (data->enable_sensor) {\n+\t\tvl53lx_errmsg(\"can't change smudge corr mode while ranging\\n\");\n+\t\trc = -EBUSY;\n+\t} else {\n+\t\tswitch (smudge_correction_mode) {\n+\t\tcase VL53LX_SMUDGE_CORRECTION_NONE:\n+\t\tcase VL53LX_SMUDGE_CORRECTION_CONTINUOUS:\n+\t\tcase VL53LX_SMUDGE_CORRECTION_SINGLE:\n+\t\tcase VL53LX_SMUDGE_CORRECTION_DEBUG:\n+\t\t\tdata->smudge_correction_mode = smudge_correction_mode;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tvl53lx_errmsg(\"invalid smudge correction mode %d\\n\",\n+\t\t\t\tsmudge_correction_mode);\n+\t\t\trc = -EINVAL;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn rc;\n+}\n+\n+IMPLEMENT_PARAMETER_INTEGER(smudge_correction_mode, \"smudge correction mode\")\n+\n+static DEVICE_ATTR(smudge_correction_mode, 0660, stmvl53lx_show_smudge_correction_mode, stmvl53lx_store_smudge_correction_mode);\n+\n+static ssize_t stmvl53lx_show_is_xtalk_value_changed_config(struct device *dev, struct device_attribute *attr, char *buf)\n+{\n+\tstruct stmvl53lx_data *data = dev_get_drvdata(dev);\n+\tint param;\n+\n+\tmutex_lock(&data->work_mutex);\n+\tparam = data->is_xtalk_value_changed;\n+\tmutex_unlock(&data->work_mutex);\n+\n+\treturn scnprintf(buf, PAGE_SIZE, \"%d\\n\", param);\n+}\n+\n+static DEVICE_ATTR(is_xtalk_value_changed, 0440, stmvl53lx_show_is_xtalk_value_changed_config, NULL);\n+\n+static struct attribute *stmvl53lx_attributes[] = {\n+\t&dev_attr_enable_ps_sensor.attr,\n+\t&dev_attr_set_delay_ms.attr,\n+\t&dev_attr_timing_budget.attr,\n+\t&dev_attr_roi.attr,\n+\t&dev_attr_do_flush.attr,\n+\t&dev_attr_distance_mode.attr,\n+\t&dev_attr_crosstalk_enable.attr,\n+\t&dev_attr_enable_debug.attr,\n+\t&dev_attr_force_device_on_enable.attr,\n+\t&dev_attr_last_error.attr,\n+\t&dev_attr_offset_correction_mode.attr,\n+\t&dev_attr_optical_center.attr,\n+\t&dev_attr_tuning.attr,\n+\t&dev_attr_tuning_status.attr,\n+\t&dev_attr_smudge_correction_mode.attr,\n+\t&dev_attr_is_xtalk_value_changed.attr,\n+\tNULL\n+};\n+\n+static const struct attribute_group stmvl53lx_attr_group = {\n+\t.attrs = stmvl53lx_attributes,\n+};\n+\n+static int ctrl_param_last_error(struct stmvl53lx_data *data, struct stmvl53lx_parameter *param)\n+{\n+\tint rc = 0;\n+\n+\tif (param->is_read) {\n+\t\tparam->value = data->last_error;\n+\t\tparam->status = 0;\n+\t\tvl53lx_dbgmsg(\"get last error %d\", param->value);\n+\t\trc = 0;\n+\t} else {\n+\t\trc = -EINVAL;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+static int ctrl_param_optical_center(struct stmvl53lx_data *data, struct stmvl53lx_parameter *param)\n+{\n+\tif (!param->is_read)\n+\t\treturn -EINVAL;\n+\n+\tparam->value = data->optical_offset_x;\n+\tparam->value2 = data->optical_offset_y;\n+\n+\treturn 0;\n+}\n+\n+static int ctrl_param_tuning(struct stmvl53lx_data *data, struct stmvl53lx_parameter *param)\n+{\n+\tif (param->is_read)\n+\t\treturn -EINVAL;\n+\n+\treturn stmvl53lx_set_tuning(data, param->value, param->value2);\n+}\n+\n+static int ctrl_param_is_xtalk_value_changed(struct stmvl53lx_data *data, struct stmvl53lx_parameter *param)\n+{\n+\tif (!param->is_read)\n+\t\treturn -EINVAL;\n+\n+\tparam->value = data->is_xtalk_value_changed;\n+\n+\treturn 0;\n+}\n+\n+static int ctrl_params(struct stmvl53lx_data *data, void __user *p)\n+{\n+\tint rc, rc2;\n+\tstruct stmvl53lx_parameter param;\n+\n+\tmutex_lock(&data->work_mutex);\n+\n+\tif (data->is_device_remove) {\n+\t\trc = -ENODEV;\n+\t\tgoto done;\n+\t}\n+\trc = copy_from_user(&param, p, sizeof(param));\n+\tparam.status = 0;\n+\tif (rc) {\n+\t\trc = -EFAULT;\n+\t\tgoto done;\n+\t}\n+\tswitch (param.name) {\n+\tcase VL53LX_POLLDELAY_PAR:\n+\t\trc = ctrl_param_poll_delay_ms(data, &param);\n+\t\tbreak;\n+\tcase VL53LX_TIMINGBUDGET_PAR:\n+\t\trc = ctrl_param_timing_budget(data, &param);\n+\t\tbreak;\n+\tcase VL53LX_DISTANCEMODE_PAR:\n+\t\trc = ctrl_param_distance_mode(data, &param);\n+\tbreak;\n+\tcase VL53LX_XTALKENABLE_PAR:\n+\t\trc = ctrl_param_crosstalk_enable(data, &param);\n+\tbreak;\n+\tcase VL53LX_FORCEDEVICEONEN_PAR:\n+\t\trc = ctrl_param_force_device_on_en(data, &param);\n+\tbreak;\n+\tcase VL53LX_LASTERROR_PAR:\n+\t\trc = ctrl_param_last_error(data, &param);\n+\tbreak;\n+\tcase VL53LX_OFFSETCORRECTIONMODE_PAR:\n+\t\trc = ctrl_param_offset_correction_mode(data, &param);\n+\tbreak;\n+\tcase VL53LX_OPTICALCENTER_PAR:\n+\t\trc = ctrl_param_optical_center(data, &param);\n+\tbreak;\n+\tcase VL53LX_TUNING_PAR:\n+\t\trc = ctrl_param_tuning(data, &param);\n+\t\tbreak;\n+\tcase VL53LX_SMUDGECORRECTIONMODE_PAR:\n+\t\trc = ctrl_param_smudge_correction_mode(data, &param);\n+\tbreak;\n+\tcase VL53LX_ISXTALKVALUECHANGED_PAR:\n+\t\trc = ctrl_param_is_xtalk_value_changed(data, &param);\n+\tbreak;\n+\tdefault:\n+\t\tvl53lx_errmsg(\"unknown or unsupported %d\\n\", param.name);\n+\t\trc = -EINVAL;\n+\t}\n+\n+\tif (param.is_read  && rc == 0) {\n+\t\trc2 = copy_to_user(p, &param, sizeof(param));\n+\t\tif (rc2) {\n+\t\t\trc = -EFAULT;\n+\t\t\tvl53lx_errmsg(\"copy to user fail %d\\n\", rc);\n+\t\t}\n+\t}\n+done:\n+\tmutex_unlock(&data->work_mutex);\n+\treturn rc;\n+}\n+\n+VL53LX_Error VL53LX_set_part_to_part_data(VL53LX_DEV Dev, VL53LX_calibration_data_t *pcal_data)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_xtalk_config_t *pC = &(pdev->xtalk_cfg);\n+\tVL53LX_hist_post_process_config_t *pHP = &(pdev->histpostprocess);\n+\tVL53LX_customer_nvm_managed_t *pN = &(pdev->customer);\n+\tuint32_t tempu32;\n+\n+\tif (pcal_data->struct_version != VL53LX_LL_CALIBRATION_DATA_STRUCT_VERSION) {\n+\t\tstatus = VL53LX_ERROR_INVALID_PARAMS;\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tmemcpy(&(pdev->customer), &(pcal_data->customer), sizeof(VL53LX_customer_nvm_managed_t));\n+\t\tmemcpy(&(pdev->add_off_cal_data), &(pcal_data->add_off_cal_data), sizeof(VL53LX_additional_offset_cal_data_t));\n+\t\tmemcpy(&(pdev->fmt_dmax_cal), &(pcal_data->fmt_dmax_cal), sizeof(VL53LX_dmax_calibration_data_t));\n+\t\tmemcpy(&(pdev->cust_dmax_cal), &(pcal_data->cust_dmax_cal), sizeof(VL53LX_dmax_calibration_data_t));\n+\t\tmemcpy(&(pdev->xtalk_shapes), &(pcal_data->xtalkhisto), sizeof(VL53LX_xtalk_histogram_data_t));\n+\t\tmemcpy(&(pdev->gain_cal), &(pcal_data->gain_cal), sizeof(VL53LX_gain_calibration_data_t));\n+\t\tmemcpy(&(pdev->cal_peak_rate_map), &(pcal_data->cal_peak_rate_map), sizeof(VL53LX_cal_peak_rate_map_t));\n+\t\tmemcpy(&(pdev->per_vcsel_cal_data), &(pcal_data->per_vcsel_cal_data), sizeof(VL53LX_per_vcsel_period_offset_cal_data_t));\n+\n+\t\tpC->algo__crosstalk_compensation_plane_offset_kcps = pN->algo__crosstalk_compensation_plane_offset_kcps;\n+\t\tpC->algo__crosstalk_compensation_x_plane_gradient_kcps = pN->algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\t\tpC->algo__crosstalk_compensation_y_plane_gradient_kcps = pN->algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\n+\t\tpHP->algo__crosstalk_compensation_plane_offset_kcps = VL53LX_calc_crosstalk_plane_offset_with_margin(pC->algo__crosstalk_compensation_plane_offset_kcps, pC->histogram_mode_crosstalk_margin_kcps);\n+\n+\t\tpHP->algo__crosstalk_compensation_x_plane_gradient_kcps = pC->algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\t\tpHP->algo__crosstalk_compensation_y_plane_gradient_kcps = pC->algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\n+\t\tif (pC->global_crosstalk_compensation_enable == 0x00) {\n+\t\t\tpN->algo__crosstalk_compensation_plane_offset_kcps = 0x00;\n+\t\t\tpN->algo__crosstalk_compensation_x_plane_gradient_kcps = 0x00;\n+\t\t\tpN->algo__crosstalk_compensation_y_plane_gradient_kcps = 0x00;\n+\t\t} else {\n+\t\t\ttempu32 = VL53LX_calc_crosstalk_plane_offset_with_margin(pC->algo__crosstalk_compensation_plane_offset_kcps, pC->lite_mode_crosstalk_margin_kcps);\n+\t\t\tif (tempu32 > 0xFFFF)\n+\t\t\t\ttempu32 = 0xFFFF;\n+\n+\t\t\tpN->algo__crosstalk_compensation_plane_offset_kcps = (uint16_t)tempu32;\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_get_current_xtalk_settings(VL53LX_DEV Dev, VL53LX_xtalk_calibration_results_t *pxtalk)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tuint8_t i;\n+\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpxtalk->algo__crosstalk_compensation_plane_offset_kcps = pdev->xtalk_cfg.algo__crosstalk_compensation_plane_offset_kcps;\n+\tpxtalk->algo__crosstalk_compensation_x_plane_gradient_kcps = pdev->xtalk_cfg.algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\tpxtalk->algo__crosstalk_compensation_y_plane_gradient_kcps = pdev->xtalk_cfg.algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\tfor (i = 0; i < VL53LX_BIN_REC_SIZE; i++)\n+\t\tpxtalk->algo__xtalk_cpo_HistoMerge_kcps[i] = pdev->xtalk_cal.algo__xtalk_cpo_HistoMerge_kcps[i];\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_set_current_xtalk_settings(VL53LX_DEV Dev, VL53LX_xtalk_calibration_results_t *pxtalk)\n+{\n+\tuint8_t i;\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpdev->xtalk_cfg.algo__crosstalk_compensation_plane_offset_kcps = pxtalk->algo__crosstalk_compensation_plane_offset_kcps;\n+\tpdev->xtalk_cfg.algo__crosstalk_compensation_x_plane_gradient_kcps = pxtalk->algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\tpdev->xtalk_cfg.algo__crosstalk_compensation_y_plane_gradient_kcps = pxtalk->algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\tfor (i = 0; i < VL53LX_BIN_REC_SIZE; i++)\n+\t\tpdev->xtalk_cal.algo__xtalk_cpo_HistoMerge_kcps[i] = pxtalk->algo__xtalk_cpo_HistoMerge_kcps[i];\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_SetCalibrationData(VL53LX_DEV Dev, VL53LX_CalibrationData_t *pCalibrationData)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tVL53LX_CustomerNvmManaged_t          *pC;\n+\tVL53LX_calibration_data_t            cal_data;\n+\tuint32_t x;\n+\tVL53LX_xtalk_calibration_results_t xtalk;\n+\n+\tcal_data.struct_version = pCalibrationData->struct_version - VL53LX_ADDITIONAL_CALIBRATION_DATA_STRUCT_VERSION;\n+\n+\tmemcpy(&(cal_data.add_off_cal_data), &(pCalibrationData->add_off_cal_data), sizeof(VL53LX_additional_offset_cal_data_t));\n+\tmemcpy(&(cal_data.optical_centre), &(pCalibrationData->optical_centre), sizeof(VL53LX_optical_centre_t));\n+\tmemcpy(&(cal_data.xtalkhisto), &(pCalibrationData->xtalkhisto), sizeof(VL53LX_xtalk_histogram_data_t));\n+\tmemcpy(&(cal_data.gain_cal), &(pCalibrationData->gain_cal), sizeof(VL53LX_gain_calibration_data_t));\n+\tmemcpy(&(cal_data.cal_peak_rate_map), &(pCalibrationData->cal_peak_rate_map), sizeof(VL53LX_cal_peak_rate_map_t));\n+\tmemcpy(&(cal_data.per_vcsel_cal_data), &(pCalibrationData->per_vcsel_cal_data), sizeof(VL53LX_per_vcsel_period_offset_cal_data_t));\n+\n+\tpC = &pCalibrationData->customer;\n+\tx = pC->algo__crosstalk_compensation_plane_offset_kcps;\n+\tcal_data.customer.algo__crosstalk_compensation_plane_offset_kcps = (uint16_t)(x&0x0000FFFF);\n+\n+\tcal_data.customer.global_config__spad_enables_ref_0 = pC->global_config__spad_enables_ref_0;\n+\tcal_data.customer.global_config__spad_enables_ref_1 = pC->global_config__spad_enables_ref_1;\n+\tcal_data.customer.global_config__spad_enables_ref_2 = pC->global_config__spad_enables_ref_2;\n+\tcal_data.customer.global_config__spad_enables_ref_3 = pC->global_config__spad_enables_ref_3;\n+\tcal_data.customer.global_config__spad_enables_ref_4 = pC->global_config__spad_enables_ref_4;\n+\tcal_data.customer.global_config__spad_enables_ref_5 = pC->global_config__spad_enables_ref_5;\n+\tcal_data.customer.global_config__ref_en_start_select = pC->global_config__ref_en_start_select;\n+\tcal_data.customer.ref_spad_man__num_requested_ref_spads = pC->ref_spad_man__num_requested_ref_spads;\n+\tcal_data.customer.ref_spad_man__ref_location = pC->ref_spad_man__ref_location;\n+\tcal_data.customer.algo__crosstalk_compensation_x_plane_gradient_kcps = pC->algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\tcal_data.customer.algo__crosstalk_compensation_y_plane_gradient_kcps = pC->algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\tcal_data.customer.ref_spad_char__total_rate_target_mcps = pC->ref_spad_char__total_rate_target_mcps;\n+\tcal_data.customer.algo__part_to_part_range_offset_mm = pC->algo__part_to_part_range_offset_mm;\n+\tcal_data.customer.mm_config__inner_offset_mm = pC->mm_config__inner_offset_mm;\n+\tcal_data.customer.mm_config__outer_offset_mm = pC->mm_config__outer_offset_mm;\n+\n+\tStatus = VL53LX_set_part_to_part_data(Dev, &cal_data);\n+\n+\tif (Status != VL53LX_ERROR_NONE)\n+\t\tgoto ENDFUNC;\n+\n+\tStatus = VL53LX_get_current_xtalk_settings(Dev, &xtalk);\n+\n+\tif (Status != VL53LX_ERROR_NONE)\n+\t\tgoto ENDFUNC;\n+\n+\txtalk.algo__crosstalk_compensation_plane_offset_kcps = x;\n+\n+\tStatus = VL53LX_set_tuning_parm(Dev, VL53LX_TUNINGPARM_DYNXTALK_NODETECT_XTALK_OFFSET_KCPS, x);\n+\n+\tmemcpy(&(xtalk.algo__xtalk_cpo_HistoMerge_kcps[0]), &(pCalibrationData->algo__xtalk_cpo_HistoMerge_kcps[0]), sizeof(pCalibrationData->algo__xtalk_cpo_HistoMerge_kcps));\n+\n+\tStatus = VL53LX_set_current_xtalk_settings(Dev, &xtalk);\n+\n+ENDFUNC:\n+\treturn Status;\n+\n+}\n+\n+VL53LX_Error VL53LX_get_part_to_part_data(VL53LX_DEV Dev, VL53LX_calibration_data_t *pcal_data)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_xtalk_config_t *pC = &(pdev->xtalk_cfg);\n+\tVL53LX_customer_nvm_managed_t *pCN = &(pcal_data->customer);\n+\n+\tpcal_data->struct_version = VL53LX_LL_CALIBRATION_DATA_STRUCT_VERSION;\n+\tmemcpy(&(pcal_data->customer), &(pdev->customer), sizeof(VL53LX_customer_nvm_managed_t));\n+\n+\tif (pC->algo__crosstalk_compensation_plane_offset_kcps > 0xFFFF) {\n+\t\tpCN->algo__crosstalk_compensation_plane_offset_kcps = 0xFFFF;\n+\t} else {\n+\t\tpCN->algo__crosstalk_compensation_plane_offset_kcps = (uint16_t)pC->algo__crosstalk_compensation_plane_offset_kcps;\n+\t}\n+\tpCN->algo__crosstalk_compensation_x_plane_gradient_kcps = pC->algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\tpCN->algo__crosstalk_compensation_y_plane_gradient_kcps = pC->algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\n+\tmemcpy(&(pcal_data->fmt_dmax_cal), &(pdev->fmt_dmax_cal), sizeof(VL53LX_dmax_calibration_data_t));\n+\tmemcpy(&(pcal_data->cust_dmax_cal), &(pdev->cust_dmax_cal), sizeof(VL53LX_dmax_calibration_data_t));\n+\tmemcpy(&(pcal_data->add_off_cal_data), &(pdev->add_off_cal_data), sizeof(VL53LX_additional_offset_cal_data_t));\n+\tmemcpy(&(pcal_data->optical_centre), &(pdev->optical_centre), sizeof(VL53LX_optical_centre_t));\n+\tmemcpy(&(pcal_data->xtalkhisto), &(pdev->xtalk_shapes), sizeof(VL53LX_xtalk_histogram_data_t));\n+\tmemcpy(&(pcal_data->gain_cal), &(pdev->gain_cal), sizeof(VL53LX_gain_calibration_data_t));\n+\tmemcpy(&(pcal_data->cal_peak_rate_map), &(pdev->cal_peak_rate_map), sizeof(VL53LX_cal_peak_rate_map_t));\n+\tmemcpy(&(pcal_data->per_vcsel_cal_data), &(pdev->per_vcsel_cal_data), sizeof(VL53LX_per_vcsel_period_offset_cal_data_t));\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_GetCalibrationData(VL53LX_DEV Dev, VL53LX_CalibrationData_t *pCalibrationData)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tVL53LX_calibration_data_t      cal_data;\n+\tVL53LX_CustomerNvmManaged_t         *pC;\n+\tVL53LX_customer_nvm_managed_t       *pC2;\n+\tVL53LX_xtalk_calibration_results_t xtalk;\n+\tuint32_t                          tmp;\n+\n+\tStatus = VL53LX_get_part_to_part_data(Dev, &cal_data);\n+\n+\tpCalibrationData->struct_version = cal_data.struct_version + VL53LX_ADDITIONAL_CALIBRATION_DATA_STRUCT_VERSION;\n+\n+\tmemcpy(&(pCalibrationData->add_off_cal_data), &(cal_data.add_off_cal_data), sizeof(VL53LX_additional_offset_cal_data_t));\n+\tmemcpy(&(pCalibrationData->optical_centre), &(cal_data.optical_centre), sizeof(VL53LX_optical_centre_t));\n+\tmemcpy(&(pCalibrationData->xtalkhisto), &(cal_data.xtalkhisto), sizeof(VL53LX_xtalk_histogram_data_t));\n+\tmemcpy(&(pCalibrationData->gain_cal), &(cal_data.gain_cal), sizeof(VL53LX_gain_calibration_data_t));\n+\tmemcpy(&(pCalibrationData->cal_peak_rate_map), &(cal_data.cal_peak_rate_map), sizeof(VL53LX_cal_peak_rate_map_t));\n+\tmemcpy(&(pCalibrationData->per_vcsel_cal_data), &(cal_data.per_vcsel_cal_data), sizeof(VL53LX_per_vcsel_period_offset_cal_data_t));\n+\n+\tpC = &pCalibrationData->customer;\n+\tpC2 = &cal_data.customer;\n+\tpC->global_config__spad_enables_ref_0 = pC2->global_config__spad_enables_ref_0;\n+\tpC->global_config__spad_enables_ref_1 = pC2->global_config__spad_enables_ref_1;\n+\tpC->global_config__spad_enables_ref_2 = pC2->global_config__spad_enables_ref_2;\n+\tpC->global_config__spad_enables_ref_3 = pC2->global_config__spad_enables_ref_3;\n+\tpC->global_config__spad_enables_ref_4 = pC2->global_config__spad_enables_ref_4;\n+\tpC->global_config__spad_enables_ref_5 = pC2->global_config__spad_enables_ref_5;\n+\tpC->global_config__ref_en_start_select = pC2->global_config__ref_en_start_select;\n+\tpC->ref_spad_man__num_requested_ref_spads = pC2->ref_spad_man__num_requested_ref_spads;\n+\tpC->ref_spad_man__ref_location = pC2->ref_spad_man__ref_location;\n+\tpC->algo__crosstalk_compensation_x_plane_gradient_kcps = pC2->algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\tpC->algo__crosstalk_compensation_y_plane_gradient_kcps = pC2->algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\tpC->ref_spad_char__total_rate_target_mcps = pC2->ref_spad_char__total_rate_target_mcps;\n+\tpC->algo__part_to_part_range_offset_mm = pC2->algo__part_to_part_range_offset_mm;\n+\tpC->mm_config__inner_offset_mm = pC2->mm_config__inner_offset_mm;\n+\tpC->mm_config__outer_offset_mm = pC2->mm_config__outer_offset_mm;\n+\n+\tpC->algo__crosstalk_compensation_plane_offset_kcps = (uint32_t)(pC2->algo__crosstalk_compensation_plane_offset_kcps);\n+\n+\tStatus = VL53LX_get_current_xtalk_settings(Dev, &xtalk);\n+\n+\tif (Status != VL53LX_ERROR_NONE)\n+\t\tgoto ENDFUNC;\n+\n+\ttmp = xtalk.algo__crosstalk_compensation_plane_offset_kcps;\n+\tpC->algo__crosstalk_compensation_plane_offset_kcps = tmp;\n+\ttmp = xtalk.algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\tpC->algo__crosstalk_compensation_x_plane_gradient_kcps = tmp;\n+\ttmp = xtalk.algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\tpC->algo__crosstalk_compensation_y_plane_gradient_kcps = tmp;\n+\n+\tmemcpy(&(pCalibrationData->algo__xtalk_cpo_HistoMerge_kcps[0]), &(xtalk.algo__xtalk_cpo_HistoMerge_kcps[0]), sizeof(pCalibrationData->algo__xtalk_cpo_HistoMerge_kcps));\n+\n+ENDFUNC:\n+\treturn Status;\n+}\n+\n+static ssize_t stmvl53lx_calib_data_read(struct file *filp, struct kobject *kobj, const struct bin_attribute *attr, char *buf, loff_t off, size_t count)\n+{\n+\tstruct device *dev = container_of(kobj, struct device, kobj);\n+\tstruct stmvl53lx_data *data = dev_get_drvdata(dev);\n+\tVL53LX_CalibrationData_t calib;\n+\tint rc = 0;\n+\tvoid *src = (void *) &calib;\n+\n+\tmutex_lock(&data->work_mutex);\n+\n+\tvl53lx_dbgmsg(\"off = %lld / count = %d\", off, count);\n+\n+\tif (off < 0 || off > sizeof(VL53LX_CalibrationData_t))\n+\t\tgoto invalid;\n+\n+\tmemset(&calib, 0, sizeof(calib));\n+\trc = VL53LX_GetCalibrationData(&data->stdev, &calib);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"VL53LX_GetCalibrationData fail %d\", rc);\n+\t\trc = store_last_error(data, rc);\n+\t\tgoto error;\n+\t}\n+\n+\tif (off + count > sizeof(VL53LX_CalibrationData_t))\n+\t\tcount = sizeof(VL53LX_CalibrationData_t) - off;\n+\tmemcpy(buf, src + off, count);\n+\n+\tmutex_unlock(&data->work_mutex);\n+\treturn count;\n+\n+invalid:\n+\tvl53lx_errmsg(\"invalid syntax\");\n+\trc = -EINVAL;\n+\tgoto error;\n+\n+error:\n+\tmutex_unlock(&data->work_mutex);\n+\treturn rc;\n+}\n+\n+static ssize_t stmvl53lx_calib_data_write(struct file *filp, struct kobject *kobj, const struct bin_attribute *attr, char *buf, loff_t off, size_t count)\n+{\n+\tint rc = 0;\n+\tstruct device *dev = container_of(kobj, struct device, kobj);\n+\tstruct stmvl53lx_data *data = dev_get_drvdata(dev);\n+\n+\tmutex_lock(&data->work_mutex);\n+\n+\tvl53lx_dbgmsg(\"off = %lld / count = %d\", off, count);\n+\n+\tif (data->enable_sensor) {\n+\t\trc = -EBUSY;\n+\t\tvl53lx_errmsg(\"can't set calib data while ranging\\n\");\n+\t\tgoto error;\n+\t}\n+\n+\tif (off != 0 || count != sizeof(VL53LX_CalibrationData_t))\n+\t\tgoto invalid;\n+\n+\trc = VL53LX_SetCalibrationData(&data->stdev, (VL53LX_CalibrationData_t *) buf);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"VL53LX_SetCalibrationData fail %d\", rc);\n+\t\trc = store_last_error(data, rc);\n+\t\tgoto error;\n+\t}\n+\n+\tmutex_unlock(&data->work_mutex);\n+\treturn count;\n+\n+invalid:\n+\tvl53lx_errmsg(\"invalid syntax\");\n+\trc = -EINVAL;\n+\tgoto error;\n+\n+error:\n+\tmutex_unlock(&data->work_mutex);\n+\n+\treturn rc;\n+}\n+\n+static struct bin_attribute stmvl53lx_calib_data_attr = {\n+\t.attr = {\n+\t\t.name = \"calibration_data\",\n+\t\t.mode = 0660,\n+\t},\n+\t.size = sizeof(VL53LX_CalibrationData_t),\n+\t.read = stmvl53lx_calib_data_read,\n+\t.write = stmvl53lx_calib_data_write,\n+};\n+\n+void VL53LX_init_version(VL53LX_DEV Dev)\n+{\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpdev->version.ll_major    = VL53LX_LL_API_IMPLEMENTATION_VER_MAJOR;\n+\tpdev->version.ll_minor    = VL53LX_LL_API_IMPLEMENTATION_VER_MINOR;\n+\tpdev->version.ll_build    = VL53LX_LL_API_IMPLEMENTATION_VER_SUB;\n+\tpdev->version.ll_revision = VL53LX_LL_API_IMPLEMENTATION_VER_REVISION;\n+}\n+\n+VL53LX_Error VL53LX_get_static_nvm_managed(VL53LX_DEV Dev, VL53LX_static_nvm_managed_t *pdata)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tuint8_t comms_buffer[VL53LX_STATIC_NVM_MANAGED_I2C_SIZE_BYTES];\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_ReadMulti(Dev, VL53LX_I2C_SLAVE__DEVICE_ADDRESS, comms_buffer, VL53LX_STATIC_NVM_MANAGED_I2C_SIZE_BYTES);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_i2c_decode_static_nvm_managed(VL53LX_STATIC_NVM_MANAGED_I2C_SIZE_BYTES, comms_buffer, pdata);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_i2c_decode_customer_nvm_managed(uint16_t buf_size, uint8_t *pbuffer, VL53LX_customer_nvm_managed_t *pdata)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (buf_size < VL53LX_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES)\n+\t\treturn VL53LX_ERROR_COMMS_BUFFER_TOO_SMALL;\n+\n+\tpdata->global_config__spad_enables_ref_0 = (*(pbuffer +   0));\n+\tpdata->global_config__spad_enables_ref_1 = (*(pbuffer +   1));\n+\tpdata->global_config__spad_enables_ref_2 = (*(pbuffer +   2));\n+\tpdata->global_config__spad_enables_ref_3 = (*(pbuffer +   3));\n+\tpdata->global_config__spad_enables_ref_4 = (*(pbuffer +   4));\n+\tpdata->global_config__spad_enables_ref_5 = (*(pbuffer +   5)) & 0xF;\n+\tpdata->global_config__ref_en_start_select = (*(pbuffer +   6));\n+\tpdata->ref_spad_man__num_requested_ref_spads = (*(pbuffer +   7)) & 0x3F;\n+\tpdata->ref_spad_man__ref_location = (*(pbuffer +   8)) & 0x3;\n+\tpdata->algo__crosstalk_compensation_plane_offset_kcps = (VL53LX_i2c_decode_uint16_t(2, pbuffer +   9));\n+\tpdata->algo__crosstalk_compensation_x_plane_gradient_kcps = (VL53LX_i2c_decode_int16_t(2, pbuffer +  11));\n+\tpdata->algo__crosstalk_compensation_y_plane_gradient_kcps = (VL53LX_i2c_decode_int16_t(2, pbuffer +  13));\n+\tpdata->ref_spad_char__total_rate_target_mcps = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  15));\n+\tpdata->algo__part_to_part_range_offset_mm = (VL53LX_i2c_decode_int16_t(2, pbuffer +  17)) & 0x1FFF;\n+\tpdata->mm_config__inner_offset_mm = (VL53LX_i2c_decode_int16_t(2, pbuffer +  19));\n+\tpdata->mm_config__outer_offset_mm = (VL53LX_i2c_decode_int16_t(2, pbuffer +  21));\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_get_customer_nvm_managed(VL53LX_DEV Dev, VL53LX_customer_nvm_managed_t *pdata)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tuint8_t comms_buffer[VL53LX_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES];\n+\tint16_t offset;\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_ReadMulti(Dev, VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_0, comms_buffer, VL53LX_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_i2c_decode_customer_nvm_managed(VL53LX_CUSTOMER_NVM_MANAGED_I2C_SIZE_BYTES, comms_buffer, pdata);\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\toffset = pdata->algo__part_to_part_range_offset_mm;\n+\t\toffset = offset / 4;\n+\t\tif (offset >= 1024)\n+\t\t\toffset -= 2048;\n+\t\tpdata->algo__part_to_part_range_offset_mm = 0;\n+\t\tpdata->mm_config__inner_offset_mm = offset;\n+\t\tpdata->mm_config__outer_offset_mm = offset;\n+\t}\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_i2c_decode_nvm_copy_data(uint16_t buf_size, uint8_t *pbuffer, VL53LX_nvm_copy_data_t *pdata)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (buf_size < VL53LX_NVM_COPY_DATA_I2C_SIZE_BYTES)\n+\t\treturn VL53LX_ERROR_COMMS_BUFFER_TOO_SMALL;\n+\n+\tpdata->identification__model_id = (*(pbuffer +   0));\n+\tpdata->identification__module_type = (*(pbuffer +   1));\n+\tpdata->identification__revision_id = (*(pbuffer +   2));\n+\tpdata->identification__module_id = (VL53LX_i2c_decode_uint16_t(2, pbuffer +   3));\n+\tpdata->ana_config__fast_osc__trim_max = (*(pbuffer +   5)) & 0x7F;\n+\tpdata->ana_config__fast_osc__freq_set = (*(pbuffer +   6)) & 0x7;\n+\tpdata->ana_config__vcsel_trim = (*(pbuffer +   7)) & 0x7;\n+\tpdata->ana_config__vcsel_selion = (*(pbuffer +   8)) & 0x3F;\n+\tpdata->ana_config__vcsel_selion_max = (*(pbuffer +   9)) & 0x3F;\n+\tpdata->protected_laser_safety__lock_bit = (*(pbuffer +  10)) & 0x1;\n+\tpdata->laser_safety__key = (*(pbuffer +  11)) & 0x7F;\n+\tpdata->laser_safety__key_ro = (*(pbuffer +  12)) & 0x1;\n+\tpdata->laser_safety__clip = (*(pbuffer +  13)) & 0x3F;\n+\tpdata->laser_safety__mult = (*(pbuffer +  14)) & 0x3F;\n+\tpdata->global_config__spad_enables_rtn_0 = (*(pbuffer +  15));\n+\tpdata->global_config__spad_enables_rtn_1 = (*(pbuffer +  16));\n+\tpdata->global_config__spad_enables_rtn_2 = (*(pbuffer +  17));\n+\tpdata->global_config__spad_enables_rtn_3 = (*(pbuffer +  18));\n+\tpdata->global_config__spad_enables_rtn_4 = (*(pbuffer +  19));\n+\tpdata->global_config__spad_enables_rtn_5 = (*(pbuffer +  20));\n+\tpdata->global_config__spad_enables_rtn_6 = (*(pbuffer +  21));\n+\tpdata->global_config__spad_enables_rtn_7 = (*(pbuffer +  22));\n+\tpdata->global_config__spad_enables_rtn_8 = (*(pbuffer +  23));\n+\tpdata->global_config__spad_enables_rtn_9 = (*(pbuffer +  24));\n+\tpdata->global_config__spad_enables_rtn_10 = (*(pbuffer +  25));\n+\tpdata->global_config__spad_enables_rtn_11 = (*(pbuffer +  26));\n+\tpdata->global_config__spad_enables_rtn_12 = (*(pbuffer +  27));\n+\tpdata->global_config__spad_enables_rtn_13 = (*(pbuffer +  28));\n+\tpdata->global_config__spad_enables_rtn_14 = (*(pbuffer +  29));\n+\tpdata->global_config__spad_enables_rtn_15 = (*(pbuffer +  30));\n+\tpdata->global_config__spad_enables_rtn_16 = (*(pbuffer +  31));\n+\tpdata->global_config__spad_enables_rtn_17 = (*(pbuffer +  32));\n+\tpdata->global_config__spad_enables_rtn_18 = (*(pbuffer +  33));\n+\tpdata->global_config__spad_enables_rtn_19 = (*(pbuffer +  34));\n+\tpdata->global_config__spad_enables_rtn_20 = (*(pbuffer +  35));\n+\tpdata->global_config__spad_enables_rtn_21 = (*(pbuffer +  36));\n+\tpdata->global_config__spad_enables_rtn_22 = (*(pbuffer +  37));\n+\tpdata->global_config__spad_enables_rtn_23 = (*(pbuffer +  38));\n+\tpdata->global_config__spad_enables_rtn_24 = (*(pbuffer +  39));\n+\tpdata->global_config__spad_enables_rtn_25 = (*(pbuffer +  40));\n+\tpdata->global_config__spad_enables_rtn_26 = (*(pbuffer +  41));\n+\tpdata->global_config__spad_enables_rtn_27 = (*(pbuffer +  42));\n+\tpdata->global_config__spad_enables_rtn_28 = (*(pbuffer +  43));\n+\tpdata->global_config__spad_enables_rtn_29 = (*(pbuffer +  44));\n+\tpdata->global_config__spad_enables_rtn_30 = (*(pbuffer +  45));\n+\tpdata->global_config__spad_enables_rtn_31 = (*(pbuffer +  46));\n+\tpdata->roi_config__mode_roi_centre_spad = (*(pbuffer +  47));\n+\tpdata->roi_config__mode_roi_xy_size = (*(pbuffer +  48));\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_get_nvm_copy_data(VL53LX_DEV Dev, VL53LX_nvm_copy_data_t *pdata)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tuint8_t comms_buffer[VL53LX_NVM_COPY_DATA_I2C_SIZE_BYTES];\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_ReadMulti(Dev, VL53LX_IDENTIFICATION__MODEL_ID, comms_buffer, VL53LX_NVM_COPY_DATA_I2C_SIZE_BYTES);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_i2c_decode_nvm_copy_data(VL53LX_NVM_COPY_DATA_I2C_SIZE_BYTES, comms_buffer, pdata);\n+\n+\treturn status;\n+}\n+\n+void VL53LX_copy_rtn_good_spads_to_buffer(VL53LX_nvm_copy_data_t *pdata, uint8_t *pbuffer)\n+{\n+\t*(pbuffer +  0) = pdata->global_config__spad_enables_rtn_0;\n+\t*(pbuffer +  1) = pdata->global_config__spad_enables_rtn_1;\n+\t*(pbuffer +  2) = pdata->global_config__spad_enables_rtn_2;\n+\t*(pbuffer +  3) = pdata->global_config__spad_enables_rtn_3;\n+\t*(pbuffer +  4) = pdata->global_config__spad_enables_rtn_4;\n+\t*(pbuffer +  5) = pdata->global_config__spad_enables_rtn_5;\n+\t*(pbuffer +  6) = pdata->global_config__spad_enables_rtn_6;\n+\t*(pbuffer +  7) = pdata->global_config__spad_enables_rtn_7;\n+\t*(pbuffer +  8) = pdata->global_config__spad_enables_rtn_8;\n+\t*(pbuffer +  9) = pdata->global_config__spad_enables_rtn_9;\n+\t*(pbuffer + 10) = pdata->global_config__spad_enables_rtn_10;\n+\t*(pbuffer + 11) = pdata->global_config__spad_enables_rtn_11;\n+\t*(pbuffer + 12) = pdata->global_config__spad_enables_rtn_12;\n+\t*(pbuffer + 13) = pdata->global_config__spad_enables_rtn_13;\n+\t*(pbuffer + 14) = pdata->global_config__spad_enables_rtn_14;\n+\t*(pbuffer + 15) = pdata->global_config__spad_enables_rtn_15;\n+\t*(pbuffer + 16) = pdata->global_config__spad_enables_rtn_16;\n+\t*(pbuffer + 17) = pdata->global_config__spad_enables_rtn_17;\n+\t*(pbuffer + 18) = pdata->global_config__spad_enables_rtn_18;\n+\t*(pbuffer + 19) = pdata->global_config__spad_enables_rtn_19;\n+\t*(pbuffer + 20) = pdata->global_config__spad_enables_rtn_20;\n+\t*(pbuffer + 21) = pdata->global_config__spad_enables_rtn_21;\n+\t*(pbuffer + 22) = pdata->global_config__spad_enables_rtn_22;\n+\t*(pbuffer + 23) = pdata->global_config__spad_enables_rtn_23;\n+\t*(pbuffer + 24) = pdata->global_config__spad_enables_rtn_24;\n+\t*(pbuffer + 25) = pdata->global_config__spad_enables_rtn_25;\n+\t*(pbuffer + 26) = pdata->global_config__spad_enables_rtn_26;\n+\t*(pbuffer + 27) = pdata->global_config__spad_enables_rtn_27;\n+\t*(pbuffer + 28) = pdata->global_config__spad_enables_rtn_28;\n+\t*(pbuffer + 29) = pdata->global_config__spad_enables_rtn_29;\n+\t*(pbuffer + 30) = pdata->global_config__spad_enables_rtn_30;\n+\t*(pbuffer + 31) = pdata->global_config__spad_enables_rtn_31;\n+}\n+\n+VL53LX_Error VL53LX_set_firmware_enable_register(VL53LX_DEV Dev, uint8_t value)\n+{\n+\tVL53LX_Error status         = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpdev->sys_ctrl.firmware__enable = value;\n+\n+\tstatus = VL53LX_WrByte(Dev, VL53LX_FIRMWARE__ENABLE, pdev->sys_ctrl.firmware__enable);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_disable_firmware(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error status       = VL53LX_ERROR_NONE;\n+\n+\tstatus = VL53LX_set_firmware_enable_register(Dev, 0x00);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_nvm_enable(VL53LX_DEV Dev, uint16_t nvm_ctrl_pulse_width, int32_t nvm_power_up_delay_us)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_disable_firmware(Dev);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_enable_powerforce(Dev);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WaitUs(Dev, VL53LX_ENABLE_POWERFORCE_SETTLING_TIME_US);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WrByte(Dev, VL53LX_RANGING_CORE__NVM_CTRL__PDN, 0x01);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WrByte(Dev, VL53LX_RANGING_CORE__CLK_CTRL1, 0x05);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WaitUs(Dev, nvm_power_up_delay_us);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WrByte(Dev, VL53LX_RANGING_CORE__NVM_CTRL__MODE, 0x01);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WrWord(Dev, VL53LX_RANGING_CORE__NVM_CTRL__PULSE_WIDTH_MSB, nvm_ctrl_pulse_width);\n+\n+\treturn status;\n+}\n+\n+\n+VL53LX_Error VL53LX_nvm_read(VL53LX_DEV Dev, uint8_t start_address, uint8_t count, uint8_t *pdata)\n+{\n+\tVL53LX_Error status   = VL53LX_ERROR_NONE;\n+\tuint8_t      nvm_addr = 0;\n+\n+\tfor (nvm_addr = start_address;\n+\t\tnvm_addr < (start_address+count) ; nvm_addr++) {\n+\n+\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\tstatus = VL53LX_WrByte(Dev, VL53LX_RANGING_CORE__NVM_CTRL__ADDR, nvm_addr);\n+\n+\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\tstatus = VL53LX_WrByte(Dev, VL53LX_RANGING_CORE__NVM_CTRL__READN, 0x00);\n+\n+\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\tstatus = VL53LX_WaitUs(Dev, VL53LX_NVM_READ_TRIGGER_DELAY_US);\n+\n+\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\tstatus = VL53LX_WrByte(Dev, VL53LX_RANGING_CORE__NVM_CTRL__READN, 0x01);\n+\n+\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\tstatus = VL53LX_ReadMulti(Dev, VL53LX_RANGING_CORE__NVM_CTRL__DATAOUT_MMM, pdata, 4);\n+\n+\t\tpdata = pdata + 4;\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_enable_firmware(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tstatus = VL53LX_set_firmware_enable_register(Dev, 0x01);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_nvm_disable(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WrByte(Dev, VL53LX_RANGING_CORE__NVM_CTRL__READN, 0x01);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WrByte(Dev, VL53LX_RANGING_CORE__NVM_CTRL__PDN, 0x00);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_disable_powerforce(Dev);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_enable_firmware(Dev);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_read_nvm_raw_data(VL53LX_DEV Dev, uint8_t start_address, uint8_t count, uint8_t *pnvm_raw_data)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_nvm_enable(Dev, 0x0004, VL53LX_NVM_POWER_UP_DELAY_US);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_nvm_read(Dev, start_address, count, pnvm_raw_data);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_nvm_disable(Dev);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_nvm_decode_optical_centre(uint16_t buf_size, uint8_t *pbuffer, VL53LX_optical_centre_t *pdata)\n+{\n+\tVL53LX_Error status   = VL53LX_ERROR_NONE;\n+\tuint16_t  tmp = 0;\n+\n+\tif (buf_size < VL53LX_NVM__FMT__OPTICAL_CENTRE_DATA_SIZE)\n+\t\treturn VL53LX_ERROR_BUFFER_TOO_SMALL;\n+\n+\ttmp  = 0x0100;\n+\ttmp -= (uint16_t)*(pbuffer + 2);\n+\tif (tmp > 0x0FF)\n+\t\ttmp = 0;\n+\n+\tpdata->x_centre = (uint8_t)tmp;\n+\tpdata->y_centre = *(pbuffer + 3);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_read_nvm_optical_centre(VL53LX_DEV Dev, VL53LX_optical_centre_t *pcentre)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tuint8_t nvm_data[VL53LX_NVM__FMT__OPTICAL_CENTRE_DATA_SIZE];\n+\n+\tstatus = VL53LX_read_nvm_raw_data(Dev, (uint8_t)(VL53LX_NVM__FMT__OPTICAL_CENTRE_DATA_INDEX >> 2), (uint8_t)(VL53LX_NVM__FMT__OPTICAL_CENTRE_DATA_SIZE >> 2), nvm_data);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_nvm_decode_optical_centre(VL53LX_NVM__FMT__OPTICAL_CENTRE_DATA_SIZE, nvm_data, pcentre);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_nvm_decode_cal_peak_rate_map(uint16_t buf_size, uint8_t *pbuffer, VL53LX_cal_peak_rate_map_t *pdata)\n+{\n+\tVL53LX_Error status   = VL53LX_ERROR_NONE;\n+\n+\tuint8_t   *ptmp = NULL;\n+\tuint8_t       i = 0;\n+\n+\tif (buf_size < VL53LX_NVM__FMT__CAL_PEAK_RATE_MAP_DATA_SIZE)\n+\t\treturn VL53LX_ERROR_BUFFER_TOO_SMALL;\n+\n+\tpdata->cal_distance_mm = (uint16_t)VL53LX_i2c_decode_uint16_t(2, pbuffer);\n+\n+\tpdata->cal_reflectance_pc = (uint16_t)VL53LX_i2c_decode_uint16_t(2, pbuffer + 2);\n+\tpdata->cal_reflectance_pc = pdata->cal_reflectance_pc >> 6;\n+\n+\tpdata->max_samples = VL53LX_NVM_PEAK_RATE_MAP_SAMPLES;\n+\tpdata->width       = VL53LX_NVM_PEAK_RATE_MAP_WIDTH;\n+\tpdata->height      = VL53LX_NVM_PEAK_RATE_MAP_HEIGHT;\n+\n+\tptmp = pbuffer + 4;\n+\tfor (i = 0 ; i < VL53LX_NVM_PEAK_RATE_MAP_SAMPLES ; i++) {\n+\t\tpdata->peak_rate_mcps[i] = (uint16_t)VL53LX_i2c_decode_uint16_t(2, ptmp);\n+\t\tptmp += 2;\n+\t}\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_read_nvm_cal_peak_rate_map(VL53LX_DEV Dev, VL53LX_cal_peak_rate_map_t *pcal_data)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tuint8_t nvm_data[VL53LX_NVM__FMT__CAL_PEAK_RATE_MAP_DATA_SIZE];\n+\n+\tstatus = VL53LX_read_nvm_raw_data(Dev, (uint8_t)(VL53LX_NVM__FMT__CAL_PEAK_RATE_MAP_DATA_INDEX >> 2), (uint8_t)(VL53LX_NVM__FMT__CAL_PEAK_RATE_MAP_DATA_SIZE >> 2), nvm_data);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_nvm_decode_cal_peak_rate_map(VL53LX_NVM__FMT__CAL_PEAK_RATE_MAP_DATA_SIZE, nvm_data, pcal_data);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_nvm_decode_additional_offset_cal_data(uint16_t buf_size, uint8_t *pbuffer, VL53LX_additional_offset_cal_data_t *pdata)\n+{\n+\tVL53LX_Error status   = VL53LX_ERROR_NONE;\n+\tif (buf_size < VL53LX_NVM__FMT__ADDITIONAL_OFFSET_CAL_DATA_SIZE)\n+\t\treturn VL53LX_ERROR_BUFFER_TOO_SMALL;\n+\n+\tpdata->result__mm_inner_actual_effective_spads = (uint16_t)VL53LX_i2c_decode_uint16_t(2, pbuffer);\n+\tpdata->result__mm_outer_actual_effective_spads = (uint16_t)VL53LX_i2c_decode_uint16_t(2, pbuffer + 2);\n+\tpdata->result__mm_inner_peak_signal_count_rtn_mcps = (uint16_t)VL53LX_i2c_decode_uint16_t(2, pbuffer + 4);\n+\tpdata->result__mm_outer_peak_signal_count_rtn_mcps = (uint16_t)VL53LX_i2c_decode_uint16_t(2, pbuffer + 6);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_read_nvm_additional_offset_cal_data(VL53LX_DEV Dev, VL53LX_additional_offset_cal_data_t *pcal_data)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tuint8_t nvm_data[VL53LX_NVM__FMT__ADDITIONAL_OFFSET_CAL_DATA_SIZE];\n+\n+\tstatus = VL53LX_read_nvm_raw_data(Dev, (uint8_t)(VL53LX_NVM__FMT__ADDITIONAL_OFFSET_CAL_DATA_INDEX >> 2), (uint8_t)(VL53LX_NVM__FMT__ADDITIONAL_OFFSET_CAL_DATA_SIZE >> 2), nvm_data);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_nvm_decode_additional_offset_cal_data(VL53LX_NVM__FMT__ADDITIONAL_OFFSET_CAL_DATA_SIZE, nvm_data, pcal_data);\n+\n+\treturn status;\n+}\n+\n+void VL53LX_spad_number_to_byte_bit_index(uint8_t spad_number, uint8_t *pbyte_index, uint8_t *pbit_index, uint8_t *pbit_mask)\n+{\n+\t*pbyte_index  = spad_number >> 3;\n+\t*pbit_index   = spad_number & 0x07;\n+\t*pbit_mask    = 0x01 << *pbit_index;\n+}\n+\n+uint8_t VL53LX_is_aperture_location(uint8_t row, uint8_t col)\n+{\n+\tuint8_t is_aperture = 0;\n+\tuint8_t mod_row     = row % 4;\n+\tuint8_t mod_col     = col % 4;\n+\n+\tif (mod_row == 0 && mod_col == 2)\n+\t\tis_aperture = 1;\n+\n+\tif (mod_row == 2 && mod_col == 0)\n+\t\tis_aperture = 1;\n+\n+\treturn is_aperture;\n+}\n+\n+void VL53LX_decode_row_col(uint8_t spad_number, uint8_t *prow, uint8_t *pcol)\n+{\n+\tif (spad_number > 127) {\n+\t\t*prow = 8 + ((255-spad_number) & 0x07);\n+\t\t*pcol = (spad_number-128) >> 3;\n+\t} else {\n+\t\t*prow = spad_number & 0x07;\n+\t\t*pcol = (127-spad_number) >> 3;\n+\t}\n+}\n+\n+void VL53LX_decode_zone_size(uint8_t encoded_xy_size, uint8_t *pwidth, uint8_t *pheight)\n+{\n+\t*pheight = encoded_xy_size >> 4;\n+\t*pwidth  = encoded_xy_size & 0x0F;\n+}\n+\n+void VL53LX_decode_zone_limits(uint8_t encoded_xy_centre, uint8_t encoded_xy_size, int16_t *px_ll, int16_t *py_ll, int16_t *px_ur, int16_t *py_ur)\n+{\n+\tuint8_t x_centre = 0;\n+\tuint8_t y_centre = 0;\n+\tuint8_t width    = 0;\n+\tuint8_t height   = 0;\n+\n+\tVL53LX_decode_row_col(encoded_xy_centre, &y_centre, &x_centre);\n+\tVL53LX_decode_zone_size(encoded_xy_size, &width, &height);\n+\n+\t*px_ll = (int16_t)x_centre - ((int16_t)width + 1) / 2;\n+\tif (*px_ll < 0)\n+\t\t*px_ll = 0;\n+\n+\t*px_ur = *px_ll + (int16_t)width;\n+\tif (*px_ur > (VL53LX_SPAD_ARRAY_WIDTH-1))\n+\t\t*px_ur = VL53LX_SPAD_ARRAY_WIDTH-1;\n+\n+\t*py_ll = (int16_t)y_centre - ((int16_t)height + 1) / 2;\n+\tif (*py_ll < 0)\n+\t\t*py_ll = 0;\n+\n+\t*py_ur = *py_ll + (int16_t)height;\n+\tif (*py_ur > (VL53LX_SPAD_ARRAY_HEIGHT-1))\n+\t\t*py_ur = VL53LX_SPAD_ARRAY_HEIGHT-1;\n+}\n+\n+void VL53LX_calc_mm_effective_spads(\n+\tuint8_t     encoded_mm_roi_centre,\n+\tuint8_t     encoded_mm_roi_size,\n+\tuint8_t     encoded_zone_centre,\n+\tuint8_t     encoded_zone_size,\n+\tuint8_t    *pgood_spads,\n+\tuint16_t    aperture_attenuation,\n+\tuint16_t   *pmm_inner_effective_spads,\n+\tuint16_t   *pmm_outer_effective_spads)\n+{\n+\tint16_t   x         = 0;\n+\tint16_t   y         = 0;\n+\tint16_t   mm_x_ll   = 0;\n+\tint16_t   mm_y_ll   = 0;\n+\tint16_t   mm_x_ur   = 0;\n+\tint16_t   mm_y_ur   = 0;\n+\tint16_t   zone_x_ll = 0;\n+\tint16_t   zone_y_ll = 0;\n+\tint16_t   zone_x_ur = 0;\n+\tint16_t   zone_y_ur = 0;\n+\tuint8_t   spad_number = 0;\n+\tuint8_t   byte_index  = 0;\n+\tuint8_t   bit_index   = 0;\n+\tuint8_t   bit_mask    = 0;\n+\n+\tuint8_t   is_aperture = 0;\n+\tuint16_t  spad_attenuation = 0;\n+\n+\tVL53LX_decode_zone_limits(encoded_mm_roi_centre, encoded_mm_roi_size, &mm_x_ll, &mm_y_ll, &mm_x_ur, &mm_y_ur);\n+\tVL53LX_decode_zone_limits(encoded_zone_centre, encoded_zone_size, &zone_x_ll, &zone_y_ll, &zone_x_ur, &zone_y_ur);\n+\n+\t*pmm_inner_effective_spads = 0;\n+\t*pmm_outer_effective_spads = 0;\n+\n+\tfor (y = zone_y_ll; y <= zone_y_ur; y++) {\n+\t\tfor (x = zone_x_ll; x <= zone_x_ur; x++) {\n+\t\t\tVL53LX_encode_row_col((uint8_t)y, (uint8_t)x, &spad_number);\n+\t\t\tVL53LX_spad_number_to_byte_bit_index(spad_number, &byte_index, &bit_index, &bit_mask);\n+\t\t\tif ((pgood_spads[byte_index] & bit_mask) > 0) {\n+\t\t\t\tis_aperture = VL53LX_is_aperture_location((uint8_t)y, (uint8_t)x);\n+\t\t\t\tif (is_aperture > 0)\n+\t\t\t\t\tspad_attenuation = aperture_attenuation;\n+\t\t\t\telse\n+\t\t\t\t\tspad_attenuation = 0x0100;\n+\t\t\t\tif (x >= mm_x_ll && x <= mm_x_ur && y >= mm_y_ll && y <= mm_y_ur)\n+\t\t\t\t\t*pmm_inner_effective_spads += spad_attenuation;\n+\t\t\t\telse\n+\t\t\t\t\t*pmm_outer_effective_spads += spad_attenuation;\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+VL53LX_Error VL53LX_nvm_decode_fmt_range_results_data(uint16_t buf_size, uint8_t *pbuffer, VL53LX_decoded_nvm_fmt_range_data_t *pdata)\n+{\n+\tVL53LX_Error status   = VL53LX_ERROR_NONE;\n+\tif (buf_size < VL53LX_NVM__FMT__RANGE_RESULTS__SIZE_BYTES)\n+\t\treturn VL53LX_ERROR_BUFFER_TOO_SMALL;\n+\n+\tpdata->result__actual_effective_rtn_spads = (uint16_t)VL53LX_i2c_decode_uint16_t(2, pbuffer);\n+\tpdata->ref_spad_array__num_requested_ref_spads = *(pbuffer+2);\n+\tpdata->ref_spad_array__ref_location = *(pbuffer+3);\n+\tpdata->result__peak_signal_count_rate_rtn_mcps = (uint16_t)VL53LX_i2c_decode_uint16_t(2, pbuffer + 4);\n+\tpdata->result__ambient_count_rate_rtn_mcps = (uint16_t)VL53LX_i2c_decode_uint16_t(2, pbuffer + 6);\n+\tpdata->result__peak_signal_count_rate_ref_mcps = (uint16_t)VL53LX_i2c_decode_uint16_t(2, pbuffer + 8);\n+\tpdata->result__ambient_count_rate_ref_mcps = (uint16_t)VL53LX_i2c_decode_uint16_t(2, pbuffer + 10);\n+\tpdata->measured_distance_mm = (uint16_t)VL53LX_i2c_decode_uint16_t(2, pbuffer + 12);\n+\tpdata->measured_distance_stdev_mm = (uint16_t)VL53LX_i2c_decode_uint16_t(2, pbuffer + 14);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_read_nvm_fmt_range_results_data(VL53LX_DEV Dev, uint16_t range_results_select, VL53LX_decoded_nvm_fmt_range_data_t *prange_data)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tuint8_t nvm_data[VL53LX_NVM__FMT__RANGE_RESULTS__SIZE_BYTES];\n+\n+\tstatus = VL53LX_read_nvm_raw_data(Dev, (uint8_t)(range_results_select >> 2), (uint8_t)(VL53LX_NVM__FMT__RANGE_RESULTS__SIZE_BYTES >> 2),\n+nvm_data);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_nvm_decode_fmt_range_results_data(VL53LX_NVM__FMT__RANGE_RESULTS__SIZE_BYTES, nvm_data, prange_data);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_get_mode_mitigation_roi(VL53LX_DEV Dev, VL53LX_user_zone_t *pmm_roi)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tuint8_t  x       = 0;\n+\tuint8_t  y       = 0;\n+\tuint8_t  xy_size = 0;\n+\n+\tVL53LX_decode_row_col(pdev->nvm_copy_data.roi_config__mode_roi_centre_spad, &y, &x);\n+\n+\tpmm_roi->x_centre = x;\n+\tpmm_roi->y_centre = y;\n+\n+\txy_size = pdev->nvm_copy_data.roi_config__mode_roi_xy_size;\n+\n+\tpmm_roi->height = xy_size >> 4;\n+\tpmm_roi->width  = xy_size & 0x0F;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_read_p2p_data(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error status       = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_hist_post_process_config_t *pHP = &(pdev->histpostprocess);\n+\tVL53LX_customer_nvm_managed_t *pN = &(pdev->customer);\n+\tVL53LX_additional_offset_cal_data_t *pCD = &(pdev->add_off_cal_data);\n+\tVL53LX_decoded_nvm_fmt_range_data_t fmt_rrd;\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_get_static_nvm_managed(Dev, &(pdev->stat_nvm));\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_get_customer_nvm_managed(Dev, &(pdev->customer));\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tstatus = VL53LX_get_nvm_copy_data(Dev, &(pdev->nvm_copy_data));\n+\n+\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\tVL53LX_copy_rtn_good_spads_to_buffer(&(pdev->nvm_copy_data), &(pdev->rtn_good_spads[0]));\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tpHP->algo__crosstalk_compensation_plane_offset_kcps =\n+\t\tpN->algo__crosstalk_compensation_plane_offset_kcps;\n+\t\tpHP->algo__crosstalk_compensation_x_plane_gradient_kcps =\n+\t\tpN->algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\t\tpHP->algo__crosstalk_compensation_y_plane_gradient_kcps =\n+\t\tpN->algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_read_nvm_optical_centre(Dev, &(pdev->optical_centre));\n+\n+\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_read_nvm_cal_peak_rate_map(Dev, &(pdev->cal_peak_rate_map));\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tstatus = VL53LX_read_nvm_additional_offset_cal_data(Dev, &(pdev->add_off_cal_data));\n+\n+\t\tif (pCD->result__mm_inner_peak_signal_count_rtn_mcps == 0 && pCD->result__mm_outer_peak_signal_count_rtn_mcps == 0) {\n+\t\t\tpCD->result__mm_inner_peak_signal_count_rtn_mcps = 0x0080;\n+\t\t\tpCD->result__mm_outer_peak_signal_count_rtn_mcps = 0x0180;\n+\n+\t\t\tVL53LX_calc_mm_effective_spads(pdev->nvm_copy_data.roi_config__mode_roi_centre_spad, pdev->nvm_copy_data.roi_config__mode_roi_xy_size, 0xC7, 0xFF, &(pdev->rtn_good_spads[0]), VL53LX_RTN_SPAD_APERTURE_TRANSMISSION, &(pCD->result__mm_inner_actual_effective_spads), &(pCD->result__mm_outer_actual_effective_spads));\n+\t\t}\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\n+\t\tstatus = VL53LX_read_nvm_fmt_range_results_data(Dev, VL53LX_NVM__FMT__RANGE_RESULTS__140MM_DARK, &fmt_rrd);\n+\t\tif (status == VL53LX_ERROR_NONE) {\n+\t\t\tpdev->fmt_dmax_cal.ref__actual_effective_spads = fmt_rrd.result__actual_effective_rtn_spads;\n+\t\t\tpdev->fmt_dmax_cal.ref__peak_signal_count_rate_mcps = fmt_rrd.result__peak_signal_count_rate_rtn_mcps;\n+\t\t\tpdev->fmt_dmax_cal.ref__distance_mm = fmt_rrd.measured_distance_mm;\n+\n+\t\t\tif (pdev->cal_peak_rate_map.cal_reflectance_pc != 0) {\n+\t\t\t\tpdev->fmt_dmax_cal.ref_reflectance_pc = pdev->cal_peak_rate_map.cal_reflectance_pc;\n+\t\t\t} else {\n+\t\t\t\tpdev->fmt_dmax_cal.ref_reflectance_pc = 0x0014;\n+\t\t\t}\n+\t\t\tpdev->fmt_dmax_cal.coverglass_transmission = 0x0100;\n+\t\t}\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_RdWord(Dev, VL53LX_RESULT__OSC_CALIBRATE_VAL, &(pdev->dbg_results.result__osc_calibrate_val));\n+\n+\tif (pdev->stat_nvm.osc_measured__fast_osc__frequency < 0x1000) {\n+\t\tpdev->stat_nvm.osc_measured__fast_osc__frequency = 0xBCCC;\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_get_mode_mitigation_roi(Dev, &(pdev->mm_roi));\n+\n+\tif (pdev->optical_centre.x_centre == 0 && pdev->optical_centre.y_centre == 0) {\n+\t\tpdev->optical_centre.x_centre = pdev->mm_roi.x_centre << 4;\n+\t\tpdev->optical_centre.y_centre = pdev->mm_roi.y_centre << 4;\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_init_refspadchar_config_struct(VL53LX_refspadchar_config_t *pdata)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tpdata->device_test_mode          = VL53LX_TUNINGPARM_REFSPADCHAR_DEVICE_TEST_MODE_DEFAULT;\n+\tpdata->VL53LX_p_005              = VL53LX_TUNINGPARM_REFSPADCHAR_VCSEL_PERIOD_DEFAULT;\n+\tpdata->timeout_us                = VL53LX_TUNINGPARM_REFSPADCHAR_PHASECAL_TIMEOUT_US_DEFAULT;\n+\tpdata->target_count_rate_mcps    = VL53LX_TUNINGPARM_REFSPADCHAR_TARGET_COUNT_RATE_MCPS_DEFAULT;\n+\tpdata->min_count_rate_limit_mcps = VL53LX_TUNINGPARM_REFSPADCHAR_MIN_COUNTRATE_LIMIT_MCPS_DEFAULT;\n+\tpdata->max_count_rate_limit_mcps = VL53LX_TUNINGPARM_REFSPADCHAR_MAX_COUNTRATE_LIMIT_MCPS_DEFAULT;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_init_ssc_config_struct(VL53LX_ssc_config_t *pdata)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tpdata->array_select = VL53LX_DEVICESSCARRAY_RTN;\n+\tpdata->VL53LX_p_005 = VL53LX_TUNINGPARM_SPADMAP_VCSEL_PERIOD_DEFAULT;\n+\tpdata->vcsel_start  = VL53LX_TUNINGPARM_SPADMAP_VCSEL_START_DEFAULT;\n+\tpdata->vcsel_width = 0x02;\n+\tpdata->timeout_us   = 36000;\n+\tpdata->rate_limit_mcps = VL53LX_TUNINGPARM_SPADMAP_RATE_LIMIT_MCPS_DEFAULT;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_init_xtalk_config_struct(VL53LX_customer_nvm_managed_t *pnvm, VL53LX_xtalk_config_t *pdata)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tpdata->algo__crosstalk_compensation_plane_offset_kcps      = pnvm->algo__crosstalk_compensation_plane_offset_kcps;\n+\tpdata->algo__crosstalk_compensation_x_plane_gradient_kcps  = pnvm->algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\tpdata->algo__crosstalk_compensation_y_plane_gradient_kcps  = pnvm->algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\n+\tpdata->nvm_default__crosstalk_compensation_plane_offset_kcps      = (uint32_t)pnvm->algo__crosstalk_compensation_plane_offset_kcps;\n+\tpdata->nvm_default__crosstalk_compensation_x_plane_gradient_kcps  = pnvm->algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\tpdata->nvm_default__crosstalk_compensation_y_plane_gradient_kcps  = pnvm->algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\n+\tpdata->histogram_mode_crosstalk_margin_kcps                = VL53LX_TUNINGPARM_HIST_XTALK_MARGIN_KCPS_DEFAULT;\n+\tpdata->lite_mode_crosstalk_margin_kcps                     = VL53LX_TUNINGPARM_LITE_XTALK_MARGIN_KCPS_DEFAULT;\n+\n+\tpdata->crosstalk_range_ignore_threshold_mult = VL53LX_TUNINGPARM_LITE_RIT_MULT_DEFAULT;\n+\n+\tif ((pdata->algo__crosstalk_compensation_plane_offset_kcps == 0x00) && (pdata->algo__crosstalk_compensation_x_plane_gradient_kcps == 0x00) && (pdata->algo__crosstalk_compensation_y_plane_gradient_kcps == 0x00))\n+\t\tpdata->global_crosstalk_compensation_enable = 0x00;\n+\telse\n+\t\tpdata->global_crosstalk_compensation_enable = 0x01;\n+\n+\tif ((status == VL53LX_ERROR_NONE) && (pdata->global_crosstalk_compensation_enable == 0x01)) {\n+\t\tpdata->crosstalk_range_ignore_threshold_rate_mcps = VL53LX_calc_range_ignore_threshold(pdata->algo__crosstalk_compensation_plane_offset_kcps, pdata->algo__crosstalk_compensation_x_plane_gradient_kcps, pdata->algo__crosstalk_compensation_y_plane_gradient_kcps, pdata->crosstalk_range_ignore_threshold_mult);\n+\t} else {\n+\t\tpdata->crosstalk_range_ignore_threshold_rate_mcps = 0;\n+\t}\n+\n+\tpdata->algo__crosstalk_detect_min_valid_range_mm  = VL53LX_TUNINGPARM_XTALK_DETECT_MIN_VALID_RANGE_MM_DEFAULT;\n+\tpdata->algo__crosstalk_detect_max_valid_range_mm  = VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RANGE_MM_DEFAULT;\n+\tpdata->algo__crosstalk_detect_max_valid_rate_kcps = VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RATE_KCPS_DEFAULT;\n+\tpdata->algo__crosstalk_detect_max_sigma_mm        = VL53LX_TUNINGPARM_XTALK_DETECT_MAX_SIGMA_MM_DEFAULT;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_init_xtalk_extract_config_struct(VL53LX_xtalkextract_config_t *pdata)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tpdata->dss_config__target_total_rate_mcps          = VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_RATE_MCPS_DEFAULT;\n+\tpdata->mm_config_timeout_us                        = VL53LX_TUNINGPARM_XTALK_EXTRACT_DSS_TIMEOUT_US_DEFAULT;\n+\tpdata->num_of_samples                              = VL53LX_TUNINGPARM_XTALK_EXTRACT_NUM_OF_SAMPLES_DEFAULT;\n+\tpdata->phasecal_config_timeout_us                  = VL53LX_TUNINGPARM_XTALK_EXTRACT_PHASECAL_TIMEOUT_US_DEFAULT;\n+\tpdata->range_config_timeout_us                     = VL53LX_TUNINGPARM_XTALK_EXTRACT_BIN_TIMEOUT_US_DEFAULT;\n+\tpdata->algo__crosstalk_extract_min_valid_range_mm  = VL53LX_TUNINGPARM_XTALK_EXTRACT_MIN_FILTER_THRESH_MM_DEFAULT;\n+\tpdata->algo__crosstalk_extract_max_valid_range_mm  = VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_FILTER_THRESH_MM_DEFAULT;\n+\tpdata->algo__crosstalk_extract_max_valid_rate_kcps = VL53LX_TUNINGPARM_XTALK_EXTRACT_MAX_VALID_RATE_KCPS_DEFAULT;\n+\tpdata->algo__crosstalk_extract_max_sigma_mm        = VL53LX_TUNINGPARM_XTALK_EXTRACT_SIGMA_THRESHOLD_MM_DEFAULT;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_init_offset_cal_config_struct(VL53LX_offsetcal_config_t *pdata)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tpdata->dss_config__target_total_rate_mcps          = VL53LX_TUNINGPARM_OFFSET_CAL_DSS_RATE_MCPS_DEFAULT;\n+\tpdata->phasecal_config_timeout_us                  = VL53LX_TUNINGPARM_OFFSET_CAL_PHASECAL_TIMEOUT_US_DEFAULT;\n+\tpdata->range_config_timeout_us                     = VL53LX_TUNINGPARM_OFFSET_CAL_RANGE_TIMEOUT_US_DEFAULT;\n+\tpdata->mm_config_timeout_us                        = VL53LX_TUNINGPARM_OFFSET_CAL_MM_TIMEOUT_US_DEFAULT;\n+\tpdata->pre_num_of_samples                          = VL53LX_TUNINGPARM_OFFSET_CAL_PRE_SAMPLES_DEFAULT;\n+\tpdata->mm1_num_of_samples                          = VL53LX_TUNINGPARM_OFFSET_CAL_MM1_SAMPLES_DEFAULT;\n+\tpdata->mm2_num_of_samples                          = VL53LX_TUNINGPARM_OFFSET_CAL_MM2_SAMPLES_DEFAULT;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_init_zone_cal_config_struct(VL53LX_zonecal_config_t *pdata)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tpdata->dss_config__target_total_rate_mcps          = VL53LX_TUNINGPARM_ZONE_CAL_DSS_RATE_MCPS_DEFAULT;\n+\tpdata->phasecal_config_timeout_us                  = VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_TIMEOUT_US_DEFAULT;\n+\tpdata->range_config_timeout_us                     = VL53LX_TUNINGPARM_ZONE_CAL_RANGE_TIMEOUT_US_DEFAULT;\n+\tpdata->mm_config_timeout_us                        = VL53LX_TUNINGPARM_ZONE_CAL_DSS_TIMEOUT_US_DEFAULT;\n+\tpdata->phasecal_num_of_samples                     = VL53LX_TUNINGPARM_ZONE_CAL_PHASECAL_NUM_SAMPLES_DEFAULT;\n+\tpdata->zone_num_of_samples                         = VL53LX_TUNINGPARM_ZONE_CAL_ZONE_NUM_SAMPLES_DEFAULT;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_init_hist_post_process_config_struct(uint8_t xtalk_compensation_enable, VL53LX_hist_post_process_config_t *pdata)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tpdata->hist_algo_select = VL53LX_TUNINGPARM_HIST_ALGO_SELECT_DEFAULT;\n+\tpdata->hist_target_order = VL53LX_TUNINGPARM_HIST_TARGET_ORDER_DEFAULT;\n+\n+\tpdata->filter_woi0                   = VL53LX_TUNINGPARM_HIST_FILTER_WOI_0_DEFAULT;\n+\tpdata->filter_woi1                   = VL53LX_TUNINGPARM_HIST_FILTER_WOI_1_DEFAULT;\n+\n+\tpdata->hist_amb_est_method = VL53LX_TUNINGPARM_HIST_AMB_EST_METHOD_DEFAULT;\n+\n+\tpdata->ambient_thresh_sigma0         = VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_0_DEFAULT;\n+\tpdata->ambient_thresh_sigma1         = VL53LX_TUNINGPARM_HIST_AMB_THRESH_SIGMA_1_DEFAULT;\n+\n+\tpdata->ambient_thresh_events_scaler     = VL53LX_TUNINGPARM_HIST_AMB_EVENTS_SCALER_DEFAULT;\n+\n+\tpdata->min_ambient_thresh_events     = VL53LX_TUNINGPARM_HIST_MIN_AMB_THRESH_EVENTS_DEFAULT;\n+\n+\tpdata->noise_threshold               = VL53LX_TUNINGPARM_HIST_NOISE_THRESHOLD_DEFAULT;\n+\n+\tpdata->signal_total_events_limit     = VL53LX_TUNINGPARM_HIST_SIGNAL_TOTAL_EVENTS_LIMIT_DEFAULT;\n+\tpdata->sigma_estimator__sigma_ref_mm = VL53LX_TUNINGPARM_HIST_SIGMA_EST_REF_MM_DEFAULT;\n+\n+\tpdata->sigma_thresh                  = VL53LX_TUNINGPARM_HIST_SIGMA_THRESH_MM_DEFAULT;\n+\tpdata->range_offset_mm            =      0;\n+\tpdata->gain_factor                = VL53LX_TUNINGPARM_HIST_GAIN_FACTOR_DEFAULT;\n+\n+\tpdata->valid_phase_low = 0x08;\n+\tpdata->valid_phase_high = 0x88;\n+\n+\tpdata->algo__consistency_check__phase_tolerance = VL53LX_TUNINGPARM_CONSISTENCY_HIST_PHASE_TOLERANCE_DEFAULT;\n+\tpdata->algo__consistency_check__event_sigma = VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA_DEFAULT;\n+\tpdata->algo__consistency_check__event_min_spad_count = VL53LX_TUNINGPARM_CONSISTENCY_HIST_EVENT_SIGMA_MIN_SPAD_LIMIT_DEFAULT;\n+\tpdata->algo__consistency_check__min_max_tolerance = VL53LX_TUNINGPARM_CONSISTENCY_HIST_MIN_MAX_TOLERANCE_MM_DEFAULT;\n+\tpdata->algo__crosstalk_compensation_enable = xtalk_compensation_enable;\n+\tpdata->algo__crosstalk_detect_min_valid_range_mm  = VL53LX_TUNINGPARM_XTALK_DETECT_MIN_VALID_RANGE_MM_DEFAULT;\n+\tpdata->algo__crosstalk_detect_max_valid_range_mm  = VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RANGE_MM_DEFAULT;\n+\tpdata->algo__crosstalk_detect_max_valid_rate_kcps = VL53LX_TUNINGPARM_XTALK_DETECT_MAX_VALID_RATE_KCPS_DEFAULT;\n+\tpdata->algo__crosstalk_detect_max_sigma_mm        = VL53LX_TUNINGPARM_XTALK_DETECT_MAX_SIGMA_MM_DEFAULT;\n+\n+\tpdata->algo__crosstalk_detect_event_sigma       = VL53LX_TUNINGPARM_XTALK_DETECT_EVENT_SIGMA_DEFAULT;\n+\n+\tpdata->algo__crosstalk_detect_min_max_tolerance   = VL53LX_TUNINGPARM_XTALK_DETECT_MIN_MAX_TOLERANCE_DEFAULT;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_init_hist_gen3_dmax_config_struct(VL53LX_hist_gen3_dmax_config_t *pdata)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tpdata->dss_config__target_total_rate_mcps = 0x1400;\n+\tpdata->dss_config__aperture_attenuation = 0x38;\n+\n+\tpdata->signal_thresh_sigma                 = VL53LX_TUNINGPARM_DMAX_CFG_SIGNAL_THRESH_SIGMA_DEFAULT;\n+\tpdata->ambient_thresh_sigma = 0x70;\n+\tpdata->min_ambient_thresh_events           = 16;\n+\tpdata->signal_total_events_limit           = 100;\n+\tpdata->max_effective_spads = 0xFFFF;\n+\n+\tpdata->target_reflectance_for_dmax_calc[0] = VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_0_DEFAULT;\n+\tpdata->target_reflectance_for_dmax_calc[1] = VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_1_DEFAULT;\n+\tpdata->target_reflectance_for_dmax_calc[2] = VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_2_DEFAULT;\n+\tpdata->target_reflectance_for_dmax_calc[3] = VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_3_DEFAULT;\n+\tpdata->target_reflectance_for_dmax_calc[4] = VL53LX_TUNINGPARM_DMAX_CFG_REFLECTANCE_ARRAY_4_DEFAULT;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_init_tuning_parm_storage_struct(VL53LX_tuning_parm_storage_t *pdata)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tpdata->tp_tuning_parm_version              = VL53LX_TUNINGPARM_VERSION_DEFAULT;\n+\tpdata->tp_tuning_parm_key_table_version    = VL53LX_TUNINGPARM_KEY_TABLE_VERSION_DEFAULT;\n+\tpdata->tp_tuning_parm_lld_version          = VL53LX_TUNINGPARM_LLD_VERSION_DEFAULT;\n+\tpdata->tp_init_phase_rtn_lite_long         = VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_LONG_RANGE_DEFAULT;\n+\tpdata->tp_init_phase_rtn_lite_med          = VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_MED_RANGE_DEFAULT;\n+\tpdata->tp_init_phase_rtn_lite_short        = VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_LITE_SHORT_RANGE_DEFAULT;\n+\tpdata->tp_init_phase_ref_lite_long         = VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_LONG_RANGE_DEFAULT;\n+\tpdata->tp_init_phase_ref_lite_med          = VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_MED_RANGE_DEFAULT;\n+\tpdata->tp_init_phase_ref_lite_short        = VL53LX_TUNINGPARM_INITIAL_PHASE_REF_LITE_SHORT_RANGE_DEFAULT;\n+\tpdata->tp_init_phase_rtn_hist_long         = VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_LONG_RANGE_DEFAULT;\n+\tpdata->tp_init_phase_rtn_hist_med          = VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_MED_RANGE_DEFAULT;\n+\tpdata->tp_init_phase_rtn_hist_short        = VL53LX_TUNINGPARM_INITIAL_PHASE_RTN_HISTO_SHORT_RANGE_DEFAULT;\n+\tpdata->tp_init_phase_ref_hist_long         = VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_LONG_RANGE_DEFAULT;\n+\tpdata->tp_init_phase_ref_hist_med          = VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_MED_RANGE_DEFAULT;\n+\tpdata->tp_init_phase_ref_hist_short        = VL53LX_TUNINGPARM_INITIAL_PHASE_REF_HISTO_SHORT_RANGE_DEFAULT;\n+\tpdata->tp_consistency_lite_phase_tolerance = VL53LX_TUNINGPARM_CONSISTENCY_LITE_PHASE_TOLERANCE_DEFAULT;\n+\tpdata->tp_phasecal_target                  = VL53LX_TUNINGPARM_PHASECAL_TARGET_DEFAULT;\n+\tpdata->tp_cal_repeat_rate                  = VL53LX_TUNINGPARM_LITE_CAL_REPEAT_RATE_DEFAULT;\n+\tpdata->tp_lite_min_clip                    = VL53LX_TUNINGPARM_LITE_MIN_CLIP_MM_DEFAULT;\n+\tpdata->tp_lite_long_sigma_thresh_mm        = VL53LX_TUNINGPARM_LITE_LONG_SIGMA_THRESH_MM_DEFAULT;\n+\tpdata->tp_lite_med_sigma_thresh_mm         = VL53LX_TUNINGPARM_LITE_MED_SIGMA_THRESH_MM_DEFAULT;\n+\tpdata->tp_lite_short_sigma_thresh_mm       = VL53LX_TUNINGPARM_LITE_SHORT_SIGMA_THRESH_MM_DEFAULT;\n+\tpdata->tp_lite_long_min_count_rate_rtn_mcps  = VL53LX_TUNINGPARM_LITE_LONG_MIN_COUNT_RATE_RTN_MCPS_DEFAULT;\n+\tpdata->tp_lite_med_min_count_rate_rtn_mcps   = VL53LX_TUNINGPARM_LITE_MED_MIN_COUNT_RATE_RTN_MCPS_DEFAULT;\n+\tpdata->tp_lite_short_min_count_rate_rtn_mcps = VL53LX_TUNINGPARM_LITE_SHORT_MIN_COUNT_RATE_RTN_MCPS_DEFAULT;\n+\tpdata->tp_lite_sigma_est_pulse_width_ns      = VL53LX_TUNINGPARM_LITE_SIGMA_EST_PULSE_WIDTH_DEFAULT;\n+\tpdata->tp_lite_sigma_est_amb_width_ns        = VL53LX_TUNINGPARM_LITE_SIGMA_EST_AMB_WIDTH_NS_DEFAULT;\n+\tpdata->tp_lite_sigma_ref_mm                  = VL53LX_TUNINGPARM_LITE_SIGMA_REF_MM_DEFAULT;\n+\tpdata->tp_lite_seed_cfg                      = VL53LX_TUNINGPARM_LITE_SEED_CONFIG_DEFAULT;\n+\tpdata->tp_timed_seed_cfg                     = VL53LX_TUNINGPARM_TIMED_SEED_CONFIG_DEFAULT;\n+\tpdata->tp_lite_quantifier                    = VL53LX_TUNINGPARM_LITE_QUANTIFIER_DEFAULT;\n+\tpdata->tp_lite_first_order_select            = VL53LX_TUNINGPARM_LITE_FIRST_ORDER_SELECT_DEFAULT;\n+\tpdata->tp_uwr_enable = VL53LX_TUNINGPARM_UWR_ENABLE_DEFAULT;\n+\tpdata->tp_uwr_med_z_1_min = VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_1_MIN_DEFAULT;\n+\tpdata->tp_uwr_med_z_1_max = VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_1_MAX_DEFAULT;\n+\tpdata->tp_uwr_med_z_2_min = VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_2_MIN_DEFAULT;\n+\tpdata->tp_uwr_med_z_2_max = VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_2_MAX_DEFAULT;\n+\tpdata->tp_uwr_med_z_3_min = VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_3_MIN_DEFAULT;\n+\tpdata->tp_uwr_med_z_3_max = VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_3_MAX_DEFAULT;\n+\tpdata->tp_uwr_med_z_4_min = VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_4_MIN_DEFAULT;\n+\tpdata->tp_uwr_med_z_4_max = VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_4_MAX_DEFAULT;\n+\tpdata->tp_uwr_med_z_5_min = VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_5_MIN_DEFAULT;\n+\tpdata->tp_uwr_med_z_5_max = VL53LX_TUNINGPARM_UWR_MEDIUM_ZONE_5_MAX_DEFAULT;\n+\tpdata->tp_uwr_med_corr_z_1_rangea = VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_1_RANGEA_DEFAULT;\n+\tpdata->tp_uwr_med_corr_z_1_rangeb = VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_1_RANGEB_DEFAULT;\n+\tpdata->tp_uwr_med_corr_z_2_rangea = VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_2_RANGEA_DEFAULT;\n+\tpdata->tp_uwr_med_corr_z_2_rangeb = VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_2_RANGEB_DEFAULT;\n+\tpdata->tp_uwr_med_corr_z_3_rangea = VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_3_RANGEA_DEFAULT;\n+\tpdata->tp_uwr_med_corr_z_3_rangeb = VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_3_RANGEB_DEFAULT;\n+\tpdata->tp_uwr_med_corr_z_4_rangea = VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_4_RANGEA_DEFAULT;\n+\tpdata->tp_uwr_med_corr_z_4_rangeb = VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_4_RANGEB_DEFAULT;\n+\tpdata->tp_uwr_med_corr_z_5_rangea = VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_5_RANGEA_DEFAULT;\n+\tpdata->tp_uwr_med_corr_z_5_rangeb = VL53LX_TUNINGPARM_UWR_MEDIUM_CORRECTION_ZONE_5_RANGEB_DEFAULT;\n+\tpdata->tp_uwr_lng_z_1_min = VL53LX_TUNINGPARM_UWR_LONG_ZONE_1_MIN_DEFAULT;\n+\tpdata->tp_uwr_lng_z_1_max = VL53LX_TUNINGPARM_UWR_LONG_ZONE_1_MAX_DEFAULT;\n+\tpdata->tp_uwr_lng_z_2_min = VL53LX_TUNINGPARM_UWR_LONG_ZONE_2_MIN_DEFAULT;\n+\tpdata->tp_uwr_lng_z_2_max = VL53LX_TUNINGPARM_UWR_LONG_ZONE_2_MAX_DEFAULT;\n+\tpdata->tp_uwr_lng_z_3_min = VL53LX_TUNINGPARM_UWR_LONG_ZONE_3_MIN_DEFAULT;\n+\tpdata->tp_uwr_lng_z_3_max = VL53LX_TUNINGPARM_UWR_LONG_ZONE_3_MAX_DEFAULT;\n+\tpdata->tp_uwr_lng_z_4_min = VL53LX_TUNINGPARM_UWR_LONG_ZONE_4_MIN_DEFAULT;\n+\tpdata->tp_uwr_lng_z_4_max = VL53LX_TUNINGPARM_UWR_LONG_ZONE_4_MAX_DEFAULT;\n+\tpdata->tp_uwr_lng_z_5_min = VL53LX_TUNINGPARM_UWR_LONG_ZONE_5_MIN_DEFAULT;\n+\tpdata->tp_uwr_lng_z_5_max = VL53LX_TUNINGPARM_UWR_LONG_ZONE_5_MAX_DEFAULT;\n+\tpdata->tp_uwr_lng_corr_z_1_rangea = VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_1_RANGEA_DEFAULT;\n+\tpdata->tp_uwr_lng_corr_z_1_rangeb = VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_1_RANGEB_DEFAULT;\n+\tpdata->tp_uwr_lng_corr_z_2_rangea = VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_2_RANGEA_DEFAULT;\n+\tpdata->tp_uwr_lng_corr_z_2_rangeb = VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_2_RANGEB_DEFAULT;\n+\tpdata->tp_uwr_lng_corr_z_3_rangea = VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_3_RANGEA_DEFAULT;\n+\tpdata->tp_uwr_lng_corr_z_3_rangeb = VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_3_RANGEB_DEFAULT;\n+\tpdata->tp_uwr_lng_corr_z_4_rangea = VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_4_RANGEA_DEFAULT;\n+\tpdata->tp_uwr_lng_corr_z_4_rangeb = VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_4_RANGEB_DEFAULT;\n+\tpdata->tp_uwr_lng_corr_z_5_rangea = VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_5_RANGEA_DEFAULT;\n+\tpdata->tp_uwr_lng_corr_z_5_rangeb = VL53LX_TUNINGPARM_UWR_LONG_CORRECTION_ZONE_5_RANGEB_DEFAULT;\n+\n+\tpdata->tp_dss_target_lite_mcps               = VL53LX_TUNINGPARM_LITE_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT;\n+\tpdata->tp_dss_target_histo_mcps              = VL53LX_TUNINGPARM_RANGING_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT;\n+\tpdata->tp_dss_target_histo_mz_mcps           = VL53LX_TUNINGPARM_MZ_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT;\n+\tpdata->tp_dss_target_timed_mcps              = VL53LX_TUNINGPARM_TIMED_DSS_CONFIG_TARGET_TOTAL_RATE_MCPS_DEFAULT;\n+\tpdata->tp_phasecal_timeout_lite_us           = VL53LX_TUNINGPARM_LITE_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT;\n+\tpdata->tp_phasecal_timeout_hist_long_us      = VL53LX_TUNINGPARM_RANGING_LONG_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT;\n+\tpdata->tp_phasecal_timeout_hist_med_us       = VL53LX_TUNINGPARM_RANGING_MED_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT;\n+\tpdata->tp_phasecal_timeout_hist_short_us     = VL53LX_TUNINGPARM_RANGING_SHORT_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT;\n+\tpdata->tp_phasecal_timeout_mz_long_us        = VL53LX_TUNINGPARM_MZ_LONG_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT;\n+\tpdata->tp_phasecal_timeout_mz_med_us         = VL53LX_TUNINGPARM_MZ_MED_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT;\n+\tpdata->tp_phasecal_timeout_mz_short_us       = VL53LX_TUNINGPARM_MZ_SHORT_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT;\n+\tpdata->tp_phasecal_timeout_timed_us          = VL53LX_TUNINGPARM_TIMED_PHASECAL_CONFIG_TIMEOUT_US_DEFAULT;\n+\tpdata->tp_mm_timeout_lite_us                 = VL53LX_TUNINGPARM_LITE_MM_CONFIG_TIMEOUT_US_DEFAULT;\n+\tpdata->tp_mm_timeout_histo_us                = VL53LX_TUNINGPARM_RANGING_MM_CONFIG_TIMEOUT_US_DEFAULT;\n+\tpdata->tp_mm_timeout_mz_us                   = VL53LX_TUNINGPARM_MZ_MM_CONFIG_TIMEOUT_US_DEFAULT;\n+\tpdata->tp_mm_timeout_timed_us                = VL53LX_TUNINGPARM_TIMED_MM_CONFIG_TIMEOUT_US_DEFAULT;\n+\tpdata->tp_range_timeout_lite_us              = VL53LX_TUNINGPARM_LITE_RANGE_CONFIG_TIMEOUT_US_DEFAULT;\n+\tpdata->tp_range_timeout_histo_us             = VL53LX_TUNINGPARM_RANGING_RANGE_CONFIG_TIMEOUT_US_DEFAULT;\n+\tpdata->tp_range_timeout_mz_us                = VL53LX_TUNINGPARM_MZ_RANGE_CONFIG_TIMEOUT_US_DEFAULT;\n+\tpdata->tp_range_timeout_timed_us             = VL53LX_TUNINGPARM_TIMED_RANGE_CONFIG_TIMEOUT_US_DEFAULT;\n+\n+\tpdata->tp_mm_timeout_lpa_us = VL53LX_TUNINGPARM_LOWPOWERAUTO_MM_CONFIG_TIMEOUT_US_DEFAULT;\n+\tpdata->tp_range_timeout_lpa_us = VL53LX_TUNINGPARM_LOWPOWERAUTO_RANGE_CONFIG_TIMEOUT_US_DEFAULT;\n+\n+\tpdata->tp_dss_target_very_short_mcps = VL53LX_TUNINGPARM_VERY_SHORT_DSS_RATE_MCPS_DEFAULT;\n+\n+\tpdata->tp_phasecal_patch_power = VL53LX_TUNINGPARM_PHASECAL_PATCH_POWER_DEFAULT;\n+\n+\tpdata->tp_hist_merge = VL53LX_TUNINGPARM_HIST_MERGE_DEFAULT;\n+\n+\tpdata->tp_reset_merge_threshold = VL53LX_TUNINGPARM_RESET_MERGE_THRESHOLD_DEFAULT;\n+\n+\tpdata->tp_hist_merge_max_size = VL53LX_TUNINGPARM_HIST_MERGE_MAX_SIZE_DEFAULT;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_preset_mode_histogram_short_range(\n+\tVL53LX_hist_post_process_config_t  *phistpostprocess,\n+\tVL53LX_static_config_t             *pstatic,\n+\tVL53LX_histogram_config_t          *phistogram,\n+\tVL53LX_general_config_t            *pgeneral,\n+\tVL53LX_timing_config_t             *ptiming,\n+\tVL53LX_dynamic_config_t            *pdynamic,\n+\tVL53LX_system_control_t            *psystem,\n+\tVL53LX_tuning_parm_storage_t       *ptuning_parms,\n+\tVL53LX_zone_config_t               *pzone_cfg)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tstatus = VL53LX_preset_mode_histogram_ranging(phistpostprocess, pstatic, phistogram, pgeneral, ptiming, pdynamic, psystem, ptuning_parms, pzone_cfg);\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tVL53LX_init_histogram_config_structure(7, 7, 0, 1, 1, 1, 0, 1, 1, 1, 2, 2, phistogram);\n+\t\tVL53LX_init_histogram_multizone_config_structure(7, 7, 0, 1, 1, 1, 0, 1, 1, 1, 2, 2, &(pzone_cfg->multizone_hist_cfg));\n+\t\tVL53LX_copy_hist_cfg_to_static_cfg(phistogram, pstatic, pgeneral, ptiming, pdynamic);\n+\n+\t\tptiming->range_config__vcsel_period_a = 0x03;\n+\t\tptiming->range_config__vcsel_period_b = 0x05;\n+\n+\t\tptiming->mm_config__timeout_macrop_a_hi = 0x00;\n+\t\tptiming->mm_config__timeout_macrop_a_lo = 0x52;\n+\t\tptiming->mm_config__timeout_macrop_b_hi = 0x00;\n+\t\tptiming->mm_config__timeout_macrop_b_lo = 0x37;\n+\n+\t\tptiming->range_config__timeout_macrop_a_hi = 0x00;\n+\t\tptiming->range_config__timeout_macrop_a_lo = 0x66;\n+\t\tptiming->range_config__timeout_macrop_b_hi = 0x00;\n+\t\tptiming->range_config__timeout_macrop_b_lo = 0x44;\n+\n+\t\tpgeneral->cal_config__vcsel_start = 0x03;\n+\n+\t\tpgeneral->phasecal_config__timeout_macrop = 0xF5;\n+\n+\t\tpdynamic->sd_config__woi_sd0 = 0x03;\n+\t\tpdynamic->sd_config__woi_sd1 = 0x05;\n+\t\tpdynamic->sd_config__initial_phase_sd0            = ptuning_parms->tp_init_phase_rtn_hist_short;\n+\t\tpdynamic->sd_config__initial_phase_sd1            = ptuning_parms->tp_init_phase_ref_hist_short;\n+\n+\t\tphistpostprocess->valid_phase_low = 0x08;\n+\t\tphistpostprocess->valid_phase_high = 0x28;\n+\n+\t\tpdynamic->system__sequence_config = VL53LX_SEQUENCE_VHV_EN | VL53LX_SEQUENCE_PHASECAL_EN | VL53LX_SEQUENCE_DSS1_EN | VL53LX_SEQUENCE_DSS2_EN | VL53LX_SEQUENCE_MM1_EN  | VL53LX_SEQUENCE_RANGE_EN;\n+\n+\t\tpsystem->system__mode_start = VL53LX_DEVICESCHEDULERMODE_HISTOGRAM | VL53LX_DEVICEREADOUTMODE_DUAL_SD | VL53LX_DEVICEMEASUREMENTMODE_BACKTOBACK;\n+\t}\n+\treturn status;\n+}\n+\n+void VL53LX_init_histogram_bin_data_struct(int32_t bin_value, uint16_t VL53LX_p_021, VL53LX_histogram_bin_data_t *pdata)\n+{\n+\tuint16_t          i = 0;\n+\n+\tpdata->cfg_device_state          = VL53LX_DEVICESTATE_SW_STANDBY;\n+\tpdata->rd_device_state           = VL53LX_DEVICESTATE_SW_STANDBY;\n+\tpdata->zone_id                   = 0;\n+\tpdata->time_stamp                = 0;\n+\tpdata->VL53LX_p_019                 = 0;\n+\tpdata->VL53LX_p_020               = VL53LX_HISTOGRAM_BUFFER_SIZE;\n+\tpdata->VL53LX_p_021            = (uint8_t)VL53LX_p_021;\n+\tpdata->number_of_ambient_bins    = 0;\n+\tpdata->result__interrupt_status           = 0;\n+\tpdata->result__range_status               = 0;\n+\tpdata->result__report_status              = 0;\n+\tpdata->result__stream_count               = 0;\n+\tpdata->result__dss_actual_effective_spads = 0;\n+\tpdata->phasecal_result__reference_phase   = 0;\n+\tpdata->phasecal_result__vcsel_start       = 0;\n+\tpdata->cal_config__vcsel_start            = 0;\n+\tpdata->vcsel_width                        = 0;\n+\tpdata->VL53LX_p_005                       = 0;\n+\tpdata->VL53LX_p_015                = 0;\n+\tpdata->total_periods_elapsed              = 0;\n+\tpdata->min_bin_value                      = 0;\n+\tpdata->max_bin_value                      = 0;\n+\tpdata->zero_distance_phase                = 0;\n+\tpdata->number_of_ambient_samples          = 0;\n+\tpdata->ambient_events_sum                 = 0;\n+\tpdata->VL53LX_p_028             = 0;\n+\n+\tfor (i = 0; i < VL53LX_MAX_BIN_SEQUENCE_LENGTH; i++)\n+\t\tpdata->bin_seq[i] = (uint8_t)i;\n+\n+\tfor (i = 0; i < VL53LX_MAX_BIN_SEQUENCE_LENGTH; i++)\n+\t\tpdata->bin_rep[i] = 1;\n+\n+\tfor (i = 0; i < VL53LX_HISTOGRAM_BUFFER_SIZE; i++)\n+\t\tif (i < VL53LX_p_021)\n+\t\t\tpdata->bin_data[i] = bin_value;\n+\t\telse\n+\t\t\tpdata->bin_data[i] = 0;\n+}\n+\n+void VL53LX_init_xtalk_bin_data_struct(uint32_t bin_value, uint16_t VL53LX_p_021, VL53LX_xtalk_histogram_shape_t *pdata)\n+{\n+\tuint16_t          i = 0;\n+\n+\tpdata->zone_id                   = 0;\n+\tpdata->time_stamp                = 0;\n+\tpdata->VL53LX_p_019                 = 0;\n+\tpdata->VL53LX_p_020               = VL53LX_XTALK_HISTO_BINS;\n+\tpdata->VL53LX_p_021            = (uint8_t)VL53LX_p_021;\n+\tpdata->phasecal_result__reference_phase   = 0;\n+\tpdata->phasecal_result__vcsel_start       = 0;\n+\tpdata->cal_config__vcsel_start            = 0;\n+\tpdata->vcsel_width                        = 0;\n+\tpdata->VL53LX_p_015                = 0;\n+\tpdata->zero_distance_phase                = 0;\n+\n+\tfor (i = 0; i < VL53LX_XTALK_HISTO_BINS; i++) {\n+\t\tif (i < VL53LX_p_021)\n+\t\t\tpdata->bin_data[i] = bin_value;\n+\t\telse\n+\t\t\tpdata->bin_data[i] = 0;\n+\t}\n+}\n+\n+VL53LX_Error VL53LX_xtalk_cal_data_init(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpdev->xtalk_cal.algo__crosstalk_compensation_plane_offset_kcps = 0;\n+\tpdev->xtalk_cal.algo__crosstalk_compensation_x_plane_gradient_kcps = 0;\n+\tpdev->xtalk_cal.algo__crosstalk_compensation_y_plane_gradient_kcps = 0;\n+\tmemset(&pdev->xtalk_cal.algo__xtalk_cpo_HistoMerge_kcps[0], 0, sizeof(pdev->xtalk_cal.algo__xtalk_cpo_HistoMerge_kcps));\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_output_init(VL53LX_LLDriverResults_t *pres)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_smudge_corrector_data_t *pdata;\n+\n+\tpdata = &(pres->range_results.smudge_corrector_data);\n+\n+\tpdata->smudge_corr_valid = 0;\n+\tpdata->smudge_corr_clipped = 0;\n+\tpdata->single_xtalk_delta_flag = 0;\n+\tpdata->averaged_xtalk_delta_flag = 0;\n+\tpdata->sample_limit_exceeded_flag = 0;\n+\tpdata->gradient_zero_flag = 0;\n+\tpdata->new_xtalk_applied_flag = 0;\n+\tpdata->algo__crosstalk_compensation_plane_offset_kcps = 0;\n+\tpdata->algo__crosstalk_compensation_x_plane_gradient_kcps = 0;\n+\tpdata->algo__crosstalk_compensation_y_plane_gradient_kcps = 0;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_data_init(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_LLDriverResults_t *pres = VL53LXDevStructGetLLResultsHandle(Dev);\n+\n+\tpdev->smudge_correct_config.smudge_corr_enabled       = 1;\n+\tpdev->smudge_correct_config.smudge_corr_apply_enabled = 1;\n+\tpdev->smudge_correct_config.smudge_corr_single_apply  = VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_COR_SINGLE_APPLY_DEFAULT;\n+\tpdev->smudge_correct_config.smudge_margin = VL53LX_TUNINGPARM_DYNXTALK_SMUDGE_MARGIN_DEFAULT;\n+\tpdev->smudge_correct_config.noise_margin = VL53LX_TUNINGPARM_DYNXTALK_NOISE_MARGIN_DEFAULT;\n+\tpdev->smudge_correct_config.user_xtalk_offset_limit = VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT_DEFAULT;\n+\tpdev->smudge_correct_config.user_xtalk_offset_limit_hi = VL53LX_TUNINGPARM_DYNXTALK_XTALK_OFFSET_LIMIT_HI_DEFAULT;\n+\tpdev->smudge_correct_config.sample_limit = VL53LX_TUNINGPARM_DYNXTALK_SAMPLE_LIMIT_DEFAULT;\n+\tpdev->smudge_correct_config.single_xtalk_delta = VL53LX_TUNINGPARM_DYNXTALK_SINGLE_XTALK_DELTA_DEFAULT;\n+\tpdev->smudge_correct_config.averaged_xtalk_delta = VL53LX_TUNINGPARM_DYNXTALK_AVERAGED_XTALK_DELTA_DEFAULT;\n+\tpdev->smudge_correct_config.smudge_corr_clip_limit = VL53LX_TUNINGPARM_DYNXTALK_CLIP_LIMIT_DEFAULT;\n+\tpdev->smudge_correct_config.smudge_corr_ambient_threshold = VL53LX_TUNINGPARM_DYNXTALK_XTALK_AMB_THRESHOLD_DEFAULT;\n+\tpdev->smudge_correct_config.scaler_calc_method = 0;\n+\tpdev->smudge_correct_config.x_gradient_scaler = VL53LX_TUNINGPARM_DYNXTALK_XGRADIENT_SCALER_DEFAULT;\n+\tpdev->smudge_correct_config.y_gradient_scaler = VL53LX_TUNINGPARM_DYNXTALK_YGRADIENT_SCALER_DEFAULT;\n+\tpdev->smudge_correct_config.user_scaler_set = VL53LX_TUNINGPARM_DYNXTALK_USER_SCALER_SET_DEFAULT;\n+\tpdev->smudge_correct_config.nodetect_ambient_threshold = VL53LX_TUNINGPARM_DYNXTALK_NODETECT_AMB_THRESHOLD_KCPS_DEFAULT;\n+\tpdev->smudge_correct_config.nodetect_sample_limit = VL53LX_TUNINGPARM_DYNXTALK_NODETECT_SAMPLE_LIMIT_DEFAULT;\n+\tpdev->smudge_correct_config.nodetect_xtalk_offset = VL53LX_TUNINGPARM_DYNXTALK_NODETECT_XTALK_OFFSET_KCPS_DEFAULT;\n+\tpdev->smudge_correct_config.nodetect_min_range_mm = VL53LX_TUNINGPARM_DYNXTALK_NODETECT_MIN_RANGE_MM_DEFAULT;\n+\tpdev->smudge_correct_config.max_smudge_factor = VL53LX_TUNINGPARM_DYNXTALK_MAX_SMUDGE_FACTOR_DEFAULT;\n+\tpdev->smudge_corrector_internals.current_samples = 0;\n+\tpdev->smudge_corrector_internals.required_samples = 0;\n+\tpdev->smudge_corrector_internals.accumulator = 0;\n+\tpdev->smudge_corrector_internals.nodetect_counter = 0;\n+\n+\tVL53LX_dynamic_xtalk_correction_output_init(pres);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_low_power_auto_data_init(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpdev->low_power_auto_data.vhv_loop_bound = VL53LX_TUNINGPARM_LOWPOWERAUTO_VHV_LOOP_BOUND_DEFAULT;\n+\tpdev->low_power_auto_data.is_low_power_auto_mode = 0;\n+\tpdev->low_power_auto_data.low_power_auto_range_count = 0;\n+\tpdev->low_power_auto_data.saved_interrupt_config = 0;\n+\tpdev->low_power_auto_data.saved_vhv_init = 0;\n+\tpdev->low_power_auto_data.saved_vhv_timeout = 0;\n+\tpdev->low_power_auto_data.first_run_phasecal_result = 0;\n+\tpdev->low_power_auto_data.dss__total_rate_per_spad_mcps = 0;\n+\tpdev->low_power_auto_data.dss__required_spads = 0;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_data_init(VL53LX_DEV Dev, uint8_t read_p2p_data)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_LLDriverResults_t *pres = VL53LXDevStructGetLLResultsHandle(Dev);\n+\tVL53LX_zone_objects_t    *pobjects;\n+\tuint8_t  i = 0;\n+\n+\tVL53LX_init_ll_driver_state(Dev, VL53LX_DEVICESTATE_UNKNOWN);\n+\n+\tpres->range_results.max_results    = VL53LX_MAX_RANGE_RESULTS;\n+\tpres->range_results.active_results = 0;\n+\tpres->zone_results.max_zones       = VL53LX_MAX_USER_ZONES;\n+\tpres->zone_results.active_zones    = 0;\n+\n+\tfor (i = 0; i < VL53LX_MAX_USER_ZONES; i++) {\n+\t\tpobjects = &(pres->zone_results.VL53LX_p_003[i]);\n+\t\tpobjects->xmonitor.VL53LX_p_016 = 0;\n+\t\tpobjects->xmonitor.VL53LX_p_017 = 0;\n+\t\tpobjects->xmonitor.VL53LX_p_011 = 0;\n+\t\tpobjects->xmonitor.range_status = VL53LX_DEVICEERROR_NOUPDATE;\n+\t}\n+\n+\tpres->zone_hists.max_zones = VL53LX_MAX_USER_ZONES;\n+\tpres->zone_hists.active_zones = 0;\n+\n+\tpres->zone_cal.max_zones = VL53LX_MAX_USER_ZONES;\n+\n+\tpres->zone_cal.active_zones = 0;\n+\tfor (i = 0; i < VL53LX_MAX_USER_ZONES; i++) {\n+\t\tpres->zone_cal.VL53LX_p_003[i].no_of_samples   = 0;\n+\t\tpres->zone_cal.VL53LX_p_003[i].effective_spads = 0;\n+\t\tpres->zone_cal.VL53LX_p_003[i].peak_rate_mcps  = 0;\n+\t\tpres->zone_cal.VL53LX_p_003[i].median_range_mm = 0;\n+\t\tpres->zone_cal.VL53LX_p_003[i].range_mm_offset = 0;\n+\t}\n+\n+\tpdev->wait_method   = VL53LX_WAIT_METHOD_BLOCKING;\n+\tpdev->preset_mode   = VL53LX_DEVICEPRESETMODE_HISTOGRAM_MEDIUM_RANGE;\n+\tpdev->zone_preset   = 0;\n+\tpdev->measurement_mode = VL53LX_DEVICEMEASUREMENTMODE_STOP;\n+\n+\tpdev->offset_calibration_mode = VL53LX_OFFSETCALIBRATIONMODE__MM1_MM2__STANDARD;\n+\tpdev->offset_correction_mode  = VL53LX_OFFSETCORRECTIONMODE__MM1_MM2_OFFSETS;\n+\tpdev->dmax_mode  = VL53LX_DEVICEDMAXMODE__FMT_CAL_DATA;\n+\n+\tpdev->phasecal_config_timeout_us  =  1000;\n+\tpdev->mm_config_timeout_us        =  2000;\n+\tpdev->range_config_timeout_us     = 13000;\n+\tpdev->inter_measurement_period_ms =   100;\n+\tpdev->dss_config__target_total_rate_mcps = 0x0A00;\n+\tpdev->debug_mode                  =  0x00;\n+\n+\tpdev->offset_results.max_results    = VL53LX_MAX_OFFSET_RANGE_RESULTS;\n+\tpdev->offset_results.active_results = 0;\n+\n+\tpdev->gain_cal.standard_ranging_gain_factor = VL53LX_TUNINGPARM_LITE_RANGING_GAIN_FACTOR_DEFAULT;\n+\tpdev->gain_cal.histogram_ranging_gain_factor = VL53LX_TUNINGPARM_HIST_GAIN_FACTOR_DEFAULT;\n+\n+\tVL53LX_init_version(Dev);\n+\n+\tmemset(pdev->multi_bins_rec, 0, sizeof(pdev->multi_bins_rec));\n+\tpdev->bin_rec_pos = 0;\n+\tpdev->pos_before_next_recom = 0;\n+\n+\tif (read_p2p_data > 0 && status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_read_p2p_data(Dev);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_init_refspadchar_config_struct(&(pdev->refspadchar));\n+\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_init_ssc_config_struct(&(pdev->ssc_cfg));\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_init_xtalk_config_struct(&(pdev->customer), &(pdev->xtalk_cfg));\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_init_xtalk_extract_config_struct(&(pdev->xtalk_extract_cfg));\n+\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_init_offset_cal_config_struct(&(pdev->offsetcal_cfg));\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_init_zone_cal_config_struct(&(pdev->zonecal_cfg));\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_init_hist_post_process_config_struct(pdev->xtalk_cfg.global_crosstalk_compensation_enable, &(pdev->histpostprocess));\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_init_hist_gen3_dmax_config_struct(&(pdev->dmax_cfg));\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_init_tuning_parm_storage_struct(&(pdev->tuning_parms));\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_set_preset_mode(Dev, pdev->preset_mode, pdev->dss_config__target_total_rate_mcps, pdev->phasecal_config_timeout_us, pdev->mm_config_timeout_us, pdev->range_config_timeout_us, pdev->inter_measurement_period_ms);\n+\n+\tVL53LX_init_histogram_bin_data_struct(0, VL53LX_HISTOGRAM_BUFFER_SIZE, &(pdev->hist_data));\n+\tVL53LX_init_histogram_bin_data_struct(0, VL53LX_HISTOGRAM_BUFFER_SIZE, &(pdev->hist_xtalk));\n+\tVL53LX_init_xtalk_bin_data_struct(0, VL53LX_XTALK_HISTO_BINS, &(pdev->xtalk_shapes.xtalk_shape));\n+\tVL53LX_xtalk_cal_data_init(Dev);\n+\tVL53LX_dynamic_xtalk_correction_data_init(Dev);\n+\tVL53LX_low_power_auto_data_init(Dev);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_set_dmax_mode(VL53LX_DEV Dev, VL53LX_DeviceDmaxMode dmax_mode)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpdev->dmax_mode = dmax_mode;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_DataInit(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev;\n+\tuint8_t  measurement_mode;\n+\n+#ifdef USE_I2C_2V8\n+\tStatus = VL53LX_RdByte(Dev, VL53LX_PAD_I2C_HV__EXTSUP_CONFIG, &i);\n+\tif (Status == VL53LX_ERROR_NONE) {\n+\t\ti = (i & 0xfe) | 0x01;\n+\t\tStatus = VL53LX_WrByte(Dev, VL53LX_PAD_I2C_HV__EXTSUP_CONFIG, i);\n+\t}\n+#endif\n+\n+\tif (Status == VL53LX_ERROR_NONE)\n+\t\tStatus = VL53LX_data_init(Dev, 1);\n+\n+\tif (Status == VL53LX_ERROR_NONE)\n+\t\tStatus = SetPresetModeL3CX(Dev, VL53LX_DISTANCEMODE_MEDIUM, 1000);\n+\n+\tif (Status == VL53LX_ERROR_NONE)\n+\t\tStatus = VL53LX_SetMeasurementTimingBudgetMicroSeconds(Dev, 33333);\n+\n+\tif (Status == VL53LX_ERROR_NONE) {\n+\t\tpdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\t\tmemset(&pdev->per_vcsel_cal_data, 0, sizeof(pdev->per_vcsel_cal_data));\n+\t}\n+\n+\tif (Status == VL53LX_ERROR_NONE) {\n+\t\tStatus = VL53LX_set_dmax_mode(Dev, VL53LX_DEVICEDMAXMODE__CUST_CAL_DATA);\n+\t}\n+\n+\tif (Status == VL53LX_ERROR_NONE)\n+\t\tStatus = VL53LX_SmudgeCorrectionEnable(Dev, VL53LX_SMUDGE_CORRECTION_NONE);\n+\n+\tmeasurement_mode  = VL53LX_DEVICEMEASUREMENTMODE_BACKTOBACK;\n+\tVL53LXDevDataSet(Dev, LLData.measurement_mode, measurement_mode);\n+\n+\tVL53LXDevDataSet(Dev, CurrentParameters.DistanceMode, VL53LX_DISTANCEMODE_MEDIUM);\n+\n+\treturn Status;\n+}\n+\n+VL53LX_Error VL53LX_get_zone_config(VL53LX_DEV Dev, VL53LX_zone_config_t *pzone_cfg)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tmemcpy(pzone_cfg, &(pdev->zone_cfg), sizeof(VL53LX_zone_config_t));\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_GetUserROI(VL53LX_DEV Dev, VL53LX_UserRoi_t *pRoi)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tVL53LX_zone_config_t zone_cfg;\n+\tuint8_t  TopLeftX;\n+\tuint8_t  TopLeftY;\n+\tuint8_t  BotRightX;\n+\tuint8_t  BotRightY;\n+\n+\tVL53LX_get_zone_config(Dev, &zone_cfg);\n+\n+\tTopLeftX = (2 * zone_cfg.user_zones[0].x_centre - zone_cfg.user_zones[0].width) >> 1;\n+\tTopLeftY = (2 * zone_cfg.user_zones[0].y_centre + zone_cfg.user_zones[0].height) >> 1;\n+\tBotRightX = (2 * zone_cfg.user_zones[0].x_centre + zone_cfg.user_zones[0].width) >> 1;\n+\tBotRightY = (2 * zone_cfg.user_zones[0].y_centre - zone_cfg.user_zones[0].height) >> 1;\n+\tpRoi->TopLeftX = TopLeftX;\n+\tpRoi->TopLeftY = TopLeftY;\n+\tpRoi->BotRightX = BotRightX;\n+\tpRoi->BotRightY = BotRightY;\n+\n+\treturn Status;\n+}\n+\n+VL53LX_Error VL53LX_GetDeviceInfo(VL53LX_DEV Dev, VL53LX_DeviceInfo_t *pVL53LX_DeviceInfo)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tuint8_t revision_id;\n+\tVL53LX_LLDriverData_t   *pLLData;\n+\n+\tpLLData =  VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpVL53LX_DeviceInfo->ProductType = pLLData->nvm_copy_data.identification__module_type;\n+\n+\trevision_id = pLLData->nvm_copy_data.identification__revision_id;\n+\tpVL53LX_DeviceInfo->ProductRevisionMajor = 1;\n+\tpVL53LX_DeviceInfo->ProductRevisionMinor = (revision_id & 0xF0) >> 4;\n+\n+\treturn Status;\n+}\n+\n+VL53LX_Error VL53LX_GetOpticalCenter(VL53LX_DEV Dev, FixPoint1616_t *pOpticalCenterX, FixPoint1616_t *pOpticalCenterY)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tVL53LX_calibration_data_t  CalibrationData;\n+\n+\t*pOpticalCenterX = 0;\n+\t*pOpticalCenterY = 0;\n+\tStatus = VL53LX_get_part_to_part_data(Dev, &CalibrationData);\n+\tif (Status == VL53LX_ERROR_NONE) {\n+\t\t*pOpticalCenterX = VL53LX_FIXPOINT44TOFIXPOINT1616(CalibrationData.optical_centre.x_centre);\n+\t\t*pOpticalCenterY = VL53LX_FIXPOINT44TOFIXPOINT1616(CalibrationData.optical_centre.y_centre);\n+\t}\n+\treturn Status;\n+}\n+\n+static int setup_tunings(struct stmvl53lx_data *data)\n+{\n+\tint rc = 0;\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(tunings); i++) {\n+\t\trc = VL53LX_SetTuningParameter(&data->stdev, tunings[i][0],\n+\t\t\ttunings[i][1]);\n+\t\tif (rc) {\n+\t\t\trc = store_last_error(data, rc);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\treturn rc;\n+}\n+\n+static int allocate_dev_id(void)\n+{\n+\tint i;\n+\n+\tmutex_lock(&dev_table_mutex);\n+\n+\tfor (i = 0; i < STMVL53LX_CFG_MAX_DEV; i++)\n+\t\tif (!stmvl53lx_dev_table[i])\n+\t\t\tbreak;\n+\ti = i < STMVL53LX_CFG_MAX_DEV ? i : -1;\n+\n+\tmutex_unlock(&dev_table_mutex);\n+\n+\treturn i;\n+}\n+\n+static void deallocate_dev_id(int id)\n+{\n+\tmutex_lock(&dev_table_mutex);\n+\n+\tstmvl53lx_dev_table[id] = NULL;\n+\n+\tmutex_unlock(&dev_table_mutex);\n+}\n+\n+static void vl53lx_diff_histo_stddev(VL53LX_LLDriverData_t *pdev,\n+\tVL53LX_histogram_bin_data_t *pdata, uint8_t timing, uint8_t HighIndex,\n+\tuint8_t prev_pos, int32_t *pdiff_histo_stddev)\n+{\n+\tuint16_t   bin                      = 0;\n+\tint32_t    total_rate_pre = 0;\n+\tint32_t    total_rate_cur = 0;\n+\tint32_t    PrevBin, CurrBin;\n+\n+\ttotal_rate_pre = 0;\n+\ttotal_rate_cur = 0;\n+\n+\n+\tfor (bin = timing * 4; bin < HighIndex; bin++) {\n+\t\ttotal_rate_pre += pdev->multi_bins_rec[prev_pos][timing][bin];\n+\t\ttotal_rate_cur += pdata->bin_data[bin];\n+\t}\n+\n+\tif ((total_rate_pre != 0) && (total_rate_cur != 0))\n+\t\tfor (bin = timing * 4; bin < HighIndex; bin++) {\n+\t\t\tPrevBin = pdev->multi_bins_rec[prev_pos][timing][bin];\n+\t\t\tPrevBin = (PrevBin * 1000) / total_rate_pre;\n+\t\t\tCurrBin = pdata->bin_data[bin] * 1000 / total_rate_cur;\n+\t\t\t*pdiff_histo_stddev += (PrevBin - CurrBin) * (PrevBin - CurrBin);\n+\t}\n+}\n+\n+static void vl53lx_histo_merge(VL53LX_DEV Dev, VL53LX_histogram_bin_data_t *pdata)\n+{\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tuint16_t   bin                      = 0;\n+\tuint8_t    i                        = 0;\n+\tint32_t    TuningBinRecSize\t\t    = 0;\n+\tuint8_t    recom_been_reset\t\t\t= 0;\n+\tuint8_t    timing\t\t\t\t\t= 0;\n+\tint32_t    rmt  = 0;\n+\tint32_t    diff_histo_stddev\t\t= 0;\n+\tuint8_t    HighIndex, prev_pos;\n+\tuint8_t    BuffSize = VL53LX_HISTOGRAM_BUFFER_SIZE;\n+\tuint8_t    pos;\n+\n+\tVL53LX_get_tuning_parm(Dev, VL53LX_TUNINGPARM_HIST_MERGE_MAX_SIZE, &TuningBinRecSize);\n+\tVL53LX_get_tuning_parm(Dev, VL53LX_TUNINGPARM_RESET_MERGE_THRESHOLD, &rmt);\n+\n+\tif (pdev->pos_before_next_recom == 0) {\n+\t\ttiming = 1 - pdata->result__stream_count % 2;\n+\n+\t\tdiff_histo_stddev = 0;\n+\t\tHighIndex = BuffSize - timing * 4;\n+\t\tif (pdev->bin_rec_pos > 0)\n+\t\t\tprev_pos = pdev->bin_rec_pos - 1;\n+\t\telse\n+\t\t\tprev_pos = (TuningBinRecSize - 1);\n+\n+\t\tif (pdev->multi_bins_rec[prev_pos][timing][4] > 0)\n+\t\t\tvl53lx_diff_histo_stddev(pdev, pdata, timing, HighIndex, prev_pos, &diff_histo_stddev);\n+\n+\t\tif (diff_histo_stddev >= rmt) {\n+\t\t\tmemset(pdev->multi_bins_rec, 0, sizeof(pdev->multi_bins_rec));\n+\t\t\tpdev->bin_rec_pos = 0;\n+\t\t\trecom_been_reset = 1;\n+\t\t\tif (timing == 0)\n+\t\t\t\tpdev->pos_before_next_recom = VL53LX_FRAME_WAIT_EVENT;\n+\t\t\telse\n+\t\t\t\tpdev->pos_before_next_recom = VL53LX_FRAME_WAIT_EVENT + 1;\n+\t\t} else {\n+\t\t\tpos = pdev->bin_rec_pos;\n+\t\t\tfor (i = 0; i < BuffSize; i++)\n+\t\t\t\tpdev->multi_bins_rec[pos][timing][i] = pdata->bin_data[i];\n+\t\t}\n+\t\tif (pdev->bin_rec_pos == (TuningBinRecSize - 1) && timing == 1)\n+\t\t\tpdev->bin_rec_pos = 0;\n+\t\telse if (timing == 1)\n+\t\t\tpdev->bin_rec_pos++;\n+\n+\t\tif (!((recom_been_reset == 1) && (timing == 0)) &&\n+\t\t\t (pdev->pos_before_next_recom == 0)) {\n+\n+\t\t\tfor (bin = 0; bin < BuffSize; bin++)\n+\t\t\t\tpdata->bin_data[bin] = 0;\n+\n+\t\t\tfor (bin = 0; bin < BuffSize; bin++)\n+\t\t\t\tfor (i = 0; i < TuningBinRecSize; i++)\n+\t\t\t\t\tpdata->bin_data[bin] += (pdev->multi_bins_rec[i][timing][bin]);\n+\t\t}\n+\t} else {\n+\n+\t\tpdev->pos_before_next_recom--;\n+\t\tif (pdev->pos_before_next_recom == 255)\n+\t\t\tpdev->pos_before_next_recom = 0;\n+\t}\n+}\n+\n+void VL53LX_hist_get_bin_sequence_config(VL53LX_DEV Dev, VL53LX_histogram_bin_data_t *pdata)\n+{\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tint32_t amb_thresh_low   = 0;\n+\tint32_t amb_thresh_high  = 0;\n+\tuint8_t i = 0;\n+\n+\tamb_thresh_low  = 1024 * (int32_t)pdev->hist_cfg.histogram_config__amb_thresh_low;\n+\tamb_thresh_high = 1024 * (int32_t)pdev->hist_cfg.histogram_config__amb_thresh_high;\n+\n+\tif ((pdev->ll_state.rd_stream_count & 0x01) == 0) {\n+\t\tpdata->bin_seq[5] = pdev->hist_cfg.histogram_config__mid_amb_even_bin_4_5 >> 4;\n+\t\tpdata->bin_seq[4] = pdev->hist_cfg.histogram_config__mid_amb_even_bin_4_5 & 0x0F;\n+\t\tpdata->bin_seq[3] = pdev->hist_cfg.histogram_config__mid_amb_even_bin_2_3 >> 4;\n+\t\tpdata->bin_seq[2] = pdev->hist_cfg.histogram_config__mid_amb_even_bin_2_3 & 0x0F;\n+\t\tpdata->bin_seq[1] = pdev->hist_cfg.histogram_config__mid_amb_even_bin_0_1 >> 4;\n+\t\tpdata->bin_seq[0] = pdev->hist_cfg.histogram_config__mid_amb_even_bin_0_1 & 0x0F;\n+\n+\t\tif (pdata->ambient_events_sum > amb_thresh_high) {\n+\t\t\tpdata->bin_seq[5] = pdev->hist_cfg.histogram_config__high_amb_even_bin_4_5 >> 4;\n+\t\t\tpdata->bin_seq[4] = pdev->hist_cfg.histogram_config__high_amb_even_bin_4_5 & 0x0F;\n+\t\t\tpdata->bin_seq[3] = pdev->hist_cfg.histogram_config__high_amb_even_bin_2_3 >> 4;\n+\t\t\tpdata->bin_seq[2] = pdev->hist_cfg.histogram_config__high_amb_even_bin_2_3 & 0x0F;\n+\t\t\tpdata->bin_seq[1] = pdev->hist_cfg.histogram_config__high_amb_even_bin_0_1 >> 4;\n+\t\t\tpdata->bin_seq[0] = pdev->hist_cfg.histogram_config__high_amb_even_bin_0_1 & 0x0F;\n+\t\t}\n+\t\tif (pdata->ambient_events_sum < amb_thresh_low) {\n+\t\t\tpdata->bin_seq[5] = pdev->hist_cfg.histogram_config__low_amb_even_bin_4_5 >> 4;\n+\t\t\tpdata->bin_seq[4] = pdev->hist_cfg.histogram_config__low_amb_even_bin_4_5 & 0x0F;\n+\t\t\tpdata->bin_seq[3] = pdev->hist_cfg.histogram_config__low_amb_even_bin_2_3 >> 4;\n+\t\t\tpdata->bin_seq[2] = pdev->hist_cfg.histogram_config__low_amb_even_bin_2_3 & 0x0F;\n+\t\t\tpdata->bin_seq[1] = pdev->hist_cfg.histogram_config__low_amb_even_bin_0_1 >> 4;\n+\t\t\tpdata->bin_seq[0] = pdev->hist_cfg.histogram_config__low_amb_even_bin_0_1 & 0x0F;\n+\t\t}\n+\n+\t} else {\n+\t\tpdata->bin_seq[5] = pdev->hist_cfg.histogram_config__mid_amb_odd_bin_5 & 0x0F;\n+\t\tpdata->bin_seq[4] = pdev->hist_cfg.histogram_config__mid_amb_odd_bin_3_4 & 0x0F;\n+\t\tpdata->bin_seq[3] = pdev->hist_cfg.histogram_config__mid_amb_odd_bin_3_4 >> 4;\n+\t\tpdata->bin_seq[2] = pdev->hist_cfg.histogram_config__mid_amb_odd_bin_2 & 0x0F;\n+\t\tpdata->bin_seq[1] = pdev->hist_cfg.histogram_config__mid_amb_odd_bin_0_1 >> 4;\n+\t\tpdata->bin_seq[0] = pdev->hist_cfg.histogram_config__mid_amb_odd_bin_0_1 & 0x0F;\n+\t\tif (pdata->ambient_events_sum > amb_thresh_high) {\n+\t\t\tpdata->bin_seq[5] = pdev->hist_cfg.histogram_config__high_amb_odd_bin_4_5 >> 4;\n+\t\t\tpdata->bin_seq[4] = pdev->hist_cfg.histogram_config__high_amb_odd_bin_4_5 & 0x0F;\n+\t\t\tpdata->bin_seq[3] = pdev->hist_cfg.histogram_config__high_amb_odd_bin_2_3 >> 4;\n+\t\t\tpdata->bin_seq[2] = pdev->hist_cfg.histogram_config__high_amb_odd_bin_2_3 & 0x0F;\n+\t\t\tpdata->bin_seq[1] = pdev->hist_cfg.histogram_config__high_amb_odd_bin_0_1 >> 4;\n+\t\t\tpdata->bin_seq[0] = pdev->hist_cfg.histogram_config__high_amb_odd_bin_0_1 & 0x0F;\n+\t\t}\n+\t\tif (pdata->ambient_events_sum < amb_thresh_low) {\n+\t\t\tpdata->bin_seq[5] = pdev->hist_cfg.histogram_config__low_amb_odd_bin_4_5 >> 4;\n+\t\t\tpdata->bin_seq[4] = pdev->hist_cfg.histogram_config__low_amb_odd_bin_4_5 & 0x0F;\n+\t\t\tpdata->bin_seq[3] = pdev->hist_cfg.histogram_config__low_amb_odd_bin_2_3 >> 4;\n+\t\t\tpdata->bin_seq[2] = pdev->hist_cfg.histogram_config__low_amb_odd_bin_2_3 & 0x0F;\n+\t\t\tpdata->bin_seq[1] = pdev->hist_cfg.histogram_config__low_amb_odd_bin_0_1 >> 4;\n+\t\t\tpdata->bin_seq[0] = pdev->hist_cfg.histogram_config__low_amb_odd_bin_0_1 & 0x0F;\n+\t\t}\n+\t}\n+\tfor (i = 0; i < VL53LX_MAX_BIN_SEQUENCE_LENGTH; i++)\n+\t\tpdata->bin_rep[i] = 1;\n+}\n+\n+uint32_t VL53LX_duration_maths(uint32_t pll_period_us, uint32_t vcsel_parm_pclks, uint32_t window_vclks, uint32_t elapsed_mclks)\n+{\n+\tuint64_t  tmp_long_int = 0;\n+\tuint32_t  duration_us  = 0;\n+\n+\tduration_us = window_vclks * pll_period_us;\n+\tduration_us = duration_us >> 12;\n+\ttmp_long_int = (uint64_t)duration_us;\n+\tduration_us = elapsed_mclks * vcsel_parm_pclks;\n+\tduration_us = duration_us >> 4;\n+\ttmp_long_int = tmp_long_int * (uint64_t)duration_us;\n+\ttmp_long_int = tmp_long_int >> 12;\n+\tif (tmp_long_int > 0xFFFFFFFF)\n+\t\ttmp_long_int = 0xFFFFFFFF;\n+\n+\tduration_us  = (uint32_t)tmp_long_int;\n+\treturn duration_us;\n+}\n+\n+void VL53LX_hist_calc_zero_distance_phase(VL53LX_histogram_bin_data_t *pdata)\n+{\n+\tuint32_t  period        = 0;\n+\tuint32_t  VL53LX_p_014         = 0;\n+\n+\tperiod = 2048 * (uint32_t)VL53LX_decode_vcsel_period(pdata->VL53LX_p_005);\n+\n+\tVL53LX_p_014  = period;\n+\tVL53LX_p_014 += (uint32_t)pdata->phasecal_result__reference_phase;\n+\tVL53LX_p_014 += (2048 * (uint32_t)pdata->phasecal_result__vcsel_start);\n+\tVL53LX_p_014 -= (2048 * (uint32_t)pdata->cal_config__vcsel_start);\n+\n+\tif (period != 0)\n+\t\tVL53LX_p_014  = VL53LX_p_014 % period;\n+\telse\n+\t\tVL53LX_p_014 = 0;\n+\n+\tpdata->zero_distance_phase = (uint16_t)VL53LX_p_014;\n+}\n+\n+void VL53LX_hist_estimate_ambient_from_ambient_bins(VL53LX_histogram_bin_data_t *pdata)\n+{\n+\tuint8_t  bin            = 0;\n+\n+\tif (pdata->number_of_ambient_bins > 0) {\n+\t\tpdata->number_of_ambient_samples = pdata->number_of_ambient_bins;\n+\t\tpdata->ambient_events_sum = 0;\n+\t\tfor (bin = 0; bin < pdata->number_of_ambient_bins; bin++)\n+\t\t\tpdata->ambient_events_sum += pdata->bin_data[bin];\n+\n+\t\tpdata->VL53LX_p_028 = pdata->ambient_events_sum;\n+\t\tpdata->VL53LX_p_028 += ((int32_t)pdata->number_of_ambient_bins / 2);\n+\t\tpdata->VL53LX_p_028 /= (int32_t)pdata->number_of_ambient_bins;\n+\t}\n+}\n+\n+VL53LX_Error VL53LX_get_histogram_bin_data(VL53LX_DEV Dev, VL53LX_histogram_bin_data_t *pdata)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_LLDriverResults_t *pres = VL53LXDevStructGetLLResultsHandle(Dev);\n+\tVL53LX_zone_private_dyn_cfg_t *pzone_dyn_cfg;\n+\tVL53LX_static_nvm_managed_t   *pstat_nvm = &(pdev->stat_nvm);\n+\tVL53LX_static_config_t        *pstat_cfg = &(pdev->stat_cfg);\n+\tVL53LX_general_config_t       *pgen_cfg  = &(pdev->gen_cfg);\n+\tVL53LX_timing_config_t        *ptim_cfg  = &(pdev->tim_cfg);\n+\tVL53LX_range_results_t        *presults  = &(pres->range_results);\n+\n+\tuint8_t    buffer[VL53LX_MAX_I2C_XFER_SIZE];\n+\tuint8_t   *pbuffer = &buffer[0];\n+\tuint8_t    bin_23_0 = 0x00;\n+\tuint16_t   bin                      = 0;\n+\tuint16_t   i2c_buffer_offset_bytes  = 0;\n+\tuint16_t   encoded_timeout          = 0;\n+\n+\tuint32_t   pll_period_us            = 0;\n+\tuint32_t   periods_elapsed_tmp      = 0;\n+\n+\tuint8_t    i                        = 0;\n+\n+\tint32_t    hist_merge\t\t\t\t= 0;\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_ReadMulti(Dev, VL53LX_HISTOGRAM_BIN_DATA_I2C_INDEX, pbuffer, VL53LX_HISTOGRAM_BIN_DATA_I2C_SIZE_BYTES);\n+\n+\tpdata->result__interrupt_status               = *(pbuffer +   0);\n+\tpdata->result__range_status                   = *(pbuffer +   1);\n+\tpdata->result__report_status                  = *(pbuffer +   2);\n+\tpdata->result__stream_count                   = *(pbuffer +   3);\n+\tpdata->result__dss_actual_effective_spads = VL53LX_i2c_decode_uint16_t(2, pbuffer +   4);\n+\n+\ti2c_buffer_offset_bytes = VL53LX_PHASECAL_RESULT__REFERENCE_PHASE - VL53LX_HISTOGRAM_BIN_DATA_I2C_INDEX;\n+\n+\tpbuffer = &buffer[i2c_buffer_offset_bytes];\n+\n+\tpdata->phasecal_result__reference_phase = VL53LX_i2c_decode_uint16_t(2, pbuffer);\n+\n+\ti2c_buffer_offset_bytes = VL53LX_PHASECAL_RESULT__VCSEL_START - VL53LX_HISTOGRAM_BIN_DATA_I2C_INDEX;\n+\n+\tpdata->phasecal_result__vcsel_start = buffer[i2c_buffer_offset_bytes];\n+\n+\tpdev->dbg_results.phasecal_result__reference_phase = pdata->phasecal_result__reference_phase;\n+\tpdev->dbg_results.phasecal_result__vcsel_start = pdata->phasecal_result__vcsel_start;\n+\n+\ti2c_buffer_offset_bytes = VL53LX_RESULT__HISTOGRAM_BIN_23_0_MSB - VL53LX_HISTOGRAM_BIN_DATA_I2C_INDEX;\n+\n+\tbin_23_0 = buffer[i2c_buffer_offset_bytes] << 2;\n+\n+\ti2c_buffer_offset_bytes = VL53LX_RESULT__HISTOGRAM_BIN_23_0_LSB - VL53LX_HISTOGRAM_BIN_DATA_I2C_INDEX;\n+\n+\tbin_23_0 += buffer[i2c_buffer_offset_bytes];\n+\n+\ti2c_buffer_offset_bytes = VL53LX_RESULT__HISTOGRAM_BIN_23_0 - VL53LX_HISTOGRAM_BIN_DATA_I2C_INDEX;\n+\n+\tbuffer[i2c_buffer_offset_bytes] = bin_23_0;\n+\n+\ti2c_buffer_offset_bytes = VL53LX_RESULT__HISTOGRAM_BIN_0_2 - VL53LX_HISTOGRAM_BIN_DATA_I2C_INDEX;\n+\n+\tpbuffer = &buffer[i2c_buffer_offset_bytes];\n+\tfor (bin = 0; bin < VL53LX_HISTOGRAM_BUFFER_SIZE; bin++) {\n+\t\tpdata->bin_data[bin] = (int32_t)VL53LX_i2c_decode_uint32_t(3, pbuffer);\n+\t\tpbuffer += 3;\n+\t}\n+\n+\tVL53LX_get_tuning_parm(Dev, VL53LX_TUNINGPARM_HIST_MERGE, &hist_merge);\n+\tif (pdata->result__stream_count == 0) {\n+\n+\t\tmemset(pdev->multi_bins_rec, 0, sizeof(pdev->multi_bins_rec));\n+\t\tpdev->bin_rec_pos = 0;\n+\t\tpdev->pos_before_next_recom = 0;\n+\t}\n+\tif (hist_merge == 1)\n+\t\tvl53lx_histo_merge(Dev, pdata);\n+\n+\tpdata->zone_id                 = pdev->ll_state.rd_zone_id;\n+\tpdata->VL53LX_p_019               = 0;\n+\tpdata->VL53LX_p_020             = VL53LX_HISTOGRAM_BUFFER_SIZE;\n+\tpdata->VL53LX_p_021          = VL53LX_HISTOGRAM_BUFFER_SIZE;\n+\n+\tpdata->cal_config__vcsel_start = pgen_cfg->cal_config__vcsel_start;\n+\n+\n+\n+\tpdata->vcsel_width = ((uint16_t)pgen_cfg->global_config__vcsel_width) << 4;\n+\tpdata->vcsel_width += (uint16_t)pstat_cfg->ana_config__vcsel_pulse_width_offset;\n+\n+\tpdata->VL53LX_p_015 = pstat_nvm->osc_measured__fast_osc__frequency;\n+\n+\tVL53LX_hist_get_bin_sequence_config(Dev, pdata);\n+\n+\tif (pdev->ll_state.rd_timing_status == 0) {\n+\t\tencoded_timeout = (ptim_cfg->range_config__timeout_macrop_a_hi << 8) + ptim_cfg->range_config__timeout_macrop_a_lo;\n+\t\tpdata->VL53LX_p_005 =  ptim_cfg->range_config__vcsel_period_a;\n+\t} else {\n+\t\tencoded_timeout = (ptim_cfg->range_config__timeout_macrop_b_hi << 8) + ptim_cfg->range_config__timeout_macrop_b_lo;\n+\t\tpdata->VL53LX_p_005 = ptim_cfg->range_config__vcsel_period_b;\n+\t}\n+\n+\tpdata->number_of_ambient_bins  = 0;\n+\tfor (i = 0; i < 6; i++) {\n+\t\tif ((pdata->bin_seq[i] & 0x07) == 0x07)\n+\t\t\tpdata->number_of_ambient_bins = pdata->number_of_ambient_bins + 0x04;\n+\t}\n+\tpdata->total_periods_elapsed = VL53LX_decode_timeout(encoded_timeout);\n+\n+\tpll_period_us = VL53LX_calc_pll_period_us(pdata->VL53LX_p_015);\n+\n+\tperiods_elapsed_tmp = pdata->total_periods_elapsed + 1;\n+\n+\tpdata->peak_duration_us = VL53LX_duration_maths(pll_period_us, (uint32_t)pdata->vcsel_width, VL53LX_RANGING_WINDOW_VCSEL_PERIODS, periods_elapsed_tmp);\n+\n+\tpdata->woi_duration_us     = 0;\n+\n+\tVL53LX_hist_calc_zero_distance_phase(pdata);\n+\tVL53LX_hist_estimate_ambient_from_ambient_bins(pdata);\n+\n+\tpdata->cfg_device_state = pdev->ll_state.cfg_device_state;\n+\tpdata->rd_device_state  = pdev->ll_state.rd_device_state;\n+\n+\tpzone_dyn_cfg = &(pres->zone_dyn_cfgs.VL53LX_p_003[pdata->zone_id]);\n+\n+\tpdata->roi_config__user_roi_centre_spad = pzone_dyn_cfg->roi_config__user_roi_centre_spad;\n+\tpdata->roi_config__user_roi_requested_global_xy_size = pzone_dyn_cfg->roi_config__user_roi_requested_global_xy_size;\n+\n+\tpresults->device_status = VL53LX_DEVICEERROR_NOUPDATE;\n+\n+\tswitch (pdata->result__range_status & VL53LX_RANGE_STATUS__RANGE_STATUS_MASK) {\n+\tcase VL53LX_DEVICEERROR_VCSELCONTINUITYTESTFAILURE:\n+\tcase VL53LX_DEVICEERROR_VCSELWATCHDOGTESTFAILURE:\n+\tcase VL53LX_DEVICEERROR_NOVHVVALUEFOUND:\n+\tcase VL53LX_DEVICEERROR_USERROICLIP:\n+\tcase VL53LX_DEVICEERROR_MULTCLIPFAIL:\n+\t\tpresults->device_status = (pdata->result__range_status & VL53LX_RANGE_STATUS__RANGE_STATUS_MASK);\n+\t\tstatus = VL53LX_ERROR_RANGE_ERROR;\n+\t\tbreak;\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_hist_copy_and_scale_ambient_info(VL53LX_zone_hist_info_t *pidata, VL53LX_histogram_bin_data_t *podata)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tint64_t  evts              = 0;\n+\tint64_t  tmpi              = 0;\n+\tint64_t  tmpo              = 0;\n+\n+\tif (pidata->result__dss_actual_effective_spads == 0) {\n+\t\tstatus = VL53LX_ERROR_DIVISION_BY_ZERO;\n+\t} else {\n+\t\tif (pidata->number_of_ambient_bins >  0 &&\n+\t\t\tpodata->number_of_ambient_bins == 0) {\n+\t\t\ttmpo    = 1 + (int64_t)podata->total_periods_elapsed;\n+\t\t\ttmpo   *= (int64_t)podata->result__dss_actual_effective_spads;\n+\t\t\ttmpi    = 1 + (int64_t)pidata->total_periods_elapsed;\n+\t\t\ttmpi   *= (int64_t)pidata->result__dss_actual_effective_spads;\n+\t\t\tevts  = tmpo * (int64_t)pidata->ambient_events_sum;\n+\t\t\tevts += (tmpi/2);\n+\t\t\tif (tmpi != 0)\n+\t\t\t\tevts = do_division_s(evts, tmpi);\n+\n+\t\t\tpodata->ambient_events_sum = (int32_t)evts;\n+\t\t\tpodata->VL53LX_p_028 = podata->ambient_events_sum;\n+\t\t\tpodata->VL53LX_p_028 += ((int32_t)pidata->number_of_ambient_bins / 2);\n+\t\t\tpodata->VL53LX_p_028 /= (int32_t)pidata->number_of_ambient_bins;\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_compute_histo_merge_nb(VL53LX_DEV Dev, uint8_t *histo_merge_nb)\n+{\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tuint8_t i, timing;\n+\tuint8_t sum = 0;\n+\n+\ttiming = (pdev->hist_data.bin_seq[0] == 7 ? 1 : 0);\n+\tfor (i = 0; i < VL53LX_BIN_REC_SIZE; i++)\n+\t\tif (pdev->multi_bins_rec[i][timing][7] > 0)\n+\t\t\tsum++;\n+\t*histo_merge_nb = sum;\n+\treturn status;\n+}\n+\n+void VL53LX_hist_combine_mm1_mm2_offsets(\n+\tint16_t                               mm1_offset_mm,\n+\tint16_t                               mm2_offset_mm,\n+\tuint8_t                               encoded_mm_roi_centre,\n+\tuint8_t                               encoded_mm_roi_size,\n+\tuint8_t                               encoded_zone_centre,\n+\tuint8_t                               encoded_zone_size,\n+\tVL53LX_additional_offset_cal_data_t  *pcal_data,\n+\tuint8_t                              *pgood_spads,\n+\tuint16_t                              aperture_attenuation,\n+\tint16_t                               *prange_offset_mm)\n+{\n+\tuint16_t max_mm_inner_effective_spads = 0;\n+\tuint16_t max_mm_outer_effective_spads = 0;\n+\tuint16_t mm_inner_effective_spads     = 0;\n+\tuint16_t mm_outer_effective_spads     = 0;\n+\tuint32_t scaled_mm1_peak_rate_mcps    = 0;\n+\tuint32_t scaled_mm2_peak_rate_mcps    = 0;\n+\tint32_t tmp0 = 0;\n+\tint32_t tmp1 = 0;\n+\n+\tVL53LX_calc_mm_effective_spads(\n+\t\tencoded_mm_roi_centre,\n+\t\tencoded_mm_roi_size,\n+\t\t0xC7,\n+\t\t0xFF,\n+\t\tpgood_spads,\n+\t\taperture_attenuation,\n+\t\t&max_mm_inner_effective_spads,\n+\t\t&max_mm_outer_effective_spads);\n+\n+\tif ((max_mm_inner_effective_spads == 0) ||\n+\t\t(max_mm_outer_effective_spads == 0))\n+\t\tgoto FAIL;\n+\n+\tVL53LX_calc_mm_effective_spads(\n+\t\tencoded_mm_roi_centre,\n+\t\tencoded_mm_roi_size,\n+\t\tencoded_zone_centre,\n+\t\tencoded_zone_size,\n+\t\tpgood_spads,\n+\t\taperture_attenuation,\n+\t\t&mm_inner_effective_spads,\n+\t\t&mm_outer_effective_spads);\n+\n+\tscaled_mm1_peak_rate_mcps  = (uint32_t)pcal_data->result__mm_inner_peak_signal_count_rtn_mcps;\n+\tscaled_mm1_peak_rate_mcps *= (uint32_t)mm_inner_effective_spads;\n+\tscaled_mm1_peak_rate_mcps /= (uint32_t)max_mm_inner_effective_spads;\n+\n+\tscaled_mm2_peak_rate_mcps  = (uint32_t)pcal_data->result__mm_outer_peak_signal_count_rtn_mcps;\n+\tscaled_mm2_peak_rate_mcps *= (uint32_t)mm_outer_effective_spads;\n+\tscaled_mm2_peak_rate_mcps /= (uint32_t)max_mm_outer_effective_spads;\n+\n+\ttmp0  = ((int32_t)mm1_offset_mm * (int32_t)scaled_mm1_peak_rate_mcps);\n+\ttmp0 += ((int32_t)mm2_offset_mm * (int32_t)scaled_mm2_peak_rate_mcps);\n+\n+\ttmp1 =  (int32_t)scaled_mm1_peak_rate_mcps + (int32_t)scaled_mm2_peak_rate_mcps;\n+\n+\tif (tmp1 != 0)\n+\t\ttmp0 = (tmp0 * 4) / tmp1;\n+FAIL:\n+\t*prange_offset_mm = (int16_t)tmp0;\n+\n+}\n+\n+static VL53LX_Error select_offset_per_vcsel(VL53LX_LLDriverData_t *pdev, int16_t *poffset)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tint16_t tA, tB;\n+\tuint8_t isc;\n+\n+\tswitch (pdev->preset_mode) {\n+\tcase VL53LX_DEVICEPRESETMODE_HISTOGRAM_SHORT_RANGE:\n+\t\ttA = pdev->per_vcsel_cal_data.short_a_offset_mm;\n+\t\ttB = pdev->per_vcsel_cal_data.short_b_offset_mm;\n+\t\tbreak;\n+\tcase VL53LX_DEVICEPRESETMODE_HISTOGRAM_MEDIUM_RANGE:\n+\t\ttA = pdev->per_vcsel_cal_data.medium_a_offset_mm;\n+\t\ttB = pdev->per_vcsel_cal_data.medium_b_offset_mm;\n+\t\tbreak;\n+\tcase VL53LX_DEVICEPRESETMODE_HISTOGRAM_LONG_RANGE:\n+\t\ttA = pdev->per_vcsel_cal_data.long_a_offset_mm;\n+\t\ttB = pdev->per_vcsel_cal_data.long_b_offset_mm;\n+\t\tbreak;\n+\tdefault:\n+\t\ttA = pdev->per_vcsel_cal_data.long_a_offset_mm;\n+\t\ttB = pdev->per_vcsel_cal_data.long_b_offset_mm;\n+\t\tstatus = VL53LX_ERROR_INVALID_PARAMS;\n+\t\t*poffset = 0;\n+\t\tbreak;\n+\t}\n+\n+\tisc = pdev->ll_state.cfg_internal_stream_count;\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\t*poffset = (isc & 0x01) ? tA : tB;\n+\n+\treturn status;\n+}\n+\n+void VL53LX_calc_max_effective_spads(uint8_t encoded_zone_centre, uint8_t encoded_zone_size, uint8_t *pgood_spads, uint16_t aperture_attenuation, uint16_t *pmax_effective_spads)\n+{\n+\tint16_t   x         = 0;\n+\tint16_t   y         = 0;\n+\tint16_t   zone_x_ll = 0;\n+\tint16_t   zone_y_ll = 0;\n+\tint16_t   zone_x_ur = 0;\n+\tint16_t   zone_y_ur = 0;\n+\tuint8_t   spad_number = 0;\n+\tuint8_t   byte_index  = 0;\n+\tuint8_t   bit_index   = 0;\n+\tuint8_t   bit_mask    = 0;\n+\tuint8_t   is_aperture = 0;\n+\n+\tVL53LX_decode_zone_limits(encoded_zone_centre, encoded_zone_size, &zone_x_ll, &zone_y_ll, &zone_x_ur, &zone_y_ur);\n+\n+\t*pmax_effective_spads = 0;\n+\tfor (y = zone_y_ll; y <= zone_y_ur; y++) {\n+\t\tfor (x = zone_x_ll; x <= zone_x_ur; x++) {\n+\t\t\tVL53LX_encode_row_col((uint8_t)y, (uint8_t)x, &spad_number);\n+\t\t\tVL53LX_spad_number_to_byte_bit_index(spad_number, &byte_index, &bit_index, &bit_mask);\n+\t\t\tif ((pgood_spads[byte_index] & bit_mask) > 0) {\n+\t\t\t\tis_aperture = VL53LX_is_aperture_location((uint8_t)y, (uint8_t)x);\n+\t\t\t\tif (is_aperture > 0)\n+\t\t\t\t\t*pmax_effective_spads += aperture_attenuation;\n+\t\t\t\telse\n+\t\t\t\t\t*pmax_effective_spads += 0x0100;\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+VL53LX_Error VL53LX_get_dmax_calibration_data(VL53LX_DEV Dev, VL53LX_DeviceDmaxMode dmax_mode, VL53LX_dmax_calibration_data_t *pdmax_cal)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tswitch (dmax_mode) {\n+\tcase VL53LX_DEVICEDMAXMODE__CUST_CAL_DATA:\n+\t\tmemcpy(pdmax_cal, &(pdev->cust_dmax_cal), sizeof(VL53LX_dmax_calibration_data_t));\n+\t\tbreak;\n+\tcase VL53LX_DEVICEDMAXMODE__FMT_CAL_DATA:\n+\t\tmemcpy(pdmax_cal, &(pdev->fmt_dmax_cal), sizeof(VL53LX_dmax_calibration_data_t));\n+\t\tbreak;\n+\tdefault:\n+\t\tstatus = VL53LX_ERROR_INVALID_PARAMS;\n+\t\tbreak;\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_f_031(VL53LX_histogram_bin_data_t *pidata, VL53LX_histogram_bin_data_t *podata)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tuint8_t  bin_initial_index[VL53LX_MAX_BIN_SEQUENCE_CODE+1];\n+\tuint8_t  bin_repeat_count[VL53LX_MAX_BIN_SEQUENCE_CODE+1];\n+\tuint8_t  bin_cfg        = 0;\n+\tuint8_t  bin_seq_length = 0;\n+\tint32_t  repeat_count   = 0;\n+\tuint8_t  VL53LX_p_032       = 0;\n+\tuint8_t  lc       = 0;\n+\tuint8_t  i       = 0;\n+\n+\tmemcpy(podata, pidata, sizeof(VL53LX_histogram_bin_data_t));\n+\n+\tpodata->VL53LX_p_021 = 0;\n+\n+\tfor (lc = 0 ; lc < VL53LX_MAX_BIN_SEQUENCE_LENGTH ; lc++)\n+\t\tpodata->bin_seq[lc] = VL53LX_MAX_BIN_SEQUENCE_CODE+1;\n+\n+\tfor (lc = 0 ; lc < podata->VL53LX_p_020 ; lc++)\n+\t\tpodata->bin_data[lc] = 0;\n+\n+\tfor (lc = 0 ; lc <= VL53LX_MAX_BIN_SEQUENCE_CODE ; lc++) {\n+\t\tbin_initial_index[lc] = 0x00;\n+\t\tbin_repeat_count[lc]  = 0x00;\n+\t}\n+\n+\tbin_seq_length = 0x00;\n+\n+\tfor (lc = 0 ; lc < VL53LX_MAX_BIN_SEQUENCE_LENGTH ; lc++) {\n+\t\tbin_cfg = pidata->bin_seq[lc];\n+\n+\t\tif (bin_repeat_count[bin_cfg] == 0) {\n+\t\t\tbin_initial_index[bin_cfg]      = bin_seq_length * 4;\n+\t\t\tpodata->bin_seq[bin_seq_length] = bin_cfg;\n+\t\t\tbin_seq_length++;\n+\t\t}\n+\t\tbin_repeat_count[bin_cfg]++;\n+\n+\t\tVL53LX_p_032 = bin_initial_index[bin_cfg];\n+\n+\t\tfor (i = 0 ; i < 4 ; i++)\n+\t\t\tpodata->bin_data[VL53LX_p_032+i] +=\n+\t\t\t\tpidata->bin_data[lc*4+i];\n+\n+\t}\n+\tfor (lc = 0 ; lc < VL53LX_MAX_BIN_SEQUENCE_LENGTH ; lc++) {\n+\t\tbin_cfg = podata->bin_seq[lc];\n+\n+\t\tif (bin_cfg <= VL53LX_MAX_BIN_SEQUENCE_CODE)\n+\t\t\tpodata->bin_rep[lc] =\n+\t\t\t\tbin_repeat_count[bin_cfg];\n+\t\telse\n+\t\t\tpodata->bin_rep[lc] = 0;\n+\t}\n+\tpodata->VL53LX_p_021 = bin_seq_length * 4;\n+\n+\tfor (lc = 0 ; lc <= VL53LX_MAX_BIN_SEQUENCE_CODE ; lc++) {\n+\t\trepeat_count = (int32_t)bin_repeat_count[lc];\n+\t\tif (repeat_count > 0) {\n+\t\t\tVL53LX_p_032 = bin_initial_index[lc];\n+\t\t\tfor (i = 0 ; i < 4 ; i++) {\n+\t\t\t\tpodata->bin_data[VL53LX_p_032+i] += (repeat_count/2);\n+\t\t\t\tpodata->bin_data[VL53LX_p_032+i] /= repeat_count;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tpodata->number_of_ambient_bins = 0;\n+\tif ((bin_repeat_count[7] > 0) || (bin_repeat_count[15] > 0))\n+\t\tpodata->number_of_ambient_bins = 4;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_f_032(uint32_t mean_offset, int16_t xgradient, int16_t ygradient, int8_t centre_offset_x, int8_t centre_offset_y, uint16_t roi_effective_spads, uint8_t roi_centre_spad, uint8_t roi_xy_size, uint32_t *xtalk_rate_kcps)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tuint8_t row = 0;\n+\tuint8_t col = 0;\n+\tint16_t  bound_l_x = 0;\n+\tint16_t  bound_r_x = 0;\n+\tint16_t  bound_u_y = 0;\n+\tint16_t  bound_d_y = 0;\n+\tint64_t xtalk_rate_ll = 0;\n+\tint64_t xtalk_rate_ur = 0;\n+\tint64_t xtalk_avg = 0;\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tVL53LX_decode_row_col(roi_centre_spad, &row, &col);\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tif ((((int16_t)roi_xy_size / 16) & 0x01) == 1)\n+\t\t\tbound_l_x = (int16_t) col - (((int16_t)roi_xy_size / 32) + 1);\n+\t\telse\n+\t\t\tbound_l_x = (int16_t) col - ((int16_t)roi_xy_size / 32);\n+\n+\t\tbound_r_x = (int16_t) col + ((int16_t)roi_xy_size / 32);\n+\n+\t\tif ((((int16_t)roi_xy_size) & 0x01) == 1)\n+\t\t\tbound_d_y = (int16_t) row - ((((int16_t)roi_xy_size & 0x0f) / 2) + 1);\n+\t\telse\n+\t\t\tbound_d_y = (int16_t) row - (((int16_t)roi_xy_size & 0x0f) / 2);\n+\n+\t\tbound_u_y = (int16_t) row + (((int16_t)roi_xy_size & 0xf) / 2);\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tbound_l_x =  (2 * bound_l_x) - 15 + (2 * (int16_t)centre_offset_x);\n+\t\tbound_r_x =  (2 * bound_r_x) - 15 + (2 * (int16_t)centre_offset_x);\n+\t\tbound_u_y =  (2 * bound_u_y) - 15 + (2 * (int16_t)centre_offset_y);\n+\t\tbound_d_y =  (2 * bound_d_y) - 15 + (2 * (int16_t)centre_offset_y);\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\txtalk_rate_ll  = ((int64_t)bound_l_x * ((int64_t)xgradient)) + ((int64_t)bound_d_y * ((int64_t)ygradient));\n+\t\txtalk_rate_ll  = do_division_s((xtalk_rate_ll + 1), 2);\n+\t\txtalk_rate_ll += ((int64_t)mean_offset * 4);\n+\n+\t\txtalk_rate_ur  = ((int64_t)bound_r_x * ((int64_t)xgradient)) + ((int64_t)bound_u_y * ((int64_t)ygradient));\n+\t\txtalk_rate_ur  = do_division_s((xtalk_rate_ur + 1), 2);\n+\t\txtalk_rate_ur += ((int64_t)mean_offset * 4);\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\txtalk_avg = do_division_s(((xtalk_rate_ll + xtalk_rate_ur) + 1), 2);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tif (xtalk_avg < 0)\n+\t\t\txtalk_avg = 0;\n+\n+\t*xtalk_rate_kcps = (uint32_t) xtalk_avg;\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_f_033(VL53LX_histogram_bin_data_t *phist_data, VL53LX_xtalk_histogram_shape_t *pxtalk_data, uint32_t xtalk_rate_kcps, VL53LX_histogram_bin_data_t *pxtalkcount_data)\n+{\n+\tVL53LX_Error status              = VL53LX_ERROR_NONE;\n+\n+\tuint64_t xtalk_events_per_spad = 0;\n+\tuint64_t xtalk_total_events = 0;\n+\tuint64_t xtalk_temp_bin = 0;\n+\tuint8_t  i = 0;\n+\n+\txtalk_events_per_spad = do_division_u((((uint64_t)xtalk_rate_kcps * (uint64_t)phist_data->peak_duration_us) + 500), 1000);\n+\n+\txtalk_total_events = xtalk_events_per_spad * (uint64_t)phist_data->result__dss_actual_effective_spads;\n+\txtalk_total_events = do_division_u((xtalk_total_events), 256);\n+\txtalk_total_events = do_division_u((xtalk_total_events + 1024), 2048);\n+\n+\tif (xtalk_total_events > 0xFFFFFFFF)\n+\t\txtalk_total_events = 0xFFFFFFFF;\n+\n+\tfor (i = 0; i < pxtalk_data->VL53LX_p_021; i++) {\n+\t\txtalk_temp_bin = (uint64_t)pxtalk_data->bin_data[i] * (uint64_t)xtalk_total_events;\n+\t\txtalk_temp_bin = do_division_u((xtalk_temp_bin + 512), 1024);\n+\t\tpxtalkcount_data->bin_data[i] = (uint32_t)xtalk_temp_bin;\n+\t}\n+\treturn status;\n+}\n+\n+void VL53LX_copy_xtalk_bin_data_to_histogram_data_struct(VL53LX_xtalk_histogram_shape_t *pxtalk, VL53LX_histogram_bin_data_t *phist)\n+{\n+\tphist->cal_config__vcsel_start = pxtalk->cal_config__vcsel_start;\n+\tphist->VL53LX_p_015 = pxtalk->VL53LX_p_015;\n+\tphist->VL53LX_p_019 = pxtalk->VL53LX_p_019;\n+\n+\tphist->phasecal_result__reference_phase = pxtalk->phasecal_result__reference_phase;\n+\tphist->phasecal_result__vcsel_start = pxtalk->phasecal_result__vcsel_start;\n+\n+\tphist->vcsel_width = pxtalk->vcsel_width;\n+\tphist->zero_distance_phase = pxtalk->zero_distance_phase;\n+\n+\tphist->zone_id      = pxtalk->zone_id;\n+\tphist->VL53LX_p_020  = pxtalk->VL53LX_p_020;\n+\tphist->time_stamp   = pxtalk->time_stamp;\n+}\n+\n+void VL53LX_f_003(VL53LX_hist_gen3_algo_private_data_t *palgo)\n+{\n+\tuint8_t lb = 0;\n+\tpalgo->VL53LX_p_020 = VL53LX_HISTOGRAM_BUFFER_SIZE;\n+\tpalgo->VL53LX_p_019 = 0;\n+\tpalgo->VL53LX_p_021 = 0;\n+\tpalgo->VL53LX_p_039 = 0;\n+\tpalgo->VL53LX_p_028 = 0;\n+\tpalgo->VL53LX_p_031 = 0;\n+\n+\tfor (lb = palgo->VL53LX_p_019; lb < palgo->VL53LX_p_020; lb++) {\n+\t\tpalgo->VL53LX_p_040[lb]     = 0;\n+\t\tpalgo->VL53LX_p_041[lb]     = 0;\n+\t\tpalgo->VL53LX_p_042[lb]     = 0;\n+\t\tpalgo->VL53LX_p_043[lb]     = 0;\n+\t\tpalgo->VL53LX_p_018[lb]     = 0;\n+\t}\n+\tpalgo->VL53LX_p_044 = 0;\n+\tpalgo->VL53LX_p_045 = VL53LX_D_001;\n+\tpalgo->VL53LX_p_046 = 0;\n+\n+\tVL53LX_init_histogram_bin_data_struct(0, VL53LX_HISTOGRAM_BUFFER_SIZE, &(palgo->VL53LX_p_006));\n+\tVL53LX_init_histogram_bin_data_struct(0, VL53LX_HISTOGRAM_BUFFER_SIZE, &(palgo->VL53LX_p_047));\n+\tVL53LX_init_histogram_bin_data_struct(0, VL53LX_HISTOGRAM_BUFFER_SIZE, &(palgo->VL53LX_p_048));\n+\tVL53LX_init_histogram_bin_data_struct(0, VL53LX_HISTOGRAM_BUFFER_SIZE, &(palgo->VL53LX_p_049));\n+\tVL53LX_init_histogram_bin_data_struct(0, VL53LX_HISTOGRAM_BUFFER_SIZE, &(palgo->VL53LX_p_050));\n+}\n+\n+void VL53LX_hist_find_min_max_bin_values(VL53LX_histogram_bin_data_t *pdata)\n+{\n+\tuint8_t bin = 0;\n+\n+\tfor (bin = 0; bin < pdata->VL53LX_p_021; bin++) {\n+\t\tif (bin == 0 || pdata->min_bin_value >= pdata->bin_data[bin])\n+\t\t\tpdata->min_bin_value = pdata->bin_data[bin];\n+\n+\t\tif (bin == 0 || pdata->max_bin_value <= pdata->bin_data[bin])\n+\t\t\tpdata->max_bin_value = pdata->bin_data[bin];\n+\t}\n+}\n+\n+uint32_t VL53LX_isqrt(uint32_t num)\n+{\n+\tuint32_t  res = 0;\n+\tuint32_t  bit = 1 << 30;\n+\n+\twhile (bit > num)\n+\t\tbit >>= 2;\n+\n+\twhile (bit != 0) {\n+\t\tif (num >= res + bit)  {\n+\t\t\tnum -= res + bit;\n+\t\t\tres = (res >> 1) + bit;\n+\t\t} else {\n+\t\t\tres >>= 1;\n+\t\t}\n+\t\tbit >>= 2;\n+\t}\n+\n+\treturn res;\n+}\n+\n+\n+void VL53LX_hist_estimate_ambient_from_thresholded_bins(int32_t ambient_threshold_sigma, VL53LX_histogram_bin_data_t *pdata)\n+{\n+\tuint8_t  bin                      = 0;\n+\tint32_t  VL53LX_p_031 = 0;\n+\n+\tVL53LX_hist_find_min_max_bin_values(pdata);\n+\n+\tVL53LX_p_031  = (int32_t)VL53LX_isqrt((uint32_t)pdata->min_bin_value);\n+\tVL53LX_p_031 *= ambient_threshold_sigma;\n+\tVL53LX_p_031 += 0x07;\n+\tVL53LX_p_031  = VL53LX_p_031 >> 4;\n+\tVL53LX_p_031 += pdata->min_bin_value;\n+\n+\tpdata->number_of_ambient_samples = 0;\n+\tpdata->ambient_events_sum        = 0;\n+\n+\tfor (bin = 0; bin < pdata->VL53LX_p_021; bin++) {\n+\t\tif (pdata->bin_data[bin] < VL53LX_p_031) {\n+\t\t\tpdata->ambient_events_sum += pdata->bin_data[bin];\n+\t\t\tpdata->number_of_ambient_samples++;\n+\t\t}\n+\t}\n+\n+\tif (pdata->number_of_ambient_samples > 0) {\n+\t\tpdata->VL53LX_p_028  = pdata->ambient_events_sum;\n+\t\tpdata->VL53LX_p_028 += ((int32_t)pdata->number_of_ambient_samples/2);\n+\t\tpdata->VL53LX_p_028 /= (int32_t)pdata->number_of_ambient_samples;\n+\t}\n+}\n+\n+void VL53LX_hist_remove_ambient_bins(VL53LX_histogram_bin_data_t *pdata)\n+{\n+\tuint8_t bin = 0;\n+\tuint8_t lc = 0;\n+\tuint8_t i = 0;\n+\n+\tif ((pdata->bin_seq[0] & 0x07) == 0x07) {\n+\t\ti = 0;\n+\t\tfor (lc = 0; lc < VL53LX_MAX_BIN_SEQUENCE_LENGTH; lc++) {\n+\t\t\tif ((pdata->bin_seq[lc] & 0x07) != 0x07) {\n+\t\t\t\tpdata->bin_seq[i] = pdata->bin_seq[lc];\n+\t\t\t\tpdata->bin_rep[i] = pdata->bin_rep[lc];\n+\t\t\t\ti++;\n+\t\t\t}\n+\t\t}\n+\t\tfor (lc = i; lc < VL53LX_MAX_BIN_SEQUENCE_LENGTH; lc++) {\n+\t\t\tpdata->bin_seq[lc] = VL53LX_MAX_BIN_SEQUENCE_CODE + 1;\n+\t\t\tpdata->bin_rep[lc] = 0;\n+\t\t}\n+\t}\n+\tif (pdata->number_of_ambient_bins > 0) {\n+\t\tfor (bin = pdata->number_of_ambient_bins; bin < pdata->VL53LX_p_020; bin++) {\n+\t\t\tpdata->bin_data[bin-pdata->number_of_ambient_bins] = pdata->bin_data[bin];\n+\t\t}\n+\t\tpdata->VL53LX_p_021 = pdata->VL53LX_p_021 - pdata->number_of_ambient_bins;\n+\t\tpdata->number_of_ambient_bins = 0;\n+\t}\n+}\n+\n+int8_t VL53LX_f_030(VL53LX_histogram_bin_data_t *pdata1, VL53LX_histogram_bin_data_t *pdata2)\n+{\n+\tint32_t  phase_delta      = 0;\n+\tint8_t   bin_offset       = 0;\n+\tuint32_t period           = 0;\n+\tuint32_t remapped_phase   = 0;\n+\n+\tperiod = 2048 * (uint32_t)VL53LX_decode_vcsel_period(pdata1->VL53LX_p_005);\n+\n+\tif (period != 0)\n+\t\tremapped_phase = (uint32_t)pdata2->zero_distance_phase % period;\n+\n+\tphase_delta = (int32_t)pdata1->zero_distance_phase - (int32_t)remapped_phase;\n+\n+\tif (phase_delta > 0)\n+\t\tbin_offset = (int8_t)((phase_delta + 1024) / 2048);\n+\telse\n+\t\tbin_offset = (int8_t)((phase_delta - 1024) / 2048);\n+\n+\treturn bin_offset;\n+}\n+\n+void VL53LX_f_005(VL53LX_histogram_bin_data_t *pxtalk, VL53LX_histogram_bin_data_t *pbins, VL53LX_histogram_bin_data_t *pxtalk_realigned)\n+{\n+\tuint8_t i          = 0;\n+\tuint8_t min_bins   = 0;\n+\tint8_t  bin_offset = 0;\n+\tint8_t  bin_access = 0;\n+\n+\tmemcpy(pxtalk_realigned, pbins, sizeof(VL53LX_histogram_bin_data_t));\n+\n+\tfor (i = 0 ; i < pxtalk_realigned->VL53LX_p_020 ; i++)\n+\t\tpxtalk_realigned->bin_data[i] = 0;\n+\n+\tbin_offset = VL53LX_f_030(pbins, pxtalk);\n+\n+\tif (pxtalk->VL53LX_p_021 < pbins->VL53LX_p_021)\n+\t\tmin_bins = pxtalk->VL53LX_p_021;\n+\telse\n+\t\tmin_bins = pbins->VL53LX_p_021;\n+\n+\tfor (i = 0 ; i <  min_bins ; i++) {\n+\t\tif (bin_offset >= 0)\n+\t\t\tbin_access = ((int8_t)i + (int8_t)bin_offset) % (int8_t)pbins->VL53LX_p_021;\n+\t\telse\n+\t\t\tbin_access = ((int8_t)pbins->VL53LX_p_021 + ((int8_t)i + (int8_t)bin_offset)) % (int8_t)pbins->VL53LX_p_021;\n+\n+\t\tif (pbins->bin_data[(uint8_t)bin_access] > pxtalk->bin_data[i]) {\n+\t\t\tpbins->bin_data[(uint8_t)bin_access] = pbins->bin_data[(uint8_t)bin_access] - pxtalk->bin_data[i];\n+\t\t} else {\n+\t\t\tpbins->bin_data[(uint8_t)bin_access] = 0;\n+\t\t}\n+\t\tpxtalk_realigned->bin_data[(uint8_t)bin_access] = pxtalk->bin_data[i];\n+\n+\n+\n+\t}\n+}\n+\n+uint16_t VL53LX_rate_maths(int32_t VL53LX_p_018, uint32_t time_us)\n+{\n+\tuint32_t  tmp_int   = 0;\n+\tuint32_t  frac_bits = 7;\n+\tuint16_t  rate_mcps = 0;\n+\n+\tif (VL53LX_p_018 > VL53LX_SPAD_TOTAL_COUNT_MAX)\n+\t\ttmp_int = VL53LX_SPAD_TOTAL_COUNT_MAX;\n+\telse if (VL53LX_p_018 > 0)\n+\t\ttmp_int = (uint32_t)VL53LX_p_018;\n+\n+\tif (VL53LX_p_018 > VL53LX_SPAD_TOTAL_COUNT_RES_THRES)\n+\t\tfrac_bits = 3;\n+\telse\n+\t\tfrac_bits = 7;\n+\n+\tif (time_us > 0)\n+\t\ttmp_int = ((tmp_int << frac_bits) + (time_us / 2)) / time_us;\n+\n+\tif (VL53LX_p_018 > VL53LX_SPAD_TOTAL_COUNT_RES_THRES)\n+\t\ttmp_int = tmp_int << 4;\n+\n+\tif (tmp_int > 0xFFFF)\n+\t\ttmp_int = 0xFFFF;\n+\n+\trate_mcps =  (uint16_t)tmp_int;\n+\treturn rate_mcps;\n+}\n+\n+uint32_t VL53LX_events_per_spad_maths(int32_t VL53LX_p_010, uint16_t num_spads, uint32_t duration)\n+{\n+\tuint64_t total_hist_counts  = 0;\n+\tuint64_t xtalk_per_spad     = 0;\n+\tuint32_t rate_per_spad_kcps = 0;\n+\tuint64_t dividend = ((uint64_t)VL53LX_p_010 * 1000 * 256);\n+\n+\tif (num_spads != 0)\n+\t\ttotal_hist_counts = do_division_u(dividend, (uint64_t)num_spads);\n+\n+\tif (duration > 0) {\n+\t\tuint64_t dividend = (((uint64_t)(total_hist_counts << 11)) + ((uint64_t)duration / 2));\n+\t\txtalk_per_spad = do_division_u(dividend, (uint64_t)duration);\n+\t} else {\n+\t\txtalk_per_spad = (uint64_t)(total_hist_counts << 11);\n+\t}\n+\trate_per_spad_kcps = (uint32_t)xtalk_per_spad;\n+\treturn rate_per_spad_kcps;\n+}\n+\n+uint32_t VL53LX_f_002(uint32_t events_threshold, uint32_t ref_signal_events, uint32_t ref_distance_mm, uint32_t signal_thresh_sigma)\n+{\n+\tuint32_t    tmp32               = 0;\n+\tuint32_t    range_mm            = 0;\n+\n+\ttmp32 = 4 * events_threshold;\n+\ttmp32 += ((uint32_t)signal_thresh_sigma * (uint32_t)signal_thresh_sigma);\n+\ttmp32  = VL53LX_isqrt(tmp32);\n+\ttmp32 += (uint32_t)signal_thresh_sigma;\n+\n+\trange_mm = (uint32_t)VL53LX_isqrt(ref_signal_events << 4);\n+\trange_mm *= ref_distance_mm;\n+\tif (tmp32 != 0) {\n+\t\trange_mm += (tmp32);\n+\t\trange_mm /= (2*tmp32);\n+\t}\n+\treturn range_mm;\n+}\n+\n+VL53LX_Error VL53LX_f_001(\n+\tuint16_t                              target_reflectance,\n+\tVL53LX_dmax_calibration_data_t\t     *pcal,\n+\tVL53LX_hist_gen3_dmax_config_t\t     *pcfg,\n+\tVL53LX_histogram_bin_data_t          *pbins,\n+\tVL53LX_hist_gen3_dmax_private_data_t *pdata,\n+\tint16_t                              *pambient_dmax_mm)\n+{\n+\tVL53LX_Error status  = VL53LX_ERROR_NONE;\n+\tuint32_t    pll_period_us       = 0;\n+\tuint32_t    periods_elapsed     = 0;\n+\tuint32_t    tmp32               = 0;\n+\tuint64_t    tmp64               = 0;\n+\tuint32_t    amb_thres_delta     = 0;\n+\n+\tpdata->VL53LX_p_004 = 0x0000;\n+\tpdata->VL53LX_p_033 = 0x0000;\n+\tpdata->VL53LX_p_034 = 0x0000;\n+\tpdata->VL53LX_p_009 = 0x0000;\n+\tpdata->VL53LX_p_028 = 0x0000;\n+\tpdata->VL53LX_p_035 = 0x0000;\n+\tpdata->VL53LX_p_036 = 0;\n+\tpdata->VL53LX_p_022 = 0;\n+\t*pambient_dmax_mm   = 0;\n+\n+\tif ((pbins->VL53LX_p_015 != 0) && (pbins->total_periods_elapsed != 0)) {\n+\t\tpll_period_us = VL53LX_calc_pll_period_us(pbins->VL53LX_p_015);\n+\t\tperiods_elapsed = pbins->total_periods_elapsed + 1;\n+\t\tpdata->VL53LX_p_037 = VL53LX_duration_maths(pll_period_us, 1<<4, VL53LX_RANGING_WINDOW_VCSEL_PERIODS, periods_elapsed);\n+\t\tpdata->VL53LX_p_034 = VL53LX_rate_maths(pbins->VL53LX_p_028, pdata->VL53LX_p_037);\n+\t\tpdata->VL53LX_p_033 = VL53LX_events_per_spad_maths(pbins->VL53LX_p_028, pbins->result__dss_actual_effective_spads, pdata->VL53LX_p_037);\n+\t\tpdata->VL53LX_p_038 = pcfg->max_effective_spads;\n+\t\tpdata->VL53LX_p_004  = pcfg->max_effective_spads;\n+\n+\t\tif (pdata->VL53LX_p_033 > 0) {\n+\t\t\ttmp64   = (uint64_t)pcfg->dss_config__target_total_rate_mcps;\n+\t\t\ttmp64  *= 1000;\n+\t\t\ttmp64 <<= (11+1);\n+\t\t\ttmp32  = pdata->VL53LX_p_033/2;\n+\t\t\ttmp64 += (uint64_t)tmp32;\n+\t\t\ttmp64 = do_division_u(tmp64, (uint64_t)pdata->VL53LX_p_033);\n+\t\t\tif (tmp64 < (uint64_t)pcfg->max_effective_spads)\n+\t\t\t\tpdata->VL53LX_p_004 = (uint16_t)tmp64;\n+\t\t}\n+\t}\n+\tif ((pcal->ref__actual_effective_spads != 0) && (pbins->VL53LX_p_015 != 0) && (pcal->ref_reflectance_pc != 0) && (pbins->total_periods_elapsed != 0)) {\n+\t\ttmp64  = (uint64_t)pcal->ref__peak_signal_count_rate_mcps;\n+\t\ttmp64 *= (1000 * 256);\n+\t\ttmp32  = pcal->ref__actual_effective_spads/2;\n+\t\ttmp64 += (uint64_t)tmp32;\n+\t\ttmp64  = do_division_u(tmp64, (uint64_t)pcal->ref__actual_effective_spads);\n+\n+\t\tpdata->VL53LX_p_009   = (uint32_t)tmp64;\n+\t\tpdata->VL53LX_p_009 <<= 4;\n+\n+\t\ttmp64   = (uint64_t)pdata->VL53LX_p_037;\n+\t\ttmp64  *= (uint64_t)pdata->VL53LX_p_033;\n+\t\ttmp64  *= (uint64_t)pdata->VL53LX_p_004;\n+\t\ttmp64  += (1<<(11+7));\n+\t\ttmp64 >>= (11+8);\n+\t\ttmp64  +=  500;\n+\t\ttmp64   = do_division_u(tmp64, 1000);\n+\n+\t\tif (tmp64 > 0x00FFFFFF)\n+\t\t\ttmp64 = 0x00FFFFFF;\n+\n+\t\tpdata->VL53LX_p_028 = (uint32_t)tmp64;\n+\t\ttmp64   = (uint64_t)pdata->VL53LX_p_037;\n+\t\ttmp64  *= (uint64_t)pdata->VL53LX_p_009;\n+\t\ttmp64  *= (uint64_t)pdata->VL53LX_p_004;\n+\t\ttmp64  += (1<<(11+7));\n+\t\ttmp64 >>= (11+8);\n+\t\ttmp64  *= ((uint64_t)target_reflectance * (uint64_t)pcal->coverglass_transmission);\n+\t\ttmp64  += ((uint64_t)pcal->ref_reflectance_pc * 128);\n+\t\ttmp64  = do_division_u(tmp64, ((uint64_t)pcal->ref_reflectance_pc * 256));\n+\t\ttmp64  +=  500;\n+\t\ttmp64  = do_division_u(tmp64, 1000);\n+\t\tif (tmp64 > 0x00FFFFFF)\n+\t\t\ttmp64 = 0x00FFFFFF;\n+\t\tpdata->VL53LX_p_035 = (uint32_t)tmp64;\n+\t\ttmp32  = VL53LX_isqrt(pdata->VL53LX_p_028 << 8);\n+\t\ttmp32 *= (uint32_t)pcfg->ambient_thresh_sigma;\n+\t\tif (pdata->VL53LX_p_028 < (uint32_t)pcfg->min_ambient_thresh_events) {\n+\t\t\tamb_thres_delta = pcfg->min_ambient_thresh_events - (uint32_t)pdata->VL53LX_p_028;\n+\t\t\tamb_thres_delta <<= 8;\n+\t\t\tif (tmp32 < amb_thres_delta)\n+\t\t\t\ttmp32 = amb_thres_delta;\n+\t\t}\n+\t\tpdata->VL53LX_p_022 = (int16_t)VL53LX_f_002(tmp32, pdata->VL53LX_p_035, (uint32_t)pcal->ref__distance_mm, (uint32_t)pcfg->signal_thresh_sigma);\n+\n+\t\ttmp32  = (uint32_t)pdata->VL53LX_p_035;\n+\t\ttmp32 *= (uint32_t)pbins->vcsel_width;\n+\t\ttmp32 += (1 << 3);\n+\t\ttmp32 /= (1 << 4);\n+\n+\t\tpdata->VL53LX_p_036 = (int16_t)VL53LX_f_002(256 * (uint32_t)pcfg->signal_total_events_limit, tmp32, (uint32_t)pcal->ref__distance_mm, (uint32_t)pcfg->signal_thresh_sigma);\n+\n+\t\tif (pdata->VL53LX_p_036 < pdata->VL53LX_p_022)\n+\t\t\t*pambient_dmax_mm = pdata->VL53LX_p_036;\n+\t\telse\n+\t\t\t*pambient_dmax_mm = pdata->VL53LX_p_022;\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_f_006(\n+\tuint16_t ambient_threshold_events_scaler,\n+\tint32_t ambient_threshold_sigma,\n+\tint32_t min_ambient_threshold_events,\n+\tuint8_t algo__crosstalk_compensation_enable,\n+\tVL53LX_histogram_bin_data_t *pbins,\n+\tVL53LX_histogram_bin_data_t *pxtalk,\n+\tVL53LX_hist_gen3_algo_private_data_t *palgo)\n+{\n+\tVL53LX_Error  status  = VL53LX_ERROR_NONE;\n+\tuint8_t  lb            = 0;\n+\tuint8_t  VL53LX_p_001            = 0;\n+\tint64_t  tmp          = 0;\n+\tint32_t  amb_events   = 0;\n+\tint32_t  VL53LX_p_018       = 0;\n+\tint32_t  samples      = 0;\n+\n+\tpalgo->VL53LX_p_020 = pbins->VL53LX_p_020;\n+\tpalgo->VL53LX_p_019 = pbins->VL53LX_p_019;\n+\tpalgo->VL53LX_p_021 = pbins->VL53LX_p_021;\n+\tpalgo->VL53LX_p_028 = pbins->VL53LX_p_028;\n+\tpalgo->VL53LX_p_030 = VL53LX_decode_vcsel_period(pbins->VL53LX_p_005);\n+\n+\ttmp  = (int64_t)pbins->VL53LX_p_028;\n+\ttmp *= (int64_t)ambient_threshold_events_scaler;\n+\ttmp += 2048;\n+\ttmp  = do_division_s(tmp, 4096);\n+\tamb_events = (int32_t)tmp;\n+\n+\tfor (lb = 0; lb < pbins->VL53LX_p_021; lb++) {\n+\t\tVL53LX_p_001 = lb >> 2;\n+\t\tsamples = (int32_t)pbins->bin_rep[VL53LX_p_001];\n+\t\tif (samples > 0) {\n+\t\t\tif (lb < pxtalk->VL53LX_p_021 && algo__crosstalk_compensation_enable > 0)\n+\t\t\t\tVL53LX_p_018 = samples * (amb_events + pxtalk->bin_data[lb]);\n+\t\t\telse\n+\t\t\t\tVL53LX_p_018 = samples *  amb_events;\n+\t\t\tVL53LX_p_018  = VL53LX_isqrt(VL53LX_p_018);\n+\t\t\tVL53LX_p_018 += (samples/2);\n+\t\t\tVL53LX_p_018 /= samples;\n+\t\t\tVL53LX_p_018 *= ambient_threshold_sigma;\n+\t\t\tVL53LX_p_018 += 8;\n+\t\t\tVL53LX_p_018 /= 16;\n+\t\t\tVL53LX_p_018 += amb_events;\n+\t\t\tif (VL53LX_p_018 < min_ambient_threshold_events)\n+\t\t\t\tVL53LX_p_018 = min_ambient_threshold_events;\n+\t\t\tpalgo->VL53LX_p_052[lb]             = VL53LX_p_018;\n+\t\t\tpalgo->VL53LX_p_031 = VL53LX_p_018;\n+\t\t}\n+\t}\n+\tpalgo->VL53LX_p_039 = 0;\n+\tfor (lb = pbins->VL53LX_p_019; lb < pbins->VL53LX_p_021; lb++) {\n+\t\tif (pbins->bin_data[lb] > palgo->VL53LX_p_052[lb]) {\n+\t\t\tpalgo->VL53LX_p_040[lb] = 1;\n+\t\t\tpalgo->VL53LX_p_041[lb] = 1;\n+\t\t\tpalgo->VL53LX_p_039++;\n+\t\t} else {\n+\t\t\tpalgo->VL53LX_p_040[lb] = 0;\n+\t\t\tpalgo->VL53LX_p_041[lb] = 0;\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_f_007(VL53LX_hist_gen3_algo_private_data_t *palgo)\n+{\n+\tVL53LX_Error  status  = VL53LX_ERROR_NONE;\n+\tuint8_t  i            = 0;\n+\tuint8_t  j            = 0;\n+\tuint8_t  found        = 0;\n+\n+\tpalgo->VL53LX_p_044 = 0;\n+\tfor (i = 0; i < palgo->VL53LX_p_030; i++) {\n+\t\tj = (i + 1) % palgo->VL53LX_p_030;\n+\t\tif (i < palgo->VL53LX_p_021 && j < palgo->VL53LX_p_021) {\n+\t\t\tif (palgo->VL53LX_p_041[i] == 0 && palgo->VL53LX_p_041[j] == 1 && found == 0) {\n+\t\t\t\tpalgo->VL53LX_p_044 = i;\n+\t\t\t\tfound = 1;\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_f_008(VL53LX_hist_gen3_algo_private_data_t *palgo)\n+{\n+\tVL53LX_Error  status  = VL53LX_ERROR_NONE;\n+\tuint8_t  i            = 0;\n+\tuint8_t  j            = 0;\n+\tuint8_t  lb            = 0;\n+\n+\tfor (lb = palgo->VL53LX_p_044; lb < (palgo->VL53LX_p_044 + palgo->VL53LX_p_030); lb++) {\n+\t\ti =  lb      % palgo->VL53LX_p_030;\n+\t\tj = (lb + 1) % palgo->VL53LX_p_030;\n+\t\tif (i < palgo->VL53LX_p_021 && j < palgo->VL53LX_p_021) {\n+\t\t\tif (palgo->VL53LX_p_041[i] == 0 && palgo->VL53LX_p_041[j] == 1)\n+\t\t\t\tpalgo->VL53LX_p_046++;\n+\t\t\tif (palgo->VL53LX_p_046 > palgo->VL53LX_p_045)\n+\t\t\t\tpalgo->VL53LX_p_046 = palgo->VL53LX_p_045;\n+\t\t\tif (palgo->VL53LX_p_041[i] > 0)\n+\t\t\t\tpalgo->VL53LX_p_042[i] = palgo->VL53LX_p_046;\n+\t\t\telse\n+\t\t\t\tpalgo->VL53LX_p_042[i] = 0;\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_f_009(VL53LX_hist_gen3_algo_private_data_t *palgo)\n+{\n+\tVL53LX_Error  status  = VL53LX_ERROR_NONE;\n+\n+\tuint8_t  i            = 0;\n+\tuint8_t  j            = 0;\n+\tuint8_t  blb            = 0;\n+\tuint8_t  pulse_no     = 0;\n+\tuint8_t  max_filter_half_width = 0;\n+\tVL53LX_hist_pulse_data_t *pdata;\n+\n+\tmax_filter_half_width = palgo->VL53LX_p_030 - 1;\n+\tmax_filter_half_width = max_filter_half_width >> 1;\n+\n+\tfor (blb = palgo->VL53LX_p_044; blb < (palgo->VL53LX_p_044 + palgo->VL53LX_p_030); blb++) {\n+\t\ti =  blb      % palgo->VL53LX_p_030;\n+\t\tj = (blb + 1) % palgo->VL53LX_p_030;\n+\n+\t\tif (i < palgo->VL53LX_p_021 && j < palgo->VL53LX_p_021) {\n+\t\t\tif (palgo->VL53LX_p_042[i] == 0 && palgo->VL53LX_p_042[j] > 0) {\n+\t\t\t\tpulse_no = palgo->VL53LX_p_042[j] - 1;\n+\t\t\t\tif (pulse_no < palgo->VL53LX_p_045) {\n+\t\t\t\t\tpdata = &(palgo->VL53LX_p_003[pulse_no]);\n+\t\t\t\t\tpdata->VL53LX_p_012 = blb;\n+\t\t\t\t\tpdata->VL53LX_p_019    = blb + 1;\n+\t\t\t\t\tpdata->VL53LX_p_023   = 0xFF;\n+\t\t\t\t\tpdata->VL53LX_p_024     = 0;\n+\t\t\t\t\tpdata->VL53LX_p_013   = 0;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tif (palgo->VL53LX_p_042[i] > 0 && palgo->VL53LX_p_042[j] == 0) {\n+\t\t\t\tpulse_no = palgo->VL53LX_p_042[i] - 1;\n+\t\t\t\tif (pulse_no < palgo->VL53LX_p_045) {\n+\t\t\t\t\tpdata = &(palgo->VL53LX_p_003[pulse_no]);\n+\t\t\t\t\tpdata->VL53LX_p_024 = blb;\n+\t\t\t\t\tpdata->VL53LX_p_013 = blb + 1;\n+\t\t\t\t\tpdata->VL53LX_p_025 = (pdata->VL53LX_p_024 + 1) - pdata->VL53LX_p_019;\n+\t\t\t\t\tpdata->VL53LX_p_051 = (pdata->VL53LX_p_013 + 1) - pdata->VL53LX_p_012;\n+\t\t\t\t\tif (pdata->VL53LX_p_051 > max_filter_half_width)\n+\t\t\t\t\t\tpdata->VL53LX_p_051 = max_filter_half_width;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_f_010(uint8_t pulse_no, VL53LX_histogram_bin_data_t *pbins, VL53LX_hist_gen3_algo_private_data_t *palgo)\n+{\n+\tVL53LX_Error  status  = VL53LX_ERROR_NONE;\n+\tuint8_t  i            = 0;\n+\tuint8_t  lb            = 0;\n+\n+\tVL53LX_hist_pulse_data_t *pdata = &(palgo->VL53LX_p_003[pulse_no]);\n+\tpdata->VL53LX_p_017  = 0;\n+\tpdata->VL53LX_p_016 = 0;\n+\n+\tfor (lb = pdata->VL53LX_p_012; lb <= pdata->VL53LX_p_013; lb++) {\n+\t\ti =  lb % palgo->VL53LX_p_030;\n+\t\tpdata->VL53LX_p_017 += pbins->bin_data[i];\n+\t\tpdata->VL53LX_p_016 += palgo->VL53LX_p_028;\n+\t}\n+\tpdata->VL53LX_p_010 = pdata->VL53LX_p_017 - pdata->VL53LX_p_016;\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_f_011(\n+\tuint8_t                                pulse_no,\n+\tVL53LX_histogram_bin_data_t           *pbins,\n+\tVL53LX_hist_gen3_algo_private_data_t  *palgo,\n+\tint32_t                                pad_value,\n+\tVL53LX_histogram_bin_data_t           *ppulse)\n+{\n+\tVL53LX_Error  status  = VL53LX_ERROR_NONE;\n+\n+\tuint8_t  i            = 0;\n+\tuint8_t  lb            = 0;\n+\tVL53LX_hist_pulse_data_t *pdata = &(palgo->VL53LX_p_003[pulse_no]);\n+\n+\tmemcpy(ppulse, pbins, sizeof(VL53LX_histogram_bin_data_t));\n+\n+\tfor (lb = palgo->VL53LX_p_044; lb < (palgo->VL53LX_p_044 + palgo->VL53LX_p_030); lb++) {\n+\t\tif (lb < pdata->VL53LX_p_012 || lb > pdata->VL53LX_p_013) {\n+\t\t\ti =  lb % palgo->VL53LX_p_030;\n+\t\t\tif (i < ppulse->VL53LX_p_021)\n+\t\t\t\tppulse->bin_data[i] = pad_value;\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+void VL53LX_f_022(uint8_t VL53LX_p_032, uint8_t filter_woi, VL53LX_histogram_bin_data_t *pbins, int32_t *pa, int32_t *pb, int32_t *pc)\n+{\n+\tuint8_t w = 0;\n+\tuint8_t j = 0;\n+\n+\t*pa = 0;\n+\t*pb = pbins->bin_data[VL53LX_p_032];\n+\t*pc = 0;\n+\n+\tfor (w = 0 ; w < ((filter_woi << 1)+1) ; w++) {\n+\t\tj = ((VL53LX_p_032 + w + pbins->VL53LX_p_021) - filter_woi) % pbins->VL53LX_p_021;\n+\t\tif (w < filter_woi)\n+\t\t\t*pa += pbins->bin_data[j];\n+\t\telse if (w > filter_woi)\n+\t\t\t*pc += pbins->bin_data[j];\n+\t}\n+}\n+\n+VL53LX_Error VL53LX_f_026(\n+\tuint8_t                                pulse_no,\n+\tVL53LX_histogram_bin_data_t           *ppulse,\n+\tVL53LX_hist_gen3_algo_private_data_t  *palgo3,\n+\tVL53LX_hist_gen4_algo_filtered_data_t *pfiltered)\n+{\n+\tVL53LX_Error  status       = VL53LX_ERROR_NONE;\n+\tVL53LX_hist_pulse_data_t *pdata = &(palgo3->VL53LX_p_003[pulse_no]);\n+\n+\tuint8_t  lb    = 0;\n+\tuint8_t  i     = 0;\n+\tint32_t  suma  = 0;\n+\tint32_t  sumb  = 0;\n+\tint32_t  sumc  = 0;\n+\n+\tpfiltered->VL53LX_p_020 = palgo3->VL53LX_p_020;\n+\tpfiltered->VL53LX_p_019 = palgo3->VL53LX_p_019;\n+\tpfiltered->VL53LX_p_021 = palgo3->VL53LX_p_021;\n+\n+\tfor (lb = pdata->VL53LX_p_012; lb <= pdata->VL53LX_p_013; lb++) {\n+\t\ti = lb % palgo3->VL53LX_p_030;\n+\t\tVL53LX_f_022(i, pdata->VL53LX_p_051, ppulse, &suma, &sumb, &sumc);\n+\n+\t\tpfiltered->VL53LX_p_007[i] = suma;\n+\t\tpfiltered->VL53LX_p_032[i] = sumb;\n+\t\tpfiltered->VL53LX_p_001[i] = sumc;\n+\t\tpfiltered->VL53LX_p_053[i] = (suma + sumb) - (sumc + palgo3->VL53LX_p_028);\n+\t\tpfiltered->VL53LX_p_054[i] = (sumb + sumc) - (suma + palgo3->VL53LX_p_028);\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_f_028(\n+\tuint8_t   bin,\n+\tint32_t   VL53LX_p_007,\n+\tint32_t   VL53LX_p_032,\n+\tint32_t   VL53LX_p_001,\n+\tint32_t   ax,\n+\tint32_t   bx,\n+\tint32_t   cx,\n+\tint32_t   VL53LX_p_028,\n+\tuint8_t   VL53LX_p_030,\n+\tuint32_t *pmean_phase)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_DIVISION_BY_ZERO;\n+\n+\tint64_t  mean_phase  = VL53LX_MAX_ALLOWED_PHASE;\n+\tint32_t  mean_phase32;\n+\tint64_t  VL53LX_p_055   = 0;\n+\tint64_t  half_b_minus_amb = 0;\n+\n+\tVL53LX_p_055     = 4096 * ((int64_t)VL53LX_p_001 - (int64_t)cx - (int64_t)VL53LX_p_007 -  (int64_t)ax);\n+\thalf_b_minus_amb = 4096 * ((int64_t)VL53LX_p_032 - (int64_t)bx - (int64_t)VL53LX_p_028);\n+\n+\tif (half_b_minus_amb != 0) {\n+\t\tmean_phase = (4096 * VL53LX_p_055) + half_b_minus_amb;\n+\t\tmean_phase = do_division_s(mean_phase, (half_b_minus_amb * 2));\n+\t\tmean_phase  +=  2048;\n+\t\tmean_phase  += (4096 * (int64_t)bin);\n+\t\tmean_phase  = do_division_s((mean_phase + 1), 2);\n+\t\tif (mean_phase  < 0)\n+\t\t\tmean_phase = 0;\n+\t\tif (mean_phase > VL53LX_MAX_ALLOWED_PHASE)\n+\t\t\tmean_phase = VL53LX_MAX_ALLOWED_PHASE;\n+\t\tmean_phase32 = (int32_t)mean_phase;\n+\t\tmean_phase32 = mean_phase32 % ((int32_t)VL53LX_p_030 * 2048);\n+\t\tmean_phase = mean_phase32;\n+\t\tstatus = VL53LX_ERROR_NONE;\n+\t}\n+\t*pmean_phase = (uint32_t)mean_phase;\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_f_027(uint8_t pulse_no, uint16_t noise_threshold, VL53LX_hist_gen4_algo_filtered_data_t *pfiltered, VL53LX_hist_gen3_algo_private_data_t *palgo3)\n+{\n+\tVL53LX_Error  status       = VL53LX_ERROR_NONE;\n+\tVL53LX_Error  func_status  = VL53LX_ERROR_NONE;\n+\tVL53LX_hist_pulse_data_t *pdata = &(palgo3->VL53LX_p_003[pulse_no]);\n+\n+\tuint8_t  lb            = 0;\n+\tuint8_t  i            = 0;\n+\tuint8_t  j            = 0;\n+\n+\tfor (lb = pdata->VL53LX_p_012; lb < pdata->VL53LX_p_013; lb++) {\n+\t\ti =  lb    % palgo3->VL53LX_p_030;\n+\t\tj = (lb+1) % palgo3->VL53LX_p_030;\n+\t\tif (i < palgo3->VL53LX_p_021 && j < palgo3->VL53LX_p_021) {\n+\t\t\tif (pfiltered->VL53LX_p_053[i] == 0 && pfiltered->VL53LX_p_054[i] == 0)\n+\t\t\t\tpfiltered->VL53LX_p_040[i] = 0;\n+\t\t\telse if (pfiltered->VL53LX_p_053[i] >= 0 && pfiltered->VL53LX_p_054[i] >= 0)\n+\t\t\t\tpfiltered->VL53LX_p_040[i] = 1;\n+\t\t\telse if (pfiltered->VL53LX_p_053[i] <  0 && pfiltered->VL53LX_p_054[i] >= 0 && pfiltered->VL53LX_p_053[j] >= 0 && pfiltered->VL53LX_p_054[j] <  0)\n+\t\t\t\tpfiltered->VL53LX_p_040[i] = 1;\n+\t\t\telse\n+\t\t\t\tpfiltered->VL53LX_p_040[i] = 0;\n+\n+\t\t\tif (pfiltered->VL53LX_p_040[i] > 0) {\n+\t\t\t\tpdata->VL53LX_p_023 = lb;\n+\t\t\t\tfunc_status =\n+\t\t\t\t\tVL53LX_f_028(\n+\t\t\t\t\tlb,\n+\t\t\t\t\tpfiltered->VL53LX_p_007[i],\n+\t\t\t\t\tpfiltered->VL53LX_p_032[i],\n+\t\t\t\t\tpfiltered->VL53LX_p_001[i],\n+\t\t\t\t\t0,\n+\t\t\t\t\t0,\n+\t\t\t\t\t0,\n+\t\t\t\t\tpalgo3->VL53LX_p_028,\n+\t\t\t\t\tpalgo3->VL53LX_p_030,\n+\t\t\t\t\t&(pdata->VL53LX_p_011));\n+\n+\t\t\t\tif (func_status ==\n+\t\t\t\t\tVL53LX_ERROR_DIVISION_BY_ZERO)\n+\t\t\t\t\tpfiltered->VL53LX_p_040[i] = 0;\n+\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+uint32_t VL53LX_calc_pll_period_mm(uint16_t fast_osc_frequency)\n+{\n+\tuint32_t pll_period_us = 0;\n+\tuint32_t pll_period_mm = 0;\n+\n+\tpll_period_us  = VL53LX_calc_pll_period_us(fast_osc_frequency);\n+\tpll_period_mm = VL53LX_SPEED_OF_LIGHT_IN_AIR_DIV_8 * (pll_period_us >> 2);\n+\tpll_period_mm = (pll_period_mm + (0x01<<15)) >> 16;\n+\n+\treturn pll_period_mm;\n+}\n+\n+VL53LX_Error VL53LX_f_023(\n+\tuint8_t\t sigma_estimator__sigma_ref_mm,\n+\tuint32_t VL53LX_p_007,\n+\tuint32_t VL53LX_p_032,\n+\tuint32_t VL53LX_p_001,\n+\tuint32_t a_zp,\n+\tuint32_t c_zp,\n+\tuint32_t bx,\n+\tuint32_t ax_zp,\n+\tuint32_t cx_zp,\n+\tuint32_t VL53LX_p_028,\n+\tuint16_t fast_osc_frequency,\n+\tuint16_t *psigma_est)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_DIVISION_BY_ZERO;\n+\tuint32_t sigma_int  = VL53LX_D_002;\n+\tuint32_t pll_period_mm  = 0;\n+\tuint64_t tmp0        = 0;\n+\tuint64_t tmp1        = 0;\n+\tuint64_t b_minus_amb = 0;\n+\tuint64_t VL53LX_p_055   = 0;\n+\t*psigma_est  = VL53LX_D_002;\n+\tif (fast_osc_frequency != 0) {\n+\t\tpll_period_mm = VL53LX_calc_pll_period_mm(fast_osc_frequency);\n+\n+\t\tif (VL53LX_p_028 > VL53LX_p_032)\n+\t\t\tb_minus_amb = (uint64_t)VL53LX_p_028 - (uint64_t)VL53LX_p_032;\n+\t\telse\n+\t\t\tb_minus_amb =  (uint64_t)VL53LX_p_032 - (uint64_t)VL53LX_p_028;\n+\n+\t\tif (VL53LX_p_007 > VL53LX_p_001)\n+\t\t\tVL53LX_p_055 =  (uint64_t)VL53LX_p_007 - (uint64_t)VL53LX_p_001;\n+\t\telse\n+\t\t\tVL53LX_p_055 =  (uint64_t)VL53LX_p_001 - (uint64_t)VL53LX_p_007;\n+\n+\t\tif (b_minus_amb != 0) {\n+\t\t\ttmp0 = (uint64_t)VL53LX_p_032 + (uint64_t)bx + (uint64_t)VL53LX_p_028;\n+\t\t\tif (tmp0 > VL53LX_D_003)\n+\t\t\t\ttmp0 = VL53LX_D_003;\n+\n+\t\t\ttmp1 = (uint64_t)VL53LX_p_055 * (uint64_t)VL53LX_p_055;\n+\t\t\ttmp1 = tmp1 << 8;\n+\n+\t\t\tif (tmp1 > VL53LX_D_004)\n+\t\t\t\ttmp1 = VL53LX_D_004;\n+\n+\t\t\ttmp1 = do_division_u(tmp1, b_minus_amb);\n+\t\t\ttmp1 = do_division_u(tmp1, b_minus_amb);\n+\n+\t\t\tif (tmp1 > (uint64_t)VL53LX_D_005)\n+\t\t\t\ttmp1 = (uint64_t)VL53LX_D_005;\n+\n+\t\t\ttmp0 = tmp1 * tmp0;\n+\t\t\ttmp1 = (uint64_t)c_zp + (uint64_t)cx_zp + (uint64_t)a_zp + (uint64_t)ax_zp;\n+\n+\t\t\tif (tmp1 > (uint64_t)VL53LX_D_003)\n+\t\t\t\ttmp1 = (uint64_t)VL53LX_D_003;\n+\n+\t\t\ttmp1 = tmp1 << 8;\n+\n+\t\t\ttmp0 = tmp1 + tmp0;\n+\t\t\tif (tmp0 > (uint64_t)VL53LX_D_006)\n+\t\t\t\ttmp0 = (uint64_t)VL53LX_D_006;\n+\n+\t\t\tif (tmp0 > (uint64_t)VL53LX_D_007) {\n+\t\t\t\ttmp0 = do_division_u(tmp0, b_minus_amb);\n+\t\t\t\ttmp0 = tmp0 * pll_period_mm;\n+\t\t\t} else {\n+\t\t\t\ttmp0 = tmp0 * pll_period_mm;\n+\t\t\t\ttmp0 = do_division_u(tmp0, b_minus_amb);\n+\t\t\t}\n+\n+\t\t\tif (tmp0 > (uint64_t)VL53LX_D_006)\n+\t\t\t\ttmp0 = (uint64_t)VL53LX_D_006;\n+\n+\t\t\tif (tmp0 > (uint64_t)VL53LX_D_007) {\n+\t\t\t\ttmp0 = do_division_u(tmp0, b_minus_amb);\n+\t\t\t\ttmp0 = do_division_u(tmp0, 4);\n+\t\t\t\ttmp0 = tmp0 * pll_period_mm;\n+\t\t\t} else {\n+\t\t\t\ttmp0 = tmp0 * pll_period_mm;\n+\t\t\t\ttmp0 = do_division_u(tmp0, b_minus_amb);\n+\t\t\t\ttmp0 = do_division_u(tmp0, 4);\n+\t\t\t}\n+\n+\t\t\tif (tmp0 > (uint64_t)VL53LX_D_006)\n+\t\t\t\ttmp0 = (uint64_t)VL53LX_D_006;\n+\n+\t\t\ttmp0 = tmp0 >> 2;\n+\n+\t\t\tif (tmp0 > (uint64_t)VL53LX_D_007)\n+\t\t\t\ttmp0 = (uint64_t)VL53LX_D_007;\n+\n+\t\t\ttmp1 = (uint64_t)sigma_estimator__sigma_ref_mm << 7;\n+\t\t\ttmp1 = tmp1 * tmp1;\n+\t\t\ttmp0 = tmp0 + tmp1;\n+\n+\t\t\tif (tmp0 > (uint64_t)VL53LX_D_007)\n+\t\t\t\ttmp0 = (uint64_t)VL53LX_D_007;\n+\n+\t\t\tsigma_int = VL53LX_isqrt((uint32_t)tmp0);\n+\t\t\t*psigma_est = (uint16_t)sigma_int;\n+\t\t\tstatus = VL53LX_ERROR_NONE;\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_f_014(\n+\tuint8_t                       bin,\n+\tuint8_t                       sigma_estimator__sigma_ref_mm,\n+\tuint8_t                       VL53LX_p_030,\n+\tuint8_t                       VL53LX_p_051,\n+\tuint8_t                       crosstalk_compensation_enable,\n+\tVL53LX_histogram_bin_data_t  *phist_data_ap,\n+\tVL53LX_histogram_bin_data_t  *phist_data_zp,\n+\tVL53LX_histogram_bin_data_t  *pxtalk_hist,\n+\tuint16_t                     *psigma_est)\n+{\n+\tVL53LX_Error status      = VL53LX_ERROR_NONE;\n+\tVL53LX_Error func_status = VL53LX_ERROR_NONE;\n+\n+\tuint8_t  i    = 0;\n+\tint32_t  VL53LX_p_007    = 0;\n+\tint32_t  VL53LX_p_032    = 0;\n+\tint32_t  VL53LX_p_001    = 0;\n+\tint32_t  a_zp = 0;\n+\tint32_t  c_zp = 0;\n+\tint32_t  ax   = 0;\n+\tint32_t  bx   = 0;\n+\tint32_t  cx   = 0;\n+\n+\tif (VL53LX_p_030 == 0) {\n+\t\t*psigma_est = 0xFFFF;\n+\t\treturn VL53LX_ERROR_DIVISION_BY_ZERO;\n+\t}\n+\ti = bin % VL53LX_p_030;\n+\n+\tVL53LX_f_022(i, VL53LX_p_051, phist_data_zp, &a_zp, &VL53LX_p_032, &c_zp);\n+\tVL53LX_f_022(i, VL53LX_p_051, phist_data_ap, &VL53LX_p_007, &VL53LX_p_032, &VL53LX_p_001);\n+\n+\tif (crosstalk_compensation_enable > 0)\n+\t\tVL53LX_f_022(i, VL53LX_p_051, pxtalk_hist, &ax, &bx, &cx);\n+\n+\tfunc_status =\n+\t\tVL53LX_f_023(\n+\t\t\tsigma_estimator__sigma_ref_mm,\n+\t\t\t(uint32_t)VL53LX_p_007,\n+\t\t\t(uint32_t)VL53LX_p_032,\n+\t\t\t(uint32_t)VL53LX_p_001,\n+\t\t\t(uint32_t)a_zp,\n+\t\t\t(uint32_t)c_zp,\n+\t\t\t(uint32_t)bx,\n+\t\t\t(uint32_t)ax,\n+\t\t\t(uint32_t)cx,\n+\t\t\t(uint32_t)phist_data_ap->VL53LX_p_028,\n+\t\t\tphist_data_ap->VL53LX_p_015,\n+\t\t\tpsigma_est);\n+\n+\tif (func_status == VL53LX_ERROR_DIVISION_BY_ZERO)\n+\t\t*psigma_est = 0xFFFF;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_f_020(int16_t VL53LX_p_019, int16_t VL53LX_p_024, uint8_t VL53LX_p_030, uint8_t clip_events, VL53LX_histogram_bin_data_t *pbins, uint32_t *pphase)\n+{\n+\tVL53LX_Error  status  = VL53LX_ERROR_NONE;\n+\tint16_t  i            = 0;\n+\tint16_t  lb            = 0;\n+\tint64_t VL53LX_p_018        = 0;\n+\tint64_t event_sum     = 0;\n+\tint64_t weighted_sum  = 0;\n+\n+\t*pphase = VL53LX_MAX_ALLOWED_PHASE;\n+\n+\tif (VL53LX_p_030 != 0) {\n+\t\tfor (lb = VL53LX_p_019; lb <= VL53LX_p_024; lb++) {\n+\t\t\tif (lb < 0)\n+\t\t\t\ti = lb + (int16_t)VL53LX_p_030;\n+\t\t\telse\n+\t\t\t\ti = lb % (int16_t)VL53LX_p_030;\n+\n+\t\t\tif ((i >= 0) && (i < VL53LX_HISTOGRAM_BUFFER_SIZE)) {\n+\t\t\t\tVL53LX_p_018 = (int64_t)pbins->bin_data[i] - (int64_t)pbins->VL53LX_p_028;\n+\n+\t\t\t\tif (clip_events > 0 && VL53LX_p_018 < 0)\n+\t\t\t\t\tVL53LX_p_018 = 0;\n+\t\t\t\tevent_sum += VL53LX_p_018;\n+\t\t\t\tweighted_sum += (VL53LX_p_018 * (1024 + (2048*(int64_t)lb)));\n+\t\t\t}\n+\n+\t\t}\n+\t\tif (event_sum > 0) {\n+\t\t\tweighted_sum += do_division_s(event_sum, 2);\n+\t\t\tweighted_sum = do_division_s(weighted_sum, event_sum);\n+\t\t\tif (weighted_sum < 0)\n+\t\t\t\tweighted_sum = 0;\n+\t\t\t*pphase = (uint32_t)weighted_sum;\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_f_015(uint8_t pulse_no, uint8_t clip_events, VL53LX_histogram_bin_data_t *pbins, VL53LX_hist_gen3_algo_private_data_t *palgo)\n+{\n+\tVL53LX_Error  status  = VL53LX_ERROR_NONE;\n+\tuint8_t   i            = 0;\n+\tint16_t   VL53LX_p_012 = 0;\n+\tint16_t   VL53LX_p_013   = 0;\n+\tint16_t   window_width = 0;\n+\tuint32_t  tmp_phase    = 0;\n+\n+\tVL53LX_hist_pulse_data_t *pdata = &(palgo->VL53LX_p_003[pulse_no]);\n+\n+\tif (pdata->VL53LX_p_023 == 0xFF)\n+\t\tpdata->VL53LX_p_023 = 1;\n+\n+\ti = pdata->VL53LX_p_023 % palgo->VL53LX_p_030;\n+\n+\tVL53LX_p_012  = (int16_t)i;\n+\tVL53LX_p_012 += (int16_t)pdata->VL53LX_p_012;\n+\tVL53LX_p_012 -= (int16_t)pdata->VL53LX_p_023;\n+\n+\tVL53LX_p_013  = (int16_t)i;\n+\tVL53LX_p_013 += (int16_t)pdata->VL53LX_p_013;\n+\tVL53LX_p_013 -= (int16_t)pdata->VL53LX_p_023;\n+\n+\twindow_width = VL53LX_p_013 - VL53LX_p_012;\n+\tif (window_width > 3)\n+\t\twindow_width = 3;\n+\n+\tstatus = VL53LX_f_020(VL53LX_p_012, VL53LX_p_012 + window_width, palgo->VL53LX_p_030, clip_events, pbins, &(pdata->VL53LX_p_026));\n+\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_f_020(VL53LX_p_013 - window_width, VL53LX_p_013, palgo->VL53LX_p_030, clip_events, pbins, &(pdata->VL53LX_p_027));\n+\n+\tif (pdata->VL53LX_p_026 > pdata->VL53LX_p_027) {\n+\t\ttmp_phase = pdata->VL53LX_p_026;\n+\t\tpdata->VL53LX_p_026 = pdata->VL53LX_p_027;\n+\t\tpdata->VL53LX_p_027 = tmp_phase;\n+\t}\n+\n+\tif (pdata->VL53LX_p_011 < pdata->VL53LX_p_026)\n+\t\tpdata->VL53LX_p_026 = pdata->VL53LX_p_011;\n+\n+\tif (pdata->VL53LX_p_011 > pdata->VL53LX_p_027)\n+\t\tpdata->VL53LX_p_027 = pdata->VL53LX_p_011;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_f_016(VL53LX_HistTargetOrder target_order, VL53LX_hist_gen3_algo_private_data_t *palgo)\n+{\n+\tVL53LX_Error  status  = VL53LX_ERROR_NONE;\n+\n+\tVL53LX_hist_pulse_data_t  tmp;\n+\tVL53LX_hist_pulse_data_t *ptmp = &tmp;\n+\tVL53LX_hist_pulse_data_t *p0;\n+\tVL53LX_hist_pulse_data_t *p1;\n+\n+\tuint8_t i       = 0;\n+\tuint8_t swapped = 1;\n+\n+\tif (!(palgo->VL53LX_p_046 > 1))\n+\t\tgoto ENDFUNC;\n+\n+\twhile (swapped > 0) {\n+\t\tswapped = 0;\n+\t\tfor (i = 1; i < palgo->VL53LX_p_046; i++) {\n+\t\t\tp0 = &(palgo->VL53LX_p_003[i-1]);\n+\t\t\tp1 = &(palgo->VL53LX_p_003[i]);\n+\n+\t\t\tif (target_order == VL53LX_HIST_TARGET_ORDER__STRONGEST_FIRST) {\n+\t\t\t\tif (p0->VL53LX_p_010 < p1->VL53LX_p_010) {\n+\t\t\t\t\tmemcpy(ptmp, p1, sizeof(VL53LX_hist_pulse_data_t));\n+\t\t\t\t\tmemcpy(p1, p0, sizeof(VL53LX_hist_pulse_data_t));\n+\t\t\t\t\tmemcpy(p0, ptmp, sizeof(VL53LX_hist_pulse_data_t));\n+\t\t\t\t\tswapped = 1;\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tif (p0->VL53LX_p_011 > p1->VL53LX_p_011) {\n+\t\t\t\t\tmemcpy(ptmp, p1, sizeof(VL53LX_hist_pulse_data_t));\n+\t\t\t\t\tmemcpy(p1, p0,   sizeof(VL53LX_hist_pulse_data_t));\n+\t\t\t\t\tmemcpy(p0, ptmp, sizeof(VL53LX_hist_pulse_data_t));\n+\t\t\t\t\tswapped = 1;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t}\n+ENDFUNC:\n+\treturn status;\n+\n+}\n+\n+void VL53LX_f_017(\n+\tuint8_t                      range_id,\n+\tuint8_t                      valid_phase_low,\n+\tuint8_t                      valid_phase_high,\n+\tuint16_t                     sigma_thres,\n+\tVL53LX_histogram_bin_data_t *pbins,\n+\tVL53LX_hist_pulse_data_t    *ppulse,\n+\tVL53LX_range_data_t         *pdata)\n+{\n+\tuint16_t  lower_phase_limit = 0;\n+\tuint16_t  upper_phase_limit = 0;\n+\n+\tpdata->range_id     = range_id;\n+\tpdata->time_stamp   = 0;\n+\tpdata->VL53LX_p_012 = ppulse->VL53LX_p_012;\n+\tpdata->VL53LX_p_019 = ppulse->VL53LX_p_019;\n+\tpdata->VL53LX_p_023 = ppulse->VL53LX_p_023;\n+\tpdata->VL53LX_p_024 = ppulse->VL53LX_p_024;\n+\tpdata->VL53LX_p_013 = ppulse->VL53LX_p_013;\n+\tpdata->VL53LX_p_025 = ppulse->VL53LX_p_025;\n+\tpdata->VL53LX_p_029 = (ppulse->VL53LX_p_013 + 1) - ppulse->VL53LX_p_012;\n+\n+\tpdata->zero_distance_phase   = pbins->zero_distance_phase;\n+\tpdata->VL53LX_p_002 = ppulse->VL53LX_p_002;\n+\tpdata->VL53LX_p_026 = (uint16_t)ppulse->VL53LX_p_026;\n+\tpdata->VL53LX_p_011 = (uint16_t)ppulse->VL53LX_p_011;\n+\tpdata->VL53LX_p_027 = (uint16_t)ppulse->VL53LX_p_027;\n+\tpdata->VL53LX_p_017 = (uint32_t)ppulse->VL53LX_p_017;\n+\tpdata->VL53LX_p_010 = ppulse->VL53LX_p_010;\n+\tpdata->VL53LX_p_016 = (uint32_t)ppulse->VL53LX_p_016;\n+\tpdata->total_periods_elapsed = pbins->total_periods_elapsed;\n+\n+\tpdata->range_status = VL53LX_DEVICEERROR_RANGECOMPLETE_NO_WRAP_CHECK;\n+\n+\tif (sigma_thres > 0 && (uint32_t)ppulse->VL53LX_p_002 > ((uint32_t)sigma_thres << 5))\n+\t\tpdata->range_status = VL53LX_DEVICEERROR_SIGMATHRESHOLDCHECK;\n+\n+\tlower_phase_limit = (uint8_t)valid_phase_low << 8;\n+\tif (lower_phase_limit < pdata->zero_distance_phase)\n+\t\tlower_phase_limit = pdata->zero_distance_phase - lower_phase_limit;\n+\telse\n+\t\tlower_phase_limit = 0;\n+\n+\tupper_phase_limit  = (uint8_t)valid_phase_high << 8;\n+\tupper_phase_limit += pbins->zero_distance_phase;\n+\n+\tif (pdata->VL53LX_p_011 < lower_phase_limit ||\n+\t\tpdata->VL53LX_p_011 > upper_phase_limit)\n+\t\tpdata->range_status = VL53LX_DEVICEERROR_RANGEPHASECHECK;\n+}\n+\n+int32_t VL53LX_range_maths(\n+\tuint16_t  fast_osc_frequency,\n+\tuint16_t  VL53LX_p_014,\n+\tuint16_t  zero_distance_phase,\n+\tuint8_t   fractional_bits,\n+\tint32_t   gain_factor,\n+\tint32_t   range_offset_mm)\n+{\n+\tuint32_t    pll_period_us = 0;\n+\tint64_t     tmp_long_int  = 0;\n+\tint32_t     range_mm      = 0;\n+\tint32_t     range_mm_10   = 0;\n+\n+\tpll_period_us  = VL53LX_calc_pll_period_us(fast_osc_frequency);\n+\n+\ttmp_long_int = (int64_t)VL53LX_p_014 - (int64_t)zero_distance_phase;\n+\ttmp_long_int =  tmp_long_int * (int64_t)pll_period_us;\n+\ttmp_long_int =  tmp_long_int / (0x01 << 9);\n+\ttmp_long_int =  tmp_long_int * VL53LX_SPEED_OF_LIGHT_IN_AIR_DIV_8;\n+\ttmp_long_int =  tmp_long_int / (0x01 << 22);\n+\n+\trange_mm  = (int32_t)tmp_long_int + range_offset_mm;\n+\trange_mm *= gain_factor;\n+\trange_mm += 0x0400;\n+\trange_mm /= 0x0800;\n+\n+\tif (fractional_bits == 0) {\n+\t\trange_mm_10 = range_mm * 10;\n+\t\trange_mm_10 = range_mm_10 / (0x01 << 2);\n+\t\tif ((range_mm_10 % 10) < 5)\n+\t\t\trange_mm = (int16_t)(range_mm_10 / 10);\n+\t\telse\n+\t\t\trange_mm = (int16_t)(range_mm_10 / 10 + 1);\n+\t} else if (fractional_bits == 1)\n+\t\trange_mm = range_mm / (0x01 << 1);\n+\treturn range_mm;\n+}\n+\n+void VL53LX_f_019(uint16_t gain_factor, int16_t range_offset_mm, VL53LX_range_data_t *pdata)\n+{\n+\tpdata->min_range_mm =\n+\t\t(int16_t)VL53LX_range_maths(\n+\t\t\t\tpdata->fast_osc_frequency,\n+\t\t\t\tpdata->VL53LX_p_026,\n+\t\t\t\tpdata->zero_distance_phase,\n+\t\t\t\t0,\n+\t\t\t\t(int32_t)gain_factor,\n+\t\t\t\t(int32_t)range_offset_mm);\n+\n+\tpdata->median_range_mm =\n+\t\t(int16_t)VL53LX_range_maths(\n+\t\t\t\tpdata->fast_osc_frequency,\n+\t\t\t\tpdata->VL53LX_p_011,\n+\t\t\t\tpdata->zero_distance_phase,\n+\t\t\t\t0,\n+\t\t\t\t(int32_t)gain_factor,\n+\t\t\t\t(int32_t)range_offset_mm);\n+\n+\tpdata->max_range_mm =\n+\t\t(int16_t)VL53LX_range_maths(\n+\t\t\t\tpdata->fast_osc_frequency,\n+\t\t\t\tpdata->VL53LX_p_027,\n+\t\t\t\tpdata->zero_distance_phase,\n+\t\t\t\t0,\n+\t\t\t\t(int32_t)gain_factor,\n+\t\t\t\t(int32_t)range_offset_mm);\n+}\n+\n+uint16_t VL53LX_rate_per_spad_maths(uint32_t frac_bits, uint32_t peak_count_rate, uint16_t num_spads, uint32_t max_output_value)\n+{\n+\tuint32_t  tmp_int   = 0;\n+\tuint16_t  rate_per_spad = 0;\n+\n+\tif (num_spads > 0) {\n+\t\ttmp_int = (peak_count_rate << 8) << frac_bits;\n+\t\ttmp_int = (tmp_int + ((uint32_t)num_spads / 2)) / (uint32_t)num_spads;\n+\t} else {\n+\t\ttmp_int = ((peak_count_rate) << frac_bits);\n+\t}\n+\n+\tif (tmp_int > max_output_value)\n+\t\ttmp_int = max_output_value;\n+\n+\trate_per_spad = (uint16_t)tmp_int;\n+\n+\treturn rate_per_spad;\n+}\n+\n+VL53LX_Error VL53LX_f_018(\n+\tuint16_t           vcsel_width,\n+\tuint16_t           fast_osc_frequency,\n+\tuint32_t           total_periods_elapsed,\n+\tuint16_t           VL53LX_p_004,\n+\tVL53LX_range_data_t  *pdata,\n+\tuint8_t histo_merge_nb)\n+{\n+\tVL53LX_Error     status = VL53LX_ERROR_NONE;\n+\n+\tuint32_t    pll_period_us       = 0;\n+\tuint32_t    periods_elapsed     = 0;\n+\tuint32_t    count_rate_total    = 0;\n+\n+\tpdata->width                  = vcsel_width;\n+\tpdata->fast_osc_frequency     = fast_osc_frequency;\n+\tpdata->total_periods_elapsed  = total_periods_elapsed;\n+\tpdata->VL53LX_p_004 = VL53LX_p_004;\n+\n+\tif (pdata->fast_osc_frequency == 0)\n+\t\tstatus = VL53LX_ERROR_DIVISION_BY_ZERO;\n+\n+\tif (pdata->total_periods_elapsed == 0)\n+\t\tstatus = VL53LX_ERROR_DIVISION_BY_ZERO;\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tpll_period_us = VL53LX_calc_pll_period_us(pdata->fast_osc_frequency);\n+\n+\t\tperiods_elapsed      = pdata->total_periods_elapsed + 1;\n+\n+\t\tpdata->peak_duration_us    = VL53LX_duration_maths(pll_period_us, (uint32_t)pdata->width, VL53LX_RANGING_WINDOW_VCSEL_PERIODS, periods_elapsed);\n+\n+\t\tpdata->woi_duration_us     = VL53LX_duration_maths(pll_period_us, ((uint32_t)pdata->VL53LX_p_029) << 4, VL53LX_RANGING_WINDOW_VCSEL_PERIODS, periods_elapsed);\n+\n+\t\tpdata->peak_signal_count_rate_mcps = VL53LX_rate_maths((int32_t)pdata->VL53LX_p_010, pdata->peak_duration_us);\n+\n+\t\tpdata->avg_signal_count_rate_mcps = VL53LX_rate_maths((int32_t)pdata->VL53LX_p_010, pdata->woi_duration_us);\n+\n+\t\tpdata->ambient_count_rate_mcps    = VL53LX_rate_maths((int32_t)pdata->VL53LX_p_016, pdata->woi_duration_us);\n+\n+\t\tcount_rate_total = (uint32_t)pdata->peak_signal_count_rate_mcps + (uint32_t)pdata->ambient_count_rate_mcps;\n+\n+\t\tif (histo_merge_nb > 1)\n+\t\t\tcount_rate_total /= histo_merge_nb;\n+\n+\t\tpdata->total_rate_per_spad_mcps = VL53LX_rate_per_spad_maths(0x06, count_rate_total, pdata->VL53LX_p_004, 0xFFFF);\n+\n+\t\tpdata->VL53LX_p_009 = VL53LX_events_per_spad_maths(pdata->VL53LX_p_010, pdata->VL53LX_p_004, pdata->peak_duration_us);\n+\t}\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_f_025(\n+\tVL53LX_dmax_calibration_data_t         *pdmax_cal,\n+\tVL53LX_hist_gen3_dmax_config_t         *pdmax_cfg,\n+\tVL53LX_hist_post_process_config_t      *ppost_cfg,\n+\tVL53LX_histogram_bin_data_t            *pbins_input,\n+\tVL53LX_histogram_bin_data_t            *pxtalk,\n+\tVL53LX_hist_gen3_algo_private_data_t   *palgo3,\n+\tVL53LX_hist_gen4_algo_filtered_data_t  *pfiltered,\n+\tVL53LX_hist_gen3_dmax_private_data_t   *pdmax_algo,\n+\tVL53LX_range_results_t                 *presults,\n+\tuint8_t                                histo_merge_nb)\n+{\n+\tVL53LX_Error  status  = VL53LX_ERROR_NONE;\n+\n+\tVL53LX_hist_pulse_data_t     *ppulse_data;\n+\tVL53LX_range_data_t          *prange_data;\n+\tuint8_t                       p = 0;\n+\tVL53LX_histogram_bin_data_t *pB = &(palgo3->VL53LX_p_006);\n+\n+\tVL53LX_f_003(palgo3);\n+\n+\tmemcpy(&(palgo3->VL53LX_p_006), pbins_input, sizeof(VL53LX_histogram_bin_data_t));\n+\tpresults->cfg_device_state = pbins_input->cfg_device_state;\n+\tpresults->rd_device_state  = pbins_input->rd_device_state;\n+\tpresults->zone_id          = pbins_input->zone_id;\n+\tpresults->stream_count     = pbins_input->result__stream_count;\n+\tpresults->wrap_dmax_mm     = 0;\n+\tpresults->max_results      = VL53LX_MAX_RANGE_RESULTS;\n+\tpresults->active_results   = 0;\n+\n+\tfor (p = 0; p < VL53LX_MAX_AMBIENT_DMAX_VALUES; p++)\n+\t\tpresults->VL53LX_p_022[p] = 0;\n+\n+\tVL53LX_hist_calc_zero_distance_phase(&(palgo3->VL53LX_p_006));\n+\n+\tVL53LX_hist_estimate_ambient_from_thresholded_bins((int32_t)ppost_cfg->ambient_thresh_sigma0, &(palgo3->VL53LX_p_006));\n+\n+\tVL53LX_hist_estimate_ambient_from_ambient_bins(&(palgo3->VL53LX_p_006));\n+\n+\tVL53LX_hist_remove_ambient_bins(&(palgo3->VL53LX_p_006));\n+\n+\tif (ppost_cfg->algo__crosstalk_compensation_enable > 0)\n+\t\tVL53LX_f_005(pxtalk, &(palgo3->VL53LX_p_006), &(palgo3->VL53LX_p_047));\n+\n+\tpdmax_cfg->ambient_thresh_sigma = ppost_cfg->ambient_thresh_sigma1;\n+\n+\tfor (p = 0; p < VL53LX_MAX_AMBIENT_DMAX_VALUES; p++) {\n+\t\tif (status == VL53LX_ERROR_NONE) {\n+\t\t\tstatus =\n+\t\t\tVL53LX_f_001(pdmax_cfg->target_reflectance_for_dmax_calc[p], pdmax_cal, pdmax_cfg, &(palgo3->VL53LX_p_006), pdmax_algo, &(presults->VL53LX_p_022[p]));\n+\t\t}\n+\t}\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus =\n+\t\t\tVL53LX_f_006(\n+\t\t\tppost_cfg->ambient_thresh_events_scaler,\n+\t\t\t(int32_t)pdmax_cfg->ambient_thresh_sigma,\n+\t\t\t(int32_t)ppost_cfg->min_ambient_thresh_events,\n+\t\t\tppost_cfg->algo__crosstalk_compensation_enable,\n+\t\t\t&(palgo3->VL53LX_p_006),\n+\t\t\t&(palgo3->VL53LX_p_047),\n+\t\t\tpalgo3);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_f_007(palgo3);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_f_008(palgo3);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_f_009(palgo3);\n+\n+\tfor (p = 0; p < palgo3->VL53LX_p_046; p++) {\n+\t\tppulse_data = &(palgo3->VL53LX_p_003[p]);\n+\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\tstatus = VL53LX_f_010(p, &(palgo3->VL53LX_p_006), palgo3);\n+\n+\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\tstatus = VL53LX_f_011(p, &(palgo3->VL53LX_p_006), palgo3, pB->VL53LX_p_028, &(palgo3->VL53LX_p_048));\n+\n+\t\tif (status == VL53LX_ERROR_NONE) {\n+\t\t\tstatus = VL53LX_f_011(p, &(palgo3->VL53LX_p_006), palgo3, 0, &(palgo3->VL53LX_p_049));\n+\t\t}\n+\n+\t\tif (status == VL53LX_ERROR_NONE) {\n+\t\t\tstatus = VL53LX_f_011(p, &(palgo3->VL53LX_p_047), palgo3, 0, &(palgo3->VL53LX_p_050));\n+\t\t}\n+\n+\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\tstatus = VL53LX_f_026(p, &(palgo3->VL53LX_p_048), palgo3, pfiltered);\n+\n+\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\tstatus = VL53LX_f_027(p, ppost_cfg->noise_threshold, pfiltered, palgo3);\n+\n+\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\tstatus =\n+\t\t\tVL53LX_f_014(\n+\t\t\tppulse_data->VL53LX_p_023,\n+\t\t\tppost_cfg->sigma_estimator__sigma_ref_mm,\n+\t\t\tpalgo3->VL53LX_p_030,\n+\t\t\tppulse_data->VL53LX_p_051,\n+\t\t\tppost_cfg->algo__crosstalk_compensation_enable,\n+\t\t\t&(palgo3->VL53LX_p_048),\n+\t\t\t&(palgo3->VL53LX_p_049),\n+\t\t\t&(palgo3->VL53LX_p_050),\n+\t\t\t&(ppulse_data->VL53LX_p_002));\n+\n+\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\tstatus = VL53LX_f_015(p, 1, &(palgo3->VL53LX_p_006), palgo3);\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_f_016(ppost_cfg->hist_target_order, palgo3);\n+\n+\tfor (p = 0; p < palgo3->VL53LX_p_046; p++) {\n+\t\tppulse_data = &(palgo3->VL53LX_p_003[p]);\n+\t\tif (!(presults->active_results < presults->max_results))\n+\t\t\tcontinue;\n+\n+\t\tif (ppulse_data->VL53LX_p_010 > ppost_cfg->signal_total_events_limit && ppulse_data->VL53LX_p_023 < 0xFF) {\n+\t\t\tprange_data = &(presults->VL53LX_p_003[presults->active_results]);\n+\t\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\t\tVL53LX_f_017(\n+\t\t\t\t\t\tpresults->active_results,\n+\t\t\t\t\t\tppost_cfg->valid_phase_low,\n+\t\t\t\t\t\tppost_cfg->valid_phase_high,\n+\t\t\t\t\t\tppost_cfg->sigma_thresh,\n+\t\t\t\t\t\t&(palgo3->VL53LX_p_006),\n+\t\t\t\t\t\tppulse_data,\n+\t\t\t\t\t\tprange_data);\n+\n+\t\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\t\tstatus = VL53LX_f_018(pB->vcsel_width, pB->VL53LX_p_015, pB->total_periods_elapsed, pB->result__dss_actual_effective_spads, prange_data, histo_merge_nb);\n+\n+\t\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\t\tVL53LX_f_019(ppost_cfg->gain_factor, ppost_cfg->range_offset_mm, prange_data);\n+\t\t\tpresults->active_results++;\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_hist_process_data(\n+\tVL53LX_dmax_calibration_data_t     *pdmax_cal,\n+\tVL53LX_hist_gen3_dmax_config_t     *pdmax_cfg,\n+\tVL53LX_hist_post_process_config_t  *ppost_cfg,\n+\tVL53LX_histogram_bin_data_t        *pbins_input,\n+\tVL53LX_xtalk_histogram_data_t      *pxtalk_shape,\n+\tuint8_t                            *pArea1,\n+\tuint8_t                            *pArea2,\n+\tVL53LX_range_results_t             *presults,\n+\tuint8_t                            *HistMergeNumber)\n+{\n+\tVL53LX_Error  status  = VL53LX_ERROR_NONE;\n+\n+\tVL53LX_hist_gen3_algo_private_data_t *palgo_gen3 = (VL53LX_hist_gen3_algo_private_data_t *) pArea1;\n+\tVL53LX_hist_gen4_algo_filtered_data_t *pfiltered4 = (VL53LX_hist_gen4_algo_filtered_data_t *) pArea2;\n+\tVL53LX_hist_gen3_dmax_private_data_t dmax_algo_gen3;\n+\tVL53LX_hist_gen3_dmax_private_data_t  *pdmax_algo_gen3 = &dmax_algo_gen3;\n+\tVL53LX_histogram_bin_data_t             bins_averaged;\n+\tVL53LX_histogram_bin_data_t           *pbins_averaged = &bins_averaged;\n+\tVL53LX_range_data_t                   *pdata;\n+\tuint32_t xtalk_rate_kcps               = 0;\n+\tuint32_t max_xtalk_rate_per_spad_kcps  = 0;\n+\tuint8_t  xtalk_enable                  = 0;\n+\tuint8_t  r                             = 0;\n+\tuint8_t  t                             = 0;\n+\tuint32_t XtalkDetectMaxSigma           = 0;\n+\tint16_t  delta_mm                      = 0;\n+\n+\tVL53LX_f_031(pbins_input, pbins_averaged);\n+\n+\tVL53LX_init_histogram_bin_data_struct(0, pxtalk_shape->xtalk_shape.VL53LX_p_021, &(pxtalk_shape->xtalk_hist_removed));\n+\tVL53LX_copy_xtalk_bin_data_to_histogram_data_struct(&(pxtalk_shape->xtalk_shape), &(pxtalk_shape->xtalk_hist_removed));\n+\n+\tif ((status == VL53LX_ERROR_NONE) && (ppost_cfg->algo__crosstalk_compensation_enable > 0))\n+\t\tstatus =\n+\t\tVL53LX_f_032(\n+\t\t\tppost_cfg->algo__crosstalk_compensation_plane_offset_kcps,\n+\t\t\tppost_cfg->algo__crosstalk_compensation_x_plane_gradient_kcps,\n+\t\t\tppost_cfg->algo__crosstalk_compensation_y_plane_gradient_kcps,\n+\t\t\t0,\n+\t\t\t0,\n+\t\t\tpbins_input->result__dss_actual_effective_spads,\n+\t\t\tpbins_input->roi_config__user_roi_centre_spad,\n+\t\t\tpbins_input->roi_config__user_roi_requested_global_xy_size,\n+\t\t\t&(xtalk_rate_kcps));\n+\n+\tif ((status == VL53LX_ERROR_NONE) && (ppost_cfg->algo__crosstalk_compensation_enable > 0))\n+\t\tstatus = VL53LX_f_033(pbins_averaged, &(pxtalk_shape->xtalk_shape), xtalk_rate_kcps, &(pxtalk_shape->xtalk_hist_removed));\n+\n+\tpresults->xmonitor.total_periods_elapsed = pbins_averaged->total_periods_elapsed;\n+\tpresults->xmonitor.VL53LX_p_004 = pbins_averaged->result__dss_actual_effective_spads;\n+\n+\tpresults->xmonitor.peak_signal_count_rate_mcps = 0;\n+\tpresults->xmonitor.VL53LX_p_009     = 0;\n+\n+\tpresults->xmonitor.range_id     = 0;\n+\tpresults->xmonitor.range_status = VL53LX_DEVICEERROR_NOUPDATE;\n+\n+\txtalk_enable = 0;\n+\tif (ppost_cfg->algo__crosstalk_compensation_enable > 0)\n+\t\txtalk_enable = 1;\n+\n+\tfor (r = 0 ; r <= xtalk_enable ; r++) {\n+\t\tppost_cfg->algo__crosstalk_compensation_enable = r;\n+\t\tstatus =\n+\t\tVL53LX_f_025(\n+\t\t\tpdmax_cal,\n+\t\t\tpdmax_cfg,\n+\t\t\tppost_cfg,\n+\t\t\tpbins_averaged,\n+\t\t\t&(pxtalk_shape->xtalk_hist_removed),\n+\t\t\tpalgo_gen3,\n+\t\t\tpfiltered4,\n+\t\t\tpdmax_algo_gen3,\n+\t\t\tpresults,\n+\t\t\t*HistMergeNumber);\n+\n+\t\tif (!(status == VL53LX_ERROR_NONE && r == 0))\n+\t\t\tcontinue;\n+\n+\t\tif (presults->active_results == 0) {\n+\t\t\tpdata = &(presults->VL53LX_p_003[0]);\n+\t\t\tpdata->ambient_count_rate_mcps = pdmax_algo_gen3->VL53LX_p_034;\n+\t\t\tpdata->VL53LX_p_004 = pdmax_algo_gen3->VL53LX_p_004;\n+\t\t}\n+\n+\t\tmax_xtalk_rate_per_spad_kcps = (uint32_t)(ppost_cfg->algo__crosstalk_detect_max_valid_rate_kcps);\n+\t\tmax_xtalk_rate_per_spad_kcps *= (uint32_t)(*HistMergeNumber);\n+\t\tmax_xtalk_rate_per_spad_kcps <<= 4;\n+\n+\t\tfor (t = 0 ; t < presults->active_results ; t++) {\n+\t\t\tpdata = &(presults->VL53LX_p_003[t]);\n+\t\t\tif (pdata->max_range_mm > pdata->min_range_mm)\n+\t\t\t\tdelta_mm = pdata->max_range_mm - pdata->min_range_mm;\n+\t\t\telse\n+\t\t\t\tdelta_mm = pdata->min_range_mm - pdata->max_range_mm;\n+\n+\t\t\tXtalkDetectMaxSigma = ppost_cfg->algo__crosstalk_detect_max_sigma_mm;\n+\t\t\tXtalkDetectMaxSigma *= (uint32_t)(*HistMergeNumber);\n+\t\t\tXtalkDetectMaxSigma <<= 5;\n+\t\t\tif (pdata->median_range_mm  >\n+\t\t\tppost_cfg->algo__crosstalk_detect_min_valid_range_mm &&\n+\t\t\tpdata->median_range_mm  <\n+\t\t\tppost_cfg->algo__crosstalk_detect_max_valid_range_mm &&\n+\t\t\tpdata->VL53LX_p_009 <\n+\t\t\tmax_xtalk_rate_per_spad_kcps &&\n+\t\t\tpdata->VL53LX_p_002 < XtalkDetectMaxSigma &&\n+\t\t\tdelta_mm <\n+\t\t\tppost_cfg->algo__crosstalk_detect_min_max_tolerance) {\n+\t\t\t\tmemcpy(&(presults->xmonitor), pdata, sizeof(VL53LX_range_data_t));\n+\t\t\t}\n+\t\t}\n+\t}\n+\tppost_cfg->algo__crosstalk_compensation_enable = xtalk_enable;\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_hist_wrap_dmax(VL53LX_hist_post_process_config_t *phistpostprocess, VL53LX_histogram_bin_data_t *pcurrent, int16_t *pwrap_dmax_mm)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tuint32_t  pll_period_mm        = 0;\n+\tuint32_t  wrap_dmax_phase      = 0;\n+\tuint32_t  range_mm             = 0;\n+\n+\t*pwrap_dmax_mm = 0;\n+\n+\tif (pcurrent->VL53LX_p_015 != 0) {\n+\t\tpll_period_mm = VL53LX_calc_pll_period_mm(pcurrent->VL53LX_p_015);\n+\n+\t\twrap_dmax_phase = (uint32_t)phistpostprocess->valid_phase_high << 8;\n+\n+\t\trange_mm = wrap_dmax_phase * pll_period_mm;\n+\t\trange_mm = (range_mm + (1<<14)) >> 15;\n+\n+\t\t*pwrap_dmax_mm = (int16_t)range_mm;\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_ipp_hist_process_data(\n+\tVL53LX_DEV                         Dev,\n+\tVL53LX_dmax_calibration_data_t    *pdmax_cal,\n+\tVL53LX_hist_gen3_dmax_config_t    *pdmax_cfg,\n+\tVL53LX_hist_post_process_config_t *ppost_cfg,\n+\tVL53LX_histogram_bin_data_t       *pbins,\n+\tVL53LX_xtalk_histogram_data_t     *pxtalk,\n+\tuint8_t                           *pArea1,\n+\tuint8_t                           *pArea2,\n+\tuint8_t                           *phisto_merge_nb,\n+\tVL53LX_range_results_t            *presults)\n+{\n+\tVL53LX_Error status         = VL53LX_ERROR_NONE;\n+\n+\tSUPPRESS_UNUSED_WARNING(Dev);\n+\n+\tstatus = VL53LX_hist_process_data(pdmax_cal, pdmax_cfg, ppost_cfg, pbins, pxtalk, pArea1, pArea2, presults, phisto_merge_nb);\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_hist_events_consistency_check(\n+\tuint8_t                      event_sigma,\n+\tuint16_t                     min_effective_spad_count,\n+\tVL53LX_zone_hist_info_t     *phist_prev,\n+\tVL53LX_object_data_t        *prange_prev,\n+\tVL53LX_range_data_t         *prange_curr,\n+\tint32_t                     *pevents_tolerance,\n+\tint32_t                     *pevents_delta,\n+\tVL53LX_DeviceError          *prange_status)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tint64_t   tmpp                   = 0;\n+\tint64_t   tmpc                   = 0;\n+\tint64_t   events_scaler          = 0;\n+\tint64_t   events_scaler_sq       = 0;\n+\tint64_t   c_signal_events        = 0;\n+\tint64_t   c_sig_noise_sq         = 0;\n+\tint64_t   c_amb_noise_sq         = 0;\n+\tint64_t   p_amb_noise_sq         = 0;\n+\tint32_t   p_signal_events        = 0;\n+\tuint32_t  noise_sq_sum           = 0;\n+\n+\tif (event_sigma == 0) {\n+\t\t*prange_status = VL53LX_DEVICEERROR_RANGECOMPLETE;\n+\t\treturn status;\n+\t}\n+\n+\ttmpp  = 1 + (int64_t)phist_prev->total_periods_elapsed;\n+\ttmpp *= (int64_t)phist_prev->result__dss_actual_effective_spads;\n+\n+\ttmpc  = 1 + (int64_t)prange_curr->total_periods_elapsed;\n+\ttmpc *= (int64_t)prange_curr->VL53LX_p_004;\n+\n+\tevents_scaler  = tmpp * 4096;\n+\tif (tmpc != 0) {\n+\t\tevents_scaler += (tmpc/2);\n+\t\tevents_scaler  = do_division_s(events_scaler, tmpc);\n+\t}\n+\n+\tevents_scaler_sq  = events_scaler * events_scaler;\n+\tevents_scaler_sq += 2048;\n+\tevents_scaler_sq /= 4096;\n+\n+\tc_signal_events  = (int64_t)prange_curr->VL53LX_p_017;\n+\tc_signal_events -= (int64_t)prange_curr->VL53LX_p_016;\n+\tc_signal_events *= (int64_t)events_scaler;\n+\tc_signal_events += 2048;\n+\tc_signal_events /= 4096;\n+\n+\tc_sig_noise_sq  = (int64_t)events_scaler_sq;\n+\tc_sig_noise_sq *= (int64_t)prange_curr->VL53LX_p_017;\n+\tc_sig_noise_sq += 2048;\n+\tc_sig_noise_sq /= 4096;\n+\n+\tc_amb_noise_sq  = (int64_t)events_scaler_sq;\n+\tc_amb_noise_sq *= (int64_t)prange_curr->VL53LX_p_016;\n+\tc_amb_noise_sq += 2048;\n+\tc_amb_noise_sq /= 4096;\n+\n+\tc_amb_noise_sq += 2;\n+\tc_amb_noise_sq /= 4;\n+\n+\tp_amb_noise_sq  = (int64_t)prange_prev->VL53LX_p_016;\n+\n+\tp_amb_noise_sq += 2;\n+\tp_amb_noise_sq /= 4;\n+\n+\tnoise_sq_sum = (uint32_t)prange_prev->VL53LX_p_017 + (uint32_t)c_sig_noise_sq + (uint32_t)p_amb_noise_sq + (uint32_t)c_amb_noise_sq;\n+\n+\t*pevents_tolerance = (int32_t)VL53LX_isqrt(noise_sq_sum * 16);\n+\t*pevents_tolerance *= (int32_t)event_sigma;\n+\t*pevents_tolerance += 32;\n+\t*pevents_tolerance /= 64;\n+\n+\tp_signal_events  = (int32_t)prange_prev->VL53LX_p_017;\n+\tp_signal_events -= (int32_t)prange_prev->VL53LX_p_016;\n+\n+\tif ((int32_t)c_signal_events > p_signal_events)\n+\t\t*pevents_delta = (int32_t)c_signal_events - p_signal_events;\n+\telse\n+\t\t*pevents_delta = p_signal_events - (int32_t)c_signal_events;\n+\n+\tif (*pevents_delta > *pevents_tolerance && prange_curr->VL53LX_p_004 > min_effective_spad_count)\n+\t\t*prange_status = VL53LX_DEVICEERROR_EVENTCONSISTENCY;\n+\telse\n+\t\t*prange_status = VL53LX_DEVICEERROR_RANGECOMPLETE;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_hist_merged_pulse_check(int16_t min_max_tolerance_mm, VL53LX_range_data_t *pdata, VL53LX_DeviceError *prange_status)\n+{\n+\tVL53LX_Error  status   = VL53LX_ERROR_NONE;\n+\tint16_t       delta_mm = 0;\n+\n+\tif (pdata->max_range_mm > pdata->min_range_mm)\n+\t\tdelta_mm = pdata->max_range_mm - pdata->min_range_mm;\n+\telse\n+\t\tdelta_mm = pdata->min_range_mm - pdata->max_range_mm;\n+\n+\tif (min_max_tolerance_mm > 0 && delta_mm > min_max_tolerance_mm)\n+\t\t*prange_status = VL53LX_DEVICEERROR_RANGECOMPLETE_MERGED_PULSE;\n+\telse\n+\t\t*prange_status = VL53LX_DEVICEERROR_RANGECOMPLETE;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_hist_phase_consistency_check(VL53LX_DEV Dev, VL53LX_zone_hist_info_t *phist_prev, VL53LX_zone_objects_t *prange_prev, VL53LX_range_results_t *prange_curr)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tuint8_t   lc = 0;\n+\tuint8_t   p = 0;\n+\tuint16_t  phase_delta      = 0;\n+\tuint16_t  phase_tolerance  = 0;\n+\tint32_t   events_delta     = 0;\n+\tint32_t   events_tolerance = 0;\n+\tuint8_t event_sigma;\n+\tuint16_t event_min_spad_count;\n+\tuint16_t min_max_tolerance;\n+\tuint8_t pht;\n+\n+\tVL53LX_DeviceError  range_status = 0;\n+\n+\tevent_sigma = pdev->histpostprocess.algo__consistency_check__event_sigma;\n+\tevent_min_spad_count = pdev->histpostprocess.algo__consistency_check__event_min_spad_count;\n+\tmin_max_tolerance = pdev->histpostprocess.algo__consistency_check__min_max_tolerance;\n+\tpht = pdev->histpostprocess.algo__consistency_check__phase_tolerance;\n+\tphase_tolerance = (uint16_t)pht;\n+\tphase_tolerance = phase_tolerance << 8;\n+\n+\tif (prange_prev->rd_device_state != VL53LX_DEVICESTATE_RANGING_GATHER_DATA &&\n+\t\tprange_prev->rd_device_state != VL53LX_DEVICESTATE_RANGING_OUTPUT_DATA)\n+\t\treturn status;\n+\n+\tif (phase_tolerance == 0)\n+\t\treturn status;\n+\n+\tfor (lc = 0; lc < prange_curr->active_results; lc++) {\n+\t\tif (!((prange_curr->VL53LX_p_003[lc].range_status ==\n+\t\t\tVL53LX_DEVICEERROR_RANGECOMPLETE) ||\n+\t\t\t(prange_curr->VL53LX_p_003[lc].range_status ==\n+\t\t\tVL53LX_DEVICEERROR_RANGECOMPLETE_NO_WRAP_CHECK)))\n+\t\t\tcontinue;\n+\n+\t\tif (prange_prev->active_objects == 0)\n+\t\t\tprange_curr->VL53LX_p_003[lc].range_status = VL53LX_DEVICEERROR_PREV_RANGE_NO_TARGETS;\n+\t\telse\n+\t\t\tprange_curr->VL53LX_p_003[lc].range_status = VL53LX_DEVICEERROR_PHASECONSISTENCY;\n+\n+\t\tfor (p = 0; p < prange_prev->active_objects; p++) {\n+\t\t\tif (prange_curr->VL53LX_p_003[lc].VL53LX_p_011 > prange_prev->VL53LX_p_003[p].VL53LX_p_011) {\n+\t\t\t\tphase_delta = prange_curr->VL53LX_p_003[lc].VL53LX_p_011 - prange_prev->VL53LX_p_003[p].VL53LX_p_011;\n+\t\t\t} else {\n+\t\t\t\tphase_delta = prange_prev->VL53LX_p_003[p].VL53LX_p_011 - prange_curr->VL53LX_p_003[lc].VL53LX_p_011;\n+\t\t\t}\n+\n+\t\t\tif (phase_delta < phase_tolerance) {\n+\t\t\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\t\t\tstatus =\n+\t\t\t\t\tVL53LX_hist_events_consistency_check(\n+\t\t\t\t\tevent_sigma,\n+\t\t\t\t\tevent_min_spad_count,\n+\t\t\t\t\tphist_prev,\n+\t\t\t\t\t&(prange_prev->VL53LX_p_003[p]),\n+\t\t\t\t\t&(prange_curr->VL53LX_p_003[lc]),\n+\t\t\t\t\t&events_tolerance,\n+\t\t\t\t\t&events_delta,\n+\t\t\t\t\t&range_status);\n+\n+\t\t\t\tif (status == VL53LX_ERROR_NONE && range_status == VL53LX_DEVICEERROR_RANGECOMPLETE)\n+\t\t\t\t\tstatus = VL53LX_hist_merged_pulse_check(min_max_tolerance, &(prange_curr->VL53LX_p_003[lc]), &range_status);\n+\n+\t\t\t\tprange_curr->VL53LX_p_003[lc].range_status = range_status;\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_hist_xmonitor_consistency_check(VL53LX_DEV Dev, VL53LX_zone_hist_info_t *phist_prev, VL53LX_zone_objects_t *prange_prev, VL53LX_range_data_t *prange_curr)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tint32_t   events_delta     = 0;\n+\tint32_t   events_tolerance = 0;\n+\tuint8_t event_sigma;\n+\tuint16_t min_spad_count;\n+\n+\tevent_sigma = pdev->histpostprocess.algo__crosstalk_detect_event_sigma;\n+\tmin_spad_count = pdev->histpostprocess.algo__consistency_check__event_min_spad_count;\n+\n+\tif (prange_curr->range_status == VL53LX_DEVICEERROR_RANGECOMPLETE ||\n+\t\tprange_curr->range_status == VL53LX_DEVICEERROR_RANGECOMPLETE_NO_WRAP_CHECK ||\n+\t\tprange_curr->range_status == VL53LX_DEVICEERROR_EVENTCONSISTENCY) {\n+\n+\t\tif (prange_prev->xmonitor.range_status == VL53LX_DEVICEERROR_RANGECOMPLETE ||\n+\t\t\tprange_prev->xmonitor.range_status == VL53LX_DEVICEERROR_RANGECOMPLETE_NO_WRAP_CHECK ||\n+\t\t\tprange_prev->xmonitor.range_status == VL53LX_DEVICEERROR_EVENTCONSISTENCY) {\n+\t\t\tprange_curr->range_status = VL53LX_DEVICEERROR_RANGECOMPLETE;\n+\n+\t\t\tstatus =\n+\t\t\t\tVL53LX_hist_events_consistency_check(\n+\t\t\t\t\tevent_sigma,\n+\t\t\t\t\tmin_spad_count,\n+\t\t\t\t\tphist_prev,\n+\t\t\t\t\t&(prange_prev->xmonitor),\n+\t\t\t\t\tprange_curr,\n+\t\t\t\t\t&events_tolerance,\n+\t\t\t\t\t&events_delta,\n+\t\t\t\t\t&(prange_curr->range_status));\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+void VL53LX_init_system_results(VL53LX_system_results_t *pdata)\n+{\n+\tpdata->result__interrupt_status                       = 0xFF;\n+\tpdata->result__range_status                           = 0xFF;\n+\tpdata->result__report_status                          = 0xFF;\n+\tpdata->result__stream_count                           = 0xFF;\n+\tpdata->result__dss_actual_effective_spads_sd0         = 0xFFFF;\n+\tpdata->result__peak_signal_count_rate_mcps_sd0        = 0xFFFF;\n+\tpdata->result__ambient_count_rate_mcps_sd0            = 0xFFFF;\n+\tpdata->result__sigma_sd0                              = 0xFFFF;\n+\tpdata->result__phase_sd0                              = 0xFFFF;\n+\tpdata->result__final_crosstalk_corrected_range_mm_sd0 = 0xFFFF;\n+\tpdata->result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0 = 0xFFFF;\n+\tpdata->result__mm_inner_actual_effective_spads_sd0    = 0xFFFF;\n+\tpdata->result__mm_outer_actual_effective_spads_sd0    = 0xFFFF;\n+\tpdata->result__avg_signal_count_rate_mcps_sd0         = 0xFFFF;\n+\tpdata->result__dss_actual_effective_spads_sd1         = 0xFFFF;\n+\tpdata->result__peak_signal_count_rate_mcps_sd1        = 0xFFFF;\n+\tpdata->result__ambient_count_rate_mcps_sd1            = 0xFFFF;\n+\tpdata->result__sigma_sd1                              = 0xFFFF;\n+\tpdata->result__phase_sd1                              = 0xFFFF;\n+\tpdata->result__final_crosstalk_corrected_range_mm_sd1 = 0xFFFF;\n+\tpdata->result__spare_0_sd1                            = 0xFFFF;\n+\tpdata->result__spare_1_sd1                            = 0xFFFF;\n+\tpdata->result__spare_2_sd1                            = 0xFFFF;\n+\tpdata->result__spare_3_sd1                            = 0xFF;\n+}\n+\n+void VL53LX_hist_copy_results_to_sys_and_core(\n+\tVL53LX_histogram_bin_data_t      *pbins,\n+\tVL53LX_range_results_t           *phist,\n+\tVL53LX_system_results_t          *psys,\n+\tVL53LX_core_results_t            *pcore)\n+{\n+\tuint8_t  i = 0;\n+\tVL53LX_range_data_t  *pdata;\n+\n+\tVL53LX_init_system_results(psys);\n+\n+\tpsys->result__interrupt_status = pbins->result__interrupt_status;\n+\tpsys->result__range_status     = phist->active_results;\n+\tpsys->result__report_status    = pbins->result__report_status;\n+\tpsys->result__stream_count     = pbins->result__stream_count;\n+\n+\tpdata = &(phist->VL53LX_p_003[0]);\n+\n+\tfor (i = 0; i < phist->active_results; i++) {\n+\t\tswitch (i) {\n+\t\tcase 0:\n+\t\t\tpsys->result__dss_actual_effective_spads_sd0 = pdata->VL53LX_p_004;\n+\t\t\tpsys->result__peak_signal_count_rate_mcps_sd0 = pdata->peak_signal_count_rate_mcps;\n+\t\t\tpsys->result__avg_signal_count_rate_mcps_sd0 = pdata->avg_signal_count_rate_mcps;\n+\t\t\tpsys->result__ambient_count_rate_mcps_sd0 = pdata->ambient_count_rate_mcps;\n+\t\t\tpsys->result__sigma_sd0 = pdata->VL53LX_p_002;\n+\t\t\tpsys->result__phase_sd0 = pdata->VL53LX_p_011;\n+\t\t\tpsys->result__final_crosstalk_corrected_range_mm_sd0 = (uint16_t)pdata->median_range_mm;\n+\t\t\tpsys->result__phase_sd1  = pdata->zero_distance_phase;\n+\t\t\tpcore->result_core__ranging_total_events_sd0 = pdata->VL53LX_p_017;\n+\t\t\tpcore->result_core__signal_total_events_sd0 = pdata->VL53LX_p_010;\n+\t\t\tpcore->result_core__total_periods_elapsed_sd0 = pdata->total_periods_elapsed;\n+\t\t\tpcore->result_core__ambient_window_events_sd0 = pdata->VL53LX_p_016;\n+\t\t\tbreak;\n+\t\tcase 1:\n+\t\t\tpsys->result__dss_actual_effective_spads_sd1 = pdata->VL53LX_p_004;\n+\t\t\tpsys->result__peak_signal_count_rate_mcps_sd1 = pdata->peak_signal_count_rate_mcps;\n+\t\t\tpsys->result__ambient_count_rate_mcps_sd1 = pdata->ambient_count_rate_mcps;\n+\t\t\tpsys->result__sigma_sd1 = pdata->VL53LX_p_002;\n+\t\t\tpsys->result__phase_sd1 = pdata->VL53LX_p_011;\n+\t\t\tpsys->result__final_crosstalk_corrected_range_mm_sd1 = (uint16_t)pdata->median_range_mm;\n+\t\t\tpcore->result_core__ranging_total_events_sd1 = pdata->VL53LX_p_017;\n+\t\t\tpcore->result_core__signal_total_events_sd1 = pdata->VL53LX_p_010;\n+\t\t\tpcore->result_core__total_periods_elapsed_sd1 = pdata->total_periods_elapsed;\n+\t\t\tpcore->result_core__ambient_window_events_sd1 = pdata->VL53LX_p_016;\n+\t\t\tbreak;\n+\t\t}\n+\t\tpdata++;\n+\t}\n+}\n+\n+VL53LX_Error VL53LX_dynamic_zone_update(VL53LX_DEV Dev, VL53LX_range_results_t *presults)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t  *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_LLDriverResults_t  *pres = VL53LXDevStructGetLLResultsHandle(Dev);\n+\tVL53LX_zone_private_dyn_cfgs_t *pZ = &(pres->zone_dyn_cfgs);\n+\n+\tuint8_t   zone_id = pdev->ll_state.rd_zone_id;\n+\tuint8_t   i;\n+\tuint16_t  max_total_rate_per_spads;\n+\tuint16_t  target_rate = pdev->stat_cfg.dss_config__target_total_rate_mcps;\n+\tuint32_t  temp = 0xFFFF;\n+#ifdef VL53LX_LOG_ENABLE\n+\tuint16_t eff_spad_cnt =\n+\t\tpZ->VL53LX_p_003[zone_id].dss_requested_effective_spad_count;\n+#endif\n+\n+\tpZ->VL53LX_p_003[zone_id].dss_requested_effective_spad_count = 0;\n+\n+\tmax_total_rate_per_spads = presults->VL53LX_p_003[0].total_rate_per_spad_mcps;\n+\n+\tfor (i = 1; i < presults->active_results; i++) {\n+\t\tif (presults->VL53LX_p_003[i].total_rate_per_spad_mcps > max_total_rate_per_spads)\n+\t\t\tmax_total_rate_per_spads = presults->VL53LX_p_003[i].total_rate_per_spad_mcps;\n+\t}\n+\n+\tif (max_total_rate_per_spads == 0) {\n+\t\ttemp = 0xFFFF;\n+\t} else {\n+\t\ttemp = target_rate << 14;\n+\t\ttemp = temp / max_total_rate_per_spads;\n+\t\tif (temp > 0xFFFF)\n+\t\t\ttemp = 0xFFFF;\n+\t}\n+\n+\tpZ->VL53LX_p_003[zone_id].dss_requested_effective_spad_count = (uint16_t)temp;\n+\n+\treturn status;\n+}\n+\n+void VL53LX_copy_hist_bins_to_static_cfg(VL53LX_histogram_config_t *phistogram, VL53LX_static_config_t *pstatic, VL53LX_timing_config_t *ptiming)\n+{\n+\tpstatic->sigma_estimator__effective_pulse_width_ns = phistogram->histogram_config__high_amb_even_bin_0_1;\n+\tpstatic->sigma_estimator__effective_ambient_width_ns = phistogram->histogram_config__high_amb_even_bin_2_3;\n+\tpstatic->sigma_estimator__sigma_ref_mm = phistogram->histogram_config__high_amb_even_bin_4_5;\n+\tpstatic->algo__crosstalk_compensation_valid_height_mm = phistogram->histogram_config__high_amb_odd_bin_0_1;\n+\tpstatic->spare_host_config__static_config_spare_0 = phistogram->histogram_config__high_amb_odd_bin_2_3;\n+\tpstatic->spare_host_config__static_config_spare_1 = phistogram->histogram_config__high_amb_odd_bin_4_5;\n+\tpstatic->algo__range_ignore_threshold_mcps =\n+\t\t(((uint16_t)phistogram->histogram_config__mid_amb_even_bin_0_1)\n+\t\t\t\t<< 8)\n+\t\t+ (uint16_t)phistogram->histogram_config__mid_amb_even_bin_2_3;\n+\tpstatic->algo__range_ignore_valid_height_mm = phistogram->histogram_config__mid_amb_even_bin_4_5;\n+\tpstatic->algo__range_min_clip = phistogram->histogram_config__mid_amb_odd_bin_0_1;\n+\tpstatic->algo__consistency_check__tolerance = phistogram->histogram_config__mid_amb_odd_bin_2;\n+\tpstatic->spare_host_config__static_config_spare_2 = phistogram->histogram_config__mid_amb_odd_bin_3_4;\n+\tpstatic->sd_config__reset_stages_msb = phistogram->histogram_config__mid_amb_odd_bin_5;\n+\tptiming->range_config__sigma_thresh =\n+\t\t(((uint16_t)phistogram->histogram_config__low_amb_even_bin_0_1)\n+\t\t\t\t<< 8)\n+\t\t+ (uint16_t)phistogram->histogram_config__low_amb_even_bin_2_3;\n+\tptiming->range_config__min_count_rate_rtn_limit_mcps =\n+\t\t(((uint16_t)phistogram->histogram_config__low_amb_even_bin_4_5)\n+\t\t\t\t<< 8)\n+\t\t+ (uint16_t)phistogram->histogram_config__low_amb_odd_bin_0_1;\n+\tptiming->range_config__valid_phase_low =\n+\t\t\tphistogram->histogram_config__low_amb_odd_bin_2_3;\n+\tptiming->range_config__valid_phase_high =\n+\t\t\tphistogram->histogram_config__low_amb_odd_bin_4_5;\n+}\n+\n+VL53LX_Error VL53LX_multizone_hist_bins_update(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_histogram_config_t *phist_cfg = &(pdev->hist_cfg);\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tVL53LX_copy_hist_bins_to_static_cfg(phist_cfg, &(pdev->stat_cfg), &(pdev->tim_cfg));\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_calc_required_samples(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_LLDriverResults_t *pres = VL53LXDevStructGetLLResultsHandle(Dev);\n+\tVL53LX_smudge_corrector_config_t *pconfig = &(pdev->smudge_correct_config);\n+\tVL53LX_smudge_corrector_internals_t *pint = &(pdev->smudge_corrector_internals);\n+\tVL53LX_range_results_t *presults = &(pres->range_results);\n+\tVL53LX_range_data_t *pxmonitor = &(presults->xmonitor);\n+\n+\tuint32_t peak_duration_us = pxmonitor->peak_duration_us;\n+\tuint64_t temp64a;\n+\tuint64_t temp64z;\n+\n+\ttemp64a = pxmonitor->VL53LX_p_017 + pxmonitor->VL53LX_p_016;\n+\tif (peak_duration_us == 0)\n+\t\tpeak_duration_us = 1000;\n+\ttemp64a = do_division_u((temp64a * 1000), peak_duration_us);\n+\ttemp64a = do_division_u((temp64a * 1000), peak_duration_us);\n+\n+\ttemp64z = pconfig->noise_margin * pxmonitor->VL53LX_p_004;\n+\tif (temp64z == 0)\n+\t\ttemp64z = 1;\n+\ttemp64a = temp64a * 1000 * 256;\n+\ttemp64a = do_division_u(temp64a, temp64z);\n+\ttemp64a = temp64a * 1000 * 256;\n+\ttemp64a = do_division_u(temp64a, temp64z);\n+\n+\tpint->required_samples = (uint32_t)temp64a;\n+\n+\tif (pint->required_samples < 2)\n+\t\tpint->required_samples = 2;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_calc_new_xtalk(\n+\tVL53LX_DEV\t\t\t\tDev,\n+\tuint32_t\t\t\t\txtalk_offset_out,\n+\tVL53LX_smudge_corrector_config_t\t*pconfig,\n+\tVL53LX_smudge_corrector_data_t\t\t*pout,\n+\tuint8_t\t\t\t\t\tadd_smudge,\n+\tuint8_t\t\t\t\t\tsoft_update\n+\t)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tint16_t  x_gradient_scaler;\n+\tint16_t  y_gradient_scaler;\n+\tuint32_t orig_xtalk_offset;\n+\tint16_t  orig_x_gradient;\n+\tint16_t  orig_y_gradient;\n+\tuint8_t  histo_merge_nb;\n+\tuint8_t  i;\n+\tint32_t  itemp32;\n+\tuint32_t SmudgeFactor;\n+\tVL53LX_xtalk_config_t  *pX = &(pdev->xtalk_cfg);\n+\tVL53LX_xtalk_calibration_results_t  *pC = &(pdev->xtalk_cal);\n+\tuint32_t *pcpo;\n+\tuint32_t max, nXtalk, cXtalk;\n+\tuint32_t incXtalk, cval;\n+\n+\tif (add_smudge == 1) {\n+\t\tpout->algo__crosstalk_compensation_plane_offset_kcps = (uint32_t)xtalk_offset_out + (uint32_t)pconfig->smudge_margin;\n+\t} else {\n+\t\tpout->algo__crosstalk_compensation_plane_offset_kcps = (uint32_t)xtalk_offset_out;\n+\t}\n+\n+\torig_xtalk_offset = pX->nvm_default__crosstalk_compensation_plane_offset_kcps;\n+\torig_x_gradient = pX->nvm_default__crosstalk_compensation_x_plane_gradient_kcps;\n+\torig_y_gradient = pX->nvm_default__crosstalk_compensation_y_plane_gradient_kcps;\n+\n+\tif (((pconfig->user_scaler_set == 0) || (pconfig->scaler_calc_method == 1)) && (pC->algo__crosstalk_compensation_plane_offset_kcps != 0)) {\n+\t\tVL53LX_compute_histo_merge_nb(Dev, &histo_merge_nb);\n+\n+\t\tif (histo_merge_nb == 0)\n+\t\t\thisto_merge_nb = 1;\n+\t\tif (pdev->tuning_parms.tp_hist_merge != 1)\n+\t\t\torig_xtalk_offset = pC->algo__crosstalk_compensation_plane_offset_kcps;\n+\t\telse\n+\t\t\torig_xtalk_offset = pC->algo__xtalk_cpo_HistoMerge_kcps[histo_merge_nb-1];\n+\n+\t\torig_x_gradient = pC->algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\t\torig_y_gradient = pC->algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\t}\n+\n+\tif ((pconfig->user_scaler_set == 0) && (orig_x_gradient == 0))\n+\t\tpout->gradient_zero_flag |= 0x01;\n+\n+\tif ((pconfig->user_scaler_set == 0) && (orig_y_gradient == 0))\n+\t\tpout->gradient_zero_flag |= 0x02;\n+\n+\tif (orig_xtalk_offset == 0)\n+\t\torig_xtalk_offset = 1;\n+\n+\tif (pconfig->user_scaler_set == 1) {\n+\t\tx_gradient_scaler = pconfig->x_gradient_scaler;\n+\t\ty_gradient_scaler = pconfig->y_gradient_scaler;\n+\t} else {\n+\t\tx_gradient_scaler = (int16_t)do_division_s((((int32_t)orig_x_gradient) << 6), orig_xtalk_offset);\n+\t\tpconfig->x_gradient_scaler = x_gradient_scaler;\n+\t\ty_gradient_scaler = (int16_t)do_division_s((((int32_t)orig_y_gradient) << 6), orig_xtalk_offset);\n+\t\tpconfig->y_gradient_scaler = y_gradient_scaler;\n+\t}\n+\n+\tif (pconfig->scaler_calc_method == 0) {\n+\t\titemp32 = (int32_t)(pout->algo__crosstalk_compensation_plane_offset_kcps * x_gradient_scaler);\n+\t\titemp32 = itemp32 >> 6;\n+\t\tif (itemp32 > 0xFFFF)\n+\t\t\titemp32 = 0xFFFF;\n+\n+\t\tpout->algo__crosstalk_compensation_x_plane_gradient_kcps = (int16_t)itemp32;\n+\n+\t\titemp32 = (int32_t)(pout->algo__crosstalk_compensation_plane_offset_kcps * y_gradient_scaler);\n+\t\titemp32 = itemp32 >> 6;\n+\t\tif (itemp32 > 0xFFFF)\n+\t\t\titemp32 = 0xFFFF;\n+\n+\t\tpout->algo__crosstalk_compensation_y_plane_gradient_kcps = (int16_t)itemp32;\n+\t} else if (pconfig->scaler_calc_method == 1) {\n+\t\titemp32 = (int32_t)(orig_xtalk_offset - pout->algo__crosstalk_compensation_plane_offset_kcps);\n+\t\titemp32 = (int32_t)(do_division_s(itemp32, 16));\n+\t\titemp32 = itemp32 << 2;\n+\t\titemp32 = itemp32 + (int32_t)(orig_x_gradient);\n+\t\tif (itemp32 > 0xFFFF)\n+\t\t\titemp32 = 0xFFFF;\n+\n+\t\tpout->algo__crosstalk_compensation_x_plane_gradient_kcps = (int16_t)itemp32;\n+\n+\t\titemp32 = (int32_t)(orig_xtalk_offset - pout->algo__crosstalk_compensation_plane_offset_kcps);\n+\t\titemp32 = (int32_t)(do_division_s(itemp32, 80));\n+\t\titemp32 = itemp32 << 2;\n+\t\titemp32 = itemp32 + (int32_t)(orig_y_gradient);\n+\t\tif (itemp32 > 0xFFFF)\n+\t\t\titemp32 = 0xFFFF;\n+\n+\t\tpout->algo__crosstalk_compensation_y_plane_gradient_kcps = (int16_t)itemp32;\n+\t}\n+\n+\tif ((pconfig->smudge_corr_apply_enabled == 1) && (soft_update != 1)) {\n+\t\tpout->new_xtalk_applied_flag = 1;\n+\t\tnXtalk = pout->algo__crosstalk_compensation_plane_offset_kcps;\n+\t\tVL53LX_compute_histo_merge_nb(Dev, &histo_merge_nb);\n+\t\tmax = pdev->tuning_parms.tp_hist_merge_max_size;\n+\t\tpcpo = &(pC->algo__xtalk_cpo_HistoMerge_kcps[0]);\n+\t\tif ((histo_merge_nb > 0) && (pdev->tuning_parms.tp_hist_merge == 1) && (nXtalk != 0)) {\n+\t\t\tcXtalk = pX->algo__crosstalk_compensation_plane_offset_kcps;\n+\t\t\tSmudgeFactor = cXtalk * 1000 / nXtalk;\n+\t\t\tif ((max ==  0) || (SmudgeFactor >= pconfig->max_smudge_factor))\n+\t\t\t\tpout->new_xtalk_applied_flag = 0;\n+\t\t\telse {\n+\t\t\t\tincXtalk = nXtalk / max;\n+\t\t\t\tcval = 0;\n+\t\t\t\tfor (i = 0; i < max-1; i++) {\n+\t\t\t\t\tcval += incXtalk;\n+\t\t\t\t\t*pcpo = cval;\n+\t\t\t\t\tpcpo++;\n+\t\t\t\t}\n+\t\t\t\t*pcpo = nXtalk;\n+\t\t\t}\n+\t\t}\n+\t\tif (pout->new_xtalk_applied_flag) {\n+\t\t\tpX->algo__crosstalk_compensation_plane_offset_kcps =\n+\t\t\tpout->algo__crosstalk_compensation_plane_offset_kcps;\n+\t\t\tpX->algo__crosstalk_compensation_x_plane_gradient_kcps =\n+\t\t\tpout->algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\t\t\tpX->algo__crosstalk_compensation_y_plane_gradient_kcps =\n+\t\t\tpout->algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\n+\t\t\tif (pconfig->smudge_corr_single_apply == 1) {\n+\t\t\t\tpconfig->smudge_corr_apply_enabled = 0;\n+\t\t\t\tpconfig->smudge_corr_single_apply = 0;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tif (soft_update != 1)\n+\t\tpout->smudge_corr_valid = 1;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_dynamic_xtalk_correction_corrector(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_LLDriverResults_t *pres = VL53LXDevStructGetLLResultsHandle(Dev);\n+\tVL53LX_smudge_corrector_config_t *pconfig = &(pdev->smudge_correct_config);\n+\tVL53LX_smudge_corrector_internals_t *pint = &(pdev->smudge_corrector_internals);\n+\tVL53LX_smudge_corrector_data_t *pout = &(pres->range_results.smudge_corrector_data);\n+\tVL53LX_range_results_t  *pR = &(pres->range_results);\n+\tVL53LX_xtalk_config_t  *pX = &(pdev->xtalk_cfg);\n+\n+\tuint8_t\trun_smudge_detection = 0;\n+\tuint8_t merging_complete = 0;\n+\tuint8_t\trun_nodetect = 0;\n+\tuint8_t ambient_check = 0;\n+\tint32_t itemp32 = 0;\n+\tuint64_t utemp64 = 0;\n+\tuint8_t continue_processing = CONT_CONTINUE;\n+\tuint32_t xtalk_offset_out = 0;\n+\tuint32_t xtalk_offset_in = 0;\n+\tuint32_t current_xtalk = 0;\n+\tuint32_t smudge_margin_adjusted = 0;\n+\tuint8_t i = 0;\n+\tuint8_t nodetect_index = 0;\n+\tuint16_t    amr;\n+\tuint32_t    cco;\n+\tuint8_t histo_merge_nb;\n+\n+\tVL53LX_compute_histo_merge_nb(Dev, &histo_merge_nb);\n+\tif ((histo_merge_nb == 0) || (pdev->tuning_parms.tp_hist_merge != 1))\n+\t\thisto_merge_nb = 1;\n+\n+\tVL53LX_dynamic_xtalk_correction_output_init(pres);\n+\n+\tambient_check = (pconfig->smudge_corr_ambient_threshold == 0) ||\n+\t\t((pconfig->smudge_corr_ambient_threshold * histo_merge_nb)  >\n+\t\t((uint32_t)pR->xmonitor.ambient_count_rate_mcps));\n+\n+\tmerging_complete = ((pdev->tuning_parms.tp_hist_merge != 1) || (histo_merge_nb == pdev->tuning_parms.tp_hist_merge_max_size));\n+\trun_smudge_detection = (pconfig->smudge_corr_enabled == 1) && ambient_check && (pR->xmonitor.range_status == VL53LX_DEVICEERROR_RANGECOMPLETE) && merging_complete;\n+\n+\tif ((pR->xmonitor.range_status != VL53LX_DEVICEERROR_RANGECOMPLETE) && (pconfig->smudge_corr_enabled == 1)) {\n+\t\trun_nodetect = 2;\n+\t\tfor (i = 0; i < pR->active_results; i++) {\n+\t\t\tif (pR->VL53LX_p_003[i].range_status == VL53LX_DEVICEERROR_RANGECOMPLETE) {\n+\t\t\t\tif (pR->VL53LX_p_003[i].median_range_mm <= pconfig->nodetect_min_range_mm) {\n+\t\t\t\t\trun_nodetect = 0;\n+\t\t\t\t} else {\n+\t\t\t\t\tif (run_nodetect == 2) {\n+\t\t\t\t\t\trun_nodetect = 1;\n+\t\t\t\t\t\tnodetect_index = i;\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (run_nodetect == 2)\n+\t\t\trun_nodetect = 0;\n+\n+\t\tamr = pR->VL53LX_p_003[nodetect_index].ambient_count_rate_mcps;\n+\n+\t\tif (run_nodetect == 1) {\n+\t\t\tutemp64 = 1000 * ((uint64_t)amr);\n+\t\t\tutemp64 = utemp64 << 9;\n+\n+\t\t\tif (utemp64 < pconfig->nodetect_ambient_threshold)\n+\t\t\t\trun_nodetect = 1;\n+\t\t\telse\n+\t\t\t\trun_nodetect = 0;\n+\t\t}\n+\t}\n+\n+\tif (run_smudge_detection) {\n+\t\tpint->nodetect_counter = 0;\n+\t\tVL53LX_dynamic_xtalk_correction_calc_required_samples(Dev);\n+\n+\t\txtalk_offset_in = pR->xmonitor.VL53LX_p_009;\n+\n+\t\tcco = pX->algo__crosstalk_compensation_plane_offset_kcps;\n+\t\tcurrent_xtalk = ((uint32_t)cco) << 2;\n+\n+\t\tsmudge_margin_adjusted = ((uint32_t)(pconfig->smudge_margin)) << 2;\n+\n+\t\titemp32 = xtalk_offset_in - current_xtalk + smudge_margin_adjusted;\n+\n+\t\tif (itemp32 < 0)\n+\t\t\titemp32 = itemp32 * (-1);\n+\n+\t\tif (itemp32 > ((int32_t)pconfig->single_xtalk_delta)) {\n+\t\t\tif ((int32_t)xtalk_offset_in > ((int32_t)current_xtalk - (int32_t)smudge_margin_adjusted)) {\n+\t\t\t\tpout->single_xtalk_delta_flag = 1;\n+\t\t\t} else {\n+\t\t\t\tpout->single_xtalk_delta_flag = 2;\n+\t\t\t}\n+\t\t}\n+\n+\t\tpint->current_samples = pint->current_samples + 1;\n+\n+\t\tif (pint->current_samples > pconfig->sample_limit) {\n+\t\t\tpout->sample_limit_exceeded_flag = 1;\n+\t\t\tcontinue_processing = CONT_RESET;\n+\t\t} else {\n+\t\t\tpint->accumulator = pint->accumulator + xtalk_offset_in;\n+\t\t}\n+\n+\t\tif (pint->current_samples < pint->required_samples)\n+\t\t\tcontinue_processing = CONT_NEXT_LOOP;\n+\n+\t\txtalk_offset_out = (uint32_t)(do_division_u(pint->accumulator, pint->current_samples));\n+\n+\t\titemp32 = xtalk_offset_out - current_xtalk + smudge_margin_adjusted;\n+\n+\t\tif (itemp32 < 0)\n+\t\t\titemp32 = itemp32 * (-1);\n+\n+\t\tif (continue_processing == CONT_CONTINUE && (itemp32 >= ((int32_t)(pconfig->averaged_xtalk_delta)))) {\n+\t\t\tif ((int32_t)xtalk_offset_out > ((int32_t)current_xtalk - (int32_t)smudge_margin_adjusted))\n+\t\t\t\tpout->averaged_xtalk_delta_flag = 1;\n+\t\t\telse\n+\t\t\t\tpout->averaged_xtalk_delta_flag = 2;\n+\t\t}\n+\n+\t\tif (continue_processing == CONT_CONTINUE && (itemp32 < ((int32_t)(pconfig->averaged_xtalk_delta))))\n+\t\t\tcontinue_processing = CONT_RESET;\n+\n+\t\tpout->smudge_corr_clipped = 0;\n+\t\tif ((continue_processing == CONT_CONTINUE) && (pconfig->smudge_corr_clip_limit != 0)) {\n+\t\t\tif (xtalk_offset_out > (pconfig->smudge_corr_clip_limit * histo_merge_nb)) {\n+\t\t\t\tpout->smudge_corr_clipped = 1;\n+\t\t\t\tcontinue_processing = CONT_RESET;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (pconfig->user_xtalk_offset_limit_hi && (xtalk_offset_out > pconfig->user_xtalk_offset_limit))\n+\t\t\txtalk_offset_out = pconfig->user_xtalk_offset_limit;\n+\n+\t\tif ((pconfig->user_xtalk_offset_limit_hi == 0) && (xtalk_offset_out < pconfig->user_xtalk_offset_limit))\n+\t\t\txtalk_offset_out = pconfig->user_xtalk_offset_limit;\n+\n+\t\txtalk_offset_out = xtalk_offset_out >> 2;\n+\t\tif (xtalk_offset_out > 0x3FFFF)\n+\t\t\txtalk_offset_out = 0x3FFFF;\n+\n+\t\tif (continue_processing == CONT_CONTINUE) {\n+\t\t\tVL53LX_dynamic_xtalk_correction_calc_new_xtalk(Dev, xtalk_offset_out, pconfig, pout, 1, 0);\n+\t\t\tcontinue_processing = CONT_RESET;\n+\t\t} else {\n+\t\t\tVL53LX_dynamic_xtalk_correction_calc_new_xtalk(Dev, xtalk_offset_out, pconfig, pout, 1, 1);\n+\t\t}\n+\n+\t\tif (continue_processing == CONT_RESET) {\n+\t\t\tpint->accumulator = 0;\n+\t\t\tpint->current_samples = 0;\n+\t\t\tpint->nodetect_counter = 0;\n+\t\t}\n+\t}\n+\n+\tcontinue_processing = CONT_CONTINUE;\n+\tif (run_nodetect == 1) {\n+\t\tpint->nodetect_counter += 1;\n+\t\tif (pint->nodetect_counter < pconfig->nodetect_sample_limit)\n+\t\t\tcontinue_processing = CONT_NEXT_LOOP;\n+\n+\t\txtalk_offset_out = (uint32_t)(pconfig->nodetect_xtalk_offset);\n+\n+\t\tif (continue_processing == CONT_CONTINUE) {\n+\t\t\tVL53LX_dynamic_xtalk_correction_calc_new_xtalk(Dev, xtalk_offset_out, pconfig, pout, 0, 0);\n+\t\t\tpout->smudge_corr_valid = 2;\n+\t\t\tcontinue_processing = CONT_RESET;\n+\t\t} else {\n+\t\t\tVL53LX_dynamic_xtalk_correction_calc_new_xtalk(Dev, xtalk_offset_out, pconfig, pout, 0, 1);\n+\t\t}\n+\n+\t\tif (continue_processing == CONT_RESET) {\n+\t\t\tpint->accumulator = 0;\n+\t\t\tpint->current_samples = 0;\n+\t\t\tpint->nodetect_counter = 0;\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_i2c_decode_debug_results(uint16_t buf_size, uint8_t *pbuffer, VL53LX_debug_results_t *pdata)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (buf_size < VL53LX_DEBUG_RESULTS_I2C_SIZE_BYTES)\n+\t\treturn VL53LX_ERROR_COMMS_BUFFER_TOO_SMALL;\n+\n+\tpdata->phasecal_result__reference_phase = (VL53LX_i2c_decode_uint16_t(2, pbuffer +   0));\n+\tpdata->phasecal_result__vcsel_start = (*(pbuffer +   2)) & 0x7F;\n+\tpdata->ref_spad_char_result__num_actual_ref_spads = (*(pbuffer +   3)) & 0x3F;\n+\tpdata->ref_spad_char_result__ref_location = (*(pbuffer +   4)) & 0x3;\n+\tpdata->vhv_result__coldboot_status = (*(pbuffer +   5)) & 0x1;\n+\tpdata->vhv_result__search_result = (*(pbuffer +   6)) & 0x3F;\n+\tpdata->vhv_result__latest_setting = (*(pbuffer +   7)) & 0x3F;\n+\tpdata->result__osc_calibrate_val = (VL53LX_i2c_decode_uint16_t(2, pbuffer +   8)) & 0x3FF;\n+\tpdata->ana_config__powerdown_go1 = (*(pbuffer +  10)) & 0x3;\n+\tpdata->ana_config__ref_bg_ctrl = (*(pbuffer +  11)) & 0x3;\n+\tpdata->ana_config__regdvdd1v2_ctrl = (*(pbuffer +  12)) & 0xF;\n+\tpdata->ana_config__osc_slow_ctrl = (*(pbuffer +  13)) & 0x7;\n+\tpdata->test_mode__status = (*(pbuffer +  14)) & 0x1;\n+\tpdata->firmware__system_status = (*(pbuffer +  15)) & 0x3;\n+\tpdata->firmware__mode_status = (*(pbuffer +  16));\n+\tpdata->firmware__secondary_mode_status = (*(pbuffer +  17));\n+\tpdata->firmware__cal_repeat_rate_counter = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  18)) & 0xFFF;\n+\tpdata->gph__system__thresh_high = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  22));\n+\tpdata->gph__system__thresh_low = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  24));\n+\tpdata->gph__system__enable_xtalk_per_quadrant = (*(pbuffer +  26)) & 0x1;\n+\tpdata->gph__spare_0 = (*(pbuffer +  27)) & 0x7;\n+\tpdata->gph__sd_config__woi_sd0 = (*(pbuffer +  28));\n+\tpdata->gph__sd_config__woi_sd1 = (*(pbuffer +  29));\n+\tpdata->gph__sd_config__initial_phase_sd0 = (*(pbuffer +  30)) & 0x7F;\n+\tpdata->gph__sd_config__initial_phase_sd1 = (*(pbuffer +  31)) & 0x7F;\n+\tpdata->gph__sd_config__first_order_select = (*(pbuffer +  32)) & 0x3;\n+\tpdata->gph__sd_config__quantifier = (*(pbuffer +  33)) & 0xF;\n+\tpdata->gph__roi_config__user_roi_centre_spad = (*(pbuffer +  34));\n+\tpdata->gph__roi_config__user_roi_requested_global_xy_size = (*(pbuffer +  35));\n+\tpdata->gph__system__sequence_config = (*(pbuffer +  36));\n+\tpdata->gph__gph_id = (*(pbuffer +  37)) & 0x1;\n+\tpdata->system__interrupt_set = (*(pbuffer +  38)) & 0x3;\n+\tpdata->interrupt_manager__enables = (*(pbuffer +  39)) & 0x1F;\n+\tpdata->interrupt_manager__clear = (*(pbuffer +  40)) & 0x1F;\n+\tpdata->interrupt_manager__status = (*(pbuffer +  41)) & 0x1F;\n+\tpdata->mcu_to_host_bank__wr_access_en = (*(pbuffer +  42)) & 0x1;\n+\tpdata->power_management__go1_reset_status = (*(pbuffer +  43)) & 0x1;\n+\tpdata->pad_startup_mode__value_ro = (*(pbuffer +  44)) & 0x3;\n+\tpdata->pad_startup_mode__value_ctrl = (*(pbuffer +  45)) & 0x3F;\n+\tpdata->pll_period_us = (VL53LX_i2c_decode_uint32_t(4, pbuffer +  46)) & 0x3FFFF;\n+\tpdata->interrupt_scheduler__data_out = (VL53LX_i2c_decode_uint32_t(4, pbuffer +  50));\n+\tpdata->nvm_bist__complete = (*(pbuffer +  54)) & 0x1;\n+\tpdata->nvm_bist__status = (*(pbuffer +  55)) & 0x1;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_i2c_decode_core_results(uint16_t buf_size, uint8_t *pbuffer, VL53LX_core_results_t *pdata)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (buf_size < VL53LX_CORE_RESULTS_I2C_SIZE_BYTES)\n+\t\treturn VL53LX_ERROR_COMMS_BUFFER_TOO_SMALL;\n+\n+\tpdata->result_core__ambient_window_events_sd0 = (VL53LX_i2c_decode_uint32_t(4, pbuffer +   0));\n+\tpdata->result_core__ranging_total_events_sd0 = (VL53LX_i2c_decode_uint32_t(4, pbuffer +   4));\n+\tpdata->result_core__signal_total_events_sd0 = (VL53LX_i2c_decode_int32_t(4, pbuffer +   8));\n+\tpdata->result_core__total_periods_elapsed_sd0 = (VL53LX_i2c_decode_uint32_t(4, pbuffer +  12));\n+\tpdata->result_core__ambient_window_events_sd1 = (VL53LX_i2c_decode_uint32_t(4, pbuffer +  16));\n+\tpdata->result_core__ranging_total_events_sd1 = (VL53LX_i2c_decode_uint32_t(4, pbuffer +  20));\n+\tpdata->result_core__signal_total_events_sd1 = (VL53LX_i2c_decode_int32_t(4, pbuffer +  24));\n+\tpdata->result_core__total_periods_elapsed_sd1 = (VL53LX_i2c_decode_uint32_t(4, pbuffer +  28));\n+\tpdata->result_core__spare_0 = (*(pbuffer +  32));\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_i2c_decode_system_results(uint16_t buf_size, uint8_t *pbuffer, VL53LX_system_results_t *pdata)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (buf_size < VL53LX_SYSTEM_RESULTS_I2C_SIZE_BYTES)\n+\t\treturn VL53LX_ERROR_COMMS_BUFFER_TOO_SMALL;\n+\n+\tpdata->result__interrupt_status = (*(pbuffer +   0)) & 0x3F;\n+\tpdata->result__range_status = (*(pbuffer +   1));\n+\tpdata->result__report_status = (*(pbuffer +   2)) & 0xF;\n+\tpdata->result__stream_count = (*(pbuffer +   3));\n+\tpdata->result__dss_actual_effective_spads_sd0 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +   4));\n+\tpdata->result__peak_signal_count_rate_mcps_sd0 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +   6));\n+\tpdata->result__ambient_count_rate_mcps_sd0 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +   8));\n+\tpdata->result__sigma_sd0 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  10));\n+\tpdata->result__phase_sd0 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  12));\n+\tpdata->result__final_crosstalk_corrected_range_mm_sd0 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  14));\n+\tpdata->result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  16));\n+\tpdata->result__mm_inner_actual_effective_spads_sd0 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  18));\n+\tpdata->result__mm_outer_actual_effective_spads_sd0 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  20));\n+\tpdata->result__avg_signal_count_rate_mcps_sd0 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  22));\n+\tpdata->result__dss_actual_effective_spads_sd1 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  24));\n+\tpdata->result__peak_signal_count_rate_mcps_sd1 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  26));\n+\tpdata->result__ambient_count_rate_mcps_sd1 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  28));\n+\tpdata->result__sigma_sd1 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  30));\n+\tpdata->result__phase_sd1 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  32));\n+\tpdata->result__final_crosstalk_corrected_range_mm_sd1 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  34));\n+\tpdata->result__spare_0_sd1 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  36));\n+\tpdata->result__spare_1_sd1 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  38));\n+\tpdata->result__spare_2_sd1 = (VL53LX_i2c_decode_uint16_t(2, pbuffer +  40));\n+\tpdata->result__spare_3_sd1 = (*(pbuffer +  42));\n+\tpdata->result__thresh_info = (*(pbuffer +  43));\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_get_measurement_results(VL53LX_DEV Dev, VL53LX_DeviceResultsLevel device_results_level)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tuint8_t buffer[VL53LX_MAX_I2C_XFER_SIZE];\n+\tVL53LX_system_results_t   *psystem_results = &(pdev->sys_results);\n+\tVL53LX_core_results_t     *pcore_results   = &(pdev->core_results);\n+\tVL53LX_debug_results_t    *pdebug_results  = &(pdev->dbg_results);\n+\tuint16_t i2c_index               = VL53LX_SYSTEM_RESULTS_I2C_INDEX;\n+\tuint16_t i2c_buffer_offset_bytes = 0;\n+\tuint16_t i2c_buffer_size_bytes   = 0;\n+\n+\tswitch (device_results_level) {\n+\tcase VL53LX_DEVICERESULTSLEVEL_FULL:\n+\t\ti2c_buffer_size_bytes = (VL53LX_DEBUG_RESULTS_I2C_INDEX + VL53LX_DEBUG_RESULTS_I2C_SIZE_BYTES) - i2c_index;\n+\t\tbreak;\n+\tcase VL53LX_DEVICERESULTSLEVEL_UPTO_CORE:\n+\t\ti2c_buffer_size_bytes = (VL53LX_CORE_RESULTS_I2C_INDEX + VL53LX_CORE_RESULTS_I2C_SIZE_BYTES) - i2c_index;\n+\t\tbreak;\n+\tdefault:\n+\t\ti2c_buffer_size_bytes = VL53LX_SYSTEM_RESULTS_I2C_SIZE_BYTES;\n+\t\tbreak;\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_ReadMulti(Dev, i2c_index, buffer, (uint32_t)i2c_buffer_size_bytes);\n+\n+\tif (device_results_level >= VL53LX_DEVICERESULTSLEVEL_FULL && status == VL53LX_ERROR_NONE) {\n+\t\ti2c_buffer_offset_bytes = VL53LX_DEBUG_RESULTS_I2C_INDEX - i2c_index;\n+\t\tstatus = VL53LX_i2c_decode_debug_results(VL53LX_DEBUG_RESULTS_I2C_SIZE_BYTES, &buffer[i2c_buffer_offset_bytes], pdebug_results);\n+\t}\n+\n+\tif (device_results_level >= VL53LX_DEVICERESULTSLEVEL_UPTO_CORE && status == VL53LX_ERROR_NONE) {\n+\t\ti2c_buffer_offset_bytes = VL53LX_CORE_RESULTS_I2C_INDEX - i2c_index;\n+\t\tstatus = VL53LX_i2c_decode_core_results(VL53LX_CORE_RESULTS_I2C_SIZE_BYTES, &buffer[i2c_buffer_offset_bytes], pcore_results);\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\ti2c_buffer_offset_bytes = 0;\n+\t\tstatus = VL53LX_i2c_decode_system_results(VL53LX_SYSTEM_RESULTS_I2C_SIZE_BYTES, &buffer[i2c_buffer_offset_bytes], psystem_results);\n+\t}\n+\n+\treturn status;\n+}\n+\n+void VL53LX_copy_sys_and_core_results_to_range_results(int32_t gain_factor, VL53LX_system_results_t *psys, VL53LX_core_results_t *pcore, VL53LX_range_results_t *presults)\n+{\n+\tuint8_t  i = 0;\n+\tVL53LX_range_data_t *pdata;\n+\tint32_t range_mm = 0;\n+\tuint32_t tmpu32 = 0;\n+\tuint16_t rpscr_crosstalk_corrected_mcps_sd0;\n+\tuint16_t rmmo_effective_spads_sd0;\n+\tuint16_t rmmi_effective_spads_sd0;\n+\n+\tpresults->zone_id         = 0;\n+\tpresults->stream_count    = psys->result__stream_count;\n+\tpresults->wrap_dmax_mm    = 0;\n+\tpresults->max_results     = VL53LX_MAX_RANGE_RESULTS;\n+\tpresults->active_results  = 1;\n+\trpscr_crosstalk_corrected_mcps_sd0 = psys->result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0;\n+\trmmo_effective_spads_sd0 = psys->result__mm_outer_actual_effective_spads_sd0;\n+\trmmi_effective_spads_sd0 = psys->result__mm_inner_actual_effective_spads_sd0;\n+\n+\tfor (i = 0; i < VL53LX_MAX_AMBIENT_DMAX_VALUES; i++)\n+\t\tpresults->VL53LX_p_022[i] = 0;\n+\n+\tpdata = &(presults->VL53LX_p_003[0]);\n+\n+\tfor (i = 0; i < 2; i++) {\n+\t\tpdata->range_id     = i;\n+\t\tpdata->time_stamp   = 0;\n+\n+\t\tif ((psys->result__stream_count == 0) && ((psys->result__range_status & VL53LX_RANGE_STATUS__RANGE_STATUS_MASK) == VL53LX_DEVICEERROR_RANGECOMPLETE)) {\n+\t\t\tpdata->range_status = VL53LX_DEVICEERROR_RANGECOMPLETE_NO_WRAP_CHECK;\n+\t\t} else {\n+\t\t\tpdata->range_status = psys->result__range_status & VL53LX_RANGE_STATUS__RANGE_STATUS_MASK;\n+\t\t}\n+\n+\t\tpdata->VL53LX_p_012 = 0;\n+\t\tpdata->VL53LX_p_019    = 0;\n+\t\tpdata->VL53LX_p_023   = 0;\n+\t\tpdata->VL53LX_p_024     = 0;\n+\t\tpdata->VL53LX_p_013   = 0;\n+\t\tpdata->VL53LX_p_025    = 0;\n+\n+\t\tswitch (i) {\n+\t\tcase 0:\n+\t\t\tif (psys->result__report_status == VL53LX_DEVICEREPORTSTATUS_MM1)\n+\t\t\t\tpdata->VL53LX_p_004 = rmmi_effective_spads_sd0;\n+\t\t\telse if (psys->result__report_status == VL53LX_DEVICEREPORTSTATUS_MM2)\n+\t\t\t\tpdata->VL53LX_p_004 = rmmo_effective_spads_sd0;\n+\t\t\telse\n+\t\t\t\tpdata->VL53LX_p_004 = psys->result__dss_actual_effective_spads_sd0;\n+\n+\t\t\tpdata->peak_signal_count_rate_mcps = rpscr_crosstalk_corrected_mcps_sd0;\n+\t\t\tpdata->avg_signal_count_rate_mcps = psys->result__avg_signal_count_rate_mcps_sd0;\n+\t\t\tpdata->ambient_count_rate_mcps = psys->result__ambient_count_rate_mcps_sd0;\n+\n+\t\t\ttmpu32 = ((uint32_t)psys->result__sigma_sd0 << 5);\n+\t\t\tif (tmpu32 > 0xFFFF)\n+\t\t\t\ttmpu32 = 0xFFFF;\n+\t\t\tpdata->VL53LX_p_002 = (uint16_t)tmpu32;\n+\t\t\tpdata->VL53LX_p_011 = psys->result__phase_sd0;\n+\n+\t\t\trange_mm = (int32_t)(psys->result__final_crosstalk_corrected_range_mm_sd0);\n+\t\t\trange_mm *= gain_factor;\n+\t\t\trange_mm += 0x0400;\n+\t\t\trange_mm /= 0x0800;\n+\n+\t\t\tpdata->median_range_mm = (int16_t)range_mm;\n+\t\t\tpdata->VL53LX_p_017 = pcore->result_core__ranging_total_events_sd0;\n+\t\t\tpdata->VL53LX_p_010 =                          pcore->result_core__signal_total_events_sd0;\n+\t\t\tpdata->total_periods_elapsed = pcore->result_core__total_periods_elapsed_sd0;\n+\t\t\tpdata->VL53LX_p_016 = pcore->result_core__ambient_window_events_sd0;\n+\t\t\tbreak;\n+\t\tcase 1:\n+\t\t\tpdata->VL53LX_p_004 = psys->result__dss_actual_effective_spads_sd1;\n+\t\t\tpdata->peak_signal_count_rate_mcps = psys->result__peak_signal_count_rate_mcps_sd1;\n+\t\t\tpdata->avg_signal_count_rate_mcps = 0xFFFF;\n+\t\t\tpdata->ambient_count_rate_mcps = psys->result__ambient_count_rate_mcps_sd1;\n+\n+\t\t\ttmpu32 = ((uint32_t)psys->result__sigma_sd1 << 5);\n+\t\t\tif (tmpu32 > 0xFFFF)\n+\t\t\t\ttmpu32 = 0xFFFF;\n+\t\t\tpdata->VL53LX_p_002 = (uint16_t)tmpu32;\n+\t\t\tpdata->VL53LX_p_011 = psys->result__phase_sd1;\n+\n+\t\t\trange_mm = (int32_t)(psys->result__final_crosstalk_corrected_range_mm_sd1);\n+\t\t\trange_mm *= gain_factor;\n+\t\t\trange_mm += 0x0400;\n+\t\t\trange_mm /= 0x0800;\n+\n+\t\t\tpdata->median_range_mm = (int16_t)range_mm;\n+\t\t\tpdata->VL53LX_p_017 = pcore->result_core__ranging_total_events_sd1;\n+\t\t\tpdata->VL53LX_p_010 = pcore->result_core__signal_total_events_sd1;\n+\t\t\tpdata->total_periods_elapsed  = pcore->result_core__total_periods_elapsed_sd1;\n+\t\t\tpdata->VL53LX_p_016 = pcore->result_core__ambient_window_events_sd1;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tpdata->VL53LX_p_026    = pdata->VL53LX_p_011;\n+\t\tpdata->VL53LX_p_027    = pdata->VL53LX_p_011;\n+\t\tpdata->min_range_mm = pdata->median_range_mm;\n+\t\tpdata->max_range_mm = pdata->median_range_mm;\n+\t\tpdata++;\n+\t}\n+\n+\tpresults->device_status = VL53LX_DEVICEERROR_NOUPDATE;\n+\n+\tswitch (psys->result__range_status & VL53LX_RANGE_STATUS__RANGE_STATUS_MASK) {\n+\tcase VL53LX_DEVICEERROR_VCSELCONTINUITYTESTFAILURE:\n+\tcase VL53LX_DEVICEERROR_VCSELWATCHDOGTESTFAILURE:\n+\tcase VL53LX_DEVICEERROR_NOVHVVALUEFOUND:\n+\tcase VL53LX_DEVICEERROR_USERROICLIP:\n+\tcase VL53LX_DEVICEERROR_MULTCLIPFAIL:\n+\t\tpresults->device_status = (psys->result__range_status & VL53LX_RANGE_STATUS__RANGE_STATUS_MASK);\n+\t\tpresults->VL53LX_p_003[0].range_status = VL53LX_DEVICEERROR_NOUPDATE;\n+\tbreak;\n+\t}\n+}\n+\n+VL53LX_Error VL53LX_low_power_auto_setup_manual_calibration(VL53LX_DEV Dev)\n+{\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tpdev->low_power_auto_data.saved_vhv_init = pdev->stat_nvm.vhv_config__init;\n+\tpdev->low_power_auto_data.saved_vhv_timeout = pdev->stat_nvm.vhv_config__timeout_macrop_loop_bound;\n+\tpdev->stat_nvm.vhv_config__init &= 0x7F;\n+\tpdev->stat_nvm.vhv_config__timeout_macrop_loop_bound = (pdev->stat_nvm.vhv_config__timeout_macrop_loop_bound & 0x03) + (pdev->low_power_auto_data.vhv_loop_bound << 2);\n+\tpdev->gen_cfg.phasecal_config__override = 0x01;\n+\tpdev->low_power_auto_data.first_run_phasecal_result = pdev->dbg_results.phasecal_result__vcsel_start;\n+\tpdev->gen_cfg.cal_config__vcsel_start = pdev->low_power_auto_data.first_run_phasecal_result;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_low_power_auto_update_DSS(VL53LX_DEV Dev)\n+{\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_system_results_t *pS = &(pdev->sys_results);\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tuint32_t utemp32a;\n+\n+\tutemp32a = pS->result__peak_signal_count_rate_crosstalk_corrected_mcps_sd0 + pS->result__ambient_count_rate_mcps_sd0;\n+\n+\tif (utemp32a > 0xFFFF)\n+\t\tutemp32a = 0xFFFF;\n+\n+\tutemp32a = utemp32a << 16;\n+\n+\tif (pdev->sys_results.result__dss_actual_effective_spads_sd0 == 0)\n+\t\tstatus = VL53LX_ERROR_DIVISION_BY_ZERO;\n+\telse {\n+\t\tutemp32a = utemp32a /\n+\t\tpdev->sys_results.result__dss_actual_effective_spads_sd0;\n+\t\tpdev->low_power_auto_data.dss__total_rate_per_spad_mcps = utemp32a;\n+\t\tutemp32a = pdev->stat_cfg.dss_config__target_total_rate_mcps << 16;\n+\t\tif (pdev->low_power_auto_data.dss__total_rate_per_spad_mcps == 0)\n+\t\t\tstatus = VL53LX_ERROR_DIVISION_BY_ZERO;\n+\t\telse {\n+\t\t\tutemp32a = utemp32a / pdev->low_power_auto_data.dss__total_rate_per_spad_mcps;\n+\n+\t\t\tif (utemp32a > 0xFFFF)\n+\t\t\t\tutemp32a = 0xFFFF;\n+\n+\t\t\tpdev->low_power_auto_data.dss__required_spads = (uint16_t)utemp32a;\n+\t\t\tpdev->gen_cfg.dss_config__manual_effective_spads_select = pdev->low_power_auto_data.dss__required_spads;\n+\t\t\tpdev->gen_cfg.dss_config__roi_mode_control = VL53LX_DEVICEDSSMODE__REQUESTED_EFFFECTIVE_SPADS;\n+\t\t}\n+\t}\n+\n+\tif (status == VL53LX_ERROR_DIVISION_BY_ZERO) {\n+\t\tpdev->low_power_auto_data.dss__required_spads = 0x8000;\n+\t\tpdev->gen_cfg.dss_config__manual_effective_spads_select = pdev->low_power_auto_data.dss__required_spads;\n+\t\tpdev->gen_cfg.dss_config__roi_mode_control = VL53LX_DEVICEDSSMODE__REQUESTED_EFFFECTIVE_SPADS;\n+\t\tstatus = VL53LX_ERROR_NONE;\n+\t}\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_check_ll_driver_rd_state(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error         status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t  *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_LLDriverResults_t  *pres = VL53LXDevStructGetLLResultsHandle(Dev);\n+\tVL53LX_ll_driver_state_t  *pstate       = &(pdev->ll_state);\n+\tVL53LX_system_results_t   *psys_results = &(pdev->sys_results);\n+\tVL53LX_histogram_bin_data_t *phist_data = &(pdev->hist_data);\n+\tVL53LX_zone_private_dyn_cfgs_t *pZ = &(pres->zone_dyn_cfgs);\n+\n+\tuint8_t   device_range_status   = 0;\n+\tuint8_t   device_stream_count   = 0;\n+\tuint8_t   device_gph_id         = 0;\n+\tuint8_t   histogram_mode        = 0;\n+\tuint8_t   expected_stream_count = 0;\n+\tuint8_t   expected_gph_id       = 0;\n+\n+\tdevice_range_status = psys_results->result__range_status & VL53LX_RANGE_STATUS__RANGE_STATUS_MASK;\n+\tdevice_stream_count = psys_results->result__stream_count;\n+\n+\thistogram_mode = (pdev->sys_ctrl.system__mode_start & VL53LX_DEVICESCHEDULERMODE_HISTOGRAM) == VL53LX_DEVICESCHEDULERMODE_HISTOGRAM;\n+\n+\tdevice_gph_id = (psys_results->result__interrupt_status & VL53LX_INTERRUPT_STATUS__GPH_ID_INT_STATUS_MASK) >> 4;\n+\n+\tif (histogram_mode)\n+\t\tdevice_gph_id = (phist_data->result__interrupt_status & VL53LX_INTERRUPT_STATUS__GPH_ID_INT_STATUS_MASK) >> 4;\n+\n+\tif (!((pdev->sys_ctrl.system__mode_start & VL53LX_DEVICEMEASUREMENTMODE_BACKTOBACK) == VL53LX_DEVICEMEASUREMENTMODE_BACKTOBACK))\n+\t\tgoto ENDFUNC;\n+\n+\tif (pstate->rd_device_state == VL53LX_DEVICESTATE_RANGING_WAIT_GPH_SYNC) {\n+\t\tif (histogram_mode == 0) {\n+\t\t\tif (device_range_status != VL53LX_DEVICEERROR_GPHSTREAMCOUNT0READY)\n+\t\t\t\tstatus = VL53LX_ERROR_GPH_SYNC_CHECK_FAIL;\n+\t\t}\n+\t} else {\n+\t\tif (pstate->rd_stream_count != device_stream_count)\n+\t\t\tstatus = VL53LX_ERROR_STREAM_COUNT_CHECK_FAIL;\n+\n+\t\tif (pstate->rd_gph_id != device_gph_id)\n+\t\t\tstatus = VL53LX_ERROR_GPH_ID_CHECK_FAIL;\n+\n+\t\texpected_stream_count = pZ->VL53LX_p_003[pstate->rd_zone_id].expected_stream_count;\n+\t\texpected_gph_id = pZ->VL53LX_p_003[pstate->rd_zone_id].expected_gph_id;\n+\n+\t\tif (expected_stream_count != device_stream_count) {\n+\t\t\tif (!((pdev->zone_cfg.active_zones == 0) && (device_stream_count == 255)))\n+\t\t\t\tstatus = VL53LX_ERROR_ZONE_STREAM_COUNT_CHECK_FAIL;\n+\t\t}\n+\n+\t\tif (expected_gph_id != device_gph_id)\n+\t\t\tstatus = VL53LX_ERROR_ZONE_GPH_ID_CHECK_FAIL;\n+\t}\n+\n+ENDFUNC:\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_get_device_results(VL53LX_DEV Dev, VL53LX_DeviceResultsLevel device_results_level, VL53LX_range_results_t *prange_results)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_LLDriverResults_t *pres = VL53LXDevStructGetLLResultsHandle(Dev);\n+\tVL53LX_range_results_t *presults = &(pres->range_results);\n+\tVL53LX_zone_objects_t *pobjects = &(pres->zone_results.VL53LX_p_003[0]);\n+\tVL53LX_ll_driver_state_t *pstate = &(pdev->ll_state);\n+\tVL53LX_zone_config_t *pzone_cfg = &(pdev->zone_cfg);\n+\tVL53LX_zone_hist_info_t *phist_info = &(pres->zone_hists.VL53LX_p_003[0]);\n+\tVL53LX_dmax_calibration_data_t   dmax_cal;\n+\tVL53LX_dmax_calibration_data_t *pdmax_cal = &dmax_cal;\n+\tVL53LX_hist_post_process_config_t *pHP = &(pdev->histpostprocess);\n+\tVL53LX_xtalk_config_t *pC = &(pdev->xtalk_cfg);\n+\tVL53LX_low_power_auto_data_t *pL = &(pdev->low_power_auto_data);\n+\tVL53LX_histogram_bin_data_t *pHD = &(pdev->hist_data);\n+\tVL53LX_customer_nvm_managed_t *pN = &(pdev->customer);\n+\tVL53LX_zone_histograms_t *pZH = &(pres->zone_hists);\n+\tVL53LX_xtalk_calibration_results_t *pXCR = &(pdev->xtalk_cal);\n+\tuint8_t tmp8;\n+\tuint8_t zid;\n+\tuint8_t i;\n+\tuint8_t histo_merge_nb, idx;\n+\tVL53LX_range_data_t *pdata;\n+\n+\tif ((pdev->sys_ctrl.system__mode_start & VL53LX_DEVICESCHEDULERMODE_HISTOGRAM) == VL53LX_DEVICESCHEDULERMODE_HISTOGRAM) {\n+\t\tstatus = VL53LX_get_histogram_bin_data(Dev, &(pdev->hist_data));\n+\t\tif (status == VL53LX_ERROR_NONE &&\n+\t\t\tpHD->number_of_ambient_bins == 0) {\n+\t\t\tzid = pdev->ll_state.rd_zone_id;\n+\t\t\tstatus = VL53LX_hist_copy_and_scale_ambient_info(&(pZH->VL53LX_p_003[zid]), &(pdev->hist_data));\n+\t\t}\n+\t\tif (status != VL53LX_ERROR_NONE)\n+\t\t\tgoto UPDATE_DYNAMIC_CONFIG;\n+\n+\t\tVL53LX_compute_histo_merge_nb(Dev, &histo_merge_nb);\n+\t\tif (histo_merge_nb == 0)\n+\t\t\thisto_merge_nb = 1;\n+\t\tidx = histo_merge_nb - 1;\n+\t\tif (pdev->tuning_parms.tp_hist_merge == 1)\n+\t\t\tpC->algo__crosstalk_compensation_plane_offset_kcps = pXCR->algo__xtalk_cpo_HistoMerge_kcps[idx];\n+\n+\t\tpHP->gain_factor = pdev->gain_cal.histogram_ranging_gain_factor;\n+\n+\t\tpHP->algo__crosstalk_compensation_plane_offset_kcps = VL53LX_calc_crosstalk_plane_offset_with_margin(pC->algo__crosstalk_compensation_plane_offset_kcps, pC->histogram_mode_crosstalk_margin_kcps);\n+\n+\t\tpHP->algo__crosstalk_compensation_x_plane_gradient_kcps = pC->algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\t\tpHP->algo__crosstalk_compensation_y_plane_gradient_kcps = pC->algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\n+\t\tpdev->dmax_cfg.ambient_thresh_sigma = pHP->ambient_thresh_sigma1;\n+\t\tpdev->dmax_cfg.min_ambient_thresh_events = pHP->min_ambient_thresh_events;\n+\t\tpdev->dmax_cfg.signal_total_events_limit = pHP->signal_total_events_limit;\n+\t\tpdev->dmax_cfg.dss_config__target_total_rate_mcps = pdev->stat_cfg.dss_config__target_total_rate_mcps;\n+\t\tpdev->dmax_cfg.dss_config__aperture_attenuation = pdev->gen_cfg.dss_config__aperture_attenuation;\n+\n+\t\tpHP->algo__crosstalk_detect_max_valid_range_mm = pC->algo__crosstalk_detect_max_valid_range_mm;\n+\t\tpHP->algo__crosstalk_detect_min_valid_range_mm = pC->algo__crosstalk_detect_min_valid_range_mm;\n+\t\tpHP->algo__crosstalk_detect_max_valid_rate_kcps = pC->algo__crosstalk_detect_max_valid_rate_kcps;\n+\t\tpHP->algo__crosstalk_detect_max_sigma_mm = pC->algo__crosstalk_detect_max_sigma_mm;\n+\n+\t\tVL53LX_copy_rtn_good_spads_to_buffer(&(pdev->nvm_copy_data), &(pdev->rtn_good_spads[0]));\n+\n+\t\tswitch (pdev->offset_correction_mode) {\n+\t\tcase VL53LX_OFFSETCORRECTIONMODE__MM1_MM2_OFFSETS:\n+\t\t\ttmp8 = pdev->gen_cfg.dss_config__aperture_attenuation;\n+\t\t\tVL53LX_hist_combine_mm1_mm2_offsets(\n+\t\t\tpN->mm_config__inner_offset_mm,\n+\t\t\tpN->mm_config__outer_offset_mm,\n+\t\t\tpdev->nvm_copy_data.roi_config__mode_roi_centre_spad,\n+\t\t\tpdev->nvm_copy_data.roi_config__mode_roi_xy_size,\n+\t\t\tpHD->roi_config__user_roi_centre_spad,\n+\t\t\tpHD->roi_config__user_roi_requested_global_xy_size,\n+\t\t\t&(pdev->add_off_cal_data),\n+\t\t\t&(pdev->rtn_good_spads[0]),\n+\t\t\t(uint16_t)tmp8,\n+\t\t\t&(pHP->range_offset_mm));\n+\t\t\tbreak;\n+\t\tcase VL53LX_OFFSETCORRECTIONMODE__PER_VCSEL_OFFSETS:\n+\t\t\tselect_offset_per_vcsel(pdev, &(pHP->range_offset_mm));\n+\t\t\tpHP->range_offset_mm *= 4;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tpHP->range_offset_mm = 0;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (status != VL53LX_ERROR_NONE)\n+\t\t\tgoto UPDATE_DYNAMIC_CONFIG;\n+\n+\t\tVL53LX_calc_max_effective_spads(\n+\t\tpHD->roi_config__user_roi_centre_spad,\n+\t\tpHD->roi_config__user_roi_requested_global_xy_size,\n+\t\t&(pdev->rtn_good_spads[0]),\n+\t\t(uint16_t)pdev->gen_cfg.dss_config__aperture_attenuation,\n+\t\t&(pdev->dmax_cfg.max_effective_spads));\n+\n+\t\tstatus = VL53LX_get_dmax_calibration_data(Dev, pdev->dmax_mode, pdmax_cal);\n+\n+\t\tif (status != VL53LX_ERROR_NONE)\n+\t\t\tgoto UPDATE_DYNAMIC_CONFIG;\n+\n+\t\tstatus = VL53LX_ipp_hist_process_data(\n+\t\t\t\tDev,\n+\t\t\t\tpdmax_cal,\n+\t\t\t\t&(pdev->dmax_cfg),\n+\t\t\t\t&(pdev->histpostprocess),\n+\t\t\t\t&(pdev->hist_data),\n+\t\t\t\t&(pdev->xtalk_shapes),\n+\t\t\t\tpdev->wArea1,\n+\t\t\t\tpdev->wArea2,\n+\t\t\t\t&histo_merge_nb,\n+\t\t\t\tpresults);\n+\n+\t\tif ((pdev->tuning_parms.tp_hist_merge == 1) &&\n+\t\t\t(histo_merge_nb > 1))\n+\t\tfor (i = 0; i < VL53LX_MAX_RANGE_RESULTS; i++) {\n+\t\t\tpdata = &(presults->VL53LX_p_003[i]);\n+\t\t\tpdata->VL53LX_p_016 /= histo_merge_nb;\n+\t\t\tpdata->VL53LX_p_017 /= histo_merge_nb;\n+\t\t\tpdata->VL53LX_p_010 /= histo_merge_nb;\n+\t\t\tpdata->peak_signal_count_rate_mcps /= histo_merge_nb;\n+\t\t\tpdata->avg_signal_count_rate_mcps /= histo_merge_nb;\n+\t\t\tpdata->ambient_count_rate_mcps /= histo_merge_nb;\n+\t\t\tpdata->VL53LX_p_009 /= histo_merge_nb;\n+\t\t}\n+\n+\t\tif (status != VL53LX_ERROR_NONE)\n+\t\t\tgoto UPDATE_DYNAMIC_CONFIG;\n+\n+\t\tstatus = VL53LX_hist_wrap_dmax(&(pdev->histpostprocess), &(pdev->hist_data), &(presults->wrap_dmax_mm));\n+\n+\t\tif (status != VL53LX_ERROR_NONE)\n+\t\t\tgoto UPDATE_DYNAMIC_CONFIG;\n+\n+\t\tzid = pdev->ll_state.rd_zone_id;\n+\t\tstatus = VL53LX_hist_phase_consistency_check(Dev, &(pZH->VL53LX_p_003[zid]), &(pres->zone_results.VL53LX_p_003[zid]), presults);\n+\n+\t\tif (status != VL53LX_ERROR_NONE)\n+\t\t\tgoto UPDATE_DYNAMIC_CONFIG;\n+\n+\t\tzid = pdev->ll_state.rd_zone_id;\n+\t\tstatus = VL53LX_hist_xmonitor_consistency_check(Dev, &(pZH->VL53LX_p_003[zid]), &(pres->zone_results.VL53LX_p_003[zid]), &(presults->xmonitor));\n+\n+\t\tif (status != VL53LX_ERROR_NONE)\n+\t\t\tgoto UPDATE_DYNAMIC_CONFIG;\n+\n+\t\tzid = pdev->ll_state.rd_zone_id;\n+\t\tpZH->max_zones    = VL53LX_MAX_USER_ZONES;\n+\t\tpZH->active_zones = pdev->zone_cfg.active_zones+1;\n+\t\tpHD->zone_id       = zid;\n+\n+\t\tif (zid < pres->zone_results.max_zones) {\n+\t\t\tphist_info = &(pZH->VL53LX_p_003[zid]);\n+\t\t\tphist_info->rd_device_state = pHD->rd_device_state;\n+\t\t\tphist_info->number_of_ambient_bins = pHD->number_of_ambient_bins;\n+\t\t\tphist_info->result__dss_actual_effective_spads = pHD->result__dss_actual_effective_spads;\n+\t\t\tphist_info->VL53LX_p_005 = pHD->VL53LX_p_005;\n+\t\t\tphist_info->total_periods_elapsed = pHD->total_periods_elapsed;\n+\t\t\tphist_info->ambient_events_sum = pHD->ambient_events_sum;\n+\t\t}\n+\n+\t\tif (status != VL53LX_ERROR_NONE)\n+\t\t\tgoto UPDATE_DYNAMIC_CONFIG;\n+\t\tVL53LX_hist_copy_results_to_sys_and_core(&(pdev->hist_data), presults, &(pdev->sys_results), &(pdev->core_results));\n+\n+UPDATE_DYNAMIC_CONFIG:\n+\t\tif (pzone_cfg->active_zones > 0) {\n+\t\t\tif (pstate->rd_device_state != VL53LX_DEVICESTATE_RANGING_WAIT_GPH_SYNC) {\n+\t\t\t\tif (status == VL53LX_ERROR_NONE) {\n+\t\t\t\t\tstatus = VL53LX_dynamic_zone_update(Dev, presults);\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\tfor (i = 0; i < VL53LX_MAX_USER_ZONES; i++) {\n+\t\t\t\tpzone_cfg->bin_config[i] = ((pdev->ll_state.cfg_internal_stream_count) & 0x01) ? VL53LX_ZONECONFIG_BINCONFIG__HIGHAMB : VL53LX_ZONECONFIG_BINCONFIG__LOWAMB;\n+\t\t\t}\n+\n+\t\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\t\tstatus = VL53LX_multizone_hist_bins_update(Dev);\n+\t\t}\n+\n+\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\tstatus = VL53LX_dynamic_xtalk_correction_corrector(Dev);\n+\n+\t\tif (pdev->tuning_parms.tp_hist_merge == 1)\n+\t\t\tpC->algo__crosstalk_compensation_plane_offset_kcps = pXCR->algo__xtalk_cpo_HistoMerge_kcps[0];\n+\t} else {\n+\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\tstatus = VL53LX_get_measurement_results(Dev, device_results_level);\n+\n+\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\tVL53LX_copy_sys_and_core_results_to_range_results((int32_t)pdev->gain_cal.standard_ranging_gain_factor, &(pdev->sys_results), &(pdev->core_results), presults);\n+\n+\t\tif (pL->is_low_power_auto_mode == 1) {\n+\t\t\tif ((status == VL53LX_ERROR_NONE) && (pL->low_power_auto_range_count == 0)) {\n+\t\t\t\tstatus = VL53LX_low_power_auto_setup_manual_calibration(Dev);\n+\t\t\t\tpL->low_power_auto_range_count = 1;\n+\t\t\t} else if ((status == VL53LX_ERROR_NONE) && (pL->low_power_auto_range_count == 1)) {\n+\t\t\t\tpL->low_power_auto_range_count = 2;\n+\t\t\t}\n+\n+\t\t\tif ((pL->low_power_auto_range_count != 0xFF) && (status == VL53LX_ERROR_NONE)) {\n+\t\t\t\tstatus = VL53LX_low_power_auto_update_DSS(Dev);\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tpresults->cfg_device_state = pdev->ll_state.cfg_device_state;\n+\tpresults->rd_device_state  = pdev->ll_state.rd_device_state;\n+\tpresults->zone_id          = pdev->ll_state.rd_zone_id;\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tpres->zone_results.max_zones    = VL53LX_MAX_USER_ZONES;\n+\t\tpres->zone_results.active_zones = pdev->zone_cfg.active_zones+1;\n+\t\tzid = pdev->ll_state.rd_zone_id;\n+\n+\t\tif (zid < pres->zone_results.max_zones) {\n+\t\t\tpobjects = &(pres->zone_results.VL53LX_p_003[zid]);\n+\t\t\tpobjects->cfg_device_state  = presults->cfg_device_state;\n+\t\t\tpobjects->rd_device_state   = presults->rd_device_state;\n+\t\t\tpobjects->zone_id           = presults->zone_id;\n+\t\t\tpobjects->stream_count      = presults->stream_count;\n+\n+\t\t\tpobjects->xmonitor.VL53LX_p_016 = presults->xmonitor.VL53LX_p_016;\n+\t\t\tpobjects->xmonitor.VL53LX_p_017 = presults->xmonitor.VL53LX_p_017;\n+\t\t\tpobjects->xmonitor.VL53LX_p_011 = presults->xmonitor.VL53LX_p_011;\n+\t\t\tpobjects->xmonitor.range_status = presults->xmonitor.range_status;\n+\n+\t\t\tpobjects->max_objects      = presults->max_results;\n+\t\t\tpobjects->active_objects   = presults->active_results;\n+\n+\t\t\tfor (i = 0; i < presults->active_results; i++) {\n+\t\t\t\tpobjects->VL53LX_p_003[i].VL53LX_p_016 = presults->VL53LX_p_003[i].VL53LX_p_016;\n+\t\t\t\tpobjects->VL53LX_p_003[i].VL53LX_p_017 = presults->VL53LX_p_003[i].VL53LX_p_017;\n+\t\t\t\tpobjects->VL53LX_p_003[i].VL53LX_p_011 = presults->VL53LX_p_003[i].VL53LX_p_011;\n+\t\t\t\tpobjects->VL53LX_p_003[i].range_status = presults->VL53LX_p_003[i].range_status;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tmemcpy(prange_results, presults, sizeof(VL53LX_range_results_t));\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_check_ll_driver_rd_state(Dev);\n+\treturn status;\n+}\n+\n+static uint8_t ConvertStatusHisto(uint8_t FilteredRangeStatus)\n+{\n+\tuint8_t RangeStatus;\n+\n+\tswitch (FilteredRangeStatus) {\n+\tcase VL53LX_DEVICEERROR_RANGEPHASECHECK:\n+\t\tRangeStatus = VL53LX_RANGESTATUS_OUTOFBOUNDS_FAIL;\n+\t\tbreak;\n+\tcase VL53LX_DEVICEERROR_SIGMATHRESHOLDCHECK:\n+\t\tRangeStatus = VL53LX_RANGESTATUS_SIGMA_FAIL;\n+\t\tbreak;\n+\tcase VL53LX_DEVICEERROR_RANGECOMPLETE_NO_WRAP_CHECK:\n+\t\tRangeStatus = VL53LX_RANGESTATUS_RANGE_VALID_NO_WRAP_CHECK_FAIL;\n+\t\tbreak;\n+\tcase VL53LX_DEVICEERROR_PHASECONSISTENCY:\n+\t\tRangeStatus = VL53LX_RANGESTATUS_WRAP_TARGET_FAIL;\n+\t\tbreak;\n+\tcase VL53LX_DEVICEERROR_PREV_RANGE_NO_TARGETS:\n+\t\tRangeStatus = VL53LX_RANGESTATUS_TARGET_PRESENT_LACK_OF_SIGNAL;\n+\t\tbreak;\n+\tcase VL53LX_DEVICEERROR_EVENTCONSISTENCY:\n+\t\tRangeStatus = VL53LX_RANGESTATUS_WRAP_TARGET_FAIL;\n+\t\tbreak;\n+\tcase VL53LX_DEVICEERROR_RANGECOMPLETE_MERGED_PULSE:\n+\t\tRangeStatus = VL53LX_RANGESTATUS_RANGE_VALID_MERGED_PULSE;\n+\t\tbreak;\n+\tcase VL53LX_DEVICEERROR_RANGECOMPLETE:\n+\t\tRangeStatus = VL53LX_RANGESTATUS_RANGE_VALID;\n+\t\tbreak;\n+\tdefault:\n+\t\tRangeStatus = VL53LX_RANGESTATUS_NONE;\n+\t}\n+\treturn RangeStatus;\n+}\n+\n+static VL53LX_Error SetTargetData(VL53LX_DEV Dev,\n+\tuint8_t active_results, uint8_t streamcount, uint8_t iteration,\n+\tuint8_t device_status, VL53LX_range_data_t *presults_data,\n+\tVL53LX_TargetRangeData_t *pRangeData)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_tuning_parm_storage_t *tp = &(pdev->tuning_parms);\n+\tuint8_t sequency;\n+\tuint8_t FilteredRangeStatus;\n+\tFixPoint1616_t AmbientRate;\n+\tFixPoint1616_t SignalRate;\n+\tFixPoint1616_t TempFix1616;\n+\tint16_t Range, RangeDiff, RangeMillimeterInit;\n+\tint32_t ExtendedRangeEnabled = 0;\n+\tuint8_t uwr_status;\n+\tint16_t AddOffset;\n+\n+\tSUPPRESS_UNUSED_WARNING(Dev);\n+\n+\tFilteredRangeStatus = presults_data->range_status & 0x1F;\n+\n+\tSignalRate = VL53LX_FIXPOINT97TOFIXPOINT1616(presults_data->peak_signal_count_rate_mcps);\n+\tpRangeData->SignalRateRtnMegaCps = SignalRate;\n+\n+\tAmbientRate = VL53LX_FIXPOINT97TOFIXPOINT1616(presults_data->ambient_count_rate_mcps);\n+\tpRangeData->AmbientRateRtnMegaCps = AmbientRate;\n+\n+\tTempFix1616 = VL53LX_FIXPOINT97TOFIXPOINT1616(presults_data->VL53LX_p_002);\n+\n+\tpRangeData->SigmaMilliMeter = TempFix1616;\n+\n+\tpRangeData->RangeMilliMeter = presults_data->median_range_mm;\n+\tpRangeData->RangeMaxMilliMeter = presults_data->max_range_mm;\n+\tpRangeData->RangeMinMilliMeter = presults_data->min_range_mm;\n+\n+\tswitch (device_status) {\n+\tcase VL53LX_DEVICEERROR_MULTCLIPFAIL:\n+\tcase VL53LX_DEVICEERROR_VCSELWATCHDOGTESTFAILURE:\n+\tcase VL53LX_DEVICEERROR_VCSELCONTINUITYTESTFAILURE:\n+\tcase VL53LX_DEVICEERROR_NOVHVVALUEFOUND:\n+\t\tpRangeData->RangeStatus =  VL53LX_RANGESTATUS_HARDWARE_FAIL;\n+\t\tbreak;\n+\tcase VL53LX_DEVICEERROR_USERROICLIP:\n+\t\tpRangeData->RangeStatus =  VL53LX_RANGESTATUS_MIN_RANGE_FAIL;\n+\t\tbreak;\n+\tdefault:\n+\t\tpRangeData->RangeStatus =  VL53LX_RANGESTATUS_RANGE_VALID;\n+\t}\n+\n+\tif ((pRangeData->RangeStatus ==  VL53LX_RANGESTATUS_RANGE_VALID) && (active_results == 0)) {\n+\t\tpRangeData->RangeStatus = VL53LX_RANGESTATUS_NONE;\n+\t\tpRangeData->SignalRateRtnMegaCps = 0;\n+\t\tpRangeData->SigmaMilliMeter = 0;\n+\t\tpRangeData->RangeMilliMeter = 8191;\n+\t\tpRangeData->RangeMaxMilliMeter = 8191;\n+\t\tpRangeData->RangeMinMilliMeter = 8191;\n+\t}\n+\n+\tif (pRangeData->RangeStatus ==  VL53LX_RANGESTATUS_RANGE_VALID)\n+\t\tpRangeData->RangeStatus = ConvertStatusHisto(FilteredRangeStatus);\n+\n+\tVL53LX_get_tuning_parm(Dev, VL53LX_TUNINGPARM_UWR_ENABLE, &ExtendedRangeEnabled);\n+\n+\tsequency = streamcount % 2;\n+\tuwr_status = 0;\n+\tRangeMillimeterInit = pRangeData->RangeMilliMeter;\n+\tAddOffset = 0;\n+\n+\tpRangeData->ExtendedRange = 0;\n+\n+\tif ((active_results != 1) || (pdev->PreviousRangeActiveResults != 1))\n+\t\tExtendedRangeEnabled = 0;\n+\n+\tif (ExtendedRangeEnabled &&\n+\t\t(pRangeData->RangeStatus ==\n+\t\t\tVL53LX_RANGESTATUS_WRAP_TARGET_FAIL ||\n+\t\t\tpRangeData->RangeStatus ==\n+\t\t\tVL53LX_RANGESTATUS_OUTOFBOUNDS_FAIL)\n+\t\t&& (pdev->PreviousRangeStatus[iteration] ==\n+\t\t\tVL53LX_RANGESTATUS_WRAP_TARGET_FAIL ||\n+\t\t\tpdev->PreviousRangeStatus[iteration] ==\n+\t\t\tVL53LX_RANGESTATUS_OUTOFBOUNDS_FAIL ||\n+\t\t\t(pdev->PreviousRangeStatus[iteration] ==\n+\t\t\tVL53LX_RANGESTATUS_RANGE_VALID &&\n+\t\t\tpdev->PreviousExtendedRange[iteration] == 1))) {\n+\t\tif (((pdev->PreviousStreamCount) == (pdev->hist_data.result__stream_count - 1)) || ((pdev->PreviousStreamCount) == (pdev->hist_data.result__stream_count + 127))) {\n+\t\t\tRangeDiff = pRangeData->RangeMilliMeter - pdev->PreviousRangeMilliMeter[iteration];\n+\t\t\tuwr_status = 1;\n+\t\t\tswitch (pdev->preset_mode) {\n+\t\t\tcase VL53LX_DEVICEPRESETMODE_HISTOGRAM_SHORT_RANGE:\n+\t\t\t\tuwr_status = 0;\n+\t\t\t\tbreak;\n+\t\t\tcase VL53LX_DEVICEPRESETMODE_HISTOGRAM_MEDIUM_RANGE:\n+\t\t\t\tif (RangeDiff > tp->tp_uwr_med_z_1_min && RangeDiff < tp->tp_uwr_med_z_1_max && sequency == 1) {\n+\t\t\t\t\tAddOffset =\n+\t\t\t\t\ttp->tp_uwr_med_corr_z_1_rangeb;\n+\t\t\t\t} else if (RangeDiff < -tp->tp_uwr_med_z_1_min && RangeDiff > -tp->tp_uwr_med_z_1_max && sequency == 0) {\n+\t\t\t\t\tAddOffset = tp->tp_uwr_med_corr_z_1_rangea;\n+\t\t\t\t} else if (RangeDiff > tp->tp_uwr_med_z_2_min && RangeDiff < tp->tp_uwr_med_z_2_max && sequency == 0) {\n+\t\t\t\t\tAddOffset = tp->tp_uwr_med_corr_z_2_rangea;\n+\t\t\t\t} else if (RangeDiff < -tp->tp_uwr_med_z_2_min && RangeDiff > -tp->tp_uwr_med_z_2_max && sequency == 1) {\n+\t\t\t\t\tAddOffset = tp->tp_uwr_med_corr_z_2_rangeb;\n+\t\t\t\t} else if (RangeDiff > tp->tp_uwr_med_z_3_min && RangeDiff < tp->tp_uwr_med_z_3_max && sequency == 1) {\n+\t\t\t\t\tAddOffset = tp->tp_uwr_med_corr_z_3_rangeb;\n+\t\t\t\t} else if (RangeDiff < -tp->tp_uwr_med_z_3_min && RangeDiff > -tp->tp_uwr_med_z_3_max && sequency == 0) {\n+\t\t\t\t\tAddOffset = tp->tp_uwr_med_corr_z_3_rangea;\n+\t\t\t\t} else if (RangeDiff > tp->tp_uwr_med_z_4_min && RangeDiff < tp->tp_uwr_med_z_4_max && sequency == 0) {\n+\t\t\t\t\tAddOffset = tp->tp_uwr_med_corr_z_4_rangea;\n+\t\t\t\t} else if (RangeDiff < -tp->tp_uwr_med_z_4_min && RangeDiff > -tp->tp_uwr_med_z_4_max && sequency == 1) {\n+\t\t\t\t\tAddOffset = tp->tp_uwr_med_corr_z_4_rangeb;\n+\t\t\t\t} else if (RangeDiff < tp->tp_uwr_med_z_5_max && RangeDiff > tp->tp_uwr_med_z_5_min) {\n+\t\t\t\t\tAddOffset = tp->tp_uwr_med_corr_z_5_rangea;\n+\t\t\t\t} else\n+\t\t\t\t\tuwr_status = 0;\n+\t\t\t\tbreak;\n+\t\t\tcase VL53LX_DEVICEPRESETMODE_HISTOGRAM_LONG_RANGE:\n+\t\t\t\tif (RangeDiff > tp->tp_uwr_lng_z_1_min && RangeDiff < tp->tp_uwr_lng_z_1_max && sequency == 0) {\n+\t\t\t\t\tAddOffset = tp->tp_uwr_lng_corr_z_1_rangea;\n+\t\t\t\t} else if (RangeDiff < -tp->tp_uwr_lng_z_1_min && RangeDiff > -tp->tp_uwr_lng_z_1_max && sequency == 1) {\n+\t\t\t\t\tAddOffset = tp->tp_uwr_lng_corr_z_1_rangeb;\n+\t\t\t\t} else if (RangeDiff > tp->tp_uwr_lng_z_2_min && RangeDiff < tp->tp_uwr_lng_z_2_max && sequency == 1) {\n+\t\t\t\t\tAddOffset = tp->tp_uwr_lng_corr_z_2_rangeb;\n+\t\t\t\t} else if (RangeDiff < -tp->tp_uwr_lng_z_2_min && RangeDiff > -tp->tp_uwr_lng_z_2_max && sequency == 0) {\n+\t\t\t\t\tAddOffset = tp->tp_uwr_lng_corr_z_2_rangea;\n+\t\t\t\t} else if (RangeDiff < tp->tp_uwr_lng_z_3_max && RangeDiff > tp->tp_uwr_lng_z_3_min) {\n+\t\t\t\t\tAddOffset = tp->tp_uwr_lng_corr_z_3_rangea;\n+\t\t\t\t} else\n+\t\t\t\t\tuwr_status = 0;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tuwr_status = 0;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (uwr_status) {\n+\t\t\tpRangeData->RangeMilliMeter += AddOffset;\n+\t\t\tpRangeData->RangeMinMilliMeter += AddOffset;\n+\t\t\tpRangeData->RangeMaxMilliMeter += AddOffset;\n+\t\t\tpRangeData->ExtendedRange = 1;\n+\t\t\tpRangeData->RangeStatus = 0;\n+\t\t}\n+\n+\t}\n+\n+\tpdev->PreviousRangeMilliMeter[iteration] = RangeMillimeterInit;\n+\tpdev->PreviousRangeStatus[iteration] = pRangeData->RangeStatus;\n+\tpdev->PreviousExtendedRange[iteration] = pRangeData->ExtendedRange;\n+\tpdev->PreviousRangeActiveResults = active_results;\n+\n+\tRange = pRangeData->RangeMilliMeter;\n+\tif ((pRangeData->RangeStatus ==  VL53LX_RANGESTATUS_RANGE_VALID) && (Range < 0)) {\n+\t\tif (Range < BDTable[VL53LX_TUNING_PROXY_MIN])\n+\t\t\tpRangeData->RangeStatus = VL53LX_RANGESTATUS_RANGE_INVALID;\n+\t\telse\n+\t\t\tpRangeData->RangeMilliMeter = 0;\n+\t}\n+\n+\treturn Status;\n+}\n+\n+static VL53LX_Error SetMeasurementData(VL53LX_DEV Dev, VL53LX_range_results_t *presults, VL53LX_MultiRangingData_t *pMultiRangingData)\n+{\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tuint8_t i;\n+\tuint8_t iteration;\n+\tVL53LX_TargetRangeData_t *pRangeData;\n+\tVL53LX_range_data_t *presults_data;\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tuint8_t ActiveResults;\n+\n+\tpMultiRangingData->NumberOfObjectsFound = presults->active_results;\n+\tpMultiRangingData->HasXtalkValueChanged = presults->smudge_corrector_data.new_xtalk_applied_flag;\n+\n+\tpMultiRangingData->TimeStamp = 0;\n+\n+\tpMultiRangingData->StreamCount = presults->stream_count;\n+\n+\tActiveResults = presults->active_results;\n+\tif (ActiveResults < 1)\n+\t\titeration = 1;\n+\telse\n+\t\titeration = ActiveResults;\n+\tfor (i = 0; i < iteration; i++) {\n+\t\tpRangeData = &(pMultiRangingData->RangeData[i]);\n+\t\tpresults_data = &(presults->VL53LX_p_003[i]);\n+\t\tif (Status == VL53LX_ERROR_NONE)\n+\t\t\tStatus = SetTargetData(Dev, ActiveResults, pMultiRangingData->StreamCount, i, presults->device_status, presults_data, pRangeData);\n+\n+\t\tpMultiRangingData->EffectiveSpadRtnCount = presults_data->VL53LX_p_004;\n+\t}\n+\tpdev->PreviousStreamCount = pdev->hist_data.result__stream_count;\n+\tfor (i = iteration; i < VL53LX_MAX_RANGE_RESULTS; i++) {\n+\t\tpdev->PreviousRangeMilliMeter[i] = 0;\n+\t\tpdev->PreviousRangeStatus[i] = 255;\n+\t\tpdev->PreviousExtendedRange[i] = 0;\n+\t}\n+\n+\treturn Status;\n+}\n+\n+static void stmvl53lx_work_handler(struct work_struct *work)\n+{\n+\tstruct stmvl53lx_data *data;\n+\n+\tdata = container_of(work, struct stmvl53lx_data, dwork.work);\n+\twork_dbg(\"enter\");\n+\tmutex_lock(&data->work_mutex);\n+\tstmvl53lx_intr_process(data);\n+\tif (data->poll_mode && data->enable_sensor) {\n+\t\tschedule_delayed_work(&data->dwork, msecs_to_jiffies(data->poll_delay_ms));\n+\t}\n+\tmutex_unlock(&data->work_mutex);\n+}\n+\n+static int ctrl_roi(struct stmvl53lx_data *data, void __user *p)\n+{\n+\tint rc;\n+\tstruct stmvl53lx_ioctl_roi_t roi;\n+\n+\tmutex_lock(&data->work_mutex);\n+\n+\tif (data->is_device_remove) {\n+\t\trc = -ENODEV;\n+\t\tgoto done;\n+\t}\n+\trc = copy_from_user(&roi, p, sizeof(roi));\n+\tif (rc) {\n+\t\trc = -EFAULT;\n+\t\tgoto done;\n+\t}\n+\n+\tif (roi.is_read) {\n+\t\tmemcpy(&roi.Roi, &data->roi_cfg, sizeof(roi.Roi));\n+\t\trc = copy_to_user(p, &roi, sizeof(roi));\n+\t\tif (rc) {\n+\t\t\tvl53lx_errmsg(\"fail to copy Roi to user %d\", rc);\n+\t\t\trc = -EFAULT;\n+\t\t\tgoto done;\n+\t\t}\n+\t} else {\n+\t\tif (data->enable_sensor) {\n+\t\t\trc = -EBUSY;\n+\t\t\tvl53lx_errmsg(\"can't set roi while ranging\\n\");\n+\t\t\tgoto done;\n+\t\t}\n+\t\tmemcpy(&data->roi_cfg, &roi.Roi, sizeof(data->roi_cfg));\n+\t\tvl53lx_dbgmsg(\"ROI modified TopLeft(%d %d) BottomRight(%d %d)\\n\", data->roi_cfg.TopLeftX, data->roi_cfg.TopLeftY, data->roi_cfg.BotRightX, data->roi_cfg.BotRightY);\n+\t}\n+\n+done:\n+\tmutex_unlock(&data->work_mutex);\n+\treturn rc;\n+}\n+\n+static bool is_pid_in_list(pid_t pid, struct list_head *head)\n+{\n+\tstruct stmvl53lx_waiters *waiter;\n+\n+\tlist_for_each_entry(waiter, head, list)\n+\t\tif (waiter->pid == pid)\n+\t\t\treturn true;\n+\n+\treturn false;\n+}\n+\n+static bool is_new_data_for_me(struct stmvl53lx_data *data, pid_t pid, struct list_head *head)\n+{\n+\treturn data->is_data_valid && !is_pid_in_list(pid, head);\n+}\n+\n+static bool sleep_for_data_condition(struct stmvl53lx_data *data, pid_t pid, struct list_head *head)\n+{\n+\tbool res;\n+\n+\tmutex_lock(&data->work_mutex);\n+\tres = is_new_data_for_me(data, pid, head);\n+\tmutex_unlock(&data->work_mutex);\n+\n+\treturn res;\n+}\n+\n+static int sleep_for_data(struct stmvl53lx_data *data, pid_t pid, struct list_head *head)\n+{\n+\tint rc = 0;\n+\n+\tmutex_unlock(&data->work_mutex);\n+\trc = wait_event_interruptible_timeout(data->waiter_for_data, sleep_for_data_condition(data, pid, head), usecs_to_jiffies(2 * data->timing_budget));\n+\tif (rc == 0)\n+\t\trc = -EAGAIN;\n+\telse\n+\t\trc = 0;\n+\tmutex_lock(&data->work_mutex);\n+\n+\treturn data->enable_sensor ? rc : -ENODEV;\n+}\n+\n+static int add_reader(pid_t pid, struct list_head *head)\n+{\n+\tstruct stmvl53lx_waiters *new_waiter;\n+\n+\tnew_waiter = kmalloc(sizeof(struct stmvl53lx_waiters), GFP_KERNEL);\n+\tif (!new_waiter)\n+\t\treturn -ENOMEM;\n+\tnew_waiter->pid = pid;\n+\tlist_add(&new_waiter->list, head);\n+\n+\treturn 0;\n+}\n+\n+static int ctrl_mz_data_blocking_common(struct stmvl53lx_data *data, void __user *p, bool is_additional)\n+{\n+\tint rc = 0;\n+\tint rc0;\n+\tstruct stmvl53lx_data_with_additional __user *d = p;\n+\tpid_t pid = current->pid;\n+\n+\tmutex_lock(&data->work_mutex);\n+\tif (data->is_device_remove) {\n+\t\trc = -ENODEV;\n+\t\tgoto done;\n+\t}\n+\tif (!data->enable_sensor) {\n+\t\trc = -ENODEV;\n+\t\tgoto done;\n+\t}\n+\tif (!is_new_data_for_me(data, pid, &data->mz_data_reader_list))\n+\t\trc = sleep_for_data(data, pid, &data->mz_data_reader_list);\n+\tif (rc) {\n+\t\tkill_mz_data(&data->meas.multi_range_data);\n+\t\trc0 = copy_to_user(&d->data, &data->meas.multi_range_data, sizeof(VL53LX_MultiRangingData_t));\n+\t\tgoto done;\n+\t}\n+\n+\trc = copy_to_user(&d->data, &data->meas.multi_range_data, sizeof(VL53LX_MultiRangingData_t));\n+\tif (rc)\n+\t\tgoto done;\n+\tif (is_additional) {\n+\t\trc = copy_to_user(&d->additional_data, &data->meas.additional_data, sizeof(VL53LX_AdditionalData_t));\n+\t\tif (rc)\n+\t\t\tgoto done;\n+\t}\n+\trc = add_reader(pid, &data->mz_data_reader_list);\n+\n+done:\n+\tmutex_unlock(&data->work_mutex);\n+\n+\treturn rc;\n+}\n+\n+static int ctrl_mz_data_common(struct stmvl53lx_data *data, void __user *p, bool is_additional)\n+{\n+\tstruct stmvl53lx_data_with_additional __user *d = p;\n+\tint rc = 0;\n+\n+\tmutex_lock(&data->work_mutex);\n+\tif (data->is_device_remove) {\n+\t\trc = -ENODEV;\n+\t\tgoto done;\n+\t}\n+\trc = copy_to_user(&d->data, &data->meas.multi_range_data, sizeof(VL53LX_MultiRangingData_t));\n+\tif (rc) {\n+\t\tvl53lx_dbgmsg(\"copy to user fail %d\", rc);\n+\t\trc = -EFAULT;\n+\t\tgoto done;\n+\t}\n+\tif (is_additional) {\n+\t\trc = copy_to_user(&d->additional_data, &data->meas.additional_data, sizeof(VL53LX_AdditionalData_t));\n+\t\tif (rc) {\n+\t\t\tvl53lx_dbgmsg(\"copy to user fail %d\", rc);\n+\t\t\trc = -EFAULT;\n+\t\t\tgoto done;\n+\t\t}\n+\t}\n+\tif (!data->enable_sensor)\n+\t\trc = -ENODEV;\n+\n+done:\n+\tmutex_unlock(&data->work_mutex);\n+\treturn rc;\n+}\n+\n+static int ctrl_mz_data(struct stmvl53lx_data *data, void __user *p)\n+{\n+\treturn ctrl_mz_data_common(data, p, false);\n+}\n+\n+static int ctrl_mz_data_blocking(struct stmvl53lx_data *data, void __user *p)\n+{\n+\treturn ctrl_mz_data_blocking_common(data, p, false);\n+}\n+\n+static int ctrl_calibration_data(struct stmvl53lx_data *data, void __user *p)\n+{\n+\tint rc = 0;\n+\tstruct stmvl53lx_ioctl_calibration_data_t calib;\n+\tint data_offset = offsetof(struct stmvl53lx_ioctl_calibration_data_t, data);\n+\n+\tmutex_lock(&data->work_mutex);\n+\n+\tif (data->is_device_remove) {\n+\t\trc = -ENODEV;\n+\t\tgoto done;\n+\t}\n+\trc = copy_from_user(&calib, p, data_offset);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"fail to detect read or write %d\", rc);\n+\t\trc = -EFAULT;\n+\t\tgoto done;\n+\t}\n+\n+\tif (calib.is_read) {\n+\t\tmemset(&calib.data, 0, sizeof(calib.data));\n+\t\trc = VL53LX_GetCalibrationData(&data->stdev, &calib.data);\n+\t\tif (rc) {\n+\t\t\tvl53lx_errmsg(\"VL53LX_GetCalibrationData fail %d\", rc);\n+\t\t\trc = store_last_error(data, rc);\n+\t\t\tgoto done;\n+\t\t}\n+\t\trc = copy_to_user(p + data_offset, &calib.data,\n+\t\t\tsizeof(calib.data));\n+\t} else {\n+\t\tif (data->enable_sensor) {\n+\t\t\trc = -EBUSY;\n+\t\t\tvl53lx_errmsg(\"can't set calib data while ranging\\n\");\n+\t\t\tgoto done;\n+\t\t}\n+\t\trc = copy_from_user(&calib.data, p + data_offset,\n+\t\t\tsizeof(calib.data));\n+\t\tif (rc) {\n+\t\t\tvl53lx_errmsg(\"fail to copy calib data\");\n+\t\t\trc = -EFAULT;\n+\t\t\tgoto done;\n+\t\t}\n+\t\trc = VL53LX_SetCalibrationData(&data->stdev, &calib.data);\n+\t\tif (rc) {\n+\t\t\tvl53lx_errmsg(\"VL53LX_SetCalibrationData fail %d\", rc);\n+\t\t\trc = store_last_error(data, rc);\n+\t\t}\n+\t}\n+\n+done:\n+\tmutex_unlock(&data->work_mutex);\n+\treturn rc;\n+}\n+\n+VL53LX_Error VL53LX_set_ref_spad_char_config(\n+\tVL53LX_DEV    Dev,\n+\tuint8_t       vcsel_period_a,\n+\tuint32_t      phasecal_timeout_us,\n+\tuint16_t      total_rate_target_mcps,\n+\tuint16_t      max_count_rate_rtn_limit_mcps,\n+\tuint16_t      min_count_rate_rtn_limit_mcps,\n+\tuint16_t      fast_osc_frequency)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tuint8_t buffer[2];\n+\n+\tuint32_t macro_period_us = 0;\n+\tuint32_t timeout_mclks   = 0;\n+\n+\tmacro_period_us = VL53LX_calc_macro_period_us(fast_osc_frequency, vcsel_period_a);\n+\tif (macro_period_us == 0)\n+\t\tmacro_period_us = 1;\n+\n+\ttimeout_mclks = phasecal_timeout_us << 12;\n+\ttimeout_mclks = timeout_mclks + (macro_period_us>>1);\n+\ttimeout_mclks = timeout_mclks / macro_period_us;\n+\n+\tif (timeout_mclks > 0xFF)\n+\t\tpdev->gen_cfg.phasecal_config__timeout_macrop = 0xFF;\n+\telse\n+\t\tpdev->gen_cfg.phasecal_config__timeout_macrop = (uint8_t)timeout_mclks;\n+\n+\tpdev->tim_cfg.range_config__vcsel_period_a = vcsel_period_a;\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WrByte(Dev, VL53LX_PHASECAL_CONFIG__TIMEOUT_MACROP, pdev->gen_cfg.phasecal_config__timeout_macrop);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WrByte(Dev, VL53LX_RANGE_CONFIG__VCSEL_PERIOD_A, pdev->tim_cfg.range_config__vcsel_period_a);\n+\n+\tbuffer[0] = pdev->tim_cfg.range_config__vcsel_period_a;\n+\tbuffer[1] = pdev->tim_cfg.range_config__vcsel_period_a;\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WriteMulti(Dev, VL53LX_SD_CONFIG__WOI_SD0, buffer, 2);\n+\n+\tpdev->customer.ref_spad_char__total_rate_target_mcps = total_rate_target_mcps;\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WrWord(Dev, VL53LX_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS, total_rate_target_mcps);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WrWord(Dev, VL53LX_RANGE_CONFIG__SIGMA_THRESH, max_count_rate_rtn_limit_mcps);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WrWord(Dev, VL53LX_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS, min_count_rate_rtn_limit_mcps);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_start_test(VL53LX_DEV Dev, uint8_t test_mode__ctrl)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tstatus = VL53LX_WrByte(Dev, VL53LX_TEST_MODE__CTRL, test_mode__ctrl);\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_poll_for_range_completion(VL53LX_DEV Dev, uint32_t timeout_ms)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tuint8_t  gpio__mux_active_high_hv = 0;\n+\tuint8_t  interrupt_ready          = 0;\n+\n+\tgpio__mux_active_high_hv = pdev->stat_cfg.gpio_hv_mux__ctrl & VL53LX_DEVICEINTERRUPTLEVEL_ACTIVE_MASK;\n+\n+\tif (gpio__mux_active_high_hv == VL53LX_DEVICEINTERRUPTLEVEL_ACTIVE_HIGH)\n+\t\tinterrupt_ready = 0x01;\n+\telse\n+\t\tinterrupt_ready = 0x00;\n+\n+\tstatus = VL53LX_WaitValueMaskEx(Dev, timeout_ms, VL53LX_GPIO__TIO_HV_STATUS, interrupt_ready, 0x01, VL53LX_POLLING_DELAY_MS);\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_wait_for_test_completion(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tuint8_t data_ready  = 0;\n+\n+\tif (pdev->wait_method == VL53LX_WAIT_METHOD_BLOCKING) {\n+\t\tstatus = VL53LX_poll_for_range_completion(Dev, VL53LX_TEST_COMPLETION_POLLING_TIMEOUT_MS);\n+\n+\t} else {\n+\t\tdata_ready = 0;\n+\t\twhile (data_ready == 0x00 && status == VL53LX_ERROR_NONE) {\n+\t\t\tstatus = VL53LX_is_new_data_ready(Dev, &data_ready);\n+\t\t\tif (status == VL53LX_ERROR_NONE) {\n+\t\t\t\tstatus = VL53LX_WaitMs(Dev, VL53LX_POLLING_DELAY_MS);\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_clear_interrupt(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error status       = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tpdev->sys_ctrl.system__interrupt_clear = VL53LX_CLEAR_RANGE_INT;\n+\n+\tstatus = VL53LX_WrByte(Dev, VL53LX_SYSTEM__INTERRUPT_CLEAR, pdev->sys_ctrl.system__interrupt_clear);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_run_device_test(VL53LX_DEV Dev, VL53LX_DeviceTestMode device_test_mode)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tuint8_t      comms_buffer[2];\n+\tuint8_t      gpio_hv_mux__ctrl = 0;\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_RdByte(Dev, VL53LX_GPIO_HV_MUX__CTRL, &gpio_hv_mux__ctrl);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tpdev->stat_cfg.gpio_hv_mux__ctrl = gpio_hv_mux__ctrl;\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_start_test(Dev, device_test_mode);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_wait_for_test_completion(Dev);\n+\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_ReadMulti(Dev, VL53LX_RESULT__RANGE_STATUS, comms_buffer, 2);\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tpdev->sys_results.result__range_status  = comms_buffer[0];\n+\t\tpdev->sys_results.result__report_status = comms_buffer[1];\n+\t}\n+\n+\tpdev->sys_results.result__range_status &= VL53LX_RANGE_STATUS__RANGE_STATUS_MASK;\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\tstatus = VL53LX_clear_interrupt(Dev);\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_start_test(Dev, 0x00);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_run_ref_spad_char(VL53LX_DEV Dev, VL53LX_Error *pcal_status)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tuint8_t comms_buffer[6];\n+\n+\tVL53LX_refspadchar_config_t *prefspadchar  = &(pdev->refspadchar);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_enable_powerforce(Dev);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus =\n+\t\tVL53LX_set_ref_spad_char_config(\n+\t\t\tDev,\n+\t\t\tprefspadchar->VL53LX_p_005,\n+\t\t\tprefspadchar->timeout_us,\n+\t\t\tprefspadchar->target_count_rate_mcps,\n+\t\t\tprefspadchar->max_count_rate_limit_mcps,\n+\t\t\tprefspadchar->min_count_rate_limit_mcps,\n+\t\t\tpdev->stat_nvm.osc_measured__fast_osc__frequency);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_run_device_test(Dev, prefspadchar->device_test_mode);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_ReadMulti(Dev, VL53LX_REF_SPAD_CHAR_RESULT__NUM_ACTUAL_REF_SPADS, comms_buffer, 2);\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tpdev->dbg_results.ref_spad_char_result__num_actual_ref_spads = comms_buffer[0];\n+\t\tpdev->dbg_results.ref_spad_char_result__ref_location = comms_buffer[1];\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WriteMulti(Dev, VL53LX_REF_SPAD_MAN__NUM_REQUESTED_REF_SPADS, comms_buffer, 2);\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tpdev->customer.ref_spad_man__num_requested_ref_spads = comms_buffer[0];\n+\t\tpdev->customer.ref_spad_man__ref_location = comms_buffer[1];\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_ReadMulti(Dev, VL53LX_RESULT__SPARE_0_SD1, comms_buffer, 6);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_WriteMulti(Dev, VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_0, comms_buffer, 6);\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tpdev->customer.global_config__spad_enables_ref_0 = comms_buffer[0];\n+\t\tpdev->customer.global_config__spad_enables_ref_1 = comms_buffer[1];\n+\t\tpdev->customer.global_config__spad_enables_ref_2 = comms_buffer[2];\n+\t\tpdev->customer.global_config__spad_enables_ref_3 = comms_buffer[3];\n+\t\tpdev->customer.global_config__spad_enables_ref_4 = comms_buffer[4];\n+\t\tpdev->customer.global_config__spad_enables_ref_5 = comms_buffer[5];\n+\t}\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tswitch (pdev->sys_results.result__range_status) {\n+\t\tcase VL53LX_DEVICEERROR_REFSPADCHARNOTENOUGHDPADS:\n+\t\t\tstatus = VL53LX_WARNING_REF_SPAD_CHAR_NOT_ENOUGH_SPADS;\n+\t\t\tbreak;\n+\t\tcase VL53LX_DEVICEERROR_REFSPADCHARMORETHANTARGET:\n+\t\t\tstatus = VL53LX_WARNING_REF_SPAD_CHAR_RATE_TOO_HIGH;\n+\t\t\tbreak;\n+\t\tcase VL53LX_DEVICEERROR_REFSPADCHARLESSTHANTARGET:\n+\t\t\tstatus = VL53LX_WARNING_REF_SPAD_CHAR_RATE_TOO_LOW;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\t*pcal_status = status;\n+\tIGNORE_STATUS(IGNORE_REF_SPAD_CHAR_NOT_ENOUGH_SPADS, VL53LX_WARNING_REF_SPAD_CHAR_NOT_ENOUGH_SPADS, status);\n+\tIGNORE_STATUS(IGNORE_REF_SPAD_CHAR_RATE_TOO_HIGH, VL53LX_WARNING_REF_SPAD_CHAR_RATE_TOO_HIGH, status);\n+\tIGNORE_STATUS(IGNORE_REF_SPAD_CHAR_RATE_TOO_LOW, VL53LX_WARNING_REF_SPAD_CHAR_RATE_TOO_LOW, status);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_PerformRefSpadManagement(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tVL53LX_Error RawStatus;\n+\tuint8_t dcrbuffer[24];\n+\tuint8_t *commbuf;\n+\tuint8_t numloc[2] = {5, 3};\n+\tVL53LX_LLDriverData_t *pdev;\n+\tVL53LX_customer_nvm_managed_t *pc;\n+\tVL53LX_DistanceModes DistanceMode;\n+\n+\tpdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tpc = &pdev->customer;\n+\n+\tif (Status == VL53LX_ERROR_NONE) {\n+\t\tDistanceMode = VL53LXDevDataGet(Dev, CurrentParameters.DistanceMode);\n+\t\tStatus = VL53LX_run_ref_spad_char(Dev, &RawStatus);\n+\n+\t\tif (Status == VL53LX_ERROR_NONE)\n+\t\t\tStatus = VL53LX_SetDistanceMode(Dev, DistanceMode);\n+\t}\n+\n+\tif (Status == VL53LX_WARNING_REF_SPAD_CHAR_RATE_TOO_HIGH) {\n+\t\tStatus = VL53LX_read_nvm_raw_data(Dev, (uint8_t)(0xA0 >> 2), (uint8_t)(24 >> 2), dcrbuffer);\n+\n+\t\tif (Status == VL53LX_ERROR_NONE)\n+\t\t\tStatus = VL53LX_WriteMulti(Dev, VL53LX_REF_SPAD_MAN__NUM_REQUESTED_REF_SPADS, numloc, 2);\n+\n+\t\tif (Status == VL53LX_ERROR_NONE) {\n+\t\t\tpc->ref_spad_man__num_requested_ref_spads = numloc[0];\n+\t\t\tpc->ref_spad_man__ref_location = numloc[1];\n+\t\t}\n+\t\tcommbuf = &dcrbuffer[16];\n+\n+\t\tif (Status == VL53LX_ERROR_NONE)\n+\t\t\tStatus = VL53LX_WriteMulti(Dev, VL53LX_GLOBAL_CONFIG__SPAD_ENABLES_REF_0, commbuf, 6);\n+\n+\t\tif (Status == VL53LX_ERROR_NONE) {\n+\t\t\tpc->global_config__spad_enables_ref_0 = commbuf[0];\n+\t\t\tpc->global_config__spad_enables_ref_1 = commbuf[1];\n+\t\t\tpc->global_config__spad_enables_ref_2 = commbuf[2];\n+\t\t\tpc->global_config__spad_enables_ref_3 = commbuf[3];\n+\t\t\tpc->global_config__spad_enables_ref_4 = commbuf[4];\n+\t\t\tpc->global_config__spad_enables_ref_5 = commbuf[5];\n+\t\t}\n+\t}\n+\treturn Status;\n+}\n+\n+static int ctrl_perform_calibration_ref_spad_lock(struct stmvl53lx_data *data, struct stmvl53lx_ioctl_perform_calibration_t *calib)\n+{\n+\tint rc = VL53LX_PerformRefSpadManagement(&data->stdev);\n+\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"VL53LX_PerformRefSpadManagement fail => %d\", rc);\n+\t\trc = store_last_error(data, rc);\n+\t}\n+\treturn rc;\n+}\n+\n+void VL53LX_hist_xtalk_extract_data_init(VL53LX_hist_xtalk_extract_data_t *pxtalk_data)\n+{\tint32_t lb = 0;\n+\n+\tpxtalk_data->sample_count             = 0U;\n+\tpxtalk_data->pll_period_mm            = 0U;\n+\tpxtalk_data->peak_duration_us_sum     = 0U;\n+\tpxtalk_data->effective_spad_count_sum = 0U;\n+\tpxtalk_data->zero_distance_phase_sum  = 0U;\n+\tpxtalk_data->zero_distance_phase_avg  = 0U;\n+\tpxtalk_data->event_scaler_sum         = 0U;\n+\tpxtalk_data->event_scaler_avg         = 4096U;\n+\tpxtalk_data->signal_events_sum        = 0;\n+\tpxtalk_data->xtalk_rate_kcps_per_spad = 0U;\n+\tpxtalk_data->VL53LX_p_012             = 0U;\n+\tpxtalk_data->VL53LX_p_013               = 0U;\n+\tpxtalk_data->target_start             = 0U;\n+\n+\tfor (lb = 0; lb < VL53LX_XTALK_HISTO_BINS; lb++)\n+\t\tpxtalk_data->bin_data_sums[lb] = 0;\n+}\n+\n+VL53LX_Error VL53LX_wait_for_range_completion(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tuint8_t      data_ready  = 0;\n+\n+\tif (pdev->wait_method == VL53LX_WAIT_METHOD_BLOCKING) {\n+\t\tstatus = VL53LX_poll_for_range_completion(Dev, VL53LX_RANGE_COMPLETION_POLLING_TIMEOUT_MS);\n+\t} else {\n+\t\tdata_ready = 0;\n+\t\twhile (data_ready == 0x00 && status == VL53LX_ERROR_NONE) {\n+\t\t\tstatus = VL53LX_is_new_data_ready(Dev, &data_ready);\n+\t\t\tif (status == VL53LX_ERROR_NONE) {\n+\t\t\t\tstatus = VL53LX_WaitMs(Dev, VL53LX_POLLING_DELAY_MS);\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_hist_xtalk_extract_calc_window(\n+\tint16_t                             target_distance_mm,\n+\tuint16_t                            target_width_oversize,\n+\tVL53LX_histogram_bin_data_t        *phist_bins,\n+\tVL53LX_hist_xtalk_extract_data_t   *pxtalk_data)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tpxtalk_data->pll_period_mm = VL53LX_calc_pll_period_mm(phist_bins->VL53LX_p_015);\n+\tif (pxtalk_data->pll_period_mm == 0)\n+\t\tpxtalk_data->pll_period_mm = 1;\n+\n+\tpxtalk_data->xtalk_width_phase = (int32_t)phist_bins->vcsel_width * 128;\n+\tpxtalk_data->target_width_phase = pxtalk_data->xtalk_width_phase + (int32_t)target_width_oversize * 128;\n+\n+\tpxtalk_data->xtalk_start_phase = (int32_t)phist_bins->zero_distance_phase - (pxtalk_data->xtalk_width_phase / 2);\n+\tpxtalk_data->xtalk_end_phase  = (int32_t)pxtalk_data->xtalk_start_phase + pxtalk_data->xtalk_width_phase;\n+\n+\tif (pxtalk_data->xtalk_start_phase < 0)\n+\t\tpxtalk_data->xtalk_start_phase = 0;\n+\n+\tpxtalk_data->VL53LX_p_012 = (uint8_t)(pxtalk_data->xtalk_start_phase / 2048);\n+\tpxtalk_data->VL53LX_p_013 = (uint8_t)((pxtalk_data->xtalk_end_phase + 2047) / 2048);\n+\n+\tpxtalk_data->target_start_phase  = (int32_t)target_distance_mm * 2048 * 16;\n+\tpxtalk_data->target_start_phase += ((int32_t)pxtalk_data->pll_period_mm / 2);\n+\tpxtalk_data->target_start_phase /= (int32_t)pxtalk_data->pll_period_mm;\n+\tpxtalk_data->target_start_phase += (int32_t)phist_bins->zero_distance_phase;\n+\tpxtalk_data->target_start_phase -= (pxtalk_data->target_width_phase / 2);\n+\tpxtalk_data->target_end_phase  = (int32_t)pxtalk_data->target_start_phase + pxtalk_data->target_width_phase;\n+\n+\tif (pxtalk_data->target_start_phase < 0)\n+\t\tpxtalk_data->target_start_phase = 0;\n+\n+\tpxtalk_data->target_start = (uint8_t)(pxtalk_data->target_start_phase / 2048);\n+\n+\tif (pxtalk_data->VL53LX_p_013 > (pxtalk_data->target_start-1))\n+\t\tpxtalk_data->VL53LX_p_013 = pxtalk_data->target_start-1;\n+\n+\tpxtalk_data->effective_width = (2048 * ((int32_t)pxtalk_data->VL53LX_p_013+1));\n+\tpxtalk_data->effective_width -= pxtalk_data->xtalk_start_phase;\n+\n+\tif (pxtalk_data->effective_width > pxtalk_data->xtalk_width_phase)\n+\t\tpxtalk_data->effective_width = pxtalk_data->xtalk_width_phase;\n+\n+\tif (pxtalk_data->effective_width < 1)\n+\t\tpxtalk_data->effective_width = 1;\n+\n+\tpxtalk_data->event_scaler  =  pxtalk_data->xtalk_width_phase * 1000;\n+\tpxtalk_data->event_scaler +=  (pxtalk_data->effective_width / 2);\n+\tpxtalk_data->event_scaler /=  pxtalk_data->effective_width;\n+\n+\tif (pxtalk_data->event_scaler < 1000)\n+\t\tpxtalk_data->event_scaler = 1000;\n+\n+\tif (pxtalk_data->event_scaler > 4000)\n+\t\tpxtalk_data->event_scaler = 4000;\n+\n+\tpxtalk_data->event_scaler_sum += pxtalk_data->event_scaler;\n+\n+\tpxtalk_data->peak_duration_us_sum += (uint32_t)phist_bins->peak_duration_us;\n+\n+\tpxtalk_data->effective_spad_count_sum += (uint32_t)phist_bins->result__dss_actual_effective_spads;\n+\n+\tpxtalk_data->zero_distance_phase_sum += (uint32_t)phist_bins->zero_distance_phase;\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_hist_xtalk_extract_calc_event_sums(VL53LX_histogram_bin_data_t *phist_bins, VL53LX_hist_xtalk_extract_data_t *pxtalk_data)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tuint8_t   lb = 0;\n+\tuint8_t   i = 0;\n+\n+\tfor (lb  = pxtalk_data->VL53LX_p_012; lb <= pxtalk_data->VL53LX_p_013; lb++) {\n+\t\ti = (lb + phist_bins->number_of_ambient_bins + phist_bins->VL53LX_p_021) % phist_bins->VL53LX_p_021;\n+\n+\t\tpxtalk_data->signal_events_sum += phist_bins->bin_data[i];\n+\t\tpxtalk_data->signal_events_sum -= phist_bins->VL53LX_p_028;\n+\t}\n+\n+\tfor (lb  = 0; lb < VL53LX_XTALK_HISTO_BINS  && lb < phist_bins->VL53LX_p_021; lb++) {\n+\t\ti = (lb + phist_bins->number_of_ambient_bins + phist_bins->VL53LX_p_021) % phist_bins->VL53LX_p_021;\n+\n+\t\tpxtalk_data->bin_data_sums[lb] += phist_bins->bin_data[i];\n+\t\tpxtalk_data->bin_data_sums[lb] -= phist_bins->VL53LX_p_028;\n+\t}\n+\n+\tpxtalk_data->sample_count += 1;\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_hist_xtalk_extract_update(\n+\tint16_t                             target_distance_mm,\n+\tuint16_t                            target_width_oversize,\n+\tVL53LX_histogram_bin_data_t        *phist_bins,\n+\tVL53LX_hist_xtalk_extract_data_t   *pxtalk_data)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tstatus = VL53LX_hist_xtalk_extract_calc_window(target_distance_mm, target_width_oversize, phist_bins, pxtalk_data);\n+\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tstatus = VL53LX_hist_xtalk_extract_calc_event_sums(phist_bins, pxtalk_data);\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_hist_xtalk_extract_calc_rate_per_spad(VL53LX_hist_xtalk_extract_data_t *pxtalk_data)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tuint64_t tmp64_0        = 0;\n+\tuint64_t tmp64_1        = 0;\n+\tuint64_t xtalk_per_spad = 0;\n+\n+\ttmp64_1 = (uint64_t)pxtalk_data->effective_spad_count_sum * (uint64_t)pxtalk_data->peak_duration_us_sum;\n+\n+\tif (pxtalk_data->signal_events_sum < 0) {\n+\t\tpxtalk_data->signal_events_sum = 0;\n+\n+\t\ttmp64_0 = ((uint64_t)pxtalk_data->sample_count * (uint64_t)pxtalk_data->event_scaler_avg * 256U) << 9U;\n+\t\tif (tmp64_0 > 0) {\n+\t\t\tpxtalk_data->signal_events_sum = (int32_t)do_division_u((50U * tmp64_1), tmp64_0);\n+\t\t}\n+\t}\n+\ttmp64_0 = ((uint64_t)pxtalk_data->signal_events_sum * (uint64_t)pxtalk_data->sample_count * (uint64_t)pxtalk_data->event_scaler_avg * 256U) << 9U;\n+\tif (tmp64_1 > 0U) {\n+\t\ttmp64_0 = tmp64_0 + (tmp64_1 >> 1U);\n+\t\txtalk_per_spad = do_division_u(tmp64_0, tmp64_1);\n+\t} else {\n+\t\txtalk_per_spad = (uint64_t)tmp64_0;\n+\t}\n+\n+\tpxtalk_data->xtalk_rate_kcps_per_spad = (uint32_t)xtalk_per_spad;\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_hist_xtalk_extract_calc_shape(VL53LX_hist_xtalk_extract_data_t *pxtalk_data, VL53LX_xtalk_histogram_shape_t *pxtalk_shape)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\n+\tint32_t  lb = 0;\n+\tuint64_t total_events    = 0U;\n+\tuint64_t tmp64_0         = 0U;\n+\tint32_t  remaining_area  = 1024;\n+\n+\tpxtalk_shape->VL53LX_p_019 = 0;\n+\tpxtalk_shape->VL53LX_p_020 = VL53LX_XTALK_HISTO_BINS;\n+\tpxtalk_shape->VL53LX_p_021 = VL53LX_XTALK_HISTO_BINS;\n+\n+\tpxtalk_shape->zero_distance_phase = (uint16_t)pxtalk_data->zero_distance_phase_avg;\n+\tpxtalk_shape->phasecal_result__reference_phase = (uint16_t)pxtalk_data->zero_distance_phase_avg + (3*2048);\n+\n+\tif (pxtalk_data->signal_events_sum > 0)\n+\t\ttotal_events = (uint64_t)pxtalk_data->signal_events_sum * (uint64_t)pxtalk_data->event_scaler_avg;\n+\telse\n+\t\ttotal_events = 1;\n+\tif (total_events == 0)\n+\t\ttotal_events = 1;\n+\n+\tremaining_area  = 1024;\n+\tpxtalk_data->max_shape_value = 0;\n+\n+\tfor (lb = 0; lb < VL53LX_XTALK_HISTO_BINS; lb++) {\n+\t\tif ((lb < (int32_t)pxtalk_data->VL53LX_p_012 || lb > (int32_t)pxtalk_data->VL53LX_p_013)  || pxtalk_data->bin_data_sums[lb] < 0) {\n+\t\t\tif (remaining_area > 0 && remaining_area < 1024) {\n+\t\t\t\tif (remaining_area > pxtalk_data->max_shape_value) {\n+\t\t\t\t\tpxtalk_shape->bin_data[lb] = (uint32_t)pxtalk_data->max_shape_value;\n+\t\t\t\t\tremaining_area -= pxtalk_data->max_shape_value;\n+\t\t\t\t} else {\n+\t\t\t\t\tpxtalk_shape->bin_data[lb] = (uint32_t)remaining_area;\n+\t\t\t\t\tremaining_area = 0;\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tpxtalk_shape->bin_data[lb] = 0;\n+\t\t\t}\n+\t\t} else {\n+\t\t\ttmp64_0 = (uint64_t)pxtalk_data->bin_data_sums[lb] * 1024U * 1000U;\n+\t\t\ttmp64_0 += (total_events >> 1);\n+\t\t\ttmp64_0 = do_division_u(tmp64_0, total_events);\n+\t\t\tif (tmp64_0 > 0xFFFFU)\n+\t\t\t\ttmp64_0 = 0xFFFFU;\n+\n+\t\t\tpxtalk_shape->bin_data[lb] = (uint32_t)tmp64_0;\n+\n+\t\t\tif ((int32_t)pxtalk_shape->bin_data[lb] > pxtalk_data->max_shape_value)\n+\t\t\t\tpxtalk_data->max_shape_value = (int32_t)pxtalk_shape->bin_data[lb];\n+\n+\t\t\tremaining_area -= (int32_t)pxtalk_shape->bin_data[lb];\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_hist_xtalk_extract_fini(\n+\tVL53LX_histogram_bin_data_t        *phist_bins,\n+\tVL53LX_hist_xtalk_extract_data_t   *pxtalk_data,\n+\tVL53LX_xtalk_calibration_results_t *pxtalk_cal,\n+\tVL53LX_xtalk_histogram_shape_t     *pxtalk_shape)\n+{\n+\tVL53LX_Error  status = VL53LX_ERROR_NONE;\n+\tVL53LX_xtalk_calibration_results_t *pX = pxtalk_cal;\n+\n+\tif (pxtalk_data->sample_count > 0) {\n+\t\tpxtalk_data->event_scaler_avg  = pxtalk_data->event_scaler_sum;\n+\t\tpxtalk_data->event_scaler_avg += (pxtalk_data->sample_count >> 1);\n+\t\tpxtalk_data->event_scaler_avg /=  pxtalk_data->sample_count;\n+\n+\t\tstatus = VL53LX_hist_xtalk_extract_calc_rate_per_spad(pxtalk_data);\n+\t\tif (status == VL53LX_ERROR_NONE) {\n+\t\t\tpxtalk_data->zero_distance_phase_avg  = pxtalk_data->zero_distance_phase_sum;\n+\t\t\tpxtalk_data->zero_distance_phase_avg += (pxtalk_data->sample_count >> 1);\n+\t\t\tpxtalk_data->zero_distance_phase_avg /= pxtalk_data->sample_count;\n+\t\t\tstatus = VL53LX_hist_xtalk_extract_calc_shape(pxtalk_data, pxtalk_shape);\n+\n+\t\t\tpxtalk_shape->phasecal_result__vcsel_start = phist_bins->phasecal_result__vcsel_start;\n+\t\t\tpxtalk_shape->cal_config__vcsel_start = phist_bins->cal_config__vcsel_start;\n+\t\t\tpxtalk_shape->vcsel_width = phist_bins->vcsel_width;\n+\t\t\tpxtalk_shape->VL53LX_p_015 = phist_bins->VL53LX_p_015;\n+\t\t}\n+\n+\t\tif (status == VL53LX_ERROR_NONE) {\n+\t\t\tpX->algo__crosstalk_compensation_plane_offset_kcps = pxtalk_data->xtalk_rate_kcps_per_spad;\n+\t\t\tpX->algo__crosstalk_compensation_x_plane_gradient_kcps = 0U;\n+\t\t\tpX->algo__crosstalk_compensation_y_plane_gradient_kcps = 0U;\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_run_hist_xtalk_extraction(VL53LX_DEV Dev, int16_t cal_distance_mm, VL53LX_Error *pcal_status)\n+{\n+\t#define OVERSIZE 4\n+\tVL53LX_Error status = VL53LX_ERROR_NONE;\n+\tVL53LX_LLDriverData_t *pdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tVL53LX_xtalkextract_config_t *pX = &(pdev->xtalk_extract_cfg);\n+\tVL53LX_xtalk_config_t *pC = &(pdev->xtalk_cfg);\n+\tVL53LX_xtalk_calibration_results_t *pXC = &(pdev->xtalk_cal);\n+\n+\tuint8_t smudge_corr_en   = 0;\n+\tuint8_t i                = 0;\n+\tint8_t k = 0;\n+\tuint8_t nbloops;\n+\tint32_t initMergeSize = 0;\n+\tint32_t MergeEnabled = 0;\n+\tuint32_t deltaXtalk;\n+\tuint32_t stepXtalk;\n+\tuint32_t XtalkMin;\n+\tuint32_t XtalkMax;\n+\tuint8_t measurement_mode = VL53LX_DEVICEMEASUREMENTMODE_BACKTOBACK;\n+\tint8_t MaxId;\n+\tuint8_t histo_merge_nb;\n+\tuint8_t wait_for_accumulation;\n+\tVL53LX_range_results_t *prange_results = (VL53LX_range_results_t *) pdev->wArea1;\n+\tuint8_t Very1stRange = 0;\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus =\n+\t\t\tVL53LX_set_preset_mode(\n+\t\t\t\tDev,\n+\t\t\t\tVL53LX_DEVICEPRESETMODE_HISTOGRAM_LONG_RANGE,\n+\t\t\t\tpX->dss_config__target_total_rate_mcps,\n+\t\t\t\tpX->phasecal_config_timeout_us,\n+\t\t\t\tpX->mm_config_timeout_us,\n+\t\t\t\tpX->range_config_timeout_us,\n+\t\t\t\t100);\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_disable_xtalk_compensation(Dev);\n+\n+\tsmudge_corr_en = pdev->smudge_correct_config.smudge_corr_enabled;\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_dynamic_xtalk_correction_disable(Dev);\n+\n+\tVL53LX_load_patch(Dev);\n+\n+\tVL53LX_get_tuning_parm(Dev, VL53LX_TUNINGPARM_HIST_MERGE_MAX_SIZE, &initMergeSize);\n+\tVL53LX_get_tuning_parm(Dev, VL53LX_TUNINGPARM_HIST_MERGE, &MergeEnabled);\n+\tmemset(&pdev->xtalk_cal, 0,\tsizeof(pdev->xtalk_cal));\n+\n+\tif (status == VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_init_and_start_range(Dev, measurement_mode, VL53LX_DEVICECONFIGLEVEL_CUSTOMER_ONWARDS);\n+\n+\tMaxId = pdev->tuning_parms.tp_hist_merge_max_size - 1;\n+\tnbloops = (MergeEnabled == 0 ? 1 : 2);\n+\tfor (k = 0; k < nbloops; k++) {\n+\t\tVL53LX_hist_xtalk_extract_data_init(&(pdev->xtalk_extract));\n+\t\tVL53LX_set_tuning_parm(Dev, VL53LX_TUNINGPARM_HIST_MERGE_MAX_SIZE, k * MaxId + 1);\n+\n+\t\tfor (i = 0; i <= pX->num_of_samples; i++) {\n+\t\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\t\tstatus = VL53LX_wait_for_range_completion(Dev);\n+\t\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\t\tstatus = VL53LX_get_device_results(Dev, VL53LX_DEVICERESULTSLEVEL_FULL, prange_results);\n+\t\t\tVery1stRange = (pdev->ll_state.rd_device_state == VL53LX_DEVICESTATE_RANGING_WAIT_GPH_SYNC);\n+\n+\t\t\tVL53LX_compute_histo_merge_nb(Dev, &histo_merge_nb);\n+\t\t\twait_for_accumulation = ((k != 0) && (MergeEnabled) && (status == VL53LX_ERROR_NONE) && (histo_merge_nb < pdev->tuning_parms.tp_hist_merge_max_size));\n+\t\t\tif (wait_for_accumulation)\n+\t\t\t\ti = 0;\n+\t\t\telse {\n+\t\t\t\tif ((status == VL53LX_ERROR_NONE) && (!Very1stRange)) {\n+\t\t\t\t\tstatus = VL53LX_hist_xtalk_extract_update(cal_distance_mm, OVERSIZE, &(pdev->hist_data), &(pdev->xtalk_extract));\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\t\tstatus = VL53LX_clear_interrupt_and_enable_next_range(Dev, measurement_mode);\n+\t\t}\n+\t\tif (status == VL53LX_ERROR_NONE)\n+\t\t\tstatus = VL53LX_hist_xtalk_extract_fini(&(pdev->hist_data), &(pdev->xtalk_extract), &(pdev->xtalk_cal), &(pdev->xtalk_shapes.xtalk_shape));\n+\n+\t\tif (status == VL53LX_ERROR_NONE) {\n+\t\t\tpXC->algo__xtalk_cpo_HistoMerge_kcps[k * MaxId] = pXC->algo__crosstalk_compensation_plane_offset_kcps;\n+\t\t}\n+\t}\n+\tVL53LX_stop_range(Dev);\n+\n+\tVL53LX_set_tuning_parm(Dev, VL53LX_TUNINGPARM_HIST_MERGE_MAX_SIZE, initMergeSize);\n+\tVL53LX_unload_patch(Dev);\n+\n+\tif (status != VL53LX_ERROR_NONE)\n+\t\tstatus = VL53LX_ERROR_XTALK_EXTRACTION_SIGMA_LIMIT_FAIL;\n+\telse if ((MergeEnabled == 1) && (MaxId > 0)) {\n+\t\tXtalkMin = pdev->xtalk_cal.algo__xtalk_cpo_HistoMerge_kcps[0];\n+\t\tXtalkMax = pdev->xtalk_cal.algo__xtalk_cpo_HistoMerge_kcps[MaxId];\n+\t\tpdev->xtalk_cal.algo__crosstalk_compensation_plane_offset_kcps = XtalkMin;\n+\t\tif (XtalkMax > XtalkMin) {\n+\t\t\tdeltaXtalk =  XtalkMax - XtalkMin;\n+\t\t\tstepXtalk = deltaXtalk / MaxId;\n+\t\t\tfor (k = 1; k < MaxId; k++)\n+\t\t\tpdev->xtalk_cal.algo__xtalk_cpo_HistoMerge_kcps[k] = XtalkMin + stepXtalk * k;\n+\t\t} else\n+\t\t\tstatus = VL53LX_ERROR_XTALK_EXTRACTION_SIGMA_LIMIT_FAIL;\n+\t}\n+\tif (status == VL53LX_ERROR_NONE) {\n+\t\tpC->algo__crosstalk_compensation_x_plane_gradient_kcps = pXC->algo__crosstalk_compensation_x_plane_gradient_kcps;\n+\t\tpC->algo__crosstalk_compensation_y_plane_gradient_kcps = pXC->algo__crosstalk_compensation_y_plane_gradient_kcps;\n+\t\tpC->algo__crosstalk_compensation_plane_offset_kcps = pXC->algo__crosstalk_compensation_plane_offset_kcps;\n+\t}\n+\tpdev->xtalk_results.cal_status = status;\n+\t*pcal_status = pdev->xtalk_results.cal_status;\n+\n+\tstatus = VL53LX_enable_xtalk_compensation(Dev);\n+\tif (smudge_corr_en == 1)\n+\t\tstatus = VL53LX_dynamic_xtalk_correction_enable(Dev);\n+\n+\treturn status;\n+}\n+\n+VL53LX_Error VL53LX_PerformXTalkCalibration(VL53LX_DEV Dev)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tVL53LX_Error UStatus;\n+\tint16_t CalDistanceMm;\n+\tVL53LX_xtalk_calibration_results_t xtalk;\n+\n+\tVL53LX_CalibrationData_t caldata;\n+\tVL53LX_LLDriverData_t *pLLData;\n+\tint i;\n+\tuint32_t *pPlaneOffsetKcps;\n+\tuint32_t Margin = BDTable[VL53LX_TUNING_XTALK_FULL_ROI_BIN_SUM_MARGIN];\n+\tuint32_t DefaultOffset = BDTable[VL53LX_TUNING_XTALK_FULL_ROI_DEFAULT_OFFSET];\n+\tuint32_t *pLLDataPlaneOffsetKcps;\n+\tuint32_t sum = 0;\n+\tuint8_t binok = 0;\n+\n+\tpPlaneOffsetKcps = &caldata.customer.algo__crosstalk_compensation_plane_offset_kcps;\n+\tpLLData = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tpLLDataPlaneOffsetKcps = &pLLData->xtalk_cal.algo__crosstalk_compensation_plane_offset_kcps;\n+\n+\tCalDistanceMm = (int16_t)\n+\tBDTable[VL53LX_TUNING_XTALK_FULL_ROI_TARGET_DISTANCE_MM];\n+\tStatus = VL53LX_run_hist_xtalk_extraction(Dev, CalDistanceMm, &UStatus);\n+\n+\tVL53LX_GetCalibrationData(Dev, &caldata);\n+\tfor (i = 0; i < VL53LX_XTALK_HISTO_BINS; i++) {\n+\t\tsum += caldata.xtalkhisto.xtalk_shape.bin_data[i];\n+\t\tif (caldata.xtalkhisto.xtalk_shape.bin_data[i] > 0)\n+\t\t\tbinok++;\n+\t}\n+\tif ((UStatus == VL53LX_ERROR_XTALK_EXTRACTION_SIGMA_LIMIT_FAIL) || (sum > (1024 + Margin)) || (sum < (1024 - Margin)) || (binok < 3)) {\n+\t\t*pPlaneOffsetKcps = DefaultOffset;\n+\t\t*pLLDataPlaneOffsetKcps = DefaultOffset;\n+\t\tcaldata.xtalkhisto.xtalk_shape.bin_data[0] = 307;\n+\t\tcaldata.xtalkhisto.xtalk_shape.bin_data[1] = 410;\n+\t\tcaldata.xtalkhisto.xtalk_shape.bin_data[2] = 410;\n+\t\tcaldata.xtalkhisto.xtalk_shape.bin_data[3] = 307;\n+\t\tfor (i = 4; i < VL53LX_XTALK_HISTO_BINS; i++)\n+\t\t\tcaldata.xtalkhisto.xtalk_shape.bin_data[i] = 0;\n+\t\tfor (i = 0; i < VL53LX_BIN_REC_SIZE; i++)\n+\t\t\tcaldata.algo__xtalk_cpo_HistoMerge_kcps[i] = DefaultOffset + DefaultOffset * i;\n+\t\tVL53LX_SetCalibrationData(Dev, &caldata);\n+\t}\n+\n+\tif (Status == VL53LX_ERROR_NONE) {\n+\t\tStatus = VL53LX_get_current_xtalk_settings(Dev, &xtalk);\n+\t\tStatus = VL53LX_set_tuning_parm(Dev, VL53LX_TUNINGPARM_DYNXTALK_NODETECT_XTALK_OFFSET_KCPS, xtalk.algo__crosstalk_compensation_plane_offset_kcps);\n+\t}\n+\n+\treturn Status;\n+}\n+\n+static int ctrl_perform_calibration_crosstalk_lock(struct stmvl53lx_data *data, struct stmvl53lx_ioctl_perform_calibration_t *calib)\n+{\n+\tint rc = 0;\n+\n+\trc = stmvl53lx_sendparams(data);\n+\tif (rc)\n+\t\tgoto done;\n+\n+\trc = VL53LX_PerformXTalkCalibration(&data->stdev);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"VL53LX_PerformXTalkCalibration fail => %d\", rc);\n+\t\trc = store_last_error(data, rc);\n+\t}\n+\n+\tdata->crosstalk_enable = 1;\n+done:\n+\t\treturn rc;\n+}\n+\n+VL53LX_Error VL53LX_PerformOffsetSimpleCalibration(VL53LX_DEV Dev, int32_t CalDistanceMilliMeter)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tint32_t sum_ranging;\n+\tuint8_t offset_meas;\n+\tint16_t Max, UnderMax, OverMax, Repeat;\n+\tint32_t total_count, inloopcount;\n+\tint32_t IncRounding;\n+\tint16_t meanDistance_mm;\n+\tint16_t offset;\n+\tVL53LX_MultiRangingData_t RangingMeasurementData;\n+\tVL53LX_LLDriverData_t *pdev;\n+\tuint8_t goodmeas;\n+\tVL53LX_Error SmudgeStatus = VL53LX_ERROR_NONE;\n+\tuint8_t smudge_corr_en;\n+\tVL53LX_TargetRangeData_t *pRange;\n+\n+\tpdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tsmudge_corr_en = pdev->smudge_correct_config.smudge_corr_enabled;\n+\tSmudgeStatus = VL53LX_dynamic_xtalk_correction_disable(Dev);\n+\n+\tpdev->customer.algo__part_to_part_range_offset_mm = 0;\n+\tpdev->customer.mm_config__inner_offset_mm = 0;\n+\tpdev->customer.mm_config__outer_offset_mm = 0;\n+\tmemset(&pdev->per_vcsel_cal_data, 0, sizeof(pdev->per_vcsel_cal_data));\n+\tRepeat = BDTable[VL53LX_TUNING_SIMPLE_OFFSET_CALIBRATION_REPEAT];\n+\tMax = BDTable[VL53LX_TUNING_MAX_SIMPLE_OFFSET_CALIBRATION_SAMPLE_NUMBER];\n+\tUnderMax = 1 + (Max / 2);\n+\tOverMax = Max + (Max / 2);\n+\tsum_ranging = 0;\n+\ttotal_count = 0;\n+\n+\twhile ((Repeat > 0) && (Status == VL53LX_ERROR_NONE)) {\n+\t\tStatus = VL53LX_StartMeasurement(Dev);\n+\t\tif (Status == VL53LX_ERROR_NONE) {\n+\t\t\tVL53LX_WaitMeasurementDataReady(Dev);\n+\t\t\tVL53LX_GetMultiRangingData(Dev, &RangingMeasurementData);\n+\t\t\tVL53LX_ClearInterruptAndStartMeasurement(Dev);\n+\t\t}\n+\t\tinloopcount = 0;\n+\t\toffset_meas = 0;\n+\t\twhile ((Status == VL53LX_ERROR_NONE) && (inloopcount < Max) && (offset_meas < OverMax)) {\n+\t\t\tStatus = VL53LX_WaitMeasurementDataReady(Dev);\n+\t\t\tif (Status == VL53LX_ERROR_NONE)\n+\t\t\t\tStatus = VL53LX_GetMultiRangingData(Dev, &RangingMeasurementData);\n+\t\t\tpRange = &(RangingMeasurementData.RangeData[0]);\n+\t\t\tgoodmeas = (pRange->RangeStatus == VL53LX_RANGESTATUS_RANGE_VALID);\n+\t\t\tif ((Status == VL53LX_ERROR_NONE) && goodmeas) {\n+\t\t\t\tsum_ranging += pRange->RangeMilliMeter;\n+\t\t\t\tinloopcount++;\n+\t\t\t}\n+\t\t\tStatus = VL53LX_ClearInterruptAndStartMeasurement(Dev);\n+\t\t\toffset_meas++;\n+\t\t}\n+\t\ttotal_count += inloopcount;\n+\t\tif (inloopcount < UnderMax)\n+\t\t\tStatus = VL53LX_ERROR_OFFSET_CAL_NO_SAMPLE_FAIL;\n+\n+\t\tVL53LX_StopMeasurement(Dev);\n+\t\tRepeat--;\n+\t}\n+\tif ((SmudgeStatus == VL53LX_ERROR_NONE) && (smudge_corr_en == 1))\n+\t\tSmudgeStatus = VL53LX_dynamic_xtalk_correction_enable(Dev);\n+\n+\tif ((sum_ranging < 0) || (sum_ranging > ((int32_t) total_count * 0xffff)))\n+\t\tStatus = VL53LX_WARNING_OFFSET_CAL_SIGMA_TOO_HIGH;\n+\n+\tif ((Status == VL53LX_ERROR_NONE) && (total_count > 0)) {\n+\t\tIncRounding = total_count / 2;\n+\t\tmeanDistance_mm = (int16_t)((sum_ranging + IncRounding) / total_count);\n+\t\toffset = (int16_t)CalDistanceMilliMeter - meanDistance_mm;\n+\t\tpdev->customer.algo__part_to_part_range_offset_mm = 0;\n+\t\tpdev->customer.mm_config__inner_offset_mm = offset;\n+\t\tpdev->customer.mm_config__outer_offset_mm = offset;\n+\n+\t\tStatus = VL53LX_set_customer_nvm_managed(Dev, &(pdev->customer));\n+\t}\n+\treturn Status;\n+}\n+\n+static int ctrl_perform_simple_calibration_offset_lock(struct stmvl53lx_data *data, struct stmvl53lx_ioctl_perform_calibration_t *calib)\n+{\n+\tint rc = 0;\n+\n+\tdata->is_delay_allowed = 1;\n+\trc = stmvl53lx_sendparams(data);\n+\tif (rc)\n+\t\tgoto done;\n+\n+\trc = VL53LX_PerformOffsetSimpleCalibration(&data->stdev, calib->param1);\n+\tdata->is_delay_allowed = 0;\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\n+\t\t\t\"VL53LX_PerformOffsetSimpleCalibration fail => %d\", rc);\n+\t\trc = store_last_error(data, rc);\n+\t}\n+\n+done:\n+\treturn rc;\n+}\n+\n+VL53LX_Error VL53LX_GetDistanceMode(VL53LX_DEV Dev, VL53LX_DistanceModes *pDistanceMode)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\n+\t*pDistanceMode = VL53LXDevDataGet(Dev, CurrentParameters.DistanceMode);\n+\n+\treturn Status;\n+}\n+\n+VL53LX_Error VL53LX_PerformOffsetPerVcselCalibration(VL53LX_DEV Dev, int32_t CalDistanceMilliMeter)\n+{\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tint32_t sum_ranging_range_A, sum_ranging_range_B;\n+\tuint8_t offset_meas_range_A, offset_meas_range_B;\n+\tint16_t Max, UnderMax, OverMax, Repeat;\n+\tint32_t inloopcount;\n+\tint32_t IncRounding;\n+\tint16_t meanDistance_mm;\n+\tVL53LX_MultiRangingData_t RangingMeasurementData;\n+\tVL53LX_LLDriverData_t *pdev;\n+\tuint8_t goodmeas;\n+\tVL53LX_DistanceModes currentDist;\n+\tVL53LX_DistanceModes DistMode[3] = {VL53LX_DISTANCEMODE_SHORT, VL53LX_DISTANCEMODE_MEDIUM, VL53LX_DISTANCEMODE_LONG};\n+\tint16_t offsetA[3] = {0, 0, 0};\n+\tint16_t offsetB[3] = {0, 0, 0};\n+\n+\tVL53LX_Error SmudgeStatus = VL53LX_ERROR_NONE;\n+\tuint8_t smudge_corr_en, ics;\n+\tVL53LX_TargetRangeData_t *pRange;\n+\n+\tpdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\n+\tsmudge_corr_en = pdev->smudge_correct_config.smudge_corr_enabled;\n+\tSmudgeStatus = VL53LX_dynamic_xtalk_correction_disable(Dev);\n+\n+\tpdev->customer.algo__part_to_part_range_offset_mm = 0;\n+\tpdev->customer.mm_config__inner_offset_mm = 0;\n+\tpdev->customer.mm_config__outer_offset_mm = 0;\n+\tpdev->customer.mm_config__outer_offset_mm = 0;\n+\tmemset(&pdev->per_vcsel_cal_data, 0, sizeof(pdev->per_vcsel_cal_data));\n+\n+\tRepeat = 0;\n+\tif (IsL4(Dev))\n+\t\tRepeat = 1;\n+\tMax = 2 * BDTable[VL53LX_TUNING_MAX_SIMPLE_OFFSET_CALIBRATION_SAMPLE_NUMBER];\n+\tUnderMax = 1 + (Max / 2);\n+\tOverMax = Max + (Max / 2);\n+\n+\tStatus = VL53LX_GetDistanceMode(Dev, &currentDist);\n+\n+\twhile ((Repeat < 3) && (Status == VL53LX_ERROR_NONE)) {\n+\t\tStatus = VL53LX_SetDistanceMode(Dev, DistMode[Repeat]);\n+\t\tStatus = VL53LX_StartMeasurement(Dev);\n+\n+\t\tif (Status == VL53LX_ERROR_NONE) {\n+\t\t\tVL53LX_WaitMeasurementDataReady(Dev);\n+\t\t\tVL53LX_GetMultiRangingData(Dev, &RangingMeasurementData);\n+\t\t\tVL53LX_ClearInterruptAndStartMeasurement(Dev);\n+\t\t}\n+\t\tinloopcount = 0;\n+\t\toffset_meas_range_A = 0;\n+\t\tsum_ranging_range_A = 0;\n+\t\toffset_meas_range_B = 0;\n+\t\tsum_ranging_range_B = 0;\n+\t\twhile ((Status == VL53LX_ERROR_NONE) && (inloopcount < Max) && (inloopcount < OverMax)) {\n+\t\t\tStatus = VL53LX_WaitMeasurementDataReady(Dev);\n+\t\t\tif (Status == VL53LX_ERROR_NONE)\n+\t\t\t\tStatus = VL53LX_GetMultiRangingData(Dev, &RangingMeasurementData);\n+\t\t\tpRange = &(RangingMeasurementData.RangeData[0]);\n+\t\t\tgoodmeas = (pRange->RangeStatus == VL53LX_RANGESTATUS_RANGE_VALID);\n+\t\t\tics = pdev->ll_state.cfg_internal_stream_count;\n+\t\t\tif ((Status == VL53LX_ERROR_NONE) && goodmeas) {\n+\t\t\t\tif (ics & 0x01) {\n+\t\t\t\t\tsum_ranging_range_A += pRange->RangeMilliMeter;\n+\t\t\t\t\toffset_meas_range_A++;\n+\t\t\t\t} else {\n+\t\t\t\t\tsum_ranging_range_B += pRange->RangeMilliMeter;\n+\t\t\t\t\toffset_meas_range_B++;\n+\t\t\t\t}\n+\t\t\t\tinloopcount = offset_meas_range_A + offset_meas_range_B;\n+\t\t\t}\n+\t\t\tStatus = VL53LX_ClearInterruptAndStartMeasurement(Dev);\n+\t\t}\n+\t\tif (inloopcount < UnderMax)\n+\t\t\tStatus = VL53LX_ERROR_OFFSET_CAL_NO_SAMPLE_FAIL;\n+\n+\t\tVL53LX_StopMeasurement(Dev);\n+\n+\t\tif ((sum_ranging_range_A < 0) ||\n+\t\t\t(sum_ranging_range_B < 0) ||\n+\t\t\t(sum_ranging_range_A >\n+\t\t\t((int32_t) offset_meas_range_A * 0xffff)) ||\n+\t\t\t(sum_ranging_range_B >\n+\t\t\t((int32_t) offset_meas_range_B * 0xffff))) {\n+\t\t\tStatus = VL53LX_WARNING_OFFSET_CAL_SIGMA_TOO_HIGH;\n+\t\t}\n+\n+\t\tif ((Status == VL53LX_ERROR_NONE) && (offset_meas_range_A > 0)) {\n+\t\t\tIncRounding = offset_meas_range_A / 2;\n+\t\t\tmeanDistance_mm = (int16_t)((sum_ranging_range_A + IncRounding) / offset_meas_range_A);\n+\t\t\toffsetA[Repeat] = (int16_t)CalDistanceMilliMeter - meanDistance_mm;\n+\t\t}\n+\n+\t\tif ((Status == VL53LX_ERROR_NONE) && (offset_meas_range_B > 0)) {\n+\t\t\tIncRounding = offset_meas_range_B / 2;\n+\t\t\tmeanDistance_mm = (int16_t)((sum_ranging_range_B + IncRounding) / offset_meas_range_B);\n+\t\t\toffsetB[Repeat] = (int16_t)CalDistanceMilliMeter - meanDistance_mm;\n+\t\t}\n+\t\tRepeat++;\n+\t}\n+\n+\tif ((SmudgeStatus == VL53LX_ERROR_NONE) && (smudge_corr_en == 1))\n+\t\tSmudgeStatus = VL53LX_dynamic_xtalk_correction_enable(Dev);\n+\n+\tif (Status == VL53LX_ERROR_NONE) {\n+\t\tpdev->per_vcsel_cal_data.short_a_offset_mm  = offsetA[0];\n+\t\tpdev->per_vcsel_cal_data.short_b_offset_mm  = offsetB[0];\n+\t\tpdev->per_vcsel_cal_data.medium_a_offset_mm = offsetA[1];\n+\t\tpdev->per_vcsel_cal_data.medium_b_offset_mm = offsetB[1];\n+\t\tpdev->per_vcsel_cal_data.long_a_offset_mm   = offsetA[2];\n+\t\tpdev->per_vcsel_cal_data.long_b_offset_mm   = offsetB[2];\n+\t}\n+\n+\tVL53LX_SetDistanceMode(Dev, currentDist);\n+\treturn Status;\n+}\n+\n+static int ctrl_perform_per_vcsel_calibration_offset_lock(struct stmvl53lx_data *data, struct stmvl53lx_ioctl_perform_calibration_t *calib)\n+{\n+\tint rc = 0;\n+\n+\tdata->is_delay_allowed = 1;\n+\n+\trc = stmvl53lx_sendparams(data);\n+\tif (rc)\n+\t\tgoto done;\n+\n+\trc = VL53LX_PerformOffsetPerVcselCalibration(&data->stdev, calib->param1);\n+\tdata->is_delay_allowed = 0;\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\n+\t\t\"VL53LX_PerformOffsetPerVcselCalibration fail => %d\", rc);\n+\t\trc = store_last_error(data, rc);\n+\t}\n+\n+done:\n+\treturn rc;\n+}\n+\n+VL53LX_Error VL53LX_PerformOffsetZeroDistanceCalibration(VL53LX_DEV Dev)\n+{\n+\t#define START_OFFSET 50\n+\tVL53LX_Error Status = VL53LX_ERROR_NONE;\n+\tint32_t sum_ranging;\n+\tuint8_t offset_meas;\n+\tint16_t Max, UnderMax, OverMax, Repeat;\n+\tint32_t total_count, inloopcount;\n+\tint32_t IncRounding;\n+\tint16_t meanDistance_mm;\n+\tint16_t offset, ZeroDistanceOffset;\n+\tVL53LX_MultiRangingData_t RangingMeasurementData;\n+\tVL53LX_LLDriverData_t *pdev;\n+\tuint8_t goodmeas;\n+\tVL53LX_Error SmudgeStatus = VL53LX_ERROR_NONE;\n+\tuint8_t smudge_corr_en;\n+\tVL53LX_TargetRangeData_t *pRange;\n+\n+\tpdev = VL53LXDevStructGetLLDriverHandle(Dev);\n+\tsmudge_corr_en = pdev->smudge_correct_config.smudge_corr_enabled;\n+\tSmudgeStatus = VL53LX_dynamic_xtalk_correction_disable(Dev);\n+\tpdev->customer.algo__part_to_part_range_offset_mm = 0;\n+\tpdev->customer.mm_config__inner_offset_mm = START_OFFSET;\n+\tpdev->customer.mm_config__outer_offset_mm = START_OFFSET;\n+\tmemset(&pdev->per_vcsel_cal_data, 0, sizeof(pdev->per_vcsel_cal_data));\n+\tZeroDistanceOffset = BDTable[VL53LX_TUNING_ZERO_DISTANCE_OFFSET_NON_LINEAR_FACTOR];\n+\tRepeat = BDTable[VL53LX_TUNING_SIMPLE_OFFSET_CALIBRATION_REPEAT];\n+\tMax = BDTable[VL53LX_TUNING_MAX_SIMPLE_OFFSET_CALIBRATION_SAMPLE_NUMBER];\n+\tUnderMax = 1 + (Max / 2);\n+\tOverMax = Max + (Max / 2);\n+\tsum_ranging = 0;\n+\ttotal_count = 0;\n+\n+\twhile ((Repeat > 0) && (Status == VL53LX_ERROR_NONE)) {\n+\t\tStatus = VL53LX_StartMeasurement(Dev);\n+\t\tif (Status == VL53LX_ERROR_NONE) {\n+\t\t\tVL53LX_WaitMeasurementDataReady(Dev);\n+\t\t\tVL53LX_GetMultiRangingData(Dev, &RangingMeasurementData);\n+\t\t\tVL53LX_ClearInterruptAndStartMeasurement(Dev);\n+\t\t}\n+\t\tinloopcount = 0;\n+\t\toffset_meas = 0;\n+\t\twhile ((Status == VL53LX_ERROR_NONE) && (inloopcount < Max) && (offset_meas < OverMax)) {\n+\t\t\tStatus = VL53LX_WaitMeasurementDataReady(Dev);\n+\t\t\tif (Status == VL53LX_ERROR_NONE)\n+\t\t\t\tStatus = VL53LX_GetMultiRangingData(Dev, &RangingMeasurementData);\n+\t\t\tpRange = &(RangingMeasurementData.RangeData[0]);\n+\t\t\tgoodmeas = (pRange->RangeStatus == VL53LX_RANGESTATUS_RANGE_VALID);\n+\t\t\tif ((Status == VL53LX_ERROR_NONE) && goodmeas) {\n+\t\t\t\tsum_ranging = sum_ranging + pRange->RangeMilliMeter;\n+\t\t\t\tinloopcount++;\n+\t\t\t}\n+\t\t\tStatus = VL53LX_ClearInterruptAndStartMeasurement(Dev);\n+\t\t\toffset_meas++;\n+\t\t}\n+\t\ttotal_count += inloopcount;\n+\t\tif (inloopcount < UnderMax)\n+\t\t\tStatus = VL53LX_ERROR_OFFSET_CAL_NO_SAMPLE_FAIL;\n+\t\tVL53LX_StopMeasurement(Dev);\n+\t\tRepeat--;\n+\t}\n+\tif ((SmudgeStatus == VL53LX_ERROR_NONE) && (smudge_corr_en == 1))\n+\t\tSmudgeStatus = VL53LX_dynamic_xtalk_correction_enable(Dev);\n+\tif ((sum_ranging < 0) || (sum_ranging > ((int32_t) total_count * 0xffff)))\n+\t\tStatus = VL53LX_WARNING_OFFSET_CAL_SIGMA_TOO_HIGH;\n+\n+\tif ((Status == VL53LX_ERROR_NONE) && (total_count > 0)) {\n+\t\tIncRounding = total_count / 2;\n+\t\tmeanDistance_mm = (int16_t)((sum_ranging + IncRounding) / total_count);\n+\t\toffset = START_OFFSET - meanDistance_mm + ZeroDistanceOffset;\n+\t\tpdev->customer.algo__part_to_part_range_offset_mm = 0;\n+\t\tpdev->customer.mm_config__inner_offset_mm = offset;\n+\t\tpdev->customer.mm_config__outer_offset_mm = offset;\n+\t\tStatus = VL53LX_set_customer_nvm_managed(Dev, &(pdev->customer));\n+\t}\n+\n+\treturn Status;\n+}\n+\n+static int ctrl_perform_zero_distance_calibration_offset_lock(struct stmvl53lx_data *data, struct stmvl53lx_ioctl_perform_calibration_t *calib)\n+{\n+\tint rc = 0;\n+\n+\tdata->is_delay_allowed = 1;\n+\n+\trc = stmvl53lx_sendparams(data);\n+\tif (rc)\n+\t\tgoto done;\n+\n+\trc = VL53LX_PerformOffsetZeroDistanceCalibration(&data->stdev);\n+\tdata->is_delay_allowed = 0;\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\n+\t\t\"VL53LX_PerformOffsetZeroDistanceCalibration fail => %d\", rc);\n+\t\trc = store_last_error(data, rc);\n+\t}\n+\n+done:\n+\treturn rc;\n+}\n+\n+static int ctrl_perform_calibration(struct stmvl53lx_data *data, void __user *p)\n+{\n+\tint rc = 0;\n+\tstruct stmvl53lx_ioctl_perform_calibration_t calib;\n+\n+\tmutex_lock(&data->work_mutex);\n+\n+\tif (data->is_device_remove) {\n+\t\trc = -ENODEV;\n+\t\tgoto done;\n+\t}\n+\tdata->is_calibrating = true;\n+\trc = copy_from_user(&calib, p, sizeof(calib));\n+\tif (rc) {\n+\t\trc = -EFAULT;\n+\t\tgoto done;\n+\t}\n+\tif (data->enable_sensor) {\n+\t\trc = -EBUSY;\n+\t\tvl53lx_errmsg(\"can't perform calibration while ranging\\n\");\n+\t\tgoto done;\n+\t}\n+\n+\trc = reset_release(data);\n+\tif (rc)\n+\t\tgoto done;\n+\n+\tswitch (calib.calibration_type) {\n+\tcase VL53LX_CALIBRATION_REF_SPAD:\n+\t\trc = ctrl_perform_calibration_ref_spad_lock(data, &calib);\n+\t\tbreak;\n+\tcase VL53LX_CALIBRATION_CROSSTALK:\n+\t\trc = ctrl_perform_calibration_crosstalk_lock(data, &calib);\n+\t\tbreak;\n+\tcase VL53LX_CALIBRATION_OFFSET:\n+\t\trc = ctrl_perform_simple_calibration_offset_lock(data, &calib);\n+\t\tbreak;\n+\tcase VL53LX_CALIBRATION_OFFSET_SIMPLE:\n+\t\trc = ctrl_perform_simple_calibration_offset_lock(data, &calib);\n+\t\tbreak;\n+\tcase VL53LX_CALIBRATION_OFFSET_PER_VCSEL:\n+\t\trc = ctrl_perform_per_vcsel_calibration_offset_lock(data, &calib);\n+\t\tbreak;\n+\tcase VL53LX_CALIBRATION_OFFSET_ZERO_DISTANCE:\n+\t\trc = ctrl_perform_zero_distance_calibration_offset_lock(data,\n+\t\t\t&calib);\n+\t\tbreak;\n+\tdefault:\n+\t\trc = -EINVAL;\n+\t\tbreak;\n+\t}\n+\treset_hold(data);\n+\n+done:\n+\tdata->is_calibrating = false;\n+\tdata->is_first_start_done = true;\n+\tmutex_unlock(&data->work_mutex);\n+\n+\treturn rc;\n+}\n+\n+static int ctrl_mz_data_additional(struct stmvl53lx_data *data, void __user *p)\n+{\n+\treturn ctrl_mz_data_common(data, p, true);\n+}\n+\n+static int ctrl_mz_data_blocking_additional(struct stmvl53lx_data *data, void __user *p)\n+{\n+\treturn ctrl_mz_data_blocking_common(data, p, true);\n+}\n+\n+static int stmvl53lx_ioctl_handler(struct stmvl53lx_data *data, unsigned int cmd, unsigned long arg, void __user *p)\n+{\n+\tint rc = 0;\n+\n+\tif (!data)\n+\t\treturn -EINVAL;\n+\n+\tswitch (cmd) {\n+\tcase VL53LX_IOCTL_START:\n+\t\tvl53lx_dbgmsg(\"VL53LX_IOCTL_START\\n\");\n+\t\trc = ctrl_start(data);\n+\t\tbreak;\n+\tcase VL53LX_IOCTL_STOP:\n+\t\tvl53lx_dbgmsg(\"VL53LX_IOCTL_STOP\\n\");\n+\t\trc = ctrl_stop(data);\n+\t\tbreak;\n+\tcase VL53LX_IOCTL_REGISTER:\n+\t\tvl53lx_dbgmsg(\"VL53LX_IOCTL_REGISTER\\n\");\n+\t\trc = ctrl_reg_access(data, p);\n+\t\tbreak;\n+\tcase VL53LX_IOCTL_PARAMETER:\n+\t\tvl53lx_dbgmsg(\"VL53LX_IOCTL_PARAMETER\\n\");\n+\t\trc = ctrl_params(data, p);\n+\t\tbreak;\n+\tcase VL53LX_IOCTL_ROI:\n+\t\tvl53lx_dbgmsg(\"VL53LX_IOCTL_ROI\\n\");\n+\t\trc = ctrl_roi(data, p);\n+\t\tbreak;\n+\tcase VL53LX_IOCTL_MZ_DATA:\n+\t\trc = ctrl_mz_data(data, p);\n+\t\tbreak;\n+\tcase VL53LX_IOCTL_MZ_DATA_BLOCKING:\n+\t\trc = ctrl_mz_data_blocking(data, p);\n+\t\tbreak;\n+\tcase VL53LX_IOCTL_CALIBRATION_DATA:\n+\t\tvl53lx_dbgmsg(\"VL53LX_IOCTL_CALIBRATION_DATA\\n\");\n+\t\trc = ctrl_calibration_data(data, p);\n+\t\tbreak;\n+\tcase VL53LX_IOCTL_PERFORM_CALIBRATION:\n+\t\tvl53lx_dbgmsg(\"VL53LX_IOCTL_PERFORM_CALIBRATION\\n\");\n+\t\trc = ctrl_perform_calibration(data, p);\n+\t\tbreak;\n+\tcase VL53LX_IOCTL_MZ_DATA_ADDITIONAL:\n+\t\trc = ctrl_mz_data_additional(data, p);\n+\t\tbreak;\n+\tcase VL53LX_IOCTL_MZ_DATA_ADDITIONAL_BLOCKING:\n+\t\trc = ctrl_mz_data_blocking_additional(data, p);\n+\t\tbreak;\n+\tdefault:\n+\t\trc = -EINVAL;\n+\t\tbreak;\n+\t}\n+\treturn rc;\n+}\n+\n+static long stmvl53lx_ioctl(struct file *file, unsigned int cmd, unsigned long arg)\n+{\n+\tlong ret;\n+\tstruct stmvl53lx_data *data = container_of(file->private_data, struct stmvl53lx_data, miscdev);\n+\tret = stmvl53lx_ioctl_handler(data, cmd, arg, (void __user *)arg);\n+\treturn ret;\n+}\n+\n+static int stmvl53lx_open(struct inode *inode, struct file *file)\n+{\n+\tstruct stmvl53lx_data *data = container_of(file->private_data, struct stmvl53lx_data, miscdev);\n+\n+\tvl53lx_dbgmsg(\"Start\\n\");\n+\tstmvl53lx_module_func_tbl.get(data->client_object);\n+\tvl53lx_dbgmsg(\"End\\n\");\n+\n+\treturn 0;\n+}\n+\n+static int stmvl53lx_release(struct inode *inode, struct file *file)\n+{\n+\tstruct stmvl53lx_data *data = container_of(file->private_data, struct stmvl53lx_data, miscdev);\n+\n+\tvl53lx_dbgmsg(\"Start\\n\");\n+\tstmvl53lx_module_func_tbl.put(data->client_object);\n+\tvl53lx_dbgmsg(\"End\\n\");\n+\n+\treturn 0;\n+}\n+\n+static const struct file_operations stmvl53lx_ranging_fops = {\n+\t.owner =\t\tTHIS_MODULE,\n+\t.unlocked_ioctl =\tstmvl53lx_ioctl,\n+\t.open =\t\t\tstmvl53lx_open,\n+\t.release =\t\tstmvl53lx_release,\n+};\n+\n+int stmvl53lx_setup(struct stmvl53lx_data *data)\n+{\n+\tint rc = 0;\n+\tVL53LX_DeviceInfo_t dev_info;\n+\n+\tvl53lx_dbgmsg(\"Enter\\n\");\n+\n+\tdata->id = allocate_dev_id();\n+\tif (data->id < 0) {\n+\t\tvl53lx_errmsg(\"too many device already created\");\n+\t\treturn -1;\n+\t}\n+\tvl53lx_dbgmsg(\"Dev id %d is @%p\\n\", data->id, data);\n+\tstmvl53lx_dev_table[data->id] = data;\n+\n+\tmutex_init(&data->work_mutex);\n+\n+\tINIT_DELAYED_WORK(&data->dwork, stmvl53lx_work_handler);\n+\tdata->force_device_on_en = force_device_on_en_default;\n+\tdata->reset_state = 1;\n+\tdata->is_calibrating = false;\n+\tdata->last_error = VL53LX_ERROR_NONE;\n+\tdata->is_device_remove = false;\n+\n+\trc = stmvl53lx_module_func_tbl.power_up(data->client_object);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"%d,error rc %d\\n\", __LINE__, rc);\n+\t\tgoto exit_func_end;\n+\t}\n+\n+\trc = reset_release(data);\n+\tif (rc)\n+\t\tgoto exit_func_end;\n+\n+\trc = stmvl53lx_input_setup(data);\n+\tif (rc)\n+\t\tgoto exit_func_end;\n+\n+\tINIT_LIST_HEAD(&data->simple_data_reader_list);\n+\tINIT_LIST_HEAD(&data->mz_data_reader_list);\n+\tinit_waitqueue_head(&data->waiter_for_data);\n+\tdata->is_data_valid = false;\n+\n+\trc = sysfs_create_group(&data->input_dev_ps->dev.kobj, &stmvl53lx_attr_group);\n+\tif (rc) {\n+\t\trc = -ENOMEM;\n+\t\tvl53lx_errmsg(\"%d error:%d\\n\", __LINE__, rc);\n+\t\tgoto exit_unregister_dev_ps;\n+\t}\n+\trc = sysfs_create_bin_file(&data->input_dev_ps->dev.kobj,\n+\t\t&stmvl53lx_calib_data_attr);\n+\tif (rc) {\n+\t\trc = -ENOMEM;\n+\t\tvl53lx_errmsg(\"%d error:%d\\n\", __LINE__, rc);\n+\t\tgoto exit_unregister_dev_ps;\n+\t}\n+\tdata->enable_sensor = 0;\n+\tdata->poll_delay_ms = STMVL53LX_CFG_POLL_DELAY_MS;\n+\tdata->timing_budget = STMVL53LX_CFG_TIMING_BUDGET_US;\n+\tdata->distance_mode = STMVL53LX_CFG_DEFAULT_DISTANCE_MODE;\n+\tdata->crosstalk_enable = STMVL53LX_CFG_DEFAULT_CROSSTALK_ENABLE;\n+\tdata->offset_correction_mode = STMVL53LX_CFG_DEFAULT_OFFSET_CORRECTION_MODE;\n+\tdata->smudge_correction_mode = STMVL53LX_CFG_DEFAULT_SMUDGE_CORRECTION_MODE;\n+\tdata->is_xtalk_value_changed = false;\n+\tdata->is_delay_allowed = true;\n+\n+\trc = VL53LX_DataInit(&data->stdev);\n+\tdata->is_delay_allowed = false;\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"VL53LX_DataInit %d\\n\", rc);\n+\t\tgoto exit_unregister_dev_ps;\n+\t}\n+\n+\trc = VL53LX_GetUserROI(&data->stdev, &(data->roi_cfg));\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"VL53LX_GetUserROI %d\\n\", rc);\n+\t\tgoto exit_unregister_dev_ps;\n+\t}\n+\n+\trc = VL53LX_GetDeviceInfo(&data->stdev, &dev_info);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"VL53LX_GetDeviceInfo %d\\n\", rc);\n+\t\tgoto exit_unregister_dev_ps;\n+\t}\n+\tvl53lx_errmsg(\"device type %x\\n\", dev_info.ProductType);\n+\n+\trc = VL53LX_GetOpticalCenter(&data->stdev, &data->optical_offset_x, &data->optical_offset_y);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"VL53LX_GetOpticalCenter %d\\n\", rc);\n+\t\tgoto exit_unregister_dev_ps;\n+\t}\n+\n+\trc = setup_tunings(data);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"setup_tunings %d\\n\", rc);\n+\t\tgoto exit_unregister_dev_ps;\n+\t}\n+\n+\tdata->poll_mode = 0;\n+\trc = stmvl53lx_module_func_tbl.start_intr(data->client_object, &data->poll_mode);\n+\tif (rc < 0) {\n+\t\tvl53lx_errmsg(\"can't start no  intr\\n\");\n+\t\tgoto exit_unregister_dev_ps;\n+\t}\n+\n+\tdata->is_first_irq = true;\n+\tdata->is_first_start_done = false;\n+\tdata->is_delay_allowed = false;\n+\n+\tdata->miscdev.minor = MISC_DYNAMIC_MINOR;\n+\tif (data->id == 0)\n+\t\tstrcpy(data->name, VL53LX_MISC_DEV_NAME);\n+\telse\n+\t\tsprintf(data->name, \"%s%d\", VL53LX_MISC_DEV_NAME, data->id);\n+\n+\tdata->miscdev.name = data->name;\n+\tdata->miscdev.fops = &stmvl53lx_ranging_fops;\n+\tvl53lx_errmsg(\"Misc device registration name:%s\\n\", data->miscdev.name);\n+\trc = misc_register(&data->miscdev);\n+\tif (rc != 0) {\n+\t\tvl53lx_errmsg(\"misc dev reg fail\\n\");\n+\t\tgoto exit_unregister_dev_ps;\n+\t}\n+\treset_hold(data);\n+\treturn 0;\n+\n+exit_unregister_dev_ps:\n+\tsysfs_remove_bin_file(&data->input_dev_ps->dev.kobj,\n+\t\t&stmvl53lx_calib_data_attr);\n+\tsysfs_remove_group(&data->input_dev_ps->dev.kobj,\n+\t\t&stmvl53lx_attr_group);\n+\tinput_unregister_device(data->input_dev_ps);\n+\n+exit_func_end:\n+\treturn rc;\n+}\n+\n+static int stmvl53lx_parse_tree(struct device *dev, struct i2c_data *i2c_data)\n+{\n+\tstruct i2c_client *client = (struct i2c_client *) i2c_data->client;\n+\tint rc = 0;\n+\tu32 reg;\n+\n+\ti2c_data->vdd = NULL;\n+\ti2c_data->pwren_gpio = -1;\n+\ti2c_data->xsdn_gpio = -1;\n+\ti2c_data->intr_gpio = -1;\n+\ti2c_data->boot_reg = STMVL53LX_SLAVE_ADDR;\n+\tif (force_device) {\n+\t\ti2c_data->xsdn_gpio = xsdn_gpio_nb;\n+\t\ti2c_data->pwren_gpio = pwren_gpio_nb;\n+\t\ti2c_data->intr_gpio = intr_gpio_nb;\n+\t\tclient->addr = i2c_addr_nb;\n+\t} else if (dev->of_node) {\n+\t\ti2c_data->vdd = devm_regulator_get_optional(dev, \"vdd\");\n+\t\tif (IS_ERR(i2c_data->vdd) || i2c_data->vdd == NULL) {\n+\t\t\ti2c_data->vdd = NULL;\n+\t\t\ti2c_data->pwren_gpio = of_get_named_gpio(dev->of_node, \"pwren-gpio\", 0);\n+\t\t\tif (i2c_data->pwren_gpio < 0) {\n+\t\t\t\ti2c_data->pwren_gpio = -1;\n+\t\t\t\tvl53lx_wanrmsg(\"no regulator, nor power gpio => power ctrl disabled\");\n+\t\t\t}\n+\t\t}\n+\n+\t\trc = of_property_read_u32_array(dev->of_node, \"reg\", &reg, 1);\n+\t\tif (rc) {\n+\t\t\tvl53lx_wanrmsg(\"Unable to find reg %d 0x%x\", rc, i2c_addr_nb);\n+\t\t\treg = i2c_addr_nb;\n+\t\t}\n+\t\tclient->addr = reg;\n+\n+\t\ti2c_data->xsdn_gpio = of_get_named_gpio(dev->of_node, \"xsdn-gpio\", 0);\n+\t\tif (i2c_data->xsdn_gpio < 0) {\n+\t\t\tvl53lx_wanrmsg(\"Unable to find xsdn-gpio %d %d\", rc, i2c_data->xsdn_gpio);\n+\t\t\ti2c_data->xsdn_gpio = -1;\n+\t\t}\n+\n+\t\ti2c_data->intr_gpio = of_get_named_gpio(dev->of_node, \"intr-gpio\", 0);\n+\t\tif (i2c_data->intr_gpio < 0) {\n+\t\t\tvl53lx_wanrmsg(\"Unable to find intr-gpio %d %d\", rc, i2c_data->intr_gpio);\n+\t\t\ti2c_data->intr_gpio = -1;\n+\t\t}\n+\n+\t\trc = of_property_read_u32_array(dev->of_node, \"boot-reg\", &i2c_data->boot_reg, 1);\n+\t\tif (rc) {\n+\t\t\tvl53lx_wanrmsg(\"Unable to find boot-reg %d %d\", rc, i2c_data->boot_reg);\n+\t\t\ti2c_data->boot_reg = STMVL53LX_SLAVE_ADDR;\n+\t\t}\n+\t}\n+\n+\trc = get_xsdn(dev, i2c_data);\n+\tif (rc)\n+\t\tgoto no_xsdn;\n+\trc = get_pwren(dev, i2c_data);\n+\tif (rc)\n+\t\tgoto no_pwren;\n+\trc = get_intr(dev, i2c_data);\n+\tif (rc)\n+\t\tgoto no_intr;\n+\n+\treturn rc;\n+\n+no_intr:\n+\tput_intr(i2c_data);\n+no_pwren:\n+\tif (i2c_data->vdd) {\n+\t\tregulator_put(i2c_data->vdd);\n+\t\ti2c_data->vdd = NULL;\n+\t}\n+\tput_pwren(i2c_data);\n+no_xsdn:\n+\tput_xsdn(i2c_data);\n+\treturn rc;\n+}\n+\n+static void stmvl53lx_release_gpios(struct i2c_data *i2c_data)\n+{\n+\tput_xsdn(i2c_data);\n+\tif (i2c_data->vdd) {\n+\t\tregulator_put(i2c_data->vdd);\n+\t\ti2c_data->vdd = NULL;\n+\t}\n+\tput_pwren(i2c_data);\n+\tput_intr(i2c_data);\n+}\n+\n+void stmvl53lx_cleanup(struct stmvl53lx_data *data)\n+{\n+\tint rc = 0;\n+\n+\tvl53lx_dbgmsg(\"enter\\n\");\n+\trc = _ctrl_stop(data);\n+\tif (rc < 0)\n+\t\tvl53lx_errmsg(\"stop failed %d aborting anyway\\n\", rc);\n+\n+\tif (data->input_dev_ps) {\n+\t\tvl53lx_dbgmsg(\"to remove sysfs group\\n\");\n+\t\tsysfs_remove_group(&data->input_dev_ps->dev.kobj,\n+\t\t\t\t&stmvl53lx_attr_group);\n+\t\tsysfs_remove_bin_file(&data->input_dev_ps->dev.kobj,\n+\t\t\t\t&stmvl53lx_calib_data_attr);\n+\n+\t\tvl53lx_dbgmsg(\"to unregister input dev\\n\");\n+\t\tinput_unregister_device(data->input_dev_ps);\n+\t}\n+\n+\tif (!IS_ERR(data->miscdev.this_device) &&\n+\t\t\tdata->miscdev.this_device != NULL) {\n+\t\tvl53lx_dbgmsg(\"to unregister misc dev\\n\");\n+\t\tmisc_deregister(&data->miscdev);\n+\t}\n+\n+\tdata->force_device_on_en = false;\n+\treset_hold(data);\n+\tstmvl53lx_module_func_tbl.power_down(data->client_object);\n+\tvl53lx_dbgmsg(\"done\\n\");\n+\tdeallocate_dev_id(data->id);\n+\tdata->is_device_remove = true;\n+}\n+\n+static int stmvl53lx_probe(struct i2c_client *client)\n+{\n+\tint rc = 0;\n+\tstruct stmvl53lx_data *vl53lx_data = NULL;\n+\tstruct i2c_data *i2c_data = NULL;\n+\n+\tvl53lx_dbgmsg(\"Enter %s : 0x%02x\\n\", client->name, client->addr);\n+\n+\tif (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE)) {\n+\t\trc = -EIO;\n+\t\treturn rc;\n+\t}\n+\n+\tvl53lx_data = kzalloc(sizeof(struct stmvl53lx_data), GFP_KERNEL);\n+\tif (!vl53lx_data) {\n+\t\trc = -ENOMEM;\n+\t\treturn rc;\n+\t}\n+\tif (vl53lx_data) {\n+\t\tvl53lx_data->client_object = kzalloc(sizeof(struct i2c_data), GFP_KERNEL);\n+\t\tif (!vl53lx_data)\n+\t\t\tgoto done_freemem;\n+\t\ti2c_data = (struct i2c_data *)vl53lx_data->client_object;\n+\t}\n+\n+\ti2c_data->client = client;\n+\ti2c_data->vl53lx_data = vl53lx_data;\n+\ti2c_data->irq = -1;\n+\n+\trc = stmvl53lx_parse_tree(&i2c_data->client->dev, i2c_data);\n+\tif (rc)\n+\t\tgoto done_freemem;\n+\n+\ti2c_set_clientdata(client, vl53lx_data);\n+\n+\trc = stmvl53lx_setup(vl53lx_data);\n+\tif (rc)\n+\t\tgoto release_gpios;\n+\tvl53lx_dbgmsg(\"End\\n\");\n+\n+\tkref_init(&i2c_data->ref);\n+\n+\treturn rc;\n+\n+release_gpios:\n+\tstmvl53lx_release_gpios(i2c_data);\n+\n+done_freemem:\n+\tkfree(vl53lx_data);\n+\tkfree(i2c_data);\n+\n+\treturn -1;\n+}\n+\n+static void stmvl53lx_remove(struct i2c_client *client)\n+{\n+\tstruct stmvl53lx_data *data = i2c_get_clientdata(client);\n+\tstruct i2c_data *i2c_data = (struct i2c_data *)data->client_object;\n+\n+\tvl53lx_dbgmsg(\"Enter\\n\");\n+\tmutex_lock(&data->work_mutex);\n+\tstmvl53lx_cleanup(data);\n+\n+\tstmvl53lx_release_gpios(i2c_data);\n+\n+\tmutex_unlock(&data->work_mutex);\n+\n+\tstmvl53lx_put(data->client_object);\n+\n+\tvl53lx_dbgmsg(\"End\\n\");\n+\n+\treturn;\n+}\n+\n+#ifdef CONFIG_PM_SLEEP\n+\n+void stmvl53lx_pm_suspend_stop(struct stmvl53lx_data *data)\n+{\n+\tint rc = 0;\n+\n+\tvl53lx_dbgmsg(\"Enter\\n\");\n+\n+\trc = _ctrl_stop(data);\n+\tif (rc < 0)\n+\t\tvl53lx_errmsg(\"stop failed %d aborting anyway\\n\", rc);\n+\n+\tvl53lx_dbgmsg(\"done\\n\");\n+}\n+\n+static int stmvl53lx_suspend(struct device *dev)\n+{\n+\tstruct stmvl53lx_data *data = i2c_get_clientdata(to_i2c_client(dev));\n+\n+\tvl53lx_dbgmsg(\"Enter\\n\");\n+\tmutex_lock(&data->work_mutex);\n+\n+\tstmvl53lx_pm_suspend_stop(data);\n+\n+\tmutex_unlock(&data->work_mutex);\n+\n+\tvl53lx_dbgmsg(\"End\\n\");\n+\n+\treturn 0;\n+}\n+\n+static int stmvl53lx_resume(struct device *dev)\n+{\n+#if 0\n+\tstruct stmvl53lx_data *data = i2c_get_clientdata(to_i2c_client(dev));\n+\n+\tvl53lx_dbgmsg(\"Enter\\n\");\n+\n+\tmutex_lock(&data->work_mutex);\n+\n+\t/* do nothing user will restart measurements */\n+\n+\tmutex_unlock(&data->work_mutex);\n+\n+\tvl53lx_dbgmsg(\"End\\n\");\n+#else\n+\tvl53lx_dbgmsg(\"Enter\\n\");\n+\tvl53lx_dbgmsg(\"End\\n\");\n+#endif\n+\treturn 0;\n+}\n+#endif\n+\n+static SIMPLE_DEV_PM_OPS(stmvl53lx_pm_ops, stmvl53lx_suspend, stmvl53lx_resume);\n+\n+static const struct i2c_device_id stmvl53lx_id[] = {\n+\t{ STMVL53LX_DRV_NAME, 0 },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(i2c, stmvl53lx_id);\n+\n+static const struct of_device_id st_stmvl53lx_dt_match[] = {\n+\t{ .compatible = \"st,vl53l4cx\", },\n+\t{ },\n+};\n+\n+static struct i2c_driver stmvl53lx_driver = {\n+\t.driver = {\n+\t\t.name\t= STMVL53LX_DRV_NAME,\n+\t\t.owner\t= THIS_MODULE,\n+\t\t.of_match_table = st_stmvl53lx_dt_match,\n+\t\t.pm\t= &stmvl53lx_pm_ops,\n+\t},\n+\t.probe\t= stmvl53lx_probe,\n+\t.remove\t= stmvl53lx_remove,\n+\t.id_table = stmvl53lx_id,\n+\n+};\n+\n+static int insert_device(void)\n+{\n+\tint ret = 0;\n+\tstruct i2c_adapter *adapter;\n+\tstruct i2c_board_info info = {\n+\t\t.type = \"stmvl53lx\",\n+\t\t.addr = STMVL53LX_SLAVE_ADDR,\n+\t};\n+\n+\tmemset(&info, 0, sizeof(info));\n+\tstrcpy(info.type, \"stmvl53lx\");\n+\tinfo.addr = STMVL53LX_SLAVE_ADDR;\n+\tadapter = i2c_get_adapter(adapter_nb);\n+\tif (!adapter) {\n+\t\tret = -EINVAL;\n+\t\tgoto done;\n+\t}\n+\n+\tstm_test_i2c_client = i2c_new_client_device(adapter, &info);\n+\tif (!stm_test_i2c_client)\n+\t\tret = -EINVAL;\n+\n+done:\n+\treturn ret;\n+}\n+\n+static int __init stmvl53lx_init(void)\n+{\n+\tint rc = -1;\n+\n+\tvl53lx_dbgmsg(\"Enter\\n\");\n+\n+\trc = stmvl53lx_module_func_tbl.init();\n+\n+\tvl53lx_dbgmsg(\"End %d\\n\", rc);\n+\n+\treturn rc;\n+}\n+\n+static void __exit stmvl53lx_exit(void)\n+{\n+\tvl53lx_dbgmsg(\"Enter\\n\");\n+\tstmvl53lx_module_func_tbl.deinit(NULL);\n+\tif (stmvl53lx_module_func_tbl.clean_up != NULL)\n+\t\tstmvl53lx_module_func_tbl.clean_up();\n+\tvl53lx_dbgmsg(\"End\\n\");\n+}\n+\n+int stmvl53lx_init_i2c(void)\n+{\n+\tint ret = 0;\n+\n+\tvl53lx_dbgmsg(\"Enter\\n\");\n+\n+\tret = i2c_add_driver(&stmvl53lx_driver);\n+\tif (ret)\n+\t\tvl53lx_errmsg(\"%d erro ret:%d\\n\", __LINE__, ret);\n+\n+\tif (!ret && force_device)\n+\t\tret = insert_device();\n+\n+\tif (ret)\n+\t\ti2c_del_driver(&stmvl53lx_driver);\n+\n+\tvl53lx_dbgmsg(\"End with rc:%d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+void stmvl53lx_exit_i2c(void *i2c_object)\n+{\n+\tvl53lx_dbgmsg(\"Enter\\n\");\n+\ti2c_del_driver(&stmvl53lx_driver);\n+\tvl53lx_dbgmsg(\"End\\n\");\n+}\n+\n+int stmvl53lx_power_up_i2c(void *object)\n+{\n+\tint rc = 0;\n+\tstruct i2c_data *data = (struct i2c_data *) object;\n+\n+\tvl53lx_dbgmsg(\"Enter\\n\");\n+\n+\tif (data->vdd) {\n+\t\trc = regulator_enable(data->vdd);\n+\t\tif (rc) {\n+\t\t\tvl53lx_errmsg(\"fail to turn on regulator\");\n+\t\t\treturn rc;\n+\t\t}\n+\t} else if (data->pwren_gpio != -1) {\n+\t\tgpio_set_value(data->pwren_gpio, 1);\n+\t\tvl53lx_info(\"slow power on\");\n+\t} else\n+\t\tvl53lx_wanrmsg(\"no power control\");\n+\n+\treturn rc;\n+}\n+\n+int stmvl53lx_power_down_i2c(void *i2c_object)\n+{\n+\tstruct i2c_data *data = (struct i2c_data *) i2c_object;\n+\tint rc = 0;\n+\n+\tvl53lx_dbgmsg(\"Enter\\n\");\n+\n+\tif (data->vdd) {\n+\t\trc = regulator_disable(data->vdd);\n+\t\tif (rc)\n+\t\t\tvl53lx_errmsg(\"reg disable failed. rc=%d\\n\",\n+\t\t\t\trc);\n+\t} else if (data->pwren_gpio != -1) {\n+\t\tgpio_set_value(data->pwren_gpio, 0);\n+\t}\n+\tvl53lx_dbgmsg(\"power off\");\n+\n+\tvl53lx_dbgmsg(\"End\\n\");\n+\n+\treturn rc;\n+}\n+\n+int stmvl53lx_reset_release_i2c(void *i2c_object)\n+{\n+\tint rc;\n+\tstruct i2c_data *data = (struct i2c_data *) i2c_object;\n+\n+\tvl53lx_dbgmsg(\"Enter\\n\");\n+\n+\trc = release_reset(data);\n+\tif (rc)\n+\t\tgoto error;\n+\n+\tdata->vl53lx_data->is_delay_allowed = true;\n+\trc = VL53LX_WaitDeviceBooted(&data->vl53lx_data->stdev);\n+\tdata->vl53lx_data->is_delay_allowed = false;\n+\tif (rc) {\n+\t\tgpio_set_value(data->xsdn_gpio, 0);\n+\t\tvl53lx_errmsg(\"boot fail with error %d\", rc);\n+\t\tdata->vl53lx_data->last_error = rc;\n+\t\trc = -EIO;\n+\t}\n+\n+error:\n+\tvl53lx_dbgmsg(\"End\\n\");\n+\treturn rc;\n+}\n+\n+int stmvl53lx_reset_hold_i2c(void *i2c_object)\n+{\n+\tstruct i2c_data *data = (struct i2c_data *) i2c_object;\n+\n+\tvl53lx_dbgmsg(\"Enter\\n\");\n+\n+\tgpio_set_value(data->xsdn_gpio, 0);\n+\n+\tvl53lx_dbgmsg(\"End\\n\");\n+\treturn 0;\n+}\n+\n+void stmvl53lx_clean_up_i2c(void)\n+{\n+\tif (stm_test_i2c_client) {\n+\t\tvl53lx_dbgmsg(\"to unregister i2c client\\n\");\n+\t\ti2c_unregister_device(stm_test_i2c_client);\n+\t}\n+}\n+\n+int stmvl53lx_start_intr(void *object, int *poll_mode)\n+{\n+\tstruct i2c_data *i2c_data;\n+\tint rc;\n+\n+\ti2c_data = (struct i2c_data *)object;\n+\tif (i2c_data->irq < 0) {\n+\t\t*poll_mode = -1;\n+\t\treturn 0;\n+\t}\n+\n+\ti2c_data->msg_flag.unhandled_irq_vec = 0;\n+\tif (i2c_data->io_flag.intr_started) {\n+\t\t*poll_mode = 0;\n+\t\treturn 0;\n+\t}\n+\n+\tvl53lx_dbgmsg(\"to register_irq:%d\\n\", i2c_data->irq);\n+\trc = request_threaded_irq(i2c_data->irq, NULL, stmvl53lx_irq_handler_i2c, IRQF_TRIGGER_FALLING|IRQF_ONESHOT, \"vl53lx_interrupt\", (void *)i2c_data);\n+\tif (rc) {\n+\t\tvl53lx_errmsg(\"fail to req threaded irq rc=%d\\n\", rc);\n+\t\t*poll_mode = 0;\n+\t} else {\n+\t\tvl53lx_dbgmsg(\"irq %d now handled\\n\", i2c_data->irq);\n+\t\ti2c_data->io_flag.intr_started = 1;\n+\t\t*poll_mode = 0;\n+\t}\n+\treturn rc;\n+}\n+\n+void *stmvl53lx_get(void *object)\n+{\n+\tstruct i2c_data *data = (struct i2c_data *) object;\n+\n+\tvl53lx_dbgmsg(\"Enter\\n\");\n+\tkref_get(&data->ref);\n+\tvl53lx_dbgmsg(\"End\\n\");\n+\n+\treturn object;\n+}\n+\n+void stmvl53lx_put(void *object)\n+{\n+\tstruct i2c_data *data = (struct i2c_data *) object;\n+\n+\tvl53lx_dbgmsg(\"Enter\\n\");\n+\tkref_put(&data->ref, memory_release);\n+\tvl53lx_dbgmsg(\"End\\n\");\n+}\n+\n+static struct stmvl53lx_module_fn_t stmvl53lx_module_func_tbl = {\n+\t.init = stmvl53lx_init_i2c,\n+\t.deinit = stmvl53lx_exit_i2c,\n+\t.power_up = stmvl53lx_power_up_i2c,\n+\t.power_down = stmvl53lx_power_down_i2c,\n+\t.reset_release = stmvl53lx_reset_release_i2c,\n+\t.reset_hold = stmvl53lx_reset_hold_i2c,\n+\t.clean_up = stmvl53lx_clean_up_i2c,\n+\t.start_intr = stmvl53lx_start_intr,\n+\t.get = stmvl53lx_get,\n+\t.put = stmvl53lx_put,\n+};\n+\n+module_init(stmvl53lx_init);\n+module_exit(stmvl53lx_exit);\n+\n+MODULE_AUTHOR(\"Song Qiang <songqiang1304521@gmail.com>\");\n+MODULE_DESCRIPTION(\"ST vl53l4cx ToF ranging sensor driver\");\n+MODULE_LICENSE(\"GPL v2\");\n",
    "prefixes": []
}