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GET /api/patches/2194131/?format=api
{ "id": 2194131, "url": "http://patchwork.ozlabs.org/api/patches/2194131/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260206214448.22008-11-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260206214448.22008-11-philmd@linaro.org>", "list_archive_url": null, "date": "2026-02-06T21:44:28", "name": "[PULL,10/30] target/s390x: Expand tcg_gen_qemu_ld/st_tl() as 64-bit target", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5f8a0ebb00cce77030018c06071f9ddf2c980840", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260206214448.22008-11-philmd@linaro.org/mbox/", "series": [ { "id": 491339, "url": "http://patchwork.ozlabs.org/api/series/491339/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491339", "date": "2026-02-06T21:44:19", "name": "[PULL,01/30] riscv64/test_boston.py: fix intermitent test timeout", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491339/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194131/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194131/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n 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helo=mail-wm1-x330.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The s390x target is a 64-bit one, so we have these expansions\nin the \"tcg/tcg-op.h\" header:\n\n . tcg_gen_qemu_ld_tl() -> tcg_gen_qemu_ld_i64()\n . tcg_gen_qemu_st_tl() -> tcg_gen_qemu_st_i64()\n\nUse the expanded form which is more explicit when a target\nisn't built for different words size.\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nReviewed-by: Thomas Huth <thuth@redhat.com>\nMessage-Id: <20260206181953.18683-10-philmd@linaro.org>\n---\n target/s390x/tcg/translate.c | 54 ++++++++++++++++++------------------\n 1 file changed, 27 insertions(+), 27 deletions(-)", "diff": "diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c\nindex 437f5a4aeb7..4dabd49840f 100644\n--- a/target/s390x/tcg/translate.c\n+++ b/target/s390x/tcg/translate.c\n@@ -1259,7 +1259,7 @@ static DisasJumpType op_asi(DisasContext *s, DisasOps *o)\n \n o->in1 = tcg_temp_new_i64();\n if (non_atomic) {\n- tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);\n+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), s->insn->data);\n } else {\n /* Perform the atomic addition in memory. */\n tcg_gen_atomic_fetch_add_i64(o->in1, o->addr1, o->in2, get_mem_index(s),\n@@ -1270,7 +1270,7 @@ static DisasJumpType op_asi(DisasContext *s, DisasOps *o)\n tcg_gen_add_i64(o->out, o->in1, o->in2);\n \n if (non_atomic) {\n- tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);\n+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), s->insn->data);\n }\n return DISAS_NEXT;\n }\n@@ -1281,7 +1281,7 @@ static DisasJumpType op_asiu64(DisasContext *s, DisasOps *o)\n \n o->in1 = tcg_temp_new_i64();\n if (non_atomic) {\n- tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);\n+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), s->insn->data);\n } else {\n /* Perform the atomic addition in memory. */\n tcg_gen_atomic_fetch_add_i64(o->in1, o->addr1, o->in2, get_mem_index(s),\n@@ -1293,7 +1293,7 @@ static DisasJumpType op_asiu64(DisasContext *s, DisasOps *o)\n tcg_gen_add2_i64(o->out, cc_src, o->in1, cc_src, o->in2, cc_src);\n \n if (non_atomic) {\n- tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);\n+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), s->insn->data);\n }\n return DISAS_NEXT;\n }\n@@ -1374,7 +1374,7 @@ static DisasJumpType op_ni(DisasContext *s, DisasOps *o)\n o->in1 = tcg_temp_new_i64();\n \n if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {\n- tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);\n+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), s->insn->data);\n } else {\n /* Perform the atomic operation in memory. */\n tcg_gen_atomic_fetch_and_i64(o->in1, o->addr1, o->in2, get_mem_index(s),\n@@ -1385,7 +1385,7 @@ static DisasJumpType op_ni(DisasContext *s, DisasOps *o)\n tcg_gen_and_i64(o->out, o->in1, o->in2);\n \n if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {\n- tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);\n+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), s->insn->data);\n }\n return DISAS_NEXT;\n }\n@@ -1917,8 +1917,8 @@ static DisasJumpType op_clc(DisasContext *s, DisasOps *o)\n mop = ctz32(l + 1) | MO_BE;\n /* Do not update cc_src yet: loading cc_dst may cause an exception. */\n src = tcg_temp_new_i64();\n- tcg_gen_qemu_ld_tl(src, o->addr1, get_mem_index(s), mop);\n- tcg_gen_qemu_ld_tl(cc_dst, o->in2, get_mem_index(s), mop);\n+ tcg_gen_qemu_ld_i64(src, o->addr1, get_mem_index(s), mop);\n+ tcg_gen_qemu_ld_i64(cc_dst, o->in2, get_mem_index(s), mop);\n gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, src, cc_dst);\n return DISAS_NEXT;\n default:\n@@ -2747,15 +2747,15 @@ static DisasJumpType op_ld16u(DisasContext *s, DisasOps *o)\n \n static DisasJumpType op_ld32s(DisasContext *s, DisasOps *o)\n {\n- tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s),\n- MO_BESL | s->insn->data);\n+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s),\n+ MO_BESL | s->insn->data);\n return DISAS_NEXT;\n }\n \n static DisasJumpType op_ld32u(DisasContext *s, DisasOps *o)\n {\n- tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s),\n- MO_BEUL | s->insn->data);\n+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s),\n+ MO_BEUL | s->insn->data);\n return DISAS_NEXT;\n }\n \n@@ -3087,7 +3087,7 @@ static DisasJumpType op_lpq(DisasContext *s, DisasOps *o)\n #ifndef CONFIG_USER_ONLY\n static DisasJumpType op_lura(DisasContext *s, DisasOps *o)\n {\n- tcg_gen_qemu_ld_tl(o->out, o->in2, MMU_REAL_IDX, s->insn->data);\n+ tcg_gen_qemu_ld_i64(o->out, o->in2, MMU_REAL_IDX, s->insn->data);\n return DISAS_NEXT;\n }\n #endif\n@@ -3506,7 +3506,7 @@ static DisasJumpType op_oi(DisasContext *s, DisasOps *o)\n o->in1 = tcg_temp_new_i64();\n \n if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {\n- tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);\n+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), s->insn->data);\n } else {\n /* Perform the atomic operation in memory. */\n tcg_gen_atomic_fetch_or_i64(o->in1, o->addr1, o->in2, get_mem_index(s),\n@@ -3517,7 +3517,7 @@ static DisasJumpType op_oi(DisasContext *s, DisasOps *o)\n tcg_gen_or_i64(o->out, o->in1, o->in2);\n \n if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {\n- tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);\n+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), s->insn->data);\n }\n return DISAS_NEXT;\n }\n@@ -4334,7 +4334,7 @@ static DisasJumpType op_stnosm(DisasContext *s, DisasOps *o)\n \n static DisasJumpType op_stura(DisasContext *s, DisasOps *o)\n {\n- tcg_gen_qemu_st_tl(o->in1, o->in2, MMU_REAL_IDX, s->insn->data);\n+ tcg_gen_qemu_st_i64(o->in1, o->in2, MMU_REAL_IDX, s->insn->data);\n \n if (s->base.tb->flags & FLAG_MASK_PER_STORE_REAL) {\n update_cc_op(s);\n@@ -4367,8 +4367,8 @@ static DisasJumpType op_st16(DisasContext *s, DisasOps *o)\n \n static DisasJumpType op_st32(DisasContext *s, DisasOps *o)\n {\n- tcg_gen_qemu_st_tl(o->in1, o->in2, get_mem_index(s),\n- MO_BEUL | s->insn->data);\n+ tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s),\n+ MO_BEUL | s->insn->data);\n return DISAS_NEXT;\n }\n \n@@ -4836,7 +4836,7 @@ static DisasJumpType op_xi(DisasContext *s, DisasOps *o)\n o->in1 = tcg_temp_new_i64();\n \n if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {\n- tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);\n+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), s->insn->data);\n } else {\n /* Perform the atomic operation in memory. */\n tcg_gen_atomic_fetch_xor_i64(o->in1, o->addr1, o->in2, get_mem_index(s),\n@@ -4847,7 +4847,7 @@ static DisasJumpType op_xi(DisasContext *s, DisasOps *o)\n tcg_gen_xor_i64(o->out, o->in1, o->in2);\n \n if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {\n- tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);\n+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), s->insn->data);\n }\n return DISAS_NEXT;\n }\n@@ -5291,7 +5291,7 @@ static void wout_m1_16(DisasContext *s, DisasOps *o)\n #ifndef CONFIG_USER_ONLY\n static void wout_m1_16a(DisasContext *s, DisasOps *o)\n {\n- tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_BEUW | MO_ALIGN);\n+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUW | MO_ALIGN);\n }\n #define SPEC_wout_m1_16a 0\n #endif\n@@ -5305,7 +5305,7 @@ static void wout_m1_32(DisasContext *s, DisasOps *o)\n #ifndef CONFIG_USER_ONLY\n static void wout_m1_32a(DisasContext *s, DisasOps *o)\n {\n- tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_BEUL | MO_ALIGN);\n+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUL | MO_ALIGN);\n }\n #define SPEC_wout_m1_32a 0\n #endif\n@@ -5816,7 +5816,7 @@ static void in2_m2_32u(DisasContext *s, DisasOps *o)\n static void in2_m2_32ua(DisasContext *s, DisasOps *o)\n {\n in2_a2(s, o);\n- tcg_gen_qemu_ld_tl(o->in2, o->in2, get_mem_index(s), MO_BEUL | MO_ALIGN);\n+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUL | MO_ALIGN);\n }\n #define SPEC_in2_m2_32ua 0\n #endif\n@@ -5862,16 +5862,16 @@ static void in2_mri2_16u(DisasContext *s, DisasOps *o)\n static void in2_mri2_32s(DisasContext *s, DisasOps *o)\n {\n o->in2 = tcg_temp_new_i64();\n- tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s),\n- MO_BESL | MO_ALIGN);\n+ tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s),\n+ MO_BESL | MO_ALIGN);\n }\n #define SPEC_in2_mri2_32s 0\n \n static void in2_mri2_32u(DisasContext *s, DisasOps *o)\n {\n o->in2 = tcg_temp_new_i64();\n- tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s),\n- MO_BEUL | MO_ALIGN);\n+ tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s),\n+ MO_BEUL | MO_ALIGN);\n }\n #define SPEC_in2_mri2_32u 0\n \n", "prefixes": [ "PULL", "10/30" ] }