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GET /api/patches/2194124/?format=api
{ "id": 2194124, "url": "http://patchwork.ozlabs.org/api/patches/2194124/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260206214448.22008-15-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260206214448.22008-15-philmd@linaro.org>", "list_archive_url": null, "date": "2026-02-06T21:44:32", "name": "[PULL,14/30] target/sparc: Replace MO_TE -> MO_BE", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a7a34291f01597edf32cb20bc7e7fb1661d1c37d", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260206214448.22008-15-philmd@linaro.org/mbox/", "series": [ { "id": 491339, "url": "http://patchwork.ozlabs.org/api/series/491339/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491339", "date": "2026-02-06T21:44:19", "name": "[PULL,01/30] riscv64/test_boston.py: fix intermitent test timeout", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491339/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194124/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194124/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=CRZw3Xz8;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32f;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "We only build the SPARC targets using big endianness order,\ntherefore the MO_TE definitions expand to the big endian\none. Use the latter which is more explicit.\n\nMechanical change running:\n\n $ sed -i -e s/MO_TE/MO_BE/ \\\n $(git grep -wl MO_TE target/sparc/)\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nReviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-Id: <20260203230054.23667-5-philmd@linaro.org>\n---\n target/sparc/translate.c | 58 ++++++++++++++++++++--------------------\n 1 file changed, 29 insertions(+), 29 deletions(-)", "diff": "diff --git a/target/sparc/translate.c b/target/sparc/translate.c\nindex 1a7e5cc3d73..57b50ff8b9a 100644\n--- a/target/sparc/translate.c\n+++ b/target/sparc/translate.c\n@@ -1764,7 +1764,7 @@ static DisasASI resolve_asi(DisasContext *dc, int asi, MemOp memop)\n case ASI_FL16_SL:\n case ASI_FL16_P:\n case ASI_FL16_PL:\n- memop = MO_TEUW;\n+ memop = MO_BEUW;\n type = GET_ASI_SHORT;\n break;\n }\n@@ -2215,7 +2215,7 @@ static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)\n * byte swapped. We perform one 128-bit LE load, so must swap\n * the order of the writebacks.\n */\n- if ((mop & MO_BSWAP) == MO_TE) {\n+ if ((mop & MO_BSWAP) == MO_BE) {\n tcg_gen_extr_i128_i64(lo, hi, t);\n } else {\n tcg_gen_extr_i128_i64(hi, lo, t);\n@@ -2235,7 +2235,7 @@ static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)\n /* Note that LE ldda acts as if each 32-bit register\n result is byte swapped. Having just performed one\n 64-bit bswap, we need now to swap the writebacks. */\n- if ((da->memop & MO_BSWAP) == MO_TE) {\n+ if ((da->memop & MO_BSWAP) == MO_BE) {\n tcg_gen_extr_i64_tl(lo, hi, tmp);\n } else {\n tcg_gen_extr_i64_tl(hi, lo, tmp);\n@@ -2252,7 +2252,7 @@ static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)\n gen_helper_ld_code(tmp, tcg_env, addr, tcg_constant_i32(oi));\n \n /* See above. */\n- if ((da->memop & MO_BSWAP) == MO_TE) {\n+ if ((da->memop & MO_BSWAP) == MO_BE) {\n tcg_gen_extr_i64_tl(lo, hi, tmp);\n } else {\n tcg_gen_extr_i64_tl(hi, lo, tmp);\n@@ -2277,7 +2277,7 @@ static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)\n gen_helper_ld_asi(tmp, tcg_env, addr, r_asi, r_mop);\n \n /* See above. */\n- if ((da->memop & MO_BSWAP) == MO_TE) {\n+ if ((da->memop & MO_BSWAP) == MO_BE) {\n tcg_gen_extr_i64_tl(lo, hi, tmp);\n } else {\n tcg_gen_extr_i64_tl(hi, lo, tmp);\n@@ -2310,7 +2310,7 @@ static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)\n * byte swapped. We perform one 128-bit LE store, so must swap\n * the order of the construction.\n */\n- if ((mop & MO_BSWAP) == MO_TE) {\n+ if ((mop & MO_BSWAP) == MO_BE) {\n tcg_gen_concat_i64_i128(t, lo, hi);\n } else {\n tcg_gen_concat_i64_i128(t, hi, lo);\n@@ -2329,7 +2329,7 @@ static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)\n /* Note that LE stda acts as if each 32-bit register result is\n byte swapped. We will perform one 64-bit LE store, so now\n we must swap the order of the construction. */\n- if ((da->memop & MO_BSWAP) == MO_TE) {\n+ if ((da->memop & MO_BSWAP) == MO_BE) {\n tcg_gen_concat_tl_i64(t64, lo, hi);\n } else {\n tcg_gen_concat_tl_i64(t64, hi, lo);\n@@ -2345,7 +2345,7 @@ static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)\n * See comments for GET_ASI_COPY above.\n */\n {\n- MemOp mop = MO_TE | MO_128 | MO_ATOM_IFALIGN_PAIR;\n+ MemOp mop = MO_BE | MO_128 | MO_ATOM_IFALIGN_PAIR;\n TCGv_i64 t8 = tcg_temp_new_i64();\n TCGv_i128 t16 = tcg_temp_new_i128();\n TCGv daddr = tcg_temp_new();\n@@ -2368,7 +2368,7 @@ static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)\n TCGv_i64 t64 = tcg_temp_new_i64();\n \n /* See above. */\n- if ((da->memop & MO_BSWAP) == MO_TE) {\n+ if ((da->memop & MO_BSWAP) == MO_BE) {\n tcg_gen_concat_tl_i64(t64, lo, hi);\n } else {\n tcg_gen_concat_tl_i64(t64, hi, lo);\n@@ -4428,13 +4428,13 @@ static bool do_ld_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop)\n return advance_pc(dc);\n }\n \n-TRANS(LDUW, ALL, do_ld_gpr, a, MO_TEUL)\n+TRANS(LDUW, ALL, do_ld_gpr, a, MO_BEUL)\n TRANS(LDUB, ALL, do_ld_gpr, a, MO_UB)\n-TRANS(LDUH, ALL, do_ld_gpr, a, MO_TEUW)\n+TRANS(LDUH, ALL, do_ld_gpr, a, MO_BEUW)\n TRANS(LDSB, ALL, do_ld_gpr, a, MO_SB)\n-TRANS(LDSH, ALL, do_ld_gpr, a, MO_TESW)\n-TRANS(LDSW, 64, do_ld_gpr, a, MO_TESL)\n-TRANS(LDX, 64, do_ld_gpr, a, MO_TEUQ)\n+TRANS(LDSH, ALL, do_ld_gpr, a, MO_BESW)\n+TRANS(LDSW, 64, do_ld_gpr, a, MO_BESL)\n+TRANS(LDX, 64, do_ld_gpr, a, MO_BEUQ)\n \n static bool do_st_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop)\n {\n@@ -4451,10 +4451,10 @@ static bool do_st_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop)\n return advance_pc(dc);\n }\n \n-TRANS(STW, ALL, do_st_gpr, a, MO_TEUL)\n+TRANS(STW, ALL, do_st_gpr, a, MO_BEUL)\n TRANS(STB, ALL, do_st_gpr, a, MO_UB)\n-TRANS(STH, ALL, do_st_gpr, a, MO_TEUW)\n-TRANS(STX, 64, do_st_gpr, a, MO_TEUQ)\n+TRANS(STH, ALL, do_st_gpr, a, MO_BEUW)\n+TRANS(STX, 64, do_st_gpr, a, MO_BEUQ)\n \n static bool trans_LDD(DisasContext *dc, arg_r_r_ri_asi *a)\n {\n@@ -4468,7 +4468,7 @@ static bool trans_LDD(DisasContext *dc, arg_r_r_ri_asi *a)\n if (addr == NULL) {\n return false;\n }\n- da = resolve_asi(dc, a->asi, MO_TEUQ);\n+ da = resolve_asi(dc, a->asi, MO_BEUQ);\n gen_ldda_asi(dc, &da, addr, a->rd);\n return advance_pc(dc);\n }\n@@ -4485,7 +4485,7 @@ static bool trans_STD(DisasContext *dc, arg_r_r_ri_asi *a)\n if (addr == NULL) {\n return false;\n }\n- da = resolve_asi(dc, a->asi, MO_TEUQ);\n+ da = resolve_asi(dc, a->asi, MO_BEUQ);\n gen_stda_asi(dc, &da, addr, a->rd);\n return advance_pc(dc);\n }\n@@ -4516,7 +4516,7 @@ static bool trans_SWAP(DisasContext *dc, arg_r_r_ri_asi *a)\n if (addr == NULL) {\n return false;\n }\n- da = resolve_asi(dc, a->asi, MO_TEUL);\n+ da = resolve_asi(dc, a->asi, MO_BEUL);\n \n dst = gen_dest_gpr(dc, a->rd);\n src = gen_load_gpr(dc, a->rd);\n@@ -4544,8 +4544,8 @@ static bool do_casa(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop)\n return advance_pc(dc);\n }\n \n-TRANS(CASA, CASA, do_casa, a, MO_TEUL)\n-TRANS(CASXA, 64, do_casa, a, MO_TEUQ)\n+TRANS(CASA, CASA, do_casa, a, MO_BEUL)\n+TRANS(CASXA, 64, do_casa, a, MO_BEUQ)\n \n static bool do_ld_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz)\n {\n@@ -4561,7 +4561,7 @@ static bool do_ld_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz)\n if (sz == MO_128 && gen_trap_float128(dc)) {\n return true;\n }\n- da = resolve_asi(dc, a->asi, MO_TE | sz);\n+ da = resolve_asi(dc, a->asi, MO_BE | sz);\n gen_ldf_asi(dc, &da, sz, addr, a->rd);\n gen_update_fprs_dirty(dc, a->rd);\n return advance_pc(dc);\n@@ -4590,7 +4590,7 @@ static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz)\n if (sz == MO_128 && gen_trap_float128(dc)) {\n return true;\n }\n- da = resolve_asi(dc, a->asi, MO_TE | sz);\n+ da = resolve_asi(dc, a->asi, MO_BE | sz);\n gen_stf_asi(dc, &da, sz, addr, a->rd);\n return advance_pc(dc);\n }\n@@ -4629,7 +4629,7 @@ static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a)\n /* Store the single element from the queue. */\n TCGv_i64 fq = tcg_temp_new_i64();\n tcg_gen_ld_i64(fq, tcg_env, offsetof(CPUSPARCState, fq.d));\n- tcg_gen_qemu_st_i64(fq, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN_4);\n+ tcg_gen_qemu_st_i64(fq, addr, dc->mem_idx, MO_BEUQ | MO_ALIGN_4);\n \n /* Mark the queue empty, transitioning to fp_execute state. */\n tcg_gen_st_i32(tcg_constant_i32(0), tcg_env,\n@@ -4655,7 +4655,7 @@ static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a)\n }\n \n tmp = tcg_temp_new_i32();\n- tcg_gen_qemu_ld_i32(tmp, addr, dc->mem_idx, MO_TEUL | MO_ALIGN);\n+ tcg_gen_qemu_ld_i32(tmp, addr, dc->mem_idx, MO_BEUL | MO_ALIGN);\n \n tcg_gen_extract_i32(cpu_fcc[0], tmp, FSR_FCC0_SHIFT, 2);\n /* LDFSR does not change FCC[1-3]. */\n@@ -4679,7 +4679,7 @@ static bool do_ldxfsr(DisasContext *dc, arg_r_r_ri *a, bool entire)\n }\n \n t64 = tcg_temp_new_i64();\n- tcg_gen_qemu_ld_i64(t64, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN);\n+ tcg_gen_qemu_ld_i64(t64, addr, dc->mem_idx, MO_BEUQ | MO_ALIGN);\n \n lo = tcg_temp_new_i32();\n hi = cpu_fcc[3];\n@@ -4722,8 +4722,8 @@ static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop)\n return advance_pc(dc);\n }\n \n-TRANS(STFSR, ALL, do_stfsr, a, MO_TEUL)\n-TRANS(STXFSR, 64, do_stfsr, a, MO_TEUQ)\n+TRANS(STFSR, ALL, do_stfsr, a, MO_BEUL)\n+TRANS(STXFSR, 64, do_stfsr, a, MO_BEUQ)\n \n static bool do_fc(DisasContext *dc, int rd, int32_t c)\n {\n", "prefixes": [ "PULL", "14/30" ] }