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GET /api/patches/2194104/?format=api
{ "id": 2194104, "url": "http://patchwork.ozlabs.org/api/patches/2194104/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260206205537.2906980-4-hugo@hugovil.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260206205537.2906980-4-hugo@hugovil.com>", "list_archive_url": null, "date": "2026-02-06T20:55:26", "name": "[3/6] arm: dts: imx8mn-var-som-symphony: migrate to OF_UPSTREAM", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "76b082bdf85e1bc9a2f29e5d282f92d50b558d1c", "submitter": { "id": 83028, "url": "http://patchwork.ozlabs.org/api/people/83028/?format=api", "name": "Hugo Villeneuve", "email": "hugo@hugovil.com" }, "delegate": { "id": 151988, "url": "http://patchwork.ozlabs.org/api/users/151988/?format=api", "username": "festevam", "first_name": "Fabio", "last_name": "Estevam", "email": "festevam@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260206205537.2906980-4-hugo@hugovil.com/mbox/", "series": [ { "id": 491333, "url": "http://patchwork.ozlabs.org/api/series/491333/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=491333", "date": "2026-02-06T20:55:23", "name": "Conversion of imx8mn-var-som/imx8mn-var-som-symphony to OF_UPSTREAM and fixes/improvements", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491333/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194104/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194104/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=hugovil.com header.i=@hugovil.com header.a=rsa-sha256\n header.s=x header.b=sdUQmGD9;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=hugovil.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=hugovil.com header.i=@hugovil.com header.b=\"sdUQmGD9\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=hugovil.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=hugo@hugovil.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f75wl3yDCz1xvh\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 07 Feb 2026 07:56:23 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 9277083BE1;\n\tFri, 6 Feb 2026 21:55:51 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 4FB5F83BFE; Fri, 6 Feb 2026 21:55:49 +0100 (CET)", "from mail.hugovil.com (mail.hugovil.com [162.243.120.170])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id BB6BE83642\n for <u-boot@lists.denx.de>; Fri, 6 Feb 2026 21:55:46 +0100 (CET)", "from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:35962\n helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92)\n (envelope-from <hugo@hugovil.com>)\n id 1voSrf-0001FX-Q3; Fri, 06 Feb 2026 15:55:44 -0500" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED,\n SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com\n ; s=x;\n h=Subject:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Cc:To\n :From:subject:date:message-id:reply-to;\n bh=dZ2NfcTkQ59gIxMgqf2a/Y5CTDkJYJHXlyv1v7CAPkg=; b=sdUQmGD9G7JczqAdkh2FQKQqDF\n 3pqgx+FNvO92lddGyf+iCTlkyVUVmYyn2wjJe1UuK/O9JqHOMM21NJ9ckUlWyn6lS3zrQ8bwCafnO\n KD295PeVwc7Y2rTfIFfZQyjzSaD4piPk0Vt8A5L2mne/MnNiJncpynHz0Q7Ou6A59cow=;", "From": "Hugo Villeneuve <hugo@hugovil.com>", "To": "hvilleneuve@dimonoff.com, sbabic@nabladev.com, festevam@gmail.com,\n uboot-imx@nxp.com, Tom Rini <trini@konsulko.com>", "Cc": "u-boot@lists.denx.de,\n\thugo@hugovil.com", "Date": "Fri, 6 Feb 2026 15:55:26 -0500", "Message-ID": "<20260206205537.2906980-4-hugo@hugovil.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260206205537.2906980-1-hugo@hugovil.com>", "References": "<20260206205537.2906980-1-hugo@hugovil.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-SA-Exim-Connect-IP": "70.80.174.168", "X-SA-Exim-Mail-From": "hugo@hugovil.com", "Subject": "[PATCH 3/6] arm: dts: imx8mn-var-som-symphony: migrate to OF_UPSTREAM", "X-SA-Exim-Version": "4.2.1 (built Wed, 08 May 2019 21:11:16 +0000)", "X-SA-Exim-Scanned": "Yes (on mail.hugovil.com)", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Hugo Villeneuve <hvilleneuve@dimonoff.com>\n\nSwitch to OF_UPSTREAM to make use of the upstream device trees.\n\nRemove the now obsolete device tree files:\n- imx8mn-var-som-symphony.dts\n- imx8mn-var-som.dtsi\n\nSigned-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>\n---\n arch/arm/dts/Makefile | 1 -\n arch/arm/dts/imx8mn-var-som-symphony.dts | 236 ----------\n arch/arm/dts/imx8mn-var-som.dtsi | 564 -----------------------\n arch/arm/mach-imx/imx8m/Kconfig | 1 +\n configs/imx8mn_var_som_defconfig | 2 +-\n 5 files changed, 2 insertions(+), 802 deletions(-)\n delete mode 100644 arch/arm/dts/imx8mn-var-som-symphony.dts\n delete mode 100644 arch/arm/dts/imx8mn-var-som.dtsi", "diff": "diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex 3cd762977cb..82ad3035308 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -888,7 +888,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \\\n \timx8mm-mx8menlo.dtb \\\n \timx8mm-phg.dtb \\\n \timx8mq-cm.dtb \\\n-\timx8mn-var-som-symphony.dtb \\\n \timx8mq-mnt-reform2.dtb \\\n \timx8mq-phanbell.dtb \\\n \timx8mp-data-modul-edm-sbc.dtb \\\ndiff --git a/arch/arm/dts/imx8mn-var-som-symphony.dts b/arch/arm/dts/imx8mn-var-som-symphony.dts\ndeleted file mode 100644\nindex 5c8e4e81752..00000000000\n--- a/arch/arm/dts/imx8mn-var-som-symphony.dts\n+++ /dev/null\n@@ -1,236 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright 2019-2020 Variscite Ltd.\n- * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>\n- */\n-\n-/dts-v1/;\n-\n-#include \"imx8mn-var-som.dtsi\"\n-\n-/ {\n-\tmodel = \"Variscite VAR-SOM-MX8MN Symphony evaluation board\";\n-\tcompatible = \"variscite,var-som-mx8mn-symphony\", \"variscite,var-som-mx8mn\", \"fsl,imx8mn\";\n-\n-\treg_usdhc2_vmmc: regulator-usdhc2-vmmc {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;\n-\t\tregulator-name = \"VSD_3V3\";\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tgpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t};\n-\n-\tgpio-keys {\n-\t\tcompatible = \"gpio-keys\";\n-\n-\t\tkey-back {\n-\t\t\tlabel = \"Back\";\n-\t\t\tgpios = <&pca9534 1 GPIO_ACTIVE_LOW>;\n-\t\t\tlinux,code = <KEY_BACK>;\n-\t\t};\n-\n-\t\tkey-home {\n-\t\t\tlabel = \"Home\";\n-\t\t\tgpios = <&pca9534 2 GPIO_ACTIVE_LOW>;\n-\t\t\tlinux,code = <KEY_HOME>;\n-\t\t};\n-\n-\t\tkey-menu {\n-\t\t\tlabel = \"Menu\";\n-\t\t\tgpios = <&pca9534 3 GPIO_ACTIVE_LOW>;\n-\t\t\tlinux,code = <KEY_MENU>;\n-\t\t};\n-\t};\n-\n-\tleds {\n-\t\tcompatible = \"gpio-leds\";\n-\n-\t\tled {\n-\t\t\tlabel = \"Heartbeat\";\n-\t\t\tgpios = <&pca9534 0 GPIO_ACTIVE_LOW>;\n-\t\t\tlinux,default-trigger = \"heartbeat\";\n-\t\t};\n-\t};\n-};\n-\n-&i2c2 {\n-\tclock-frequency = <400000>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_i2c2>;\n-\tstatus = \"okay\";\n-\n-\tpca9534: gpio@20 {\n-\t\tcompatible = \"nxp,pca9534\";\n-\t\treg = <0x20>;\n-\t\tgpio-controller;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_pca9534>;\n-\t\tinterrupt-parent = <&gpio1>;\n-\t\tinterrupts = <7 IRQ_TYPE_EDGE_FALLING>;\n-\t\t#gpio-cells = <2>;\n-\t\twakeup-source;\n-\n-\t\t/* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */\n-\t\tusb3-sata-sel-hog {\n-\t\t\tgpio-hog;\n-\t\t\tgpios = <4 GPIO_ACTIVE_HIGH>;\n-\t\t\toutput-low;\n-\t\t\tline-name = \"usb3_sata_sel\";\n-\t\t};\n-\n-\t\tsom-vselect-hog {\n-\t\t\tgpio-hog;\n-\t\t\tgpios = <6 GPIO_ACTIVE_HIGH>;\n-\t\t\toutput-low;\n-\t\t\tline-name = \"som_vselect\";\n-\t\t};\n-\n-\t\tenet-sel-hog {\n-\t\t\tgpio-hog;\n-\t\t\tgpios = <7 GPIO_ACTIVE_HIGH>;\n-\t\t\toutput-low;\n-\t\t\tline-name = \"enet_sel\";\n-\t\t};\n-\t};\n-\n-\textcon_usbotg1: typec@3d {\n-\t\tcompatible = \"nxp,ptn5150\";\n-\t\treg = <0x3d>;\n-\t\tinterrupt-parent = <&gpio1>;\n-\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_ptn5150>;\n-\t\tstatus = \"okay\";\n-\t};\n-};\n-\n-&i2c3 {\n-\t/* Capacitive touch controller */\n-\tft5x06_ts: touchscreen@38 {\n-\t\tcompatible = \"edt,edt-ft5406\";\n-\t\treg = <0x38>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_captouch>;\n-\t\tinterrupt-parent = <&gpio5>;\n-\t\tinterrupts = <4 IRQ_TYPE_LEVEL_HIGH>;\n-\n-\t\ttouchscreen-size-x = <800>;\n-\t\ttouchscreen-size-y = <480>;\n-\t\ttouchscreen-inverted-x;\n-\t\ttouchscreen-inverted-y;\n-\t};\n-\n-\trtc@68 {\n-\t\tcompatible = \"dallas,ds1337\";\n-\t\treg = <0x68>;\n-\t};\n-};\n-\n-/* Header */\n-&uart1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart1>;\n-\tstatus = \"okay\";\n-};\n-\n-/* Header */\n-&uart3 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart3>;\n-\tstatus = \"okay\";\n-};\n-\n-&usbotg1 {\n-\tdisable-over-current;\n-\textcon = <&extcon_usbotg1>, <&extcon_usbotg1>;\n-};\n-\n-&pinctrl_fec1 {\n-\tfsl,pins = <\n-\t\tMX8MN_IOMUXC_ENET_MDC_ENET1_MDC\t\t\t0x3\n-\t\tMX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO\t\t0x3\n-\t\tMX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3\t\t0x1f\n-\t\tMX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2\t\t0x1f\n-\t\tMX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1\t\t0x1f\n-\t\tMX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0\t\t0x1f\n-\t\tMX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3\t\t0x91\n-\t\tMX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2\t\t0x91\n-\t\tMX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1\t\t0x91\n-\t\tMX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0\t\t0x91\n-\t\tMX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC\t\t0x1f\n-\t\tMX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC\t\t0x91\n-\t\tMX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL\t0x91\n-\t\tMX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL\t0x1f\n-\t\t/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */\n-\t>;\n-};\n-\n-&pinctrl_fec1_sleep {\n-\tfsl,pins = <\n-\t\tMX8MN_IOMUXC_ENET_MDC_GPIO1_IO16\t\t0x120\n-\t\tMX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17\t\t0x120\n-\t\tMX8MN_IOMUXC_ENET_TD3_GPIO1_IO18\t\t0x120\n-\t\tMX8MN_IOMUXC_ENET_TD2_GPIO1_IO19\t\t0x120\n-\t\tMX8MN_IOMUXC_ENET_TD1_GPIO1_IO20\t\t0x120\n-\t\tMX8MN_IOMUXC_ENET_TD0_GPIO1_IO21\t\t0x120\n-\t\tMX8MN_IOMUXC_ENET_RD3_GPIO1_IO29\t\t0x120\n-\t\tMX8MN_IOMUXC_ENET_RD2_GPIO1_IO28\t\t0x120\n-\t\tMX8MN_IOMUXC_ENET_RD1_GPIO1_IO27\t\t0x120\n-\t\tMX8MN_IOMUXC_ENET_RD0_GPIO1_IO26\t\t0x120\n-\t\tMX8MN_IOMUXC_ENET_TXC_GPIO1_IO23\t\t0x120\n-\t\tMX8MN_IOMUXC_ENET_RXC_GPIO1_IO25\t\t0x120\n-\t\tMX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24\t\t0x120\n-\t\tMX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22\t\t0x120\n-\t\t/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */\n-\t>;\n-};\n-\n-&iomuxc {\n-\tpinctrl_captouch: captouchgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4\t\t0x16\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c2: i2c2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_I2C2_SCL_I2C2_SCL\t\t0x400001c3\n-\t\t\tMX8MN_IOMUXC_I2C2_SDA_I2C2_SDA\t\t0x400001c3\n-\t\t>;\n-\t};\n-\n-\tpinctrl_pca9534: pca9534grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7\t0x16\n-\t\t>;\n-\t};\n-\n-\tpinctrl_ptn5150: ptn5150grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11\t0x16\n-\t\t>;\n-\t};\n-\n-\tpinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22\t0x41\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart1: uart1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX\t0x140\n-\t\t\tMX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX\t0x140\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart3: uart3grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX\t0x140\n-\t\t\tMX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX\t0x140\n-\t\t>;\n-\t};\n-};\ndiff --git a/arch/arm/dts/imx8mn-var-som.dtsi b/arch/arm/dts/imx8mn-var-som.dtsi\ndeleted file mode 100644\nindex 4eb578a03fc..00000000000\n--- a/arch/arm/dts/imx8mn-var-som.dtsi\n+++ /dev/null\n@@ -1,564 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright 2019 NXP\n- * Copyright 2019-2020 Variscite Ltd.\n- * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>\n- */\n-\n-#include \"imx8mn.dtsi\"\n-\n-/ {\n-\tmodel = \"Variscite VAR-SOM-MX8MN module\";\n-\tcompatible = \"variscite,var-som-mx8mn\", \"fsl,imx8mn\";\n-\n-\taliases {\n-\t\teeprom-som = &eeprom_som;\n-\t};\n-\n-\tchosen {\n-\t\tstdout-path = &uart4;\n-\t};\n-\n-\tmemory@40000000 {\n-\t\tdevice_type = \"memory\";\n-\t\treg = <0x0 0x40000000 0 0x40000000>;\n-\t};\n-\n-\treg_eth_phy: regulator-eth-phy {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_reg_eth_phy>;\n-\t\tregulator-name = \"eth_phy_pwr\";\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tgpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t};\n-};\n-\n-&A53_0 {\n-\tcpu-supply = <&buck2_reg>;\n-};\n-\n-&A53_1 {\n-\tcpu-supply = <&buck2_reg>;\n-};\n-\n-&A53_2 {\n-\tcpu-supply = <&buck2_reg>;\n-};\n-\n-&A53_3 {\n-\tcpu-supply = <&buck2_reg>;\n-};\n-\n-&ecspi1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_ecspi1>;\n-\tcs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,\n-\t\t <&gpio1 0 GPIO_ACTIVE_LOW>;\n-\t/delete-property/ dmas;\n-\t/delete-property/ dma-names;\n-\tstatus = \"okay\";\n-\n-\t/* Resistive touch controller */\n-\ttouchscreen@0 {\n-\t\treg = <0>;\n-\t\tcompatible = \"ti,ads7846\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_restouch>;\n-\t\tinterrupt-parent = <&gpio1>;\n-\t\tinterrupts = <3 IRQ_TYPE_EDGE_FALLING>;\n-\n-\t\tspi-max-frequency = <1500000>;\n-\t\tpendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;\n-\n-\t\tti,x-min = /bits/ 16 <125>;\n-\t\ttouchscreen-size-x = <4008>;\n-\t\tti,y-min = /bits/ 16 <282>;\n-\t\ttouchscreen-size-y = <3864>;\n-\t\tti,x-plate-ohms = /bits/ 16 <180>;\n-\t\ttouchscreen-max-pressure = <255>;\n-\t\ttouchscreen-average-samples = <10>;\n-\t\tti,debounce-tol = /bits/ 16 <3>;\n-\t\tti,debounce-rep = /bits/ 16 <1>;\n-\t\tti,settle-delay-usec = /bits/ 16 <150>;\n-\t\tti,keep-vref-on;\n-\t\twakeup-source;\n-\t};\n-};\n-\n-&fec1 {\n-\tpinctrl-names = \"default\", \"sleep\";\n-\tpinctrl-0 = <&pinctrl_fec1>;\n-\tpinctrl-1 = <&pinctrl_fec1_sleep>;\n-\tphy-mode = \"rgmii\";\n-\tphy-handle = <ðphy>;\n-\tphy-supply = <®_eth_phy>;\n-\tfsl,magic-packet;\n-\tstatus = \"okay\";\n-\n-\tmdio {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\tethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */\n-\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n-\t\t\treg = <4>;\n-\t\t\treset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;\n-\t\t\treset-assert-us = <10000>;\n-\t\t\t/*\n-\t\t\t * Deassert delay:\n-\t\t\t * ADIN1300 requires 5ms.\n-\t\t\t * AR8033 requires 1ms.\n-\t\t\t */\n-\t\t\treset-deassert-us = <20000>;\n-\t\t};\n-\t};\n-};\n-\n-&i2c1 {\n-\tclock-frequency = <400000>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_i2c1>;\n-\tstatus = \"okay\";\n-\n-\tpmic@4b {\n-\t\tcompatible = \"rohm,bd71847\";\n-\t\treg = <0x4b>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_pmic>;\n-\t\tinterrupt-parent = <&gpio2>;\n-\t\tinterrupts = <8 IRQ_TYPE_LEVEL_LOW>;\n-\t\trohm,reset-snvs-powered;\n-\n-\t\tregulators {\n-\t\t\tbuck1_reg: BUCK1 {\n-\t\t\t\tregulator-name = \"buck1\";\n-\t\t\t\tregulator-min-microvolt = <700000>;\n-\t\t\t\tregulator-max-microvolt = <1300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-ramp-delay = <1250>;\n-\t\t\t};\n-\n-\t\t\tbuck2_reg: BUCK2 {\n-\t\t\t\tregulator-name = \"buck2\";\n-\t\t\t\tregulator-min-microvolt = <700000>;\n-\t\t\t\tregulator-max-microvolt = <1300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-ramp-delay = <1250>;\n-\t\t\t\trohm,dvs-run-voltage = <1000000>;\n-\t\t\t\trohm,dvs-idle-voltage = <900000>;\n-\t\t\t};\n-\n-\t\t\tbuck3_reg: BUCK3 {\n-\t\t\t\tregulator-name = \"buck3\";\n-\t\t\t\tregulator-min-microvolt = <700000>;\n-\t\t\t\tregulator-max-microvolt = <1350000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tbuck4_reg: BUCK4 {\n-\t\t\t\tregulator-name = \"buck4\";\n-\t\t\t\tregulator-min-microvolt = <2600000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tbuck5_reg: BUCK5 {\n-\t\t\t\tregulator-name = \"buck5\";\n-\t\t\t\tregulator-min-microvolt = <1605000>;\n-\t\t\t\tregulator-max-microvolt = <1995000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tbuck6_reg: BUCK6 {\n-\t\t\t\tregulator-name = \"buck6\";\n-\t\t\t\tregulator-min-microvolt = <800000>;\n-\t\t\t\tregulator-max-microvolt = <1400000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tldo1_reg: LDO1 {\n-\t\t\t\tregulator-name = \"ldo1\";\n-\t\t\t\tregulator-min-microvolt = <1600000>;\n-\t\t\t\tregulator-max-microvolt = <1900000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tldo2_reg: LDO2 {\n-\t\t\t\tregulator-name = \"ldo2\";\n-\t\t\t\tregulator-min-microvolt = <800000>;\n-\t\t\t\tregulator-max-microvolt = <900000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tldo3_reg: LDO3 {\n-\t\t\t\tregulator-name = \"ldo3\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tldo4_reg: LDO4 {\n-\t\t\t\tregulator-name = \"ldo4\";\n-\t\t\t\tregulator-min-microvolt = <900000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tldo5_reg: LDO5 {\n-\t\t\t\tregulator-compatible = \"ldo5\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\n-\t\t\tldo6_reg: LDO6 {\n-\t\t\t\tregulator-name = \"ldo6\";\n-\t\t\t\tregulator-min-microvolt = <900000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-always-on;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\teeprom_som: eeprom@52 {\n-\t\tcompatible = \"atmel,24c04\";\n-\t\treg = <0x52>;\n-\t\tpagesize = <16>;\n-\t};\n-};\n-\n-&i2c3 {\n-\tclock-frequency = <400000>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_i2c3>;\n-\tstatus = \"okay\";\n-\n-\t/* TODO: configure audio, as of now just put a placeholder */\n-\twm8904: codec@1a {\n-\t\tcompatible = \"wlf,wm8904\";\n-\t\treg = <0x1a>;\n-\t\tstatus = \"disabled\";\n-\t};\n-};\n-\n-&snvs_pwrkey {\n-\tstatus = \"okay\";\n-};\n-\n-/* Bluetooth */\n-&uart2 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart2>;\n-\tassigned-clocks = <&clk IMX8MN_CLK_UART2>;\n-\tassigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;\n-\tuart-has-rtscts;\n-\tstatus = \"okay\";\n-};\n-\n-/* Console */\n-&uart4 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_uart4>;\n-\tstatus = \"okay\";\n-};\n-\n-&usbotg1 {\n-\tdr_mode = \"otg\";\n-\tusb-role-switch;\n-\tstatus = \"okay\";\n-};\n-\n-/* WIFI */\n-&usdhc1 {\n-\t#address-cells = <1>;\n-\t#size-cells = <0>;\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc1>;\n-\tpinctrl-1 = <&pinctrl_usdhc1_100mhz>;\n-\tpinctrl-2 = <&pinctrl_usdhc1_200mhz>;\n-\tbus-width = <4>;\n-\tnon-removable;\n-\tkeep-power-in-suspend;\n-\tstatus = \"okay\";\n-\n-\tbrcmf: bcrmf@1 {\n-\t\treg = <1>;\n-\t\tcompatible = \"brcm,bcm4329-fmac\";\n-\t};\n-};\n-\n-/* SD */\n-&usdhc2 {\n-\tassigned-clocks = <&clk IMX8MN_CLK_USDHC2>;\n-\tassigned-clock-rates = <200000000>;\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;\n-\tpinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;\n-\tpinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;\n-\tcd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;\n-\tbus-width = <4>;\n-\tvmmc-supply = <®_usdhc2_vmmc>;\n-\tstatus = \"okay\";\n-};\n-\n-/* eMMC */\n-&usdhc3 {\n-\tassigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;\n-\tassigned-clock-rates = <400000000>;\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tpinctrl-0 = <&pinctrl_usdhc3>;\n-\tpinctrl-1 = <&pinctrl_usdhc3_100mhz>;\n-\tpinctrl-2 = <&pinctrl_usdhc3_200mhz>;\n-\tbus-width = <8>;\n-\tnon-removable;\n-\tstatus = \"okay\";\n-};\n-\n-&wdog1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_wdog>;\n-\tfsl,ext-reset-output;\n-\tstatus = \"okay\";\n-};\n-\n-&iomuxc {\n-\tpinctrl_ecspi1: ecspi1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK\t\t0x13\n-\t\t\tMX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI\t\t0x13\n-\t\t\tMX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO\t\t0x13\n-\t\t\tMX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14\t\t0x13\n-\t\t\tMX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0\t\t0x13\n-\t\t>;\n-\t};\n-\n-\tpinctrl_fec1: fec1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_ENET_MDC_ENET1_MDC\t\t\t0x3\n-\t\t\tMX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO\t\t0x3\n-\t\t\tMX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3\t\t0x1f\n-\t\t\tMX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2\t\t0x1f\n-\t\t\tMX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1\t\t0x1f\n-\t\t\tMX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0\t\t0x1f\n-\t\t\tMX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3\t\t0x91\n-\t\t\tMX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2\t\t0x91\n-\t\t\tMX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1\t\t0x91\n-\t\t\tMX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0\t\t0x91\n-\t\t\tMX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC\t\t0x1f\n-\t\t\tMX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC\t\t0x91\n-\t\t\tMX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL\t0x91\n-\t\t\tMX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL\t0x1f\n-\t\t\tMX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9\t\t0x19\n-\t\t>;\n-\t};\n-\n-\tpinctrl_fec1_sleep: fec1sleepgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_ENET_MDC_GPIO1_IO16\t\t0x120\n-\t\t\tMX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17\t\t0x120\n-\t\t\tMX8MN_IOMUXC_ENET_TD3_GPIO1_IO18\t\t0x120\n-\t\t\tMX8MN_IOMUXC_ENET_TD2_GPIO1_IO19\t\t0x120\n-\t\t\tMX8MN_IOMUXC_ENET_TD1_GPIO1_IO20\t\t0x120\n-\t\t\tMX8MN_IOMUXC_ENET_TD0_GPIO1_IO21\t\t0x120\n-\t\t\tMX8MN_IOMUXC_ENET_RD3_GPIO1_IO29\t\t0x120\n-\t\t\tMX8MN_IOMUXC_ENET_RD2_GPIO1_IO28\t\t0x120\n-\t\t\tMX8MN_IOMUXC_ENET_RD1_GPIO1_IO27\t\t0x120\n-\t\t\tMX8MN_IOMUXC_ENET_RD0_GPIO1_IO26\t\t0x120\n-\t\t\tMX8MN_IOMUXC_ENET_TXC_GPIO1_IO23\t\t0x120\n-\t\t\tMX8MN_IOMUXC_ENET_RXC_GPIO1_IO25\t\t0x120\n-\t\t\tMX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24\t\t0x120\n-\t\t\tMX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22\t\t0x120\n-\t\t\tMX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9\t\t0x120\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c1: i2c1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_I2C1_SCL_I2C1_SCL\t\t0x400001c3\n-\t\t\tMX8MN_IOMUXC_I2C1_SDA_I2C1_SDA\t\t0x400001c3\n-\t\t>;\n-\t};\n-\n-\tpinctrl_i2c3: i2c3grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_I2C3_SCL_I2C3_SCL\t\t0x400001c3\n-\t\t\tMX8MN_IOMUXC_I2C3_SDA_I2C3_SDA\t\t0x400001c3\n-\t\t>;\n-\t};\n-\n-\tpinctrl_pmic: pmicirqgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8\t0x141\n-\t\t>;\n-\t};\n-\n-\tpinctrl_reg_eth_phy: regethphygrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9\t0x41\n-\t\t>;\n-\t};\n-\n-\tpinctrl_restouch: restouchgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3\t0x1c0\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart2: uart2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX\t0x140\n-\t\t\tMX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX\t0x140\n-\t\t\tMX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B\t0x140\n-\t\t\tMX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B\t0x140\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart4: uart4grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX\t0x140\n-\t\t\tMX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX\t0x140\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1: usdhc1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_SD1_CLK_USDHC1_CLK\t\t0x190\n-\t\t\tMX8MN_IOMUXC_SD1_CMD_USDHC1_CMD\t\t0x1d0\n-\t\t\tMX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0\t0x1d0\n-\t\t\tMX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1\t0x1d0\n-\t\t\tMX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2\t0x1d0\n-\t\t\tMX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3\t0x1d0\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_SD1_CLK_USDHC1_CLK\t\t0x194\n-\t\t\tMX8MN_IOMUXC_SD1_CMD_USDHC1_CMD\t\t0x1d4\n-\t\t\tMX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0\t0x1d4\n-\t\t\tMX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1\t0x1d4\n-\t\t\tMX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2\t0x1d4\n-\t\t\tMX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3\t0x1d4\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_SD1_CLK_USDHC1_CLK\t\t0x196\n-\t\t\tMX8MN_IOMUXC_SD1_CMD_USDHC1_CMD\t\t0x1d6\n-\t\t\tMX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0\t0x1d6\n-\t\t\tMX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1\t0x1d6\n-\t\t\tMX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2\t0x1d6\n-\t\t\tMX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3\t0x1d6\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_gpio: usdhc2gpiogrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10\t0x41\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2: usdhc2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_SD2_CLK_USDHC2_CLK\t\t0x190\n-\t\t\tMX8MN_IOMUXC_SD2_CMD_USDHC2_CMD\t\t0x1d0\n-\t\t\tMX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0\t0x1d0\n-\t\t\tMX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1\t0x1d0\n-\t\t\tMX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2\t0x1d0\n-\t\t\tMX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3\t0x1d0\n-\t\t\tMX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT\t0x1d0\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_SD2_CLK_USDHC2_CLK\t\t0x194\n-\t\t\tMX8MN_IOMUXC_SD2_CMD_USDHC2_CMD\t\t0x1d4\n-\t\t\tMX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0\t0x1d4\n-\t\t\tMX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1\t0x1d4\n-\t\t\tMX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2\t0x1d4\n-\t\t\tMX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3\t0x1d4\n-\t\t\tMX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT\t0x1d0\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_SD2_CLK_USDHC2_CLK\t\t0x196\n-\t\t\tMX8MN_IOMUXC_SD2_CMD_USDHC2_CMD\t\t0x1d6\n-\t\t\tMX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0\t0x1d6\n-\t\t\tMX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1\t0x1d6\n-\t\t\tMX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2\t0x1d6\n-\t\t\tMX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3\t0x1d6\n-\t\t\tMX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT\t0x1d0\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3: usdhc3grp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK\t0x190\n-\t\t\tMX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD\t0x1d0\n-\t\t\tMX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0\t0x1d0\n-\t\t\tMX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1\t0x1d0\n-\t\t\tMX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2\t0x1d0\n-\t\t\tMX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3\t0x1d0\n-\t\t\tMX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4\t0x1d0\n-\t\t\tMX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5\t0x1d0\n-\t\t\tMX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6\t0x1d0\n-\t\t\tMX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7\t0x1d0\n-\t\t\tMX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE\t0x190\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK\t0x194\n-\t\t\tMX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD\t0x1d4\n-\t\t\tMX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0\t0x1d4\n-\t\t\tMX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1\t0x1d4\n-\t\t\tMX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2\t0x1d4\n-\t\t\tMX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3\t0x1d4\n-\t\t\tMX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4\t0x1d4\n-\t\t\tMX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5\t0x1d4\n-\t\t\tMX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6\t0x1d4\n-\t\t\tMX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7\t0x1d4\n-\t\t\tMX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE\t0x194\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK\t0x196\n-\t\t\tMX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD\t0x1d6\n-\t\t\tMX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0\t0x1d6\n-\t\t\tMX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1\t0x1d6\n-\t\t\tMX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2\t0x1d6\n-\t\t\tMX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3\t0x1d6\n-\t\t\tMX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4\t0x1d6\n-\t\t\tMX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5\t0x1d6\n-\t\t\tMX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6\t0x1d6\n-\t\t\tMX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7\t0x1d6\n-\t\t\tMX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE\t0x196\n-\t\t>;\n-\t};\n-\n-\tpinctrl_wdog: wdoggrp {\n-\t\tfsl,pins = <\n-\t\t\tMX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B\t0x166\n-\t\t>;\n-\t};\n-};\ndiff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig\nindex d25e0910328..8b0d48b07b3 100644\n--- a/arch/arm/mach-imx/imx8m/Kconfig\n+++ b/arch/arm/mach-imx/imx8m/Kconfig\n@@ -318,6 +318,7 @@ config TARGET_IMX8MN_VAR_SOM\n \tselect I2C_EEPROM\n \tselect DM_ETH_PHY\n \tselect NVMEM\n+\timply OF_UPSTREAM\n \n config TARGET_KONTRON_PITX_IMX8M\n \tbool \"Support Kontron pITX-imx8m\"\ndiff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig\nindex b9f3b9b8999..95c442389d0 100644\n--- a/configs/imx8mn_var_som_defconfig\n+++ b/configs/imx8mn_var_som_defconfig\n@@ -9,7 +9,7 @@ CONFIG_NR_DRAM_BANKS=1\n CONFIG_ENV_SIZE=0x2000\n CONFIG_ENV_OFFSET=0xFFFFDE00\n CONFIG_DM_GPIO=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx8mn-var-som-symphony\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"freescale/imx8mn-var-som-symphony\"\n CONFIG_TARGET_IMX8MN_VAR_SOM=y\n CONFIG_OF_LIBFDT_OVERLAY=y\n CONFIG_SYS_MONITOR_LEN=524288\n", "prefixes": [ "3/6" ] }