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GET /api/patches/2187620/?format=api
{ "id": 2187620, "url": "http://patchwork.ozlabs.org/api/patches/2187620/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260122111639.32346-4-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260122111639.32346-4-philmd@linaro.org>", "list_archive_url": null, "date": "2026-01-22T11:16:36", "name": "[PULL,v2,03/37] target/m68k: Use big-endian variant of cpu_ld/st_data*()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "64ab350345f9ba4f8692376ddb8c0731c7269f94", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260122111639.32346-4-philmd@linaro.org/mbox/", "series": [ { "id": 489357, "url": "http://patchwork.ozlabs.org/api/series/489357/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=489357", "date": "2026-01-22T11:16:33", "name": "[PULL,v2,01/37] target/i386: Use little-endian variant of cpu_ld/st_data*()", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/489357/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2187620/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2187620/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=my4aNYC7;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32f;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "We only build the M68k target using big endianness order,\ntherefore the cpu_ld/st_data*() definitions expand to the\nbig endian declarations. Use the explicit big-endian variants.\n\nMechanical change running:\n\n $ tgt=m68k; \\\n end=be; \\\n for op in data mmuidx_ra; do \\\n for ac in uw sw l q; do \\\n sed -i -e \"s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/\" \\\n $(git grep -l cpu_ target/${tgt}/); \\\n done;\n for ac in w l q; do \\\n sed -i -e \"s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/\" \\\n $(git grep -l cpu_ target/${tgt}/); \\\n done;\n done\n\nThen adapting indentation in do_stack_frame() to pass checkpatch.pl.\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-Id: <20251126202200.23100-8-philmd@linaro.org>\n---\n target/m68k/fpu_helper.c | 12 +++---\n target/m68k/op_helper.c | 91 ++++++++++++++++++++--------------------\n 2 files changed, 52 insertions(+), 51 deletions(-)", "diff": "diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c\nindex 56012863c85..f49f841d489 100644\n--- a/target/m68k/fpu_helper.c\n+++ b/target/m68k/fpu_helper.c\n@@ -510,8 +510,8 @@ static int cpu_ld_floatx80_ra(CPUM68KState *env, uint32_t addr, FPReg *fp,\n uint32_t high;\n uint64_t low;\n \n- high = cpu_ldl_data_ra(env, addr, ra);\n- low = cpu_ldq_data_ra(env, addr + 4, ra);\n+ high = cpu_ldl_be_data_ra(env, addr, ra);\n+ low = cpu_ldq_be_data_ra(env, addr + 4, ra);\n \n fp->l.upper = high >> 16;\n fp->l.lower = low;\n@@ -522,8 +522,8 @@ static int cpu_ld_floatx80_ra(CPUM68KState *env, uint32_t addr, FPReg *fp,\n static int cpu_st_floatx80_ra(CPUM68KState *env, uint32_t addr, FPReg *fp,\n uintptr_t ra)\n {\n- cpu_stl_data_ra(env, addr, fp->l.upper << 16, ra);\n- cpu_stq_data_ra(env, addr + 4, fp->l.lower, ra);\n+ cpu_stl_be_data_ra(env, addr, fp->l.upper << 16, ra);\n+ cpu_stq_be_data_ra(env, addr + 4, fp->l.lower, ra);\n \n return 12;\n }\n@@ -533,7 +533,7 @@ static int cpu_ld_float64_ra(CPUM68KState *env, uint32_t addr, FPReg *fp,\n {\n uint64_t val;\n \n- val = cpu_ldq_data_ra(env, addr, ra);\n+ val = cpu_ldq_be_data_ra(env, addr, ra);\n fp->d = float64_to_floatx80(*(float64 *)&val, &env->fp_status);\n \n return 8;\n@@ -545,7 +545,7 @@ static int cpu_st_float64_ra(CPUM68KState *env, uint32_t addr, FPReg *fp,\n float64 val;\n \n val = floatx80_to_float64(fp->d, &env->fp_status);\n- cpu_stq_data_ra(env, addr, *(uint64_t *)&val, ra);\n+ cpu_stq_be_data_ra(env, addr, *(uint64_t *)&val, ra);\n \n return 8;\n }\ndiff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c\nindex f7df83c850c..8148a8852e7 100644\n--- a/target/m68k/op_helper.c\n+++ b/target/m68k/op_helper.c\n@@ -32,8 +32,8 @@ static void cf_rte(CPUM68KState *env)\n uint32_t fmt;\n \n sp = env->aregs[7];\n- fmt = cpu_ldl_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);\n- env->pc = cpu_ldl_mmuidx_ra(env, sp + 4, MMU_KERNEL_IDX, 0);\n+ fmt = cpu_ldl_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);\n+ env->pc = cpu_ldl_be_mmuidx_ra(env, sp + 4, MMU_KERNEL_IDX, 0);\n sp |= (fmt >> 28) & 3;\n env->aregs[7] = sp + 8;\n \n@@ -48,13 +48,13 @@ static void m68k_rte(CPUM68KState *env)\n \n sp = env->aregs[7];\n throwaway:\n- sr = cpu_lduw_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);\n+ sr = cpu_lduw_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);\n sp += 2;\n- env->pc = cpu_ldl_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);\n+ env->pc = cpu_ldl_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);\n sp += 4;\n if (m68k_feature(env, M68K_FEATURE_EXCEPTION_FORMAT_VEC)) {\n /* all except 68000 */\n- fmt = cpu_lduw_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);\n+ fmt = cpu_lduw_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);\n sp += 2;\n switch (fmt >> 12) {\n case 0:\n@@ -250,12 +250,12 @@ static void cf_interrupt_all(CPUM68KState *env, int is_hw)\n /* ??? This could cause MMU faults. */\n sp &= ~3;\n sp -= 4;\n- cpu_stl_mmuidx_ra(env, sp, retaddr, MMU_KERNEL_IDX, 0);\n+ cpu_stl_be_mmuidx_ra(env, sp, retaddr, MMU_KERNEL_IDX, 0);\n sp -= 4;\n- cpu_stl_mmuidx_ra(env, sp, fmt, MMU_KERNEL_IDX, 0);\n+ cpu_stl_be_mmuidx_ra(env, sp, fmt, MMU_KERNEL_IDX, 0);\n env->aregs[7] = sp;\n /* Jump to vector. */\n- env->pc = cpu_ldl_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0);\n+ env->pc = cpu_ldl_be_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0);\n \n do_plugin_vcpu_interrupt_cb(cs, retaddr);\n }\n@@ -270,24 +270,25 @@ static inline void do_stack_frame(CPUM68KState *env, uint32_t *sp,\n switch (format) {\n case 4:\n *sp -= 4;\n- cpu_stl_mmuidx_ra(env, *sp, env->pc, MMU_KERNEL_IDX, 0);\n+ cpu_stl_be_mmuidx_ra(env, *sp, env->pc, MMU_KERNEL_IDX, 0);\n *sp -= 4;\n- cpu_stl_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0);\n+ cpu_stl_be_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0);\n break;\n case 3:\n case 2:\n *sp -= 4;\n- cpu_stl_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0);\n+ cpu_stl_be_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0);\n break;\n }\n *sp -= 2;\n- cpu_stw_mmuidx_ra(env, *sp, (format << 12) + (cs->exception_index << 2),\n- MMU_KERNEL_IDX, 0);\n+ cpu_stw_be_mmuidx_ra(env, *sp,\n+ (format << 12) + (cs->exception_index << 2),\n+ MMU_KERNEL_IDX, 0);\n }\n *sp -= 4;\n- cpu_stl_mmuidx_ra(env, *sp, retaddr, MMU_KERNEL_IDX, 0);\n+ cpu_stl_be_mmuidx_ra(env, *sp, retaddr, MMU_KERNEL_IDX, 0);\n *sp -= 2;\n- cpu_stw_mmuidx_ra(env, *sp, sr, MMU_KERNEL_IDX, 0);\n+ cpu_stw_be_mmuidx_ra(env, *sp, sr, MMU_KERNEL_IDX, 0);\n }\n \n static void m68k_interrupt_all(CPUM68KState *env, int is_hw)\n@@ -346,49 +347,49 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw)\n env->mmu.fault = true;\n /* push data 3 */\n sp -= 4;\n- cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n /* push data 2 */\n sp -= 4;\n- cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n /* push data 1 */\n sp -= 4;\n- cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n /* write back 1 / push data 0 */\n sp -= 4;\n- cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n /* write back 1 address */\n sp -= 4;\n- cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n /* write back 2 data */\n sp -= 4;\n- cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n /* write back 2 address */\n sp -= 4;\n- cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n /* write back 3 data */\n sp -= 4;\n- cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n /* write back 3 address */\n sp -= 4;\n- cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);\n+ cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);\n /* fault address */\n sp -= 4;\n- cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);\n+ cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);\n /* write back 1 status */\n sp -= 2;\n- cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n /* write back 2 status */\n sp -= 2;\n- cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n /* write back 3 status */\n sp -= 2;\n- cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n+ cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);\n /* special status word */\n sp -= 2;\n- cpu_stw_mmuidx_ra(env, sp, env->mmu.ssw, MMU_KERNEL_IDX, 0);\n+ cpu_stw_be_mmuidx_ra(env, sp, env->mmu.ssw, MMU_KERNEL_IDX, 0);\n /* effective address */\n sp -= 4;\n- cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);\n+ cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);\n \n do_stack_frame(env, &sp, 7, oldsr, 0, env->pc);\n env->mmu.fault = false;\n@@ -436,7 +437,7 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw)\n \n env->aregs[7] = sp;\n /* Jump to vector. */\n- env->pc = cpu_ldl_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0);\n+ env->pc = cpu_ldl_be_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0);\n \n do_plugin_vcpu_interrupt_cb(cs, last_pc);\n }\n@@ -784,11 +785,11 @@ void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2)\n int16_t l1, l2;\n uintptr_t ra = GETPC();\n \n- l1 = cpu_lduw_data_ra(env, a1, ra);\n- l2 = cpu_lduw_data_ra(env, a2, ra);\n+ l1 = cpu_lduw_be_data_ra(env, a1, ra);\n+ l2 = cpu_lduw_be_data_ra(env, a2, ra);\n if (l1 == c1 && l2 == c2) {\n- cpu_stw_data_ra(env, a1, u1, ra);\n- cpu_stw_data_ra(env, a2, u2, ra);\n+ cpu_stw_be_data_ra(env, a1, u1, ra);\n+ cpu_stw_be_data_ra(env, a2, u2, ra);\n }\n \n if (c1 != l1) {\n@@ -840,11 +841,11 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2,\n }\n } else {\n /* We're executing in a serial context -- no need to be atomic. */\n- l1 = cpu_ldl_data_ra(env, a1, ra);\n- l2 = cpu_ldl_data_ra(env, a2, ra);\n+ l1 = cpu_ldl_be_data_ra(env, a1, ra);\n+ l2 = cpu_ldl_be_data_ra(env, a2, ra);\n if (l1 == c1 && l2 == c2) {\n- cpu_stl_data_ra(env, a1, u1, ra);\n- cpu_stl_data_ra(env, a2, u2, ra);\n+ cpu_stl_be_data_ra(env, a1, u1, ra);\n+ cpu_stl_be_data_ra(env, a2, u2, ra);\n }\n }\n \n@@ -946,12 +947,12 @@ static uint64_t bf_load(CPUM68KState *env, uint32_t addr, int blen,\n case 0:\n return cpu_ldub_data_ra(env, addr, ra);\n case 1:\n- return cpu_lduw_data_ra(env, addr, ra);\n+ return cpu_lduw_be_data_ra(env, addr, ra);\n case 2:\n case 3:\n- return cpu_ldl_data_ra(env, addr, ra);\n+ return cpu_ldl_be_data_ra(env, addr, ra);\n case 4:\n- return cpu_ldq_data_ra(env, addr, ra);\n+ return cpu_ldq_be_data_ra(env, addr, ra);\n default:\n g_assert_not_reached();\n }\n@@ -965,14 +966,14 @@ static void bf_store(CPUM68KState *env, uint32_t addr, int blen,\n cpu_stb_data_ra(env, addr, data, ra);\n break;\n case 1:\n- cpu_stw_data_ra(env, addr, data, ra);\n+ cpu_stw_be_data_ra(env, addr, data, ra);\n break;\n case 2:\n case 3:\n- cpu_stl_data_ra(env, addr, data, ra);\n+ cpu_stl_be_data_ra(env, addr, data, ra);\n break;\n case 4:\n- cpu_stq_data_ra(env, addr, data, ra);\n+ cpu_stq_be_data_ra(env, addr, data, ra);\n break;\n default:\n g_assert_not_reached();\n", "prefixes": [ "PULL", "v2", "03/37" ] }