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GET /api/patches/2187618/?format=api
{ "id": 2187618, "url": "http://patchwork.ozlabs.org/api/patches/2187618/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260122111639.32346-2-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260122111639.32346-2-philmd@linaro.org>", "list_archive_url": null, "date": "2026-01-22T11:16:34", "name": "[PULL,v2,01/37] target/i386: Use little-endian variant of cpu_ld/st_data*()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2acd1a1eddcc223bbee2ade4d8da22e6dce40ddc", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260122111639.32346-2-philmd@linaro.org/mbox/", "series": [ { "id": 489357, "url": "http://patchwork.ozlabs.org/api/series/489357/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=489357", "date": "2026-01-22T11:16:33", "name": "[PULL,v2,01/37] target/i386: Use little-endian variant of cpu_ld/st_data*()", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/489357/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2187618/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2187618/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Pe35jTmK;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::332;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "We only build the X86 targets using little endianness order,\ntherefore the cpu_ld/st_data*() definitions expand to the little\nendian declarations. Use the explicit little-endian variants.\n\nMechanical change running:\n\n $ tgt=i386; \\\n end=le; \\\n for op in data mmuidx_ra; do \\\n for ac in uw sw l q; do \\\n sed -i -e \"s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/\" \\\n $(git grep -l cpu_ target/${tgt}/); \\\n done;\n for ac in w l q; do \\\n sed -i -e \"s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/\" \\\n $(git grep -l cpu_ target/${tgt}/); \\\n done;\n done\n\nThen adapting indentation in helper_vmload() to pass checkpatch.pl.\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-Id: <20251126202200.23100-3-philmd@linaro.org>\n---\n target/i386/ops_sse.h | 12 ++---\n target/i386/tcg/seg_helper.h | 12 ++---\n linux-user/vm86.c | 4 +-\n target/i386/tcg/mem_helper.c | 8 ++--\n target/i386/tcg/mpx_helper.c | 28 +++++------\n target/i386/tcg/seg_helper.c | 16 +++----\n target/i386/tcg/system/excp_helper.c | 8 ++--\n target/i386/tcg/system/svm_helper.c | 69 +++++++++++++++-------------\n 8 files changed, 80 insertions(+), 77 deletions(-)", "diff": "diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h\nindex 853196b2bbd..99c4728ec81 100644\n--- a/target/i386/ops_sse.h\n+++ b/target/i386/ops_sse.h\n@@ -2326,7 +2326,7 @@ void glue(helper_vpmaskmovd_st, SUFFIX)(CPUX86State *env,\n \n for (i = 0; i < (2 << SHIFT); i++) {\n if (v->L(i) >> 31) {\n- cpu_stl_data_ra(env, a0 + i * 4, s->L(i), GETPC());\n+ cpu_stl_le_data_ra(env, a0 + i * 4, s->L(i), GETPC());\n }\n }\n }\n@@ -2338,7 +2338,7 @@ void glue(helper_vpmaskmovq_st, SUFFIX)(CPUX86State *env,\n \n for (i = 0; i < (1 << SHIFT); i++) {\n if (v->Q(i) >> 63) {\n- cpu_stq_data_ra(env, a0 + i * 8, s->Q(i), GETPC());\n+ cpu_stq_le_data_ra(env, a0 + i * 8, s->Q(i), GETPC());\n }\n }\n }\n@@ -2369,7 +2369,7 @@ void glue(helper_vpgatherdd, SUFFIX)(CPUX86State *env,\n if (v->L(i) >> 31) {\n target_ulong addr = a0\n + ((target_ulong)(int32_t)s->L(i) << scale);\n- d->L(i) = cpu_ldl_data_ra(env, addr & amask, GETPC());\n+ d->L(i) = cpu_ldl_le_data_ra(env, addr & amask, GETPC());\n }\n v->L(i) = 0;\n }\n@@ -2383,7 +2383,7 @@ void glue(helper_vpgatherdq, SUFFIX)(CPUX86State *env,\n if (v->Q(i) >> 63) {\n target_ulong addr = a0\n + ((target_ulong)(int32_t)s->L(i) << scale);\n- d->Q(i) = cpu_ldq_data_ra(env, addr & amask, GETPC());\n+ d->Q(i) = cpu_ldq_le_data_ra(env, addr & amask, GETPC());\n }\n v->Q(i) = 0;\n }\n@@ -2397,7 +2397,7 @@ void glue(helper_vpgatherqd, SUFFIX)(CPUX86State *env,\n if (v->L(i) >> 31) {\n target_ulong addr = a0\n + ((target_ulong)(int64_t)s->Q(i) << scale);\n- d->L(i) = cpu_ldl_data_ra(env, addr & amask, GETPC());\n+ d->L(i) = cpu_ldl_le_data_ra(env, addr & amask, GETPC());\n }\n v->L(i) = 0;\n }\n@@ -2415,7 +2415,7 @@ void glue(helper_vpgatherqq, SUFFIX)(CPUX86State *env,\n if (v->Q(i) >> 63) {\n target_ulong addr = a0\n + ((target_ulong)(int64_t)s->Q(i) << scale);\n- d->Q(i) = cpu_ldq_data_ra(env, addr & amask, GETPC());\n+ d->Q(i) = cpu_ldq_le_data_ra(env, addr & amask, GETPC());\n }\n v->Q(i) = 0;\n }\ndiff --git a/target/i386/tcg/seg_helper.h b/target/i386/tcg/seg_helper.h\nindex ea98e1a98ed..20ce47d62d9 100644\n--- a/target/i386/tcg/seg_helper.h\n+++ b/target/i386/tcg/seg_helper.h\n@@ -40,18 +40,18 @@ int cpu_mmu_index_kernel(CPUX86State *env);\n * and use *_mmuidx_ra directly.\n */\n #define cpu_lduw_kernel_ra(e, p, r) \\\n- cpu_lduw_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r)\n+ cpu_lduw_le_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r)\n #define cpu_ldl_kernel_ra(e, p, r) \\\n- cpu_ldl_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r)\n+ cpu_ldl_le_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r)\n #define cpu_ldq_kernel_ra(e, p, r) \\\n- cpu_ldq_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r)\n+ cpu_ldq_le_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r)\n \n #define cpu_stw_kernel_ra(e, p, v, r) \\\n- cpu_stw_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r)\n+ cpu_stw_le_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r)\n #define cpu_stl_kernel_ra(e, p, v, r) \\\n- cpu_stl_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r)\n+ cpu_stl_le_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r)\n #define cpu_stq_kernel_ra(e, p, v, r) \\\n- cpu_stq_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r)\n+ cpu_stq_le_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r)\n \n #define cpu_lduw_kernel(e, p) cpu_lduw_kernel_ra(e, p, 0)\n #define cpu_ldl_kernel(e, p) cpu_ldl_kernel_ra(e, p, 0)\ndiff --git a/linux-user/vm86.c b/linux-user/vm86.c\nindex 5091d53fb84..4e120875a06 100644\n--- a/linux-user/vm86.c\n+++ b/linux-user/vm86.c\n@@ -44,7 +44,7 @@ static inline int is_revectored(int nr, struct target_revectored_struct *bitmap)\n static inline void vm_putw(CPUX86State *env, uint32_t segptr,\n unsigned int reg16, unsigned int val)\n {\n- cpu_stw_data(env, segptr + (reg16 & 0xffff), val);\n+ cpu_stw_le_data(env, segptr + (reg16 & 0xffff), val);\n }\n \n void save_v86_state(CPUX86State *env)\n@@ -157,7 +157,7 @@ static void do_int(CPUX86State *env, int intno)\n &ts->vm86plus.int21_revectored))\n goto cannot_handle;\n int_addr = (intno << 2);\n- segoffs = cpu_ldl_data(env, int_addr);\n+ segoffs = cpu_ldl_le_data(env, int_addr);\n if ((segoffs >> 16) == TARGET_BIOSSEG)\n goto cannot_handle;\n LOG_VM86(\"VM86: emulating int 0x%x. CS:IP=%04x:%04x\\n\",\ndiff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c\nindex 9e7c2d80293..c15a32d60ad 100644\n--- a/target/i386/tcg/mem_helper.c\n+++ b/target/i386/tcg/mem_helper.c\n@@ -30,8 +30,8 @@ void helper_boundw(CPUX86State *env, target_ulong a0, int v)\n {\n int low, high;\n \n- low = cpu_ldsw_data_ra(env, a0, GETPC());\n- high = cpu_ldsw_data_ra(env, a0 + 2, GETPC());\n+ low = cpu_ldsw_le_data_ra(env, a0, GETPC());\n+ high = cpu_ldsw_le_data_ra(env, a0 + 2, GETPC());\n v = (int16_t)v;\n if (v < low || v > high) {\n if (env->hflags & HF_MPX_EN_MASK) {\n@@ -45,8 +45,8 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v)\n {\n int low, high;\n \n- low = cpu_ldl_data_ra(env, a0, GETPC());\n- high = cpu_ldl_data_ra(env, a0 + 4, GETPC());\n+ low = cpu_ldl_le_data_ra(env, a0, GETPC());\n+ high = cpu_ldl_le_data_ra(env, a0 + 4, GETPC());\n if (v < low || v > high) {\n if (env->hflags & HF_MPX_EN_MASK) {\n env->bndcs_regs.sts = 0;\ndiff --git a/target/i386/tcg/mpx_helper.c b/target/i386/tcg/mpx_helper.c\nindex fa8abcc4820..73d33bf5e4a 100644\n--- a/target/i386/tcg/mpx_helper.c\n+++ b/target/i386/tcg/mpx_helper.c\n@@ -44,7 +44,7 @@ static uint64_t lookup_bte64(CPUX86State *env, uint64_t base, uintptr_t ra)\n }\n \n bde = (extract64(base, 20, 28) << 3) + (extract64(bndcsr, 20, 44) << 12);\n- bt = cpu_ldq_data_ra(env, bde, ra);\n+ bt = cpu_ldq_le_data_ra(env, bde, ra);\n if ((bt & 1) == 0) {\n env->bndcs_regs.sts = bde | 2;\n raise_exception_ra(env, EXCP05_BOUND, ra);\n@@ -64,7 +64,7 @@ static uint32_t lookup_bte32(CPUX86State *env, uint32_t base, uintptr_t ra)\n }\n \n bde = (extract32(base, 12, 20) << 2) + (bndcsr & TARGET_PAGE_MASK);\n- bt = cpu_ldl_data_ra(env, bde, ra);\n+ bt = cpu_ldl_le_data_ra(env, bde, ra);\n if ((bt & 1) == 0) {\n env->bndcs_regs.sts = bde | 2;\n raise_exception_ra(env, EXCP05_BOUND, ra);\n@@ -79,9 +79,9 @@ uint64_t helper_bndldx64(CPUX86State *env, target_ulong base, target_ulong ptr)\n uint64_t bte, lb, ub, pt;\n \n bte = lookup_bte64(env, base, ra);\n- lb = cpu_ldq_data_ra(env, bte, ra);\n- ub = cpu_ldq_data_ra(env, bte + 8, ra);\n- pt = cpu_ldq_data_ra(env, bte + 16, ra);\n+ lb = cpu_ldq_le_data_ra(env, bte, ra);\n+ ub = cpu_ldq_le_data_ra(env, bte + 8, ra);\n+ pt = cpu_ldq_le_data_ra(env, bte + 16, ra);\n \n if (pt != ptr) {\n lb = ub = 0;\n@@ -96,9 +96,9 @@ uint64_t helper_bndldx32(CPUX86State *env, target_ulong base, target_ulong ptr)\n uint32_t bte, lb, ub, pt;\n \n bte = lookup_bte32(env, base, ra);\n- lb = cpu_ldl_data_ra(env, bte, ra);\n- ub = cpu_ldl_data_ra(env, bte + 4, ra);\n- pt = cpu_ldl_data_ra(env, bte + 8, ra);\n+ lb = cpu_ldl_le_data_ra(env, bte, ra);\n+ ub = cpu_ldl_le_data_ra(env, bte + 4, ra);\n+ pt = cpu_ldl_le_data_ra(env, bte + 8, ra);\n \n if (pt != ptr) {\n lb = ub = 0;\n@@ -113,9 +113,9 @@ void helper_bndstx64(CPUX86State *env, target_ulong base, target_ulong ptr,\n uint64_t bte;\n \n bte = lookup_bte64(env, base, ra);\n- cpu_stq_data_ra(env, bte, lb, ra);\n- cpu_stq_data_ra(env, bte + 8, ub, ra);\n- cpu_stq_data_ra(env, bte + 16, ptr, ra);\n+ cpu_stq_le_data_ra(env, bte, lb, ra);\n+ cpu_stq_le_data_ra(env, bte + 8, ub, ra);\n+ cpu_stq_le_data_ra(env, bte + 16, ptr, ra);\n }\n \n void helper_bndstx32(CPUX86State *env, target_ulong base, target_ulong ptr,\n@@ -125,9 +125,9 @@ void helper_bndstx32(CPUX86State *env, target_ulong base, target_ulong ptr,\n uint32_t bte;\n \n bte = lookup_bte32(env, base, ra);\n- cpu_stl_data_ra(env, bte, lb, ra);\n- cpu_stl_data_ra(env, bte + 4, ub, ra);\n- cpu_stl_data_ra(env, bte + 8, ptr, ra);\n+ cpu_stl_le_data_ra(env, bte, lb, ra);\n+ cpu_stl_le_data_ra(env, bte + 4, ub, ra);\n+ cpu_stl_le_data_ra(env, bte + 8, ptr, ra);\n }\n \n void helper_bnd_jmp(CPUX86State *env)\ndiff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c\nindex 227336c4ef2..58aac720119 100644\n--- a/target/i386/tcg/seg_helper.c\n+++ b/target/i386/tcg/seg_helper.c\n@@ -65,20 +65,20 @@ typedef struct StackAccess\n static void pushw(StackAccess *sa, uint16_t val)\n {\n sa->sp -= 2;\n- cpu_stw_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask),\n+ cpu_stw_le_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask),\n val, sa->mmu_index, sa->ra);\n }\n \n static void pushl(StackAccess *sa, uint32_t val)\n {\n sa->sp -= 4;\n- cpu_stl_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask),\n+ cpu_stl_le_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask),\n val, sa->mmu_index, sa->ra);\n }\n \n static uint16_t popw(StackAccess *sa)\n {\n- uint16_t ret = cpu_lduw_mmuidx_ra(sa->env,\n+ uint16_t ret = cpu_lduw_le_mmuidx_ra(sa->env,\n sa->ss_base + (sa->sp & sa->sp_mask),\n sa->mmu_index, sa->ra);\n sa->sp += 2;\n@@ -87,7 +87,7 @@ static uint16_t popw(StackAccess *sa)\n \n static uint32_t popl(StackAccess *sa)\n {\n- uint32_t ret = cpu_ldl_mmuidx_ra(sa->env,\n+ uint32_t ret = cpu_ldl_le_mmuidx_ra(sa->env,\n sa->ss_base + (sa->sp & sa->sp_mask),\n sa->mmu_index, sa->ra);\n sa->sp += 4;\n@@ -905,12 +905,12 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,\n static void pushq(StackAccess *sa, uint64_t val)\n {\n sa->sp -= 8;\n- cpu_stq_mmuidx_ra(sa->env, sa->sp, val, sa->mmu_index, sa->ra);\n+ cpu_stq_le_mmuidx_ra(sa->env, sa->sp, val, sa->mmu_index, sa->ra);\n }\n \n static uint64_t popq(StackAccess *sa)\n {\n- uint64_t ret = cpu_ldq_mmuidx_ra(sa->env, sa->sp, sa->mmu_index, sa->ra);\n+ uint64_t ret = cpu_ldq_le_mmuidx_ra(sa->env, sa->sp, sa->mmu_index, sa->ra);\n sa->sp += 8;\n return ret;\n }\n@@ -1887,7 +1887,7 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,\n pushl(&sa, env->segs[R_SS].selector);\n pushl(&sa, env->regs[R_ESP]);\n for (i = param_count - 1; i >= 0; i--) {\n- val = cpu_ldl_data_ra(env,\n+ val = cpu_ldl_le_data_ra(env,\n old_ssp + ((env->regs[R_ESP] + i * 4) & old_sp_mask),\n GETPC());\n pushl(&sa, val);\n@@ -1896,7 +1896,7 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,\n pushw(&sa, env->segs[R_SS].selector);\n pushw(&sa, env->regs[R_ESP]);\n for (i = param_count - 1; i >= 0; i--) {\n- val = cpu_lduw_data_ra(env,\n+ val = cpu_lduw_le_data_ra(env,\n old_ssp + ((env->regs[R_ESP] + i * 2) & old_sp_mask),\n GETPC());\n pushw(&sa, val);\ndiff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/excp_helper.c\nindex f622b5d588e..d7ea77c8558 100644\n--- a/target/i386/tcg/system/excp_helper.c\n+++ b/target/i386/tcg/system/excp_helper.c\n@@ -90,7 +90,7 @@ static inline uint32_t ptw_ldl(const PTETranslate *in, uint64_t ra)\n if (likely(in->haddr)) {\n return ldl_p(in->haddr);\n }\n- return cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra);\n+ return cpu_ldl_le_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra);\n }\n \n static inline uint64_t ptw_ldq(const PTETranslate *in, uint64_t ra)\n@@ -98,7 +98,7 @@ static inline uint64_t ptw_ldq(const PTETranslate *in, uint64_t ra)\n if (likely(in->haddr)) {\n return ldq_p(in->haddr);\n }\n- return cpu_ldq_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra);\n+ return cpu_ldq_le_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra);\n }\n \n /*\n@@ -116,9 +116,9 @@ static bool ptw_setl_slow(const PTETranslate *in, uint32_t old, uint32_t new)\n cpu_exec_end(cpu);\n /* Does x86 really perform a rmw cycle on mmio for ptw? */\n start_exclusive();\n- cmp = cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0);\n+ cmp = cpu_ldl_le_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0);\n if (cmp == old) {\n- cpu_stl_mmuidx_ra(in->env, in->gaddr, new, in->ptw_idx, 0);\n+ cpu_stl_le_mmuidx_ra(in->env, in->gaddr, new, in->ptw_idx, 0);\n }\n end_exclusive();\n cpu_exec_start(cpu);\ndiff --git a/target/i386/tcg/system/svm_helper.c b/target/i386/tcg/system/svm_helper.c\nindex 524b3620d56..d5ffabc2f4d 100644\n--- a/target/i386/tcg/system/svm_helper.c\n+++ b/target/i386/tcg/system/svm_helper.c\n@@ -30,13 +30,13 @@\n static void svm_save_seg(CPUX86State *env, int mmu_idx, hwaddr addr,\n const SegmentCache *sc)\n {\n- cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector),\n+ cpu_stw_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector),\n sc->selector, mmu_idx, 0);\n- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base),\n+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base),\n sc->base, mmu_idx, 0);\n- cpu_stl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit),\n+ cpu_stl_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit),\n sc->limit, mmu_idx, 0);\n- cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib),\n+ cpu_stw_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib),\n ((sc->flags >> 8) & 0xff)\n | ((sc->flags >> 12) & 0x0f00),\n mmu_idx, 0);\n@@ -58,16 +58,16 @@ static void svm_load_seg(CPUX86State *env, int mmu_idx, hwaddr addr,\n unsigned int flags;\n \n sc->selector =\n- cpu_lduw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector),\n+ cpu_lduw_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector),\n mmu_idx, 0);\n sc->base =\n- cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base),\n+ cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base),\n mmu_idx, 0);\n sc->limit =\n- cpu_ldl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit),\n+ cpu_ldl_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit),\n mmu_idx, 0);\n flags =\n- cpu_lduw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib),\n+ cpu_lduw_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib),\n mmu_idx, 0);\n sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12);\n \n@@ -507,32 +507,35 @@ void helper_vmload(CPUX86State *env, int aflag)\n \n #ifdef TARGET_X86_64\n env->kernelgsbase =\n- cpu_ldq_mmuidx_ra(env,\n- addr + offsetof(struct vmcb, save.kernel_gs_base),\n- mmu_idx, 0);\n+ cpu_ldq_le_mmuidx_ra(env,\n+ addr + offsetof(struct vmcb, save.kernel_gs_base),\n+ mmu_idx, 0);\n env->lstar =\n- cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar),\n- mmu_idx, 0);\n+ cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar),\n+ mmu_idx, 0);\n env->cstar =\n- cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar),\n- mmu_idx, 0);\n+ cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar),\n+ mmu_idx, 0);\n env->fmask =\n- cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask),\n- mmu_idx, 0);\n+ cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask),\n+ mmu_idx, 0);\n svm_canonicalization(env, &env->kernelgsbase);\n #endif\n env->star =\n- cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star),\n- mmu_idx, 0);\n+ cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star),\n+ mmu_idx, 0);\n env->sysenter_cs =\n- cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_cs),\n- mmu_idx, 0);\n+ cpu_ldq_le_mmuidx_ra(env,\n+ addr + offsetof(struct vmcb, save.sysenter_cs),\n+ mmu_idx, 0);\n env->sysenter_esp =\n- cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_esp),\n- mmu_idx, 0);\n+ cpu_ldq_le_mmuidx_ra(env,\n+ addr + offsetof(struct vmcb, save.sysenter_esp),\n+ mmu_idx, 0);\n env->sysenter_eip =\n- cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_eip),\n- mmu_idx, 0);\n+ cpu_ldq_le_mmuidx_ra(env,\n+ addr + offsetof(struct vmcb, save.sysenter_eip),\n+ mmu_idx, 0);\n }\n \n void helper_vmsave(CPUX86State *env, int aflag)\n@@ -567,22 +570,22 @@ void helper_vmsave(CPUX86State *env, int aflag)\n &env->ldt);\n \n #ifdef TARGET_X86_64\n- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.kernel_gs_base),\n+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.kernel_gs_base),\n env->kernelgsbase, mmu_idx, 0);\n- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar),\n+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar),\n env->lstar, mmu_idx, 0);\n- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar),\n+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar),\n env->cstar, mmu_idx, 0);\n- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask),\n+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask),\n env->fmask, mmu_idx, 0);\n #endif\n- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star),\n+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star),\n env->star, mmu_idx, 0);\n- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_cs),\n+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_cs),\n env->sysenter_cs, mmu_idx, 0);\n- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_esp),\n+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_esp),\n env->sysenter_esp, mmu_idx, 0);\n- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_eip),\n+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_eip),\n env->sysenter_eip, mmu_idx, 0);\n }\n \n", "prefixes": [ "PULL", "v2", "01/37" ] }