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GET /api/patches/2180319/?format=api
{ "id": 2180319, "url": "http://patchwork.ozlabs.org/api/patches/2180319/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260106100331.1576758-1-vitaly.lifshits@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260106100331.1576758-1-vitaly.lifshits@intel.com>", "list_archive_url": null, "date": "2026-01-06T10:03:31", "name": "[iwl-next,v2,1/1] e1000e: correct TIMINCA on ADP/TGP systems with wrong XTAL frequency", "commit_ref": null, "pull_url": null, "state": "under-review", "archived": false, "hash": "f9d7c5a56c698f2da03f62beb2ed4ff69e329d25", "submitter": { "id": 76816, "url": "http://patchwork.ozlabs.org/api/people/76816/?format=api", "name": "Lifshits, Vitaly", "email": "vitaly.lifshits@intel.com" }, "delegate": { "id": 109701, "url": "http://patchwork.ozlabs.org/api/users/109701/?format=api", "username": "anguy11", "first_name": "Anthony", "last_name": "Nguyen", "email": "anthony.l.nguyen@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260106100331.1576758-1-vitaly.lifshits@intel.com/mbox/", "series": [ { "id": 487305, "url": "http://patchwork.ozlabs.org/api/series/487305/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=487305", "date": "2026-01-06T10:03:31", "name": "[iwl-next,v2,1/1] e1000e: correct TIMINCA on ADP/TGP systems with wrong XTAL frequency", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/487305/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2180319/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2180319/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=NfkZTxAL;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::138; 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envelope-from=intel-wired-lan-bounces@osuosl.org;\n receiver=<UNKNOWN> ", "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 smtp1.osuosl.org C06E9812E4", "OpenDKIM Filter v2.11.0 smtp2.osuosl.org D2C22400B4" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=osuosl.org;\n\ts=default; t=1767693821;\n\tbh=jSb2OYdJtpKAfQts6LguslBkUBsGM0l/U9xvlyPJifE=;\n\th=From:To:Cc:Date:Subject:List-Id:List-Unsubscribe:List-Archive:\n\t List-Post:List-Help:List-Subscribe:From;\n\tb=NfkZTxALEdu6cfk+LeYI/W5Vjf71fQmkgt/K0CDc5r6oHHITEzN+W3CK/2+Ecbm1A\n\t 9rNqeEyr5/zw6cAZ+hPmN9zGuV1Q2yp7n+FzBfYMQQeLVr1X01fNvB69U+N79ZwtL3\n\t oGVSwvlhWhSfwtxRPGclmZrdT+gFQXhYdhtSEcJVcVY6VyFgzodRLwx25E99nNFN5l\n\t nEaxs8m+qcHXoom2SIXf6QIrQqmPV0GaRHsu1IA/lVyfXKWkOxdpfY34umPR3nx//r\n\t 3/N7ZJUiIrZjiSB+WR9ZIKKfr+1HWqArMpenTwG9toPBwvTfPiPvL9WZgVPsJam+aP\n\t tYG8tCuzmmcEw==", "Received-SPF": "Pass (mailfrom) identity=mailfrom; client-ip=198.175.65.21;\n helo=mgamail.intel.com; envelope-from=vitaly.lifshits@intel.com;\n receiver=<UNKNOWN>", "DMARC-Filter": "OpenDMARC Filter v1.4.2 smtp2.osuosl.org D2C22400B4", "X-CSE-ConnectionGUID": [ "74phauFyQfuusi5bRMNb+Q==", "Hx0DuYACQb+1QBD2mGHkGQ==" ], "X-CSE-MsgGUID": [ "7/7C4iWeRUakorAUx15msw==", "nDT6hl4fSg6oNZHVIxVxDQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11635\"; a=\"68993759\"", "E=Sophos;i=\"6.20,256,1758610800\"; d=\"scan'208\";a=\"68993759\"", "E=Sophos;i=\"6.21,204,1763452800\"; d=\"scan'208\";a=\"203585220\"" ], "X-ExtLoop1": "1", "From": "Vitaly Lifshits <vitaly.lifshits@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Cc": "Vitaly Lifshits <vitaly.lifshits@intel.com>", "Date": "Tue, 6 Jan 2026 12:03:31 +0200", "Message-Id": "<20260106100331.1576758-1-vitaly.lifshits@intel.com>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Mailman-Original-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1767693820; x=1799229820;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=5ybJSR4lnIApWjrLPbPlCKR4LZOnVpHacMcFdFXFhDk=;\n b=Cm8txLs61lV7Iak273ffOFvuINzDCQYBe3m1yX9a/1j6VWOWuR5/WzMH\n O247QsIif0FGya4mJYdlOQD/1nwnfPmMRkvC9WU9DpC9bYjKtt6C7qyXl\n m8r1L2q0VGrFUrUA/SUt5BTPNVjJBeQ0wDKkqx36kCYAheI7Ad97XNH0b\n wSNwsXpTSgRV2jn2JJn19VyFr/ppM+9tVv13xldcIIDjvun0+J5h0FKhz\n IwAL/mZkD80s+W4CzAmNYh8zilPGnHll1ILvVLNX62xip/PvyoxOK8TVu\n 2ERKPlNDjLcwd/94o+vMOM2M2OghtPVDg5belqD4MqU/pk0jsNThEbRq7\n w==;", "X-Mailman-Original-Authentication-Results": [ "smtp2.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com", "smtp2.osuosl.org;\n dkim=pass (2048-bit key,\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=Cm8txLs6" ], "Subject": "[Intel-wired-lan] [PATCH iwl-next v2 1/1] e1000e: correct TIMINCA\n on ADP/TGP systems with wrong XTAL frequency", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n <intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "On some Tiger Lake (TGP) and Alder Lake (ADP) platforms, the hardware\nXTAL clock is incorrectly interpreted as 24 MHz instead of the actual\n38.4 MHz. This causes the PHC to run significantly faster than system\ntime, breaking PTP synchronization.\n\nTo mitigate this at runtime, measure PHC vs system time over ~1 ms using\ncross-timestamps. If the PHC increment differs from system time beyond\nthe expected tolerance (currently >100 uSecs), reprogram TIMINCA for the\n38.4 MHz profile and reinitialize the timecounter.\n\nTested on an affected system using phc_ctl:\nWithout fix:\nsudo phc_ctl enp0s31f6 set 0.0 wait 10 get\nclock time: 16.000541250 (expected ~10s)\n\nWith fix:\nsudo phc_ctl enp0s31f6 set 0.0 wait 10 get\nclock time: 9.984407212 (expected ~10s)\n\nSigned-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com>\n---\nv2: avoid resetting the systim and rephrase commit message\nv1: initial version\n---\n drivers/net/ethernet/intel/e1000e/netdev.c | 80 ++++++++++++++++++++++\n 1 file changed, 80 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c\nindex 116f3c92b5bc..edb72054d0d9 100644\n--- a/drivers/net/ethernet/intel/e1000e/netdev.c\n+++ b/drivers/net/ethernet/intel/e1000e/netdev.c\n@@ -3904,6 +3904,83 @@ static void e1000_flush_desc_rings(struct e1000_adapter *adapter)\n \t\te1000_flush_rx_ring(adapter);\n }\n \n+/**\n+ * e1000e_xtal_tgp_workaround - Adjust XTAL clock based on PHC and system\n+ * clock delta.\n+ *\n+ * Measures the time difference between the PHC (Precision Hardware Clock)\n+ * and the system clock over a 1 millisecond interval. If the delta\n+ * exceeds 100 microseconds, reconfigure the XTAL clock to 38.4 MHz.\n+ *\n+ * @adapter: Pointer to the private adapter structure\n+ **/\n+static void e1000e_xtal_tgp_workaround(struct e1000_adapter *adapter)\n+{\n+\ts64 phc_delta, sys_delta, sys_start_ns, sys_end_ns, delta_ns;\n+\tstruct ptp_system_timestamp sys_start = {}, sys_end = {};\n+\tstruct ptp_clock_info *info = &adapter->ptp_clock_info;\n+\tstruct timespec64 phc_start, phc_end;\n+\tstruct e1000_hw *hw = &adapter->hw;\n+\tstruct netlink_ext_ack extack = {};\n+\tunsigned long flags;\n+\tu32 timinca;\n+\ts32 ret_val;\n+\n+\t/* Capture start */\n+\tif (info->gettimex64(info, &phc_start, &sys_start)) {\n+\t\te_dbg(\"PHC gettimex(start) failed\\n\");\n+\t\treturn;\n+\t}\n+\n+\t/* Small interval to measure increment */\n+\tusleep_range(1000, 1100);\n+\n+\t/* Capture end */\n+\tif (info->gettimex64(info, &phc_end, &sys_end)) {\n+\t\te_dbg(\"PHC gettimex(end) failed\\n\");\n+\t\treturn;\n+\t}\n+\n+\t/* Compute deltas */\n+\tphc_delta = timespec64_to_ns(&phc_end) -\n+\t\t timespec64_to_ns(&phc_start);\n+\n+\tsys_start_ns = (timespec64_to_ns(&sys_start.pre_ts) +\n+\t\t\ttimespec64_to_ns(&sys_start.post_ts)) >> 1;\n+\n+\tsys_end_ns = (timespec64_to_ns(&sys_end.pre_ts) +\n+\t\t timespec64_to_ns(&sys_end.post_ts)) >> 1;\n+\n+\tsys_delta = sys_end_ns - sys_start_ns;\n+\n+\tdelta_ns = phc_delta - sys_delta;\n+\tif (delta_ns > 100000) {\n+\t\te_dbg(\"Corrected PHC frequency: TIMINCA set for 38.4 MHz\\n\");\n+\t\t/* Program TIMINCA for 38.4 MHz */\n+\t\ttiminca = (INCPERIOD_38400KHZ <<\n+\t\t\t E1000_TIMINCA_INCPERIOD_SHIFT) |\n+\t\t\t (((INCVALUE_38400KHZ <<\n+\t\t\t adapter->cc.shift) &\n+\t\t\t E1000_TIMINCA_INCVALUE_MASK));\n+\t\tew32(TIMINCA, timinca);\n+\n+\t\t/* reset the systim ns time counter */\n+\t\tspin_lock_irqsave(&adapter->systim_lock, flags);\n+\t\ttimecounter_init(&adapter->tc, &adapter->cc,\n+\t\t\t\t ktime_to_ns(ktime_get_real()));\n+\t\tspin_unlock_irqrestore(&adapter->systim_lock, flags);\n+\n+\t\t/* restore the previous hwtstamp configuration settings */\n+\t\tret_val = e1000e_config_hwtstamp(adapter,\n+\t\t\t\t\t\t &adapter->hwtstamp_config,\n+\t\t\t\t\t\t &extack);\n+\t\tif (ret_val) {\n+\t\t\tif (extack._msg)\n+\t\t\t\te_err(\"%s\\n\", extack._msg);\n+\t\t}\n+\t}\n+}\n+\n /**\n * e1000e_systim_reset - reset the timesync registers after a hardware reset\n * @adapter: board private structure\n@@ -3955,6 +4032,9 @@ static void e1000e_systim_reset(struct e1000_adapter *adapter)\n \t\tif (extack._msg)\n \t\t\te_err(\"%s\\n\", extack._msg);\n \t}\n+\n+\tif (hw->mac.type == e1000_pch_adp || hw->mac.type == e1000_pch_tgp)\n+\t\treturn e1000e_xtal_tgp_workaround(adapter);\n }\n \n /**\n", "prefixes": [ "iwl-next", "v2", "1/1" ] }