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GET /api/patches/2178802/?format=api
{ "id": 2178802, "url": "http://patchwork.ozlabs.org/api/patches/2178802/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20251230210633.501526-1-robert.marko@sartura.hr/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20251230210633.501526-1-robert.marko@sartura.hr>", "list_archive_url": null, "date": "2025-12-30T21:06:03", "name": "net: add Microsemi/Microchip MDIO driver", "commit_ref": "dfc39f9caf3c1a5e56a6c2b65b3bee83736e29d8", "pull_url": null, "state": "accepted", "archived": false, "hash": "b1f93da9849b830d53f51f8423fbd3fd50d8f679", "submitter": { "id": 78207, "url": "http://patchwork.ozlabs.org/api/people/78207/?format=api", "name": "Robert Marko", "email": "robert.marko@sartura.hr" }, "delegate": { "id": 157425, "url": "http://patchwork.ozlabs.org/api/users/157425/?format=api", "username": "jforissier", "first_name": "Jerome", "last_name": "Forissier", "email": "jerome.forissier@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20251230210633.501526-1-robert.marko@sartura.hr/mbox/", "series": [ { "id": 486798, "url": "http://patchwork.ozlabs.org/api/series/486798/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=486798", "date": "2025-12-30T21:06:03", "name": "net: add Microsemi/Microchip MDIO driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/486798/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2178802/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2178802/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sartura.hr header.i=@sartura.hr header.a=rsa-sha256\n header.s=sartura header.b=BSrHLQuE;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=sartura.hr", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sartura.hr header.i=@sartura.hr header.b=\"BSrHLQuE\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=sartura.hr", "phobos.denx.de;\n spf=pass smtp.mailfrom=robert.marko@sartura.hr" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dglyK0PjXz1xpS\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 31 Dec 2025 08:06:49 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 4239083FCF;\n\tTue, 30 Dec 2025 22:06:46 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id ABED783FD3; Tue, 30 Dec 2025 22:06:45 +0100 (CET)", "from mail-wm1-x329.google.com (mail-wm1-x329.google.com\n [IPv6:2a00:1450:4864:20::329])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id ACAB583FA4\n for <u-boot@lists.denx.de>; Tue, 30 Dec 2025 22:06:43 +0100 (CET)", "by mail-wm1-x329.google.com with SMTP id\n 5b1f17b1804b1-47796a837c7so66502385e9.0\n for <u-boot@lists.denx.de>; Tue, 30 Dec 2025 13:06:43 -0800 (PST)", "from fedora (cpezg-94-253-146-116-cbl.xnet.hr. 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The driver\n \t currently supports Clause 22.\n \n+config MDIO_MSCC_MIIM\n+\tbool \"Microsemi MIIM interface support\"\n+\tdepends on DM_MDIO\n+\tselect REGMAP\n+\thelp\n+\t\tThis driver supports MDIO interface found in Microsemi and Microchip\n+\t\tnetwork switches.\n+\n config MDIO_MUX_MMIOREG\n \tbool \"MDIO MUX accessed as a MMIO register access\"\n \tdepends on DM_MDIO_MUX\ndiff --git a/drivers/net/Makefile b/drivers/net/Makefile\nindex a3c3420898c..5bb40480d88 100644\n--- a/drivers/net/Makefile\n+++ b/drivers/net/Makefile\n@@ -62,6 +62,7 @@ obj-$(CONFIG_LITEETH) += liteeth.o\n obj-$(CONFIG_MACB) += macb.o\n obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o\n obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o\n+obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o\n obj-$(CONFIG_MDIO_GPIO_BITBANG) += mdio_gpio.o\n obj-$(CONFIG_MDIO_MT7531_MMIO) += mdio-mt7531-mmio.o\n obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o\ndiff --git a/drivers/net/mdio-mscc-miim.c b/drivers/net/mdio-mscc-miim.c\nnew file mode 100644\nindex 00000000000..5700b872586\n--- /dev/null\n+++ b/drivers/net/mdio-mscc-miim.c\n@@ -0,0 +1,136 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+\n+#include <asm/io.h>\n+#include <dm.h>\n+#include <time.h>\n+#include <regmap.h>\n+#include <miiphy.h>\n+#include <linux/bitfield.h>\n+\n+#define MSCC_MIIM_REG_STATUS\t\t0x0\n+#define\t\tMSCC_MIIM_STATUS_STAT_PENDING\tBIT(2)\n+#define\t\tMSCC_MIIM_STATUS_STAT_BUSY\tBIT(3)\n+#define MSCC_MIIM_REG_CMD\t\t0x8\n+#define\t\tMSCC_MIIM_CMD_OPR_WRITE\t\tBIT(1)\n+#define\t\tMSCC_MIIM_CMD_OPR_READ\t\tBIT(2)\n+#define\t\tMSCC_MIIM_CMD_WRDATA_SHIFT\t4\n+#define\t\tMSCC_MIIM_CMD_REGAD_SHIFT\t20\n+#define\t\tMSCC_MIIM_CMD_PHYAD_SHIFT\t25\n+#define\t\tMSCC_MIIM_CMD_VLD\t\tBIT(31)\n+#define MSCC_MIIM_REG_DATA\t\t0xC\n+#define\t\tMSCC_MIIM_DATA_ERROR\t\t(BIT(16) | BIT(17))\n+#define\t\tMSCC_MIIM_DATA_MASK\t\tGENMASK(15, 0)\n+#define MSCC_MIIM_REG_CFG\t\t0x10\n+#define\t\tMSCC_MIIM_CFG_PRESCALE_MASK\tGENMASK(7, 0)\n+/* 01 = Clause 22, 00 = Clause 45 */\n+#define\t\tMSCC_MIIM_CFG_ST_CFG_MASK\tGENMASK(10, 9)\n+#define\t\tMSCC_MIIM_C22\t\t\t1\n+#define\t\tMSCC_MIIM_C45\t\t\t0\n+\n+#define MSCC_MDIO_TIMEOUT 10000\n+#define MSCC_MDIO_SLEEP 50\n+\n+struct mscc_mdio_priv {\n+\tstruct regmap *map;\n+};\n+\n+static int mscc_mdio_wait_busy(struct mscc_mdio_priv *priv)\n+{\n+\tu32 busy;\n+\n+\treturn regmap_read_poll_timeout(priv->map, MSCC_MIIM_REG_STATUS, busy,\n+\t\t\t\t (busy & MSCC_MIIM_STATUS_STAT_BUSY) == 0,\n+\t\t\t\t MSCC_MDIO_SLEEP,\n+\t\t\t\t MSCC_MDIO_TIMEOUT);\n+}\n+\n+static int mscc_mdio_read(struct udevice *dev, int addr, int devad, int reg)\n+{\n+\tstruct mscc_mdio_priv *priv = dev_get_priv(dev);\n+\tu32 val;\n+\tint ret;\n+\n+\tif (mscc_mdio_wait_busy(priv))\n+\t\treturn -ETIMEDOUT;\n+\n+\tret = regmap_write(priv->map, MSCC_MIIM_REG_CMD,\n+\t\t\t MSCC_MIIM_CMD_VLD |\n+\t\t\t (addr << MSCC_MIIM_CMD_PHYAD_SHIFT) |\n+\t\t\t (reg << MSCC_MIIM_CMD_REGAD_SHIFT) |\n+\t\t\t MSCC_MIIM_CMD_OPR_READ);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (mscc_mdio_wait_busy(priv))\n+\t\treturn -ETIMEDOUT;\n+\n+\tregmap_read(priv->map, MSCC_MIIM_REG_DATA, &val);\n+\tif (val & MSCC_MIIM_DATA_ERROR)\n+\t\treturn -EIO;\n+\n+\treturn FIELD_GET(MSCC_MIIM_DATA_MASK, val);\n+}\n+\n+int mscc_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 val)\n+{\n+\tstruct mscc_mdio_priv *priv = dev_get_priv(dev);\n+\tint ret;\n+\n+\tif (mscc_mdio_wait_busy(priv))\n+\t\treturn -ETIMEDOUT;\n+\n+\tret = regmap_write(priv->map, MSCC_MIIM_REG_CMD,\n+\t\t\t MSCC_MIIM_CMD_VLD |\n+\t\t\t (addr << MSCC_MIIM_CMD_PHYAD_SHIFT) |\n+\t\t\t (reg << MSCC_MIIM_CMD_REGAD_SHIFT) |\n+\t\t\t (val << MSCC_MIIM_CMD_WRDATA_SHIFT) |\n+\t\t\t MSCC_MIIM_CMD_OPR_WRITE);\n+\n+\treturn ret;\n+}\n+\n+static const struct mdio_ops mscc_mdio_ops = {\n+\t.read = mscc_mdio_read,\n+\t.write = mscc_mdio_write,\n+};\n+\n+static int mscc_mdio_bind(struct udevice *dev)\n+{\n+\tif (ofnode_valid(dev_ofnode(dev)))\n+\t\tdevice_set_name(dev, ofnode_get_name(dev_ofnode(dev)));\n+\n+\treturn 0;\n+}\n+\n+static int mscc_mdio_probe(struct udevice *dev)\n+{\n+\tstruct mscc_mdio_priv *priv = dev_get_priv(dev);\n+\tint ret;\n+\n+\tret = regmap_init_mem(dev_ofnode(dev), &priv->map);\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\n+\t/* Enter Clause 22 mode */\n+\tret = regmap_update_bits(priv->map, MSCC_MIIM_REG_CFG,\n+\t\t\t\t MSCC_MIIM_CFG_ST_CFG_MASK,\n+\t\t\t\t FIELD_PREP(MSCC_MIIM_CFG_ST_CFG_MASK,\n+\t\t\t\t\t MSCC_MIIM_C22));\n+\n+\treturn ret;\n+}\n+\n+static const struct udevice_id mscc_mdio_ids[] = {\n+\t{ .compatible = \"mscc,ocelot-miim\", },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(mscc_mdio) = {\n+\t.name = \"mscc_mdio\",\n+\t.id = UCLASS_MDIO,\n+\t.of_match = mscc_mdio_ids,\n+\t.bind = mscc_mdio_bind,\n+\t.probe = mscc_mdio_probe,\n+\t.ops = &mscc_mdio_ops,\n+\t.priv_auto\t = sizeof(struct mscc_mdio_priv),\n+};\n", "prefixes": [] }