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GET /api/patches/2175987/?format=api
{ "id": 2175987, "url": "http://patchwork.ozlabs.org/api/patches/2175987/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20251219161559.556737-4-arnd@kernel.org/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20251219161559.556737-4-arnd@kernel.org>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20251219161559.556737-4-arnd@kernel.org/", "date": "2025-12-19T16:15:58", "name": "[3/4] ARM: remove support for highmem on VIVT", "commit_ref": null, "pull_url": null, "state": "handled-elsewhere", "archived": false, "hash": "9e0c8f3c1cbe26157c00d32ad7d07586f6897ca9", "submitter": { "id": 80402, "url": "http://patchwork.ozlabs.org/api/people/80402/?format=api", "name": "Arnd Bergmann", "email": "arnd@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20251219161559.556737-4-arnd@kernel.org/mbox/", "series": [ { "id": 486021, "url": "http://patchwork.ozlabs.org/api/series/486021/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=486021", "date": "2025-12-19T16:15:56", "name": "mm: increase lowmem size in linux-7.0", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/486021/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2175987/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2175987/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linuxppc-dev+bounces-14907-incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=tWFoP8Zs;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1766161011;\n\tbh=n8EL94QbXkjpZrKNco8jY54zTJbVUAiuP3D8k2SB3mU=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=tWFoP8ZsYkLEYCvizSOtfAaPNjhLJqzsaF7tHY3aqA7oUXtgJO3ERCYDqUD2Js3e+\n\t 5R5GQI33x+FNwMdA3E8CZJRT4GQ969i4oVXw80U8LK3ks+idDCR+70rd4jVj2rwHCu\n\t kssBP+UXAx1ooEXkfFjs0SmM6fYabVLEw6M6l6N0xvkWoXGdt/rIfFA2d216ZHS3cB\n\t FIZAc5TXF6+EHaLenImHZnM9YLo5PcMNwpzayFQHJhxsfFSftTUlPHdETPa3CUsJPF\n\t iGSBq0GmTIUzJkVMbAliGgGFOFRDBxBcKxHux2RePNHcYTYv3akMLZY0VVzM6zGNv8\n\t fCH3UMvStvSpg==", "From": "Arnd Bergmann <arnd@kernel.org>", "To": "linux-mm@kvack.org", "Cc": "Arnd Bergmann <arnd@arndb.de>,\n\tAndrew Morton <akpm@linux-foundation.org>,\n\tAndreas Larsson <andreas@gaisler.com>,\n\tChristophe Leroy <chleroy@kernel.org>,\n\tDave Hansen <dave.hansen@linux.intel.com>,\n\tJason Gunthorpe <jgg@nvidia.com>,\n\tLinus Walleij <linus.walleij@linaro.org>,\n\tMatthew Wilcox <willy@infradead.org>,\n\tRichard Weinberger <richard@nod.at>,\n\tRussell King <linux@armlinux.org.uk>,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-fsdevel@vger.kernel.org,\n\tlinuxppc-dev@lists.ozlabs.org,\n\tx86@kernel.org", "Subject": "[PATCH 3/4] ARM: remove support for highmem on VIVT", "Date": "Fri, 19 Dec 2025 17:15:58 +0100", "Message-Id": "<20251219161559.556737-4-arnd@kernel.org>", "X-Mailer": "git-send-email 2.39.5", "In-Reply-To": "<20251219161559.556737-1-arnd@kernel.org>", "References": "<20251219161559.556737-1-arnd@kernel.org>", "X-Mailing-List": "linuxppc-dev@lists.ozlabs.org", "List-Id": "<linuxppc-dev.lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev+help@lists.ozlabs.org>", "List-Owner": "<mailto:linuxppc-dev+owner@lists.ozlabs.org>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Archive": "<https://lore.kernel.org/linuxppc-dev/>,\n <https://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Subscribe": "<mailto:linuxppc-dev+subscribe@lists.ozlabs.org>,\n <mailto:linuxppc-dev+subscribe-digest@lists.ozlabs.org>,\n <mailto:linuxppc-dev+subscribe-nomail@lists.ozlabs.org>", "List-Unsubscribe": "<mailto:linuxppc-dev+unsubscribe@lists.ozlabs.org>", "Precedence": "list", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Spam-Status": "No, score=-0.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED,\n\tDKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS\n\tautolearn=disabled version=4.0.1 OzLabs 8", "X-Spam-Checker-Version": "SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org" }, "content": "From: Arnd Bergmann <arnd@arndb.de>\n\nAs Jason Gunthorpe noticed, supporting VIVT caches adds some complications\nto highmem that can be avoided these days:\n\nWhile all ARMv4 and ARMv5 CPUs use virtually indexed caches, they no\nlonger really need highmem because we have practically discontinued\nsupport for large-memory configurations already. The only machines I\ncould find anywhere for memory on ARMv5 are:\n\n - The Intel IOP platform was used on relatively large memory\n configurations but we dropped kernel support in 2019 and 2022,\n respectively.\n\n - The Marvell mv78xx0 platform was the initial user of Arm highmem,\n with the DB-78x00-BP supporting 2GB of memory. While the platform\n is still around, the only remaining board file is for\n Buffalo WLX (Terastation Duo), which has only 512MB.\n\n - The Kirkwood platform supports 2GB, and there are actually boards\n with that configuration that can still work. However, there are\n no known users of the OpenBlocks A7, and the Freebox V6 is already\n using CONFIG_VMSPLIT_2G to avoid enabling highmem.\n\nRemove the Arm specific portions here, making CONFIG_HIGHMEM conditional\non modern caches.\n\nSuggested-by: Jason Gunthorpe <jgg@nvidia.com>\nSigned-off-by: Arnd Bergmann <arnd@arndb.de>\n---\n arch/arm/Kconfig | 1 +\n arch/arm/configs/gemini_defconfig | 1 -\n arch/arm/configs/multi_v5_defconfig | 1 -\n arch/arm/configs/mvebu_v5_defconfig | 1 -\n arch/arm/include/asm/highmem.h | 56 ++---------------------------\n arch/arm/mm/cache-feroceon-l2.c | 31 ++--------------\n arch/arm/mm/cache-xsc3l2.c | 47 +++---------------------\n arch/arm/mm/dma-mapping.c | 12 ++-----\n arch/arm/mm/flush.c | 19 +++-------\n 9 files changed, 16 insertions(+), 153 deletions(-)", "diff": "diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\nindex 921ea61aa96e..790897a457d4 100644\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -1204,6 +1204,7 @@ config ARCH_SPARSEMEM_ENABLE\n config HIGHMEM\n \tbool \"High Memory Support\"\n \tdepends on MMU\n+\tdepends on !CPU_CACHE_VIVT\n \tselect KMAP_LOCAL\n \tselect KMAP_LOCAL_NON_LINEAR_PTE_ARRAY\n \thelp\ndiff --git a/arch/arm/configs/gemini_defconfig b/arch/arm/configs/gemini_defconfig\nindex 7b1daec630cb..1bb4f47ea3c8 100644\n--- a/arch/arm/configs/gemini_defconfig\n+++ b/arch/arm/configs/gemini_defconfig\n@@ -12,7 +12,6 @@ CONFIG_ARCH_MULTI_V4=y\n # CONFIG_ARCH_MULTI_V7 is not set\n CONFIG_ARCH_GEMINI=y\n CONFIG_AEABI=y\n-CONFIG_HIGHMEM=y\n CONFIG_CMDLINE=\"console=ttyS0,115200n8\"\n CONFIG_PM=y\n CONFIG_PARTITION_ADVANCED=y\ndiff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig\nindex 59b020e66a0b..5106fc2d2a00 100644\n--- a/arch/arm/configs/multi_v5_defconfig\n+++ b/arch/arm/configs/multi_v5_defconfig\n@@ -37,7 +37,6 @@ CONFIG_MACH_MSS2_DT=y\n CONFIG_ARCH_SUNXI=y\n CONFIG_ARCH_VERSATILE=y\n CONFIG_AEABI=y\n-CONFIG_HIGHMEM=y\n CONFIG_ARM_APPENDED_DTB=y\n CONFIG_ARM_ATAG_DTB_COMPAT=y\n CONFIG_CPU_FREQ=y\ndiff --git a/arch/arm/configs/mvebu_v5_defconfig b/arch/arm/configs/mvebu_v5_defconfig\nindex d1742a7cae6a..ba17bd3237fb 100644\n--- a/arch/arm/configs/mvebu_v5_defconfig\n+++ b/arch/arm/configs/mvebu_v5_defconfig\n@@ -24,7 +24,6 @@ CONFIG_MACH_D2NET_DT=y\n CONFIG_MACH_NET2BIG=y\n CONFIG_MACH_MSS2_DT=y\n CONFIG_AEABI=y\n-CONFIG_HIGHMEM=y\n CONFIG_ARM_APPENDED_DTB=y\n CONFIG_ARM_ATAG_DTB_COMPAT=y\n CONFIG_CPU_FREQ=y\ndiff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h\nindex bdb209e002a4..67ed46d1922b 100644\n--- a/arch/arm/include/asm/highmem.h\n+++ b/arch/arm/include/asm/highmem.h\n@@ -11,66 +11,14 @@\n #define PKMAP_NR(virt)\t\t(((virt) - PKMAP_BASE) >> PAGE_SHIFT)\n #define PKMAP_ADDR(nr)\t\t(PKMAP_BASE + ((nr) << PAGE_SHIFT))\n \n-#define flush_cache_kmaps() \\\n-\tdo { \\\n-\t\tif (cache_is_vivt()) \\\n-\t\t\tflush_cache_all(); \\\n-\t} while (0)\n+#define flush_cache_kmaps() do { } while (0)\n \n extern pte_t *pkmap_page_table;\n \n-/*\n- * The reason for kmap_high_get() is to ensure that the currently kmap'd\n- * page usage count does not decrease to zero while we're using its\n- * existing virtual mapping in an atomic context. With a VIVT cache this\n- * is essential to do, but with a VIPT cache this is only an optimization\n- * so not to pay the price of establishing a second mapping if an existing\n- * one can be used. However, on platforms without hardware TLB maintenance\n- * broadcast, we simply cannot use ARCH_NEEDS_KMAP_HIGH_GET at all since\n- * the locking involved must also disable IRQs which is incompatible with\n- * the IPI mechanism used by global TLB operations.\n- */\n-#define ARCH_NEEDS_KMAP_HIGH_GET\n-#if defined(CONFIG_SMP) && defined(CONFIG_CPU_TLB_V6)\n-#undef ARCH_NEEDS_KMAP_HIGH_GET\n-#if defined(CONFIG_HIGHMEM) && defined(CONFIG_CPU_CACHE_VIVT)\n-#error \"The sum of features in your kernel config cannot be supported together\"\n-#endif\n-#endif\n-\n-/*\n- * Needed to be able to broadcast the TLB invalidation for kmap.\n- */\n-#ifdef CONFIG_ARM_ERRATA_798181\n-#undef ARCH_NEEDS_KMAP_HIGH_GET\n-#endif\n-\n-#ifdef ARCH_NEEDS_KMAP_HIGH_GET\n-extern void *kmap_high_get(const struct page *page);\n-\n-static inline void *arch_kmap_local_high_get(const struct page *page)\n-{\n-\tif (IS_ENABLED(CONFIG_DEBUG_HIGHMEM) && !cache_is_vivt())\n-\t\treturn NULL;\n-\treturn kmap_high_get(page);\n-}\n-#define arch_kmap_local_high_get arch_kmap_local_high_get\n-\n-#else /* ARCH_NEEDS_KMAP_HIGH_GET */\n-static inline void *kmap_high_get(const struct page *page)\n-{\n-\treturn NULL;\n-}\n-#endif /* !ARCH_NEEDS_KMAP_HIGH_GET */\n-\n #define arch_kmap_local_post_map(vaddr, pteval)\t\t\t\t\\\n \tlocal_flush_tlb_kernel_page(vaddr)\n \n-#define arch_kmap_local_pre_unmap(vaddr)\t\t\t\t\\\n-do {\t\t\t\t\t\t\t\t\t\\\n-\tif (cache_is_vivt())\t\t\t\t\t\t\\\n-\t\t__cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE);\t\\\n-} while (0)\n+#define arch_kmap_local_pre_unmap(vaddr) do { } while (0)\n \n #define arch_kmap_local_post_unmap(vaddr)\t\t\t\t\\\n \tlocal_flush_tlb_kernel_page(vaddr)\ndiff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c\nindex 2bfefb252ffd..1316b6ab295a 100644\n--- a/arch/arm/mm/cache-feroceon-l2.c\n+++ b/arch/arm/mm/cache-feroceon-l2.c\n@@ -12,7 +12,6 @@\n #include <linux/init.h>\n #include <linux/of.h>\n #include <linux/of_address.h>\n-#include <linux/highmem.h>\n #include <linux/io.h>\n #include <asm/cacheflush.h>\n #include <asm/cp15.h>\n@@ -38,30 +37,6 @@\n * between which we don't want to be preempted.\n */\n \n-static inline unsigned long l2_get_va(unsigned long paddr)\n-{\n-#ifdef CONFIG_HIGHMEM\n-\t/*\n-\t * Because range ops can't be done on physical addresses,\n-\t * we simply install a virtual mapping for it only for the\n-\t * TLB lookup to occur, hence no need to flush the untouched\n-\t * memory mapping afterwards (note: a cache flush may happen\n-\t * in some circumstances depending on the path taken in kunmap_atomic).\n-\t */\n-\tvoid *vaddr = kmap_atomic_pfn(paddr >> PAGE_SHIFT);\n-\treturn (unsigned long)vaddr + (paddr & ~PAGE_MASK);\n-#else\n-\treturn __phys_to_virt(paddr);\n-#endif\n-}\n-\n-static inline void l2_put_va(unsigned long vaddr)\n-{\n-#ifdef CONFIG_HIGHMEM\n-\tkunmap_atomic((void *)vaddr);\n-#endif\n-}\n-\n static inline void l2_clean_pa(unsigned long addr)\n {\n \t__asm__(\"mcr p15, 1, %0, c15, c9, 3\" : : \"r\" (addr));\n@@ -78,14 +53,13 @@ static inline void l2_clean_pa_range(unsigned long start, unsigned long end)\n \t */\n \tBUG_ON((start ^ end) >> PAGE_SHIFT);\n \n-\tva_start = l2_get_va(start);\n+\tva_start = __phys_to_virt(start);\n \tva_end = va_start + (end - start);\n \traw_local_irq_save(flags);\n \t__asm__(\"mcr p15, 1, %0, c15, c9, 4\\n\\t\"\n \t\t\"mcr p15, 1, %1, c15, c9, 5\"\n \t\t: : \"r\" (va_start), \"r\" (va_end));\n \traw_local_irq_restore(flags);\n-\tl2_put_va(va_start);\n }\n \n static inline void l2_clean_inv_pa(unsigned long addr)\n@@ -109,14 +83,13 @@ static inline void l2_inv_pa_range(unsigned long start, unsigned long end)\n \t */\n \tBUG_ON((start ^ end) >> PAGE_SHIFT);\n \n-\tva_start = l2_get_va(start);\n+\tva_start = __phys_to_virt(start);\n \tva_end = va_start + (end - start);\n \traw_local_irq_save(flags);\n \t__asm__(\"mcr p15, 1, %0, c15, c11, 4\\n\\t\"\n \t\t\"mcr p15, 1, %1, c15, c11, 5\"\n \t\t: : \"r\" (va_start), \"r\" (va_end));\n \traw_local_irq_restore(flags);\n-\tl2_put_va(va_start);\n }\n \n static inline void l2_inv_all(void)\ndiff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c\nindex d20d7af02d10..477077387039 100644\n--- a/arch/arm/mm/cache-xsc3l2.c\n+++ b/arch/arm/mm/cache-xsc3l2.c\n@@ -5,7 +5,6 @@\n * Copyright (C) 2007 ARM Limited\n */\n #include <linux/init.h>\n-#include <linux/highmem.h>\n #include <asm/cp15.h>\n #include <asm/cputype.h>\n #include <asm/cacheflush.h>\n@@ -55,34 +54,6 @@ static inline void xsc3_l2_inv_all(void)\n \tdsb();\n }\n \n-static inline void l2_unmap_va(unsigned long va)\n-{\n-#ifdef CONFIG_HIGHMEM\n-\tif (va != -1)\n-\t\tkunmap_atomic((void *)va);\n-#endif\n-}\n-\n-static inline unsigned long l2_map_va(unsigned long pa, unsigned long prev_va)\n-{\n-#ifdef CONFIG_HIGHMEM\n-\tunsigned long va = prev_va & PAGE_MASK;\n-\tunsigned long pa_offset = pa << (32 - PAGE_SHIFT);\n-\tif (unlikely(pa_offset < (prev_va << (32 - PAGE_SHIFT)))) {\n-\t\t/*\n-\t\t * Switching to a new page. Because cache ops are\n-\t\t * using virtual addresses only, we must put a mapping\n-\t\t * in place for it.\n-\t\t */\n-\t\tl2_unmap_va(prev_va);\n-\t\tva = (unsigned long)kmap_atomic_pfn(pa >> PAGE_SHIFT);\n-\t}\n-\treturn va + (pa_offset >> (32 - PAGE_SHIFT));\n-#else\n-\treturn __phys_to_virt(pa);\n-#endif\n-}\n-\n static void xsc3_l2_inv_range(unsigned long start, unsigned long end)\n {\n \tunsigned long vaddr;\n@@ -92,13 +63,11 @@ static void xsc3_l2_inv_range(unsigned long start, unsigned long end)\n \t\treturn;\n \t}\n \n-\tvaddr = -1; /* to force the first mapping */\n-\n \t/*\n \t * Clean and invalidate partial first cache line.\n \t */\n \tif (start & (CACHE_LINE_SIZE - 1)) {\n-\t\tvaddr = l2_map_va(start & ~(CACHE_LINE_SIZE - 1), vaddr);\n+\t\tvaddr = __phys_to_virt(start & ~(CACHE_LINE_SIZE - 1));\n \t\txsc3_l2_clean_mva(vaddr);\n \t\txsc3_l2_inv_mva(vaddr);\n \t\tstart = (start | (CACHE_LINE_SIZE - 1)) + 1;\n@@ -108,7 +77,7 @@ static void xsc3_l2_inv_range(unsigned long start, unsigned long end)\n \t * Invalidate all full cache lines between 'start' and 'end'.\n \t */\n \twhile (start < (end & ~(CACHE_LINE_SIZE - 1))) {\n-\t\tvaddr = l2_map_va(start, vaddr);\n+\t\tvaddr = __phys_to_virt(start);\n \t\txsc3_l2_inv_mva(vaddr);\n \t\tstart += CACHE_LINE_SIZE;\n \t}\n@@ -117,13 +86,11 @@ static void xsc3_l2_inv_range(unsigned long start, unsigned long end)\n \t * Clean and invalidate partial last cache line.\n \t */\n \tif (start < end) {\n-\t\tvaddr = l2_map_va(start, vaddr);\n+\t\tvaddr = __phys_to_virt(start);\n \t\txsc3_l2_clean_mva(vaddr);\n \t\txsc3_l2_inv_mva(vaddr);\n \t}\n \n-\tl2_unmap_va(vaddr);\n-\n \tdsb();\n }\n \n@@ -135,13 +102,11 @@ static void xsc3_l2_clean_range(unsigned long start, unsigned long end)\n \n \tstart &= ~(CACHE_LINE_SIZE - 1);\n \twhile (start < end) {\n-\t\tvaddr = l2_map_va(start, vaddr);\n+\t\tvaddr = __phys_to_virt(start);\n \t\txsc3_l2_clean_mva(vaddr);\n \t\tstart += CACHE_LINE_SIZE;\n \t}\n \n-\tl2_unmap_va(vaddr);\n-\n \tdsb();\n }\n \n@@ -178,14 +143,12 @@ static void xsc3_l2_flush_range(unsigned long start, unsigned long end)\n \n \tstart &= ~(CACHE_LINE_SIZE - 1);\n \twhile (start < end) {\n-\t\tvaddr = l2_map_va(start, vaddr);\n+\t\tvaddr = __phys_to_virt(start);\n \t\txsc3_l2_clean_mva(vaddr);\n \t\txsc3_l2_inv_mva(vaddr);\n \t\tstart += CACHE_LINE_SIZE;\n \t}\n \n-\tl2_unmap_va(vaddr);\n-\n \tdsb();\n }\n \ndiff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c\nindex a4c765d24692..696f6f1f259e 100644\n--- a/arch/arm/mm/dma-mapping.c\n+++ b/arch/arm/mm/dma-mapping.c\n@@ -647,18 +647,10 @@ static void dma_cache_maint_page(phys_addr_t phys, size_t size,\n \t\t\tif (len + offset > PAGE_SIZE)\n \t\t\t\tlen = PAGE_SIZE - offset;\n \n-\t\t\tif (cache_is_vipt_nonaliasing()) {\n-\t\t\t\tvaddr = kmap_atomic_pfn(pfn);\n+\t\t\tvaddr = kmap_atomic(phys_to_page(phys));\n+\t\t\tif (vaddr) {\n \t\t\t\top(vaddr + offset, len, dir);\n \t\t\t\tkunmap_atomic(vaddr);\n-\t\t\t} else {\n-\t\t\t\tstruct page *page = phys_to_page(phys);\n-\n-\t\t\t\tvaddr = kmap_high_get(page);\n-\t\t\t\tif (vaddr) {\n-\t\t\t\t\top(vaddr + offset, len, dir);\n-\t\t\t\t\tkunmap_high(page);\n-\t\t\t\t}\n \t\t\t}\n \t\t} else {\n \t\t\tphys += offset;\ndiff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c\nindex 19470d938b23..998b75f77364 100644\n--- a/arch/arm/mm/flush.c\n+++ b/arch/arm/mm/flush.c\n@@ -208,21 +208,10 @@ void __flush_dcache_folio(struct address_space *mapping, struct folio *folio)\n \t\t\t\t\tfolio_size(folio));\n \t} else {\n \t\tunsigned long i;\n-\t\tif (cache_is_vipt_nonaliasing()) {\n-\t\t\tfor (i = 0; i < folio_nr_pages(folio); i++) {\n-\t\t\t\tvoid *addr = kmap_local_folio(folio,\n-\t\t\t\t\t\t\t\ti * PAGE_SIZE);\n-\t\t\t\t__cpuc_flush_dcache_area(addr, PAGE_SIZE);\n-\t\t\t\tkunmap_local(addr);\n-\t\t\t}\n-\t\t} else {\n-\t\t\tfor (i = 0; i < folio_nr_pages(folio); i++) {\n-\t\t\t\tvoid *addr = kmap_high_get(folio_page(folio, i));\n-\t\t\t\tif (addr) {\n-\t\t\t\t\t__cpuc_flush_dcache_area(addr, PAGE_SIZE);\n-\t\t\t\t\tkunmap_high(folio_page(folio, i));\n-\t\t\t\t}\n-\t\t\t}\n+\t\tfor (i = 0; i < folio_nr_pages(folio); i++) {\n+\t\t\tvoid *addr = kmap_local_folio(folio, i * PAGE_SIZE);\n+\t\t\t__cpuc_flush_dcache_area(addr, PAGE_SIZE);\n+\t\t\tkunmap_local(addr);\n \t\t}\n \t}\n \n", "prefixes": [ "3/4" ] }