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GET /api/patches/2173982/?format=api
{ "id": 2173982, "url": "http://patchwork.ozlabs.org/api/patches/2173982/?format=api", "web_url": "http://patchwork.ozlabs.org/project/kvm-riscv/patch/20251213150848.149729-3-jamestiotio@gmail.com/", "project": { "id": 70, "url": "http://patchwork.ozlabs.org/api/projects/70/?format=api", "name": "Linux KVM RISC-V", "link_name": "kvm-riscv", "list_id": "kvm-riscv.lists.infradead.org", "list_email": "kvm-riscv@lists.infradead.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "http://lists.infradead.org/pipermail/kvm-riscv/", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20251213150848.149729-3-jamestiotio@gmail.com>", "list_archive_url": null, "date": "2025-12-13T15:08:46", "name": "[kvm-unit-tests,2/4] lib: riscv: Add SBI PMU support", "commit_ref": null, "pull_url": null, "state": "handled-elsewhere", "archived": false, "hash": "fc81bdd4aad003195009bc6778588fa1a76300c0", "submitter": { "id": 85990, "url": "http://patchwork.ozlabs.org/api/people/85990/?format=api", "name": "James Raphael Tiovalen", "email": "jamestiotio@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/kvm-riscv/patch/20251213150848.149729-3-jamestiotio@gmail.com/mbox/", "series": [ { "id": 485289, "url": "http://patchwork.ozlabs.org/api/series/485289/?format=api", "web_url": "http://patchwork.ozlabs.org/project/kvm-riscv/list/?series=485289", "date": "2025-12-13T15:08:44", "name": "riscv: sbi: Add support to test PMU extension", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/485289/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2173982/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2173982/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=KfAGaX97;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=JeJtquNd;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org;\n envelope-from=kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n [IPv6:2607:7c80:54:3::133])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dT8qk4YSkz1y0v\n\tfor <incoming@patchwork.ozlabs.org>; Sun, 14 Dec 2025 02:09:18 +1100 (AEDT)", "from localhost ([::1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1vURFD-00000001ieQ-0nQ2;\n\tSat, 13 Dec 2025 15:09:15 +0000", "from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635])\n\tby bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1vURFA-00000001ide-3Jq6\n\tfor kvm-riscv@lists.infradead.org;\n\tSat, 13 Dec 2025 15:09:14 +0000", "by mail-pl1-x635.google.com with SMTP id\n d9443c01a7336-2984dfae043so20448115ad.0\n for <kvm-riscv@lists.infradead.org>;\n Sat, 13 Dec 2025 07:09:12 -0800 (PST)", "from JRT-PC.. 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The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: Add support for all of the SBI PMU functions, which will be\n used by the SBI tests. Signed-off-by: James Raphael Tiovalen ---\n lib/riscv/asm/sbi.h\n | 22 ++++++++++++++ lib/riscv/sbi.c | 73\n +++++++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 95 insertions(+)\n Content analysis details: (-2.1 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no\n trust\n [2607:f8b0:4864:20:0:0:0:635 listed in]\n [list.dnswl.org]\n -0.0 SPF_PASS SPF: sender matches SPF record\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n 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"kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "Add support for all of the SBI PMU functions, which will be used by the\nSBI tests.\n\nSigned-off-by: James Raphael Tiovalen <jamestiotio@gmail.com>\n---\n lib/riscv/asm/sbi.h | 22 ++++++++++++++\n lib/riscv/sbi.c | 73 +++++++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 95 insertions(+)", "diff": "diff --git a/lib/riscv/asm/sbi.h b/lib/riscv/asm/sbi.h\nindex 35dbf508..8794c126 100644\n--- a/lib/riscv/asm/sbi.h\n+++ b/lib/riscv/asm/sbi.h\n@@ -390,5 +390,27 @@ struct sbiret sbi_fwft_set(uint32_t feature, unsigned long value, unsigned long\n struct sbiret sbi_fwft_get_raw(unsigned long feature);\n struct sbiret sbi_fwft_get(uint32_t feature);\n \n+struct sbiret sbi_pmu_num_counters(void);\n+struct sbiret sbi_pmu_counter_get_info(unsigned long counter_idx);\n+struct sbiret sbi_pmu_counter_config_matching(unsigned long counter_idx_base,\n+\t\t\t\t\t unsigned long counter_idx_mask,\n+\t\t\t\t\t unsigned long config_flags,\n+\t\t\t\t\t unsigned long event_idx,\n+\t\t\t\t\t unsigned long event_data);\n+struct sbiret sbi_pmu_counter_start(unsigned long counter_idx_base, unsigned long counter_idx_mask,\n+\t\t\t\t unsigned long start_flags, unsigned long initial_value);\n+struct sbiret sbi_pmu_counter_stop(unsigned long counter_idx_base, unsigned long counter_idx_mask,\n+\t\t\t\t unsigned long stop_flags);\n+struct sbiret sbi_pmu_counter_fw_read(unsigned long counter_idx);\n+struct sbiret sbi_pmu_counter_fw_read_hi(unsigned long counter_idx);\n+struct sbiret sbi_pmu_snapshot_set_shmem_raw(unsigned long shmem_phys_lo,\n+\t\t\t\t\t unsigned long shmem_phys_hi,\n+\t\t\t\t\t unsigned long flags);\n+struct sbiret sbi_pmu_snapshot_set_shmem(unsigned long *shmem, unsigned long flags);\n+struct sbiret sbi_pmu_event_get_info_raw(unsigned long shmem_phys_lo, unsigned long shmem_phys_hi,\n+\t\t\t\t\t unsigned long num_entries, unsigned long flags);\n+struct sbiret sbi_pmu_event_get_info(unsigned long *shmem, unsigned long num_entries,\n+\t\t\t\t unsigned long flags);\n+\n #endif /* !__ASSEMBLER__ */\n #endif /* _ASMRISCV_SBI_H_ */\ndiff --git a/lib/riscv/sbi.c b/lib/riscv/sbi.c\nindex 39f6138f..ca8f3d33 100644\n--- a/lib/riscv/sbi.c\n+++ b/lib/riscv/sbi.c\n@@ -32,6 +32,79 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,\n \treturn ret;\n }\n \n+struct sbiret sbi_pmu_num_counters(void)\n+{\n+\treturn sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_NUM_COUNTERS, 0, 0, 0, 0, 0, 0);\n+}\n+\n+struct sbiret sbi_pmu_counter_get_info(unsigned long counter_idx)\n+{\n+\treturn sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, counter_idx, 0, 0, 0, 0, 0);\n+}\n+\n+struct sbiret sbi_pmu_counter_config_matching(unsigned long counter_idx_base,\n+\t\t\t\t\t unsigned long counter_idx_mask,\n+\t\t\t\t\t unsigned long config_flags,\n+\t\t\t\t\t unsigned long event_idx,\n+\t\t\t\t\t unsigned long event_data)\n+{\n+\treturn sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CONFIG_MATCHING, counter_idx_base,\n+\t\t\t counter_idx_mask, config_flags, event_idx, event_data, 0);\n+}\n+\n+struct sbiret sbi_pmu_counter_start(unsigned long counter_idx_base, unsigned long counter_idx_mask,\n+\t\t\t\t unsigned long start_flags, unsigned long initial_value)\n+{\n+\treturn sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, counter_idx_base,\n+\t\t\t counter_idx_mask, start_flags, initial_value, 0, 0);\n+}\n+\n+struct sbiret sbi_pmu_counter_stop(unsigned long counter_idx_base, unsigned long counter_idx_mask,\n+\t\t\t\t unsigned long stop_flags)\n+{\n+\treturn sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, counter_idx_base,\n+\t\t\t counter_idx_mask, stop_flags, 0, 0, 0);\n+}\n+\n+struct sbiret sbi_pmu_counter_fw_read(unsigned long counter_idx)\n+{\n+\treturn sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, counter_idx, 0, 0, 0, 0, 0);\n+}\n+\n+struct sbiret sbi_pmu_counter_fw_read_hi(unsigned long counter_idx)\n+{\n+\treturn sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ_HI, counter_idx, 0, 0, 0, 0, 0);\n+}\n+\n+struct sbiret sbi_pmu_snapshot_set_shmem_raw(unsigned long shmem_phys_lo, unsigned long shmem_phys_hi,\n+\t\t\t\t\t unsigned long flags)\n+{\n+\treturn sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, shmem_phys_lo,\n+\t\t\t shmem_phys_hi, flags, 0, 0, 0);\n+}\n+\n+struct sbiret sbi_pmu_snapshot_set_shmem(unsigned long *shmem, unsigned long flags)\n+{\n+\tphys_addr_t p = virt_to_phys(shmem);\n+\n+\treturn sbi_pmu_snapshot_set_shmem_raw(lower_32_bits(p), upper_32_bits(p), flags);\n+}\n+\n+struct sbiret sbi_pmu_event_get_info_raw(unsigned long shmem_phys_lo, unsigned long shmem_phys_hi,\n+\t\t\t\t\t unsigned long num_entries, unsigned long flags)\n+{\n+\treturn sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_EVENT_GET_INFO, shmem_phys_lo,\n+\t\t\t shmem_phys_hi, num_entries, flags, 0, 0);\n+}\n+\n+struct sbiret sbi_pmu_event_get_info(unsigned long *shmem, unsigned long num_entries,\n+\t\t\t\t unsigned long flags)\n+{\n+\tphys_addr_t p = virt_to_phys(shmem);\n+\n+\treturn sbi_pmu_event_get_info_raw(lower_32_bits(p), upper_32_bits(p), num_entries, flags);\n+}\n+\n struct sbiret sbi_sse_read_attrs_raw(unsigned long event_id, unsigned long base_attr_id,\n \t\t\t\t unsigned long attr_count, unsigned long phys_lo,\n \t\t\t\t unsigned long phys_hi)\n", "prefixes": [ "kvm-unit-tests", "2/4" ] }