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GET /api/patches/2163422/?format=api
{ "id": 2163422, "url": "http://patchwork.ozlabs.org/api/patches/2163422/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20251111070031.305281-10-jh.hsu@mediatek.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20251111070031.305281-10-jh.hsu@mediatek.com>", "list_archive_url": null, "date": "2025-11-11T06:59:23", "name": "[v7,9/9] arm64: dts: mediatek: Add mt8189 evaluation board dts", "commit_ref": null, "pull_url": null, "state": "handled-elsewhere", "archived": false, "hash": "bb358786263fceb353378e94185031e5c2a40cf6", "submitter": { "id": 92004, "url": "http://patchwork.ozlabs.org/api/people/92004/?format=api", "name": "Jack Hsu", "email": "jh.hsu@mediatek.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20251111070031.305281-10-jh.hsu@mediatek.com/mbox/", "series": [ { "id": 481635, "url": "http://patchwork.ozlabs.org/api/series/481635/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=481635", "date": "2025-11-11T06:59:15", "name": "Add mt8189 dts evaluation board and Makefile", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/481635/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2163422/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2163422/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pwm+bounces-7617-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pwm@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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"D41D8CD98F00B204E9800998ECF8427E", "From": "Jack Hsu <jh.hsu@mediatek.com>", "To": "<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,\n\t<jic23@kernel.org>, <dlechner@baylibre.com>, <nuno.sa@analog.com>,\n\t<andy@kernel.org>, <matthias.bgg@gmail.com>,\n\t<angelogioacchino.delregno@collabora.com>, <srini@kernel.org>,\n\t<ukleinek@kernel.org>, <gregkh@linuxfoundation.org>, <jirislaby@kernel.org>,\n\t<daniel.lezcano@linaro.org>, <tglx@linutronix.de>,\n\t<chunfeng.yun@mediatek.com>, <wim@linux-watchdog.org>, <linux@roeck-us.net>,\n\t<sean.wang@mediatek.com>, <zhiyong.tao@mediatek.com>,\n\t<andrew-ct.chen@mediatek.com>, <lala.lin@mediatek.com>,\n\t<jitao.shi@mediatek.com>", "CC": "<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<linux-iio@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,\n\t<linux-mediatek@lists.infradead.org>, <linux-pwm@vger.kernel.org>,\n\t<linux-serial@vger.kernel.org>, <linux-usb@vger.kernel.org>,\n\t<linux-watchdog@vger.kernel.org>,\n\t<Project_Global_Chrome_Upstream_Group@mediatek.com>, Jack Hsu\n\t<jh.hsu@mediatek.com>", "Subject": "[PATCH v7 9/9] arm64: dts: mediatek: Add mt8189 evaluation board dts", "Date": "Tue, 11 Nov 2025 14:59:23 +0800", "Message-ID": "<20251111070031.305281-10-jh.hsu@mediatek.com>", "X-Mailer": "git-send-email 2.45.2", "In-Reply-To": "<20251111070031.305281-1-jh.hsu@mediatek.com>", "References": "<20251111070031.305281-1-jh.hsu@mediatek.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pwm@vger.kernel.org", "List-Id": "<linux-pwm.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pwm+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pwm+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-MTK": "N" }, "content": "Add MediaTek mt8189 evaluation board dts, dtsi, Mafefile.\n\nSigned-off-by: Jack Hsu <jh.hsu@mediatek.com>\n\n---\nChangs in v7:\n - update mt8189 clk node\n (refer to: https://lore.kernel.org/linux-mediatek/20251106124330.1145600-1-irving-ch.lin@mediatek.com/)\n - xhci node drop \"reset-names\" property\n - update mt8189 thermal node\n (refer to: https://lore.kernel.org/linux-mediatek/20251110094113.3965182-1-hanchien.lin@mediatek.com/)\n\n - Link to v6: https://lore.kernel.org/linux-mediatek/20251030134541.784011-1-jh.hsu@mediatek.com/\n\n---\n arch/arm64/boot/dts/mediatek/Makefile | 1 +\n arch/arm64/boot/dts/mediatek/mt8189-evb.dts | 1082 ++++++\n arch/arm64/boot/dts/mediatek/mt8189.dtsi | 3310 +++++++++++++++++++\n 3 files changed, 4393 insertions(+)\n create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts\n create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi", "diff": "diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile\nindex c5fd6191a925..188e479a6916 100644\n--- a/arch/arm64/boot/dts/mediatek/Makefile\n+++ b/arch/arm64/boot/dts/mediatek/Makefile\n@@ -94,6 +94,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb\n dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb\n dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb\n dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb\n+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8189-evb.dtb\n dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb\n dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb\n dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb\ndiff --git a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts\nnew file mode 100644\nindex 000000000000..2ed404829730\n--- /dev/null\n+++ b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts\n@@ -0,0 +1,1082 @@\n+// SPDX-License-Identifier: (GPL-2.0 OR MIT)\n+/*\n+ * Copyright (C) 2025 MediaTek Inc.\n+ * Author: Sirius Wang <sirius.wang@mediatek.com>\n+ */\n+/dts-v1/;\n+#include \"mt8189.dtsi\"\n+#include \"mt8189-pinfunc.h\"\n+#include \"mt6319.dtsi\"\n+#include \"mt6359.dtsi\"\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/ {\n+\tmodel = \"MediaTek MT8189 evaluation board\";\n+\tcompatible = \"mediatek,mt8189-evb\", \"mediatek,mt8189\";\n+\n+\tchosen: chosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tusb_p0_vbus: regulator@0 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"p0_vbus\";\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tgpio = <&pio 82 0>;\n+\t\tenable-active-high;\n+\t};\n+\n+\tusb_p1_vbus: regulator@1 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"p1_vbus\";\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tgpio = <&pio 84 0>;\n+\t\tenable-active-high;\n+\t};\n+\n+\tusb_p2_vbus: regulator@2 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"p2_vbus\";\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tgpio = <&pio 85 0>;\n+\t\tenable-active-high;\n+\t};\n+\n+\tusb_p3_vbus: regulator@3 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"p3_vbus\";\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tgpio = <&pio 86 0>;\n+\t\tenable-active-high;\n+\t};\n+\n+\tusb_p4_vbus: regulator@4 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"p4_vbus\";\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tgpio = <&pio 87 0>;\n+\t\tenable-active-high;\n+\t};\n+};\n+\n+&afe{\n+\tpinctrl-names = \"aud-gpio-i2sin0-off\",\n+\t\t\"aud-gpio-i2sin0-on\",\n+\t\t\"aud-gpio-i2sout0-off\",\n+\t\t\"aud-gpio-i2sout0-on\",\n+\t\t\"aud-gpio-i2sin1-off\",\n+\t\t\"aud-gpio-i2sin1-on\",\n+\t\t\"aud-gpio-i2sout1-off\",\n+\t\t\"aud-gpio-i2sout1-on\",\n+\t\t/*dmic*/\n+\t\t\"aud-gpio-ap-dmic-off\",\n+\t\t\"aud-gpio-ap-dmic-on\",\n+\t\t\"aud-gpio-ap-dmic1-off\",\n+\t\t\"aud-gpio-ap-dmic1-on\",\n+\t\t/*pcm*/\n+\t\t\"aud-gpio-pcm-off\",\n+\t\t\"aud-gpio-pcm-on\";\n+\n+\t/* i2s */\n+\tpinctrl-0 = <&aud_gpio_i2sin0_off>;\n+\tpinctrl-1 = <&aud_gpio_i2sin0_on>;\n+\tpinctrl-2 = <&aud_gpio_i2sout0_off>;\n+\tpinctrl-3 = <&aud_gpio_i2sout0_on>;\n+\tpinctrl-4 = <&aud_gpio_i2sin1_off>;\n+\tpinctrl-5 = <&aud_gpio_i2sin1_on>;\n+\tpinctrl-6 = <&aud_gpio_i2sout1_off>;\n+\tpinctrl-7 = <&aud_gpio_i2sout1_on>;\n+\t/* dmic */\n+\tpinctrl-8 = <&aud_gpio_ap_dmic_off>;\n+\tpinctrl-9 = <&aud_gpio_ap_dmic_on>;\n+\tpinctrl-10 = <&aud_gpio_ap_dmic1_off>;\n+\tpinctrl-11 = <&aud_gpio_ap_dmic1_on>;\n+\t/* pcm */\n+\tpinctrl-12 = <&aud_gpio_pcm_off>;\n+\tpinctrl-13 = <&aud_gpio_pcm_on>;\n+\n+\tstatus = \"okay\";\n+};\n+\n+&auxadc {\n+\tstatus = \"okay\";\n+};\n+\n+&cpuhvfs {\n+\tproc1-supply = <&mt6359_vmodem_buck_reg>; //L\n+\tproc2-supply = <&mt6319_7_vbuck1>; //B\n+\tproc3-supply = <&mt6359_vmodem_buck_reg>; //DSU\n+};\n+\n+&disp_dvo0 {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport {\n+\t\t\tdisp_dvo0_out: endpoint {\n+\t\t\t\tremote-endpoint = <&edptx_in>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&disp_dvo1 {\n+\tstatus = \"okay\";\n+\n+\tport {\n+\t\tdisp1_dp_intf0_out: endpoint {\n+\t\t\tremote-endpoint = <&dptx_in0>;\n+\t\t};\n+\t};\n+};\n+\n+&dp_tx {\n+\t#sound-dai-cells = <0>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&dptx_pin>;\n+\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tdptx_in0: endpoint {\n+\t\t\t\tremote-endpoint = <&disp1_dp_intf0_out>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tdptx_out: endpoint {\n+\t\t\t\tdata-lanes = <0 1 2 3>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&dsi0 {\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\tstatus = \"okay\";\n+\n+\tpanel1@0 {\n+\t\tcompatible = \"boe,tv101wum-nl6\";\n+\t\treg = <0>;\n+\t\treset-gpios = <&pio 25 GPIO_ACTIVE_HIGH>;\n+\t\tenable-gpios = <&pio 14 GPIO_ACTIVE_HIGH>;\n+\t\tgate-ic = <4831>;\n+\t\tpinctrl-names = \"default\";\n+\t\tstatus = \"okay\";\n+\n+\t\tport {\n+\t\t\tpanel_in1: endpoint {\n+\t\t\t\tremote-endpoint = <&dsi_out>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tport {\n+\t\tdsi_out: endpoint {\n+\t\t\tremote-endpoint = <&panel_in1>;\n+\t\t};\n+\t};\n+};\n+\n+&edp_tx {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&edp_tx_hpd_pins>;\n+\tmax-lane-count = <4>;\n+\tmax-linkrate-mhz = <5400>;\n+\tuse-aux-bus;\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tedptx_in: endpoint {\n+\t\t\t\tremote-endpoint = <&disp_dvo0_out>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tedp_out: endpoint {\n+\t\t\t\tdata-lanes = <0 1 2 3>;\n+\t\t\t\tremote-endpoint = <&edp_panel_in>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\taux-bus {\n+\t\tpanel: panel {\n+\t\t\tcompatible = \"edp-panel\";\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&panel_fixed_pins>;\n+\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tport {\n+\t\t\t\tedp_panel_in: endpoint {\n+\t\t\t\t\tremote-endpoint = <&edp_out>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&gpu {\n+\tsupply-names = \"mali\";\n+\tmali-supply = <&mt6359_vproc1_buck_reg>;\n+};\n+\n+&i2c0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c0_pins>;\n+\tstatus = \"disabled\";\n+};\n+\n+&i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c1_pins>;\n+\tstatus = \"disabled\";\n+};\n+\n+&i2c2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c2_pins>;\n+\tstatus = \"disabled\";\n+\n+\tnau8825: audio-codec@1a {\n+\t\tcompatible = \"nuvoton,nau8825\";\n+\t\treg = <0x1a>;\n+\t\tinterrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&audio_codec_pins>;\n+\t\t#sound-dai-cells = <0>;\n+\n+\t\tnuvoton,jkdet-enable;\n+\t\tnuvoton,jkdet-polarity = <1>;\n+\t\tnuvoton,vref-impedance = <2>;\n+\t\tnuvoton,micbias-voltage = <6>;\n+\t\tnuvoton,sar-threshold-num = <4>;\n+\t\tnuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>;\n+\t\tnuvoton,sar-hysteresis = <1>;\n+\t\tnuvoton,sar-voltage = <0>;\n+\t\tnuvoton,sar-compare-time = <0>;\n+\t\tnuvoton,sar-sampling-time = <0>;\n+\t\tnuvoton,short-key-debounce = <2>;\n+\t\tnuvoton,jack-insert-debounce = <7>;\n+\t\tnuvoton,jack-eject-debounce = <7>;\n+\t\tnuvoton,adc-delay-ms = <300>;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\n+\n+&i2c3 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c3_pins>;\n+\tstatus = \"disabled\";\n+};\n+\n+&i2c4 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c4_pins>;\n+\tstatus = \"disabled\";\n+};\n+\n+&i2c5 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c5_pins>;\n+\tstatus = \"disabled\";\n+};\n+\n+&i2c6 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c6_pins>;\n+\tstatus = \"disabled\";\n+};\n+\n+&i2c7 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c7_pins>;\n+\tstatus = \"disabled\";\n+};\n+\n+&i2c8 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c8_pins>;\n+\tstatus = \"disabled\";\n+};\n+\n+&mipi_tx_config0 {\n+\tstatus = \"okay\";\n+};\n+\n+&mmc0 {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\", \"state_uhs\";\n+\tpinctrl-0 = <&mmc0_pins_default>;\n+\tpinctrl-1 = <&mmc0_pins_uhs>;\n+\tbus-width = <8>;\n+\tmax-frequency = <200000000>;\n+\tcap-mmc-highspeed;\n+\tmmc-hs200-1_8v;\n+\tmmc-hs400-1_8v;\n+\tmmc-hs400-enhanced-strobe;\n+\tsupports-cqe;\n+\tcap-mmc-hw-reset;\n+\tno-sdio;\n+\tno-sd;\n+\tnon-removable;\n+\ths400-ds-delay = <0x1481b>;\n+\tmediatek,hs400-ds-dly3 = <0x14>;\n+\tvmmc-supply = <&mt6359_vemc_1_ldo_reg>;\n+\tvqmmc-supply = <&mt6359_vufs_ldo_reg>;\n+};\n+\n+&mmc1 {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\", \"state_uhs\";\n+\tpinctrl-0 = <&mmc1_pins_default>;\n+\tpinctrl-1 = <&mmc1_pins_uhs>;\n+\tbus-width = <4>;\n+\tmax-frequency = <200000000>;\n+\tcap-sd-highspeed;\n+\tsd-uhs-sdr50;\n+\tsd-uhs-sdr104;\n+\tno-mmc;\n+\tno-sdio;\n+\tcd-gpios = <&pio 2 GPIO_ACTIVE_HIGH>;\n+\tvmmc-supply = <&mt6359_vpa_buck_reg>;\n+\tvqmmc-supply = <&mt6359_vsim1_ldo_reg>;\n+};\n+\n+/delete-node/ &mt6319_7_vbuck2;\n+/delete-node/ &mt6319_8_vbuck2;\n+/delete-node/ &mt6319_8_vbuck4;\n+\n+&mt6359_vpa_buck_reg {\n+\tregulator-max-microvolt = <3000000>;\n+};\n+\n+&mt6359_vmodem_buck_reg {\n+\tregulator-always-on;\n+};\n+\n+&mt6359_vsram_proc2_ldo_reg {\n+\tregulator-always-on;\n+};\n+\n+&mt6359_vsram_md_ldo_reg {\n+\tregulator-always-on;\n+};\n+\n+&mt6359_vpu_buck_reg {\n+\tregulator-always-on;\n+};\n+\n+&mt6359_vgpu11_buck_reg{\n+\tregulator-always-on;\n+};\n+\n+&mt6359_vproc2_buck_reg{\n+\tregulator-always-on;\n+};\n+\n+&mt6359_vaux18_ldo_reg{\n+\tregulator-always-on;\n+};\n+\n+&mt6359_vrf12_ldo_reg{\n+\tregulator-always-on;\n+};\n+\n+&mt6359_va09_ldo_reg{\n+\tregulator-always-on;\n+};\n+\n+&mt6359_vrfck_ldo_reg{\n+\tregulator-always-on;\n+};\n+\n+&mt6359_vbbck_ldo_reg{\n+\tregulator-always-on;\n+};\n+\n+&mt6359_vsram_proc1_ldo_reg{\n+\t /delete-property/ regulator-always-on;\n+};\n+\n+\n+&mt6359_vproc1_buck_reg {\n+\tregulator-name = \"buck_vgpu\";\n+\tregulator-min-microvolt = <550000>;\n+\tregulator-max-microvolt = <900000>;\n+\tregulator-coupled-with = <&mt6359_vsram_proc1_ldo_reg>;\n+\tregulator-coupled-max-spread = <6250>;\n+};\n+\n+&mt6359_vsram_proc1_ldo_reg {\n+\tregulator-name = \"ldo_sram_gpu\";\n+\tregulator-min-microvolt = <550000>;\n+\tregulator-max-microvolt = <900000>;\n+\tregulator-coupled-with = <&mt6359_vproc1_buck_reg>;\n+\tregulator-coupled-max-spread = <6250>;\n+};\n+\n+&mt6359rtc {\n+\tstatus = \"okay\";\n+};\n+\n+&nor_flash {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&nor_pins>;\n+\n+\tstatus = \"okay\";\n+\n+\tflash@0 {\n+\t\tcompatible = \"jedec,spi-nor\";\n+\t\treg = <0>;\n+\t\tspi-max-frequency = <52000000>;\n+\t\tspi-rx-bus-width = <2>;\n+\t\tspi-tx-bus-width = <2>;\n+\t};\n+};\n+\n+&pcie {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pcie_pins_default>;\n+\tstatus = \"okay\";\n+};\n+\n+&pciephy {\n+\tstatus = \"okay\";\n+};\n+\n+&pio {\n+\tedp_tx_hpd_pins: edp-tx-hpd-pins{\n+\t\tpins-hpd {\n+\t\t\tpinmux = <PINMUX_GPIO28__FUNC_EDP_TX_HPD>;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\t};\n+\n+\tpanel_fixed_pins: panel-fixed-pins {\n+\t\tpins1 {\n+\t\t\tpinmux = <PINMUX_GPIO29__FUNC_GPIO29>,\n+\t\t\t\t <PINMUX_GPIO108__FUNC_GPIO108>,\n+\t\t\t\t <PINMUX_GPIO109__FUNC_GPIO109>,\n+\t\t\t\t <PINMUX_GPIO110__FUNC_GPIO110>;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\t};\n+\n+\ti2c0_pins: i2c0-default-pins {\n+\t\tpins-bus {\n+\t\t\tpinmux = <PINMUX_GPIO52__FUNC_SDA0>,\n+\t\t\t\t <PINMUX_GPIO51__FUNC_SCL0>;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+\n+\ti2c1_pins: i2c1-default-pins {\n+\t\tpins-bus {\n+\t\t\tpinmux = <PINMUX_GPIO54__FUNC_SDA1>,\n+\t\t\t\t <PINMUX_GPIO53__FUNC_SCL1>;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+\n+\ti2c2_pins: i2c2-default-pins {\n+\t\tpins-bus {\n+\t\t\tpinmux = <PINMUX_GPIO56__FUNC_SDA2>,\n+\t\t\t\t <PINMUX_GPIO55__FUNC_SCL2>;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+\n+\ti2c3_pins: i2c3-default-pins {\n+\t\tpins-bus {\n+\t\t\tpinmux = <PINMUX_GPIO58__FUNC_SDA3>,\n+\t\t\t\t <PINMUX_GPIO57__FUNC_SCL3>;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+\n+\ti2c4_pins: i2c4-default-pins {\n+\t\tpins-bus {\n+\t\t\tpinmux = <PINMUX_GPIO60__FUNC_SDA4>,\n+\t\t\t\t <PINMUX_GPIO59__FUNC_SCL4>;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+\ti2c5_pins: i2c5-default-pins {\n+\t\tpins-bus {\n+\t\t\tpinmux = <PINMUX_GPIO62__FUNC_SDA5>,\n+\t\t\t\t <PINMUX_GPIO61__FUNC_SCL5>;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+\n+\ti2c6_pins: i2c6-default-pins {\n+\t\tpins-bus {\n+\t\t\tpinmux = <PINMUX_GPIO64__FUNC_SDA6>,\n+\t\t\t\t <PINMUX_GPIO63__FUNC_SCL6>;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+\n+\ti2c7_pins: i2c7-default-pins {\n+\t\tpins-bus {\n+\t\t\tpinmux = <PINMUX_GPIO66__FUNC_SDA7>,\n+\t\t\t\t <PINMUX_GPIO65__FUNC_SCL7>;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+\n+\ti2c8_pins: i2c8-default-pins {\n+\t\tpins-bus {\n+\t\t\tpinmux = <PINMUX_GPIO68__FUNC_SDA8>,\n+\t\t\t\t <PINMUX_GPIO67__FUNC_SCL8>;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+\n+\tspi0_pins: spi0-default-pins {\n+\t\tpins-cmd-dat {\n+\t\t\tpinmux = <PINMUX_GPIO69__FUNC_SPIM0_CSB>,\n+\t\t\t\t <PINMUX_GPIO70__FUNC_SPIM0_CLK>,\n+\t\t\t\t <PINMUX_GPIO71__FUNC_SPIM0_MO>,\n+\t\t\t\t <PINMUX_GPIO72__FUNC_SPIM0_MI>;\n+\t\t};\n+\t};\n+\n+\tspi1_pins: spi1-default-pins {\n+\t\tpins-cmd-dat {\n+\t\t\tpinmux = <PINMUX_GPIO73__FUNC_SPIM1_CSB>,\n+\t\t\t\t <PINMUX_GPIO74__FUNC_SPIM1_CLK>,\n+\t\t\t\t <PINMUX_GPIO75__FUNC_SPIM1_MO>,\n+\t\t\t\t <PINMUX_GPIO76__FUNC_SPIM1_MI>;\n+\t\t};\n+\t};\n+\n+\tspi2_pins: spi2-default-pins {\n+\t\tpins-cmd-dat {\n+\t\t\tpinmux = <PINMUX_GPIO77__FUNC_SPIM2_CSB>,\n+\t\t\t\t <PINMUX_GPIO78__FUNC_SPIM2_CLK>,\n+\t\t\t\t <PINMUX_GPIO79__FUNC_SPIM2_MO>,\n+\t\t\t\t <PINMUX_GPIO80__FUNC_SPIM2_MI>;\n+\t\t};\n+\t};\n+\n+\tspi3_pins: spi3-default-pins {\n+\t\tpins-cmd-dat {\n+\t\t\tpinmux = <PINMUX_GPIO0__FUNC_SPIM3_A_CSB>,\n+\t\t\t\t <PINMUX_GPIO1__FUNC_SPIM3_A_CLK>,\n+\t\t\t\t <PINMUX_GPIO2__FUNC_SPIM3_A_MO>,\n+\t\t\t\t <PINMUX_GPIO3__FUNC_SPIM3_A_MI>;\n+\t\t};\n+\t};\n+\n+\tspi4_pins: spi4-default-pins {\n+\t\tpins-cmd-dat {\n+\t\t\tpinmux = <PINMUX_GPIO4__FUNC_SPIM4_A_CSB>,\n+\t\t\t\t <PINMUX_GPIO5__FUNC_SPIM4_A_CLK>,\n+\t\t\t\t <PINMUX_GPIO6__FUNC_SPIM4_A_MO>,\n+\t\t\t\t <PINMUX_GPIO7__FUNC_SPIM4_A_MI>;\n+\t\t};\n+\t};\n+\n+\tspi5_pins: spi5-default-pins {\n+\t\tpins-cmd-dat {\n+\t\t\tpinmux = <PINMUX_GPIO8__FUNC_SPIM5_A_CSB>,\n+\t\t\t\t <PINMUX_GPIO9__FUNC_SPIM5_A_CLK>,\n+\t\t\t\t <PINMUX_GPIO10__FUNC_SPIM5_A_MO>,\n+\t\t\t\t <PINMUX_GPIO11__FUNC_SPIM5_A_MI>;\n+\t\t};\n+\t};\n+\n+\tpcie_pins_default: pcie-default-pins {\n+\t\tpins-cmd-dat {\n+\t\t\tpinmux = <PINMUX_GPIO48__FUNC_WAKEN>,\n+\t\t\t\t <PINMUX_GPIO49__FUNC_PERSTN>,\n+\t\t\t\t <PINMUX_GPIO50__FUNC_CLKREQN>;\n+\t\t};\n+\t};\n+\n+\tnor_pins: nor-pins {\n+\t\tpins-ck-io {\n+\t\t\tpinmux = <PINMUX_GPIO150__FUNC_SPINOR_CK>,\n+\t\t\t\t <PINMUX_GPIO152__FUNC_SPINOR_IO0>,\n+\t\t\t\t <PINMUX_GPIO153__FUNC_SPINOR_IO1>;\n+\t\t\tdrive-strength = <8>;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\n+\t\tpins-cs {\n+\t\t\tpinmux = <PINMUX_GPIO151__FUNC_SPINOR_CS>;\n+\t\t\tdrive-strength = <8>;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\t};\n+\n+\tdptx_pin: dptx-default-pins {\n+\t\tpins-cmd-dat {\n+\t\t\tpinmux = <PINMUX_GPIO27__FUNC_DP_TX_HPD>;\n+\t\t};\n+\t};\n+\n+\t/* AUDIO GPIO standardization start */\n+\taudio_spk_en_pins: audio-spk-en-pins {\n+\t\tpins-spk-en {\n+\t\t\tpinmux = <PINMUX_GPIO5__FUNC_GPIO5>;\n+\t\t\toutput-low;\n+\t\t};\n+\t};\n+\n+\taudio_codec_pins: audio-codec-pins {\n+\t\tpins-hp-int-odl {\n+\t\t\tpinmux = <PINMUX_GPIO4__FUNC_GPIO4>;\n+\t\t\tinput-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+\n+\taud_gpio_i2sin0_off: aud-gpio-i2sin0-off-pins {\n+\t\tpins-cmd1-dat {\n+\t\t\tpinmux = <PINMUX_GPIO106__FUNC_GPIO106>;\n+\t\t\tinput-enable;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\t};\n+\n+\taud_gpio_i2sin0_on: aud-gpio-i2sin0-on-pins {\n+\t\tpins-cmd1-dat {\n+\t\t\tpinmux = <PINMUX_GPIO106__FUNC_I2SIN0_DI>;\n+\t\t\tinput-schmitt-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+\n+\taud_gpio_i2sout0_off: aud-gpio-i2sout0-off-pins {\n+\t\tpins-cmd1-dat {\n+\t\t\tpinmux = <PINMUX_GPIO107__FUNC_GPIO107>;\n+\t\t\tinput-enable;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\n+\t\tpins-cmd2-dat {\n+\t\t\tpinmux = <PINMUX_GPIO108__FUNC_GPIO108>;\n+\t\t\tinput-enable;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\n+\t\tpins-cmd3-dat {\n+\t\t\tpinmux = <PINMUX_GPIO109__FUNC_GPIO109>;\n+\t\t\tinput-enable;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\n+\t\tpins-cmd4-dat {\n+\t\t\tpinmux = <PINMUX_GPIO110__FUNC_GPIO110>;\n+\t\t\tinput-enable;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\t};\n+\n+\taud_gpio_i2sout0_on: aud-gpio-i2sout0-on-pins {\n+\t\tpins-cmd1-dat {\n+\t\t\tpinmux = <PINMUX_GPIO107__FUNC_I2SOUT0_MCK>;\n+\t\t\tinput-schmitt-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\n+\t\tpins-cmd2-dat {\n+\t\t\tpinmux = <PINMUX_GPIO108__FUNC_I2SOUT0_BCK>;\n+\t\t\tinput-schmitt-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\n+\t\tpins-cmd3-dat {\n+\t\t\tpinmux = <PINMUX_GPIO109__FUNC_I2SOUT0_LRCK>;\n+\t\t\tinput-schmitt-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\n+\t\tpins-cmd4-dat {\n+\t\t\tpinmux = <PINMUX_GPIO110__FUNC_I2SOUT0_DO>;\n+\t\t\tinput-schmitt-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+\n+\taud_gpio_i2sin1_off: aud-gpio-i2sin1-off-pins {\n+\t\tpins-cmd1-dat {\n+\t\t\tpinmux = <PINMUX_GPIO130__FUNC_GPIO130>;\n+\t\t\tinput-enable;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\t};\n+\n+\taud_gpio_i2sin1_on: aud-gpio-i2sin1-on-pins {\n+\t\tpins-cmd1-dat {\n+\t\t\tpinmux = <PINMUX_GPIO130__FUNC_I2SIN1_DI>;\n+\t\t\tinput-schmitt-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+\n+\taud_gpio_i2sout1_off: aud-gpio-i2sout1-off-pins {\n+\t\tpins-cmd1-dat {\n+\t\t\tpinmux = <PINMUX_GPIO111__FUNC_GPIO111>;\n+\t\t\tinput-enable;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\n+\t\tpins-cmd2-dat {\n+\t\t\tpinmux = <PINMUX_GPIO112__FUNC_GPIO112>;\n+\t\t\tinput-enable;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\n+\t\tpins-cmd3-dat {\n+\t\t\tpinmux = <PINMUX_GPIO113__FUNC_GPIO113>;\n+\t\t\tinput-enable;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\n+\t\tpins-cmd4-dat {\n+\t\t\tpinmux = <PINMUX_GPIO114__FUNC_GPIO114>;\n+\t\t\tinput-enable;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\t};\n+\n+\taud_gpio_i2sout1_on: aud-gpio-i2sout1-on-pins {\n+\t\tpins-cmd1-dat {\n+\t\t\tpinmux = <PINMUX_GPIO111__FUNC_I2SOUT1_MCK>;\n+\t\t\tinput-schmitt-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\n+\t\tpins-cmd2-dat {\n+\t\t\tpinmux = <PINMUX_GPIO112__FUNC_I2SOUT1_BCK>;\n+\t\t\tinput-schmitt-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\n+\t\tpins-cmd3-dat {\n+\t\t\tpinmux = <PINMUX_GPIO113__FUNC_I2SOUT1_LRCK>;\n+\t\t\tinput-schmitt-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\n+\t\tpins-cmd4-dat {\n+\t\t\tpinmux = <PINMUX_GPIO114__FUNC_I2SOUT1_DO>;\n+\t\t\tinput-schmitt-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+\n+\taud_gpio_ap_dmic_off: aud-gpio-ap-dmic-off-pins {\n+\t\tpins-cmd1-dat {\n+\t\t\tpinmux = <PINMUX_GPIO119__FUNC_GPIO119>;\n+\t\t\tinput-enable;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\t\tpins-cmd2-dat {\n+\t\t\tpinmux = <PINMUX_GPIO120__FUNC_GPIO120>;\n+\t\t\tinput-enable;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\t};\n+\taud_gpio_ap_dmic_on: aud-gpio-ap-dmic-on-pins {\n+\t\tpins-cmd1-dat {\n+\t\t\tpinmux = <PINMUX_GPIO119__FUNC_DMIC0_CLK>;\n+\t\t\tinput-schmitt-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\t\tpins-cmd2-dat {\n+\t\t\tpinmux = <PINMUX_GPIO120__FUNC_DMIC0_DAT0>;\n+\t\t\tinput-schmitt-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+\taud_gpio_ap_dmic1_off: aud-gpio-ap-dmic1-off-pins {\n+\t\tpins-cmd1-dat {\n+\t\t\tpinmux = <PINMUX_GPIO122__FUNC_GPIO122>;\n+\t\t\tinput-enable;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\t\tpins-cmd2-dat {\n+\t\t\tpinmux = <PINMUX_GPIO123__FUNC_GPIO123>;\n+\t\t\tinput-enable;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\t};\n+\taud_gpio_ap_dmic1_on: aud-gpio-ap-dmic1-on-pins {\n+\t\tpins-cmd1-dat {\n+\t\t\tpinmux = <PINMUX_GPIO122__FUNC_DMIC1_CLK>;\n+\t\t\tinput-schmitt-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\t\tpins-cmd2-dat {\n+\t\t\tpinmux = <PINMUX_GPIO123__FUNC_DMIC1_DAT0>;\n+\t\t\tinput-schmitt-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+\n+\taud_gpio_pcm_off: aud-gpio-pcm-off-pins {\n+\t\tpins-cmd1-dat {\n+\t\t\tpinmux = <PINMUX_GPIO115__FUNC_GPIO115>;\n+\t\t\tinput-enable;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\t\tpins-cmd2-dat {\n+\t\t\tpinmux = <PINMUX_GPIO116__FUNC_GPIO116>;\n+\t\t\tinput-enable;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\t\tpins-cmd3-dat {\n+\t\t\tpinmux = <PINMUX_GPIO118__FUNC_GPIO118>;\n+\t\t\tinput-enable;\n+\t\t\tbias-pull-down;\n+\t\t};\n+\t};\n+\n+\taud_gpio_pcm_on: aud-gpio-pcm-on-pins {\n+\t\tpins-cmd1-dat {\n+\t\t\tpinmux = <PINMUX_GPIO115__FUNC_PCM0_CLK>;\n+\t\t\tinput-schmitt-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\t\tpins-cmd2-dat {\n+\t\t\tpinmux = <PINMUX_GPIO116__FUNC_PCM0_SYNC>;\n+\t\t\tinput-schmitt-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\t\tpins-cmd3-dat {\n+\t\t\tpinmux = <PINMUX_GPIO118__FUNC_PCM0_DO>;\n+\t\t\tinput-schmitt-enable;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+\t/* AUDIO GPIO standardization end */\n+\n+\tmmc0_pins_default: mmc0-default-pins {\n+\t\tpins-cmd-dat {\n+\t\t\tpinmux = <PINMUX_GPIO156__FUNC_MSDC0_DAT7>,\n+\t\t\t\t <PINMUX_GPIO157__FUNC_MSDC0_DAT6>,\n+\t\t\t\t <PINMUX_GPIO158__FUNC_MSDC0_DAT5>,\n+\t\t\t\t <PINMUX_GPIO159__FUNC_MSDC0_DAT4>,\n+\t\t\t\t <PINMUX_GPIO161__FUNC_MSDC0_CMD>,\n+\t\t\t\t <PINMUX_GPIO163__FUNC_MSDC0_DAT3>,\n+\t\t\t\t <PINMUX_GPIO164__FUNC_MSDC0_DAT2>,\n+\t\t\t\t <PINMUX_GPIO165__FUNC_MSDC0_DAT1>,\n+\t\t\t\t <PINMUX_GPIO166__FUNC_MSDC0_DAT0>;\n+\t\t\tinput-enable;\n+\t\t\tdrive-strength = <MTK_DRIVE_6mA>;\n+\t\t\tbias-pull-up = <MTK_PUPD_SET_R1R0_01>;\n+\t\t};\n+\t\tpins-clk {\n+\t\t\tpinmux = <PINMUX_GPIO162__FUNC_MSDC0_CLK>;\n+\t\t\tdrive-strength = <MTK_DRIVE_6mA>;\n+\t\t\tbias-pull-down = <MTK_PUPD_SET_R1R0_10>;\n+\t\t};\n+\t\tpins-rst {\n+\t\t\tpinmux = <PINMUX_GPIO160__FUNC_MSDC0_RSTB>;\n+\t\t\tdrive-strength = <MTK_DRIVE_6mA>;\n+\t\t\tbias-pull-up = <MTK_PUPD_SET_R1R0_00>;\n+\t\t};\n+\t};\n+\n+\tmmc0_pins_uhs: mmc0-uhs-pins {\n+\t\tpins-cmd-dat {\n+\t\t\tpinmux = <PINMUX_GPIO156__FUNC_MSDC0_DAT7>,\n+\t\t\t\t <PINMUX_GPIO157__FUNC_MSDC0_DAT6>,\n+\t\t\t\t <PINMUX_GPIO158__FUNC_MSDC0_DAT5>,\n+\t\t\t\t <PINMUX_GPIO159__FUNC_MSDC0_DAT4>,\n+\t\t\t\t <PINMUX_GPIO161__FUNC_MSDC0_CMD>,\n+\t\t\t\t <PINMUX_GPIO163__FUNC_MSDC0_DAT3>,\n+\t\t\t\t <PINMUX_GPIO164__FUNC_MSDC0_DAT2>,\n+\t\t\t\t <PINMUX_GPIO165__FUNC_MSDC0_DAT1>,\n+\t\t\t\t <PINMUX_GPIO166__FUNC_MSDC0_DAT0>;\n+\t\t\tinput-enable;\n+\t\t\tdrive-strength = <MTK_DRIVE_8mA>;\n+\t\t\tbias-pull-up = <MTK_PUPD_SET_R1R0_01>;\n+\t\t};\n+\t\tpins-clk {\n+\t\t\tpinmux = <PINMUX_GPIO162__FUNC_MSDC0_CLK>;\n+\t\t\tdrive-strength = <MTK_DRIVE_8mA>;\n+\t\t\tbias-pull-down = <MTK_PUPD_SET_R1R0_10>;\n+\t\t};\n+\t\tpins-ds {\n+\t\t\tpinmux = <PINMUX_GPIO167__FUNC_MSDC0_DSL>;\n+\t\t\tdrive-strength = <MTK_DRIVE_8mA>;\n+\t\t\tbias-pull-down = <MTK_PUPD_SET_R1R0_10>;\n+\t\t};\n+\t\tpins-rst {\n+\t\t\tpinmux = <PINMUX_GPIO160__FUNC_MSDC0_RSTB>;\n+\t\t\tbias-pull-up = <MTK_PUPD_SET_R1R0_00>;\n+\t\t};\n+\t};\n+\n+\tmmc1_pins_default: mmc1-default-pins {\n+\t\tpins-cmd-dat {\n+\t\t\tpinmux = <PINMUX_GPIO168__FUNC_MSDC1_CMD>,\n+\t\t\t\t <PINMUX_GPIO170__FUNC_MSDC1_DAT0>,\n+\t\t\t\t <PINMUX_GPIO171__FUNC_MSDC1_DAT1>,\n+\t\t\t\t <PINMUX_GPIO172__FUNC_MSDC1_DAT2>,\n+\t\t\t\t <PINMUX_GPIO173__FUNC_MSDC1_DAT3>;\n+\t\t\tinput-enable;\n+\t\t\tdrive-strength = <MTK_DRIVE_8mA>;\n+\t\t\tbias-pull-up = <MTK_PUPD_SET_R1R0_01>;\n+\t\t};\n+\t\tpins-clk {\n+\t\t\tpinmux = <PINMUX_GPIO169__FUNC_MSDC1_CLK>;\n+\t\t\tdrive-strength = <MTK_DRIVE_8mA>;\n+\t\t\tbias-pull-down = <MTK_PUPD_SET_R1R0_10>;\n+\t\t};\n+\t\tpins-insert {\n+\t\t\tpinmux = <PINMUX_GPIO2__FUNC_GPIO2>;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\t};\n+\n+\tmmc1_pins_uhs: mmc1-uhs-pins {\n+\t\tpins-cmd-dat {\n+\t\t\tpinmux = <PINMUX_GPIO168__FUNC_MSDC1_CMD>,\n+\t\t\t\t <PINMUX_GPIO170__FUNC_MSDC1_DAT0>,\n+\t\t\t\t <PINMUX_GPIO171__FUNC_MSDC1_DAT1>,\n+\t\t\t\t <PINMUX_GPIO172__FUNC_MSDC1_DAT2>,\n+\t\t\t\t <PINMUX_GPIO173__FUNC_MSDC1_DAT3>;\n+\t\t\tinput-enable;\n+\t\t\tdrive-strength = <MTK_DRIVE_8mA>;\n+\t\t\tbias-pull-up = <MTK_PUPD_SET_R1R0_01>;\n+\t\t};\n+\t\tpins-clk {\n+\t\t\tpinmux = <PINMUX_GPIO169__FUNC_MSDC1_CLK>;\n+\t\t\tdrive-strength = <MTK_DRIVE_8mA>;\n+\t\t\tbias-pull-down = <MTK_PUPD_SET_R1R0_10>;\n+\t\t};\n+\t};\n+};\n+\n+&pmic {\n+\tinterrupts-extended = <&pio 194 IRQ_TYPE_LEVEL_HIGH>;\n+};\n+\n+&sound {\n+\tcompatible = \"mediatek,mt8189-nau8825\";\n+\tmodel = \"mt8189_rt9123_8825\";\n+\tstatus = \"okay\";\n+\n+\tdai-link-0 {\n+\t\tlink-name = \"I2SOUT0_BE\";\n+\t\tmediatek,clk-provider = \"cpu\";\n+\n+\t\tcodec {\n+\t\t\tsound-dai = <&nau8825>;\n+\t\t};\n+\t};\n+\n+\tdai-link-1 {\n+\t\tlink-name = \"I2SIN0_BE\";\n+\t\tmediatek,clk-provider = \"cpu\";\n+\n+\t\tcodec {\n+\t\t\tsound-dai = <&nau8825>;\n+\t\t};\n+\t};\n+};\n+\n+&spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi0_pins>;\n+\tstatus = \"disabled\";\n+};\n+\n+&spi1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi1_pins>;\n+\tstatus = \"disabled\";\n+};\n+\n+&spi2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi2_pins>;\n+\tstatus = \"disabled\";\n+};\n+\n+&spi3 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi3_pins>;\n+\tstatus = \"disabled\";\n+};\n+\n+&spi4 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi4_pins>;\n+\tstatus = \"disabled\";\n+};\n+\n+&spi5 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi5_pins>;\n+\tstatus = \"disabled\";\n+};\n+\n+&mfg0 {\n+\tdomain-supply = <&mt6359_vproc1_buck_reg>;\n+};\n+\n+&mfg1 {\n+\tdomain-supply = <&mt6359_vsram_proc1_ldo_reg>;\n+};\n+\n+&uart0 {\n+\tstatus = \"okay\";\n+};\n+\n+&ufshci {\n+\tvcc-supply = <&mt6359_vemc_1_ldo_reg>;\n+\tvccq-supply = <&mt6359_vio18_ldo_reg>;\n+\tvccq2-supply = <&mt6359_vufs_ldo_reg>;\n+};\n+\n+&xhci0{\n+\tvbus-supply = <&usb_p0_vbus>;\n+\tstatus = \"okay\";\n+};\n+\n+&xhci1{\n+\tvbus-supply = <&usb_p1_vbus>;\n+\tstatus = \"okay\";\n+};\n+\n+&xhci2{\n+\tvbus-supply = <&usb_p2_vbus>;\n+\tstatus = \"okay\";\n+};\n+\n+&xhci3{\n+\tvbus-supply = <&usb_p3_vbus>;\n+\tstatus = \"okay\";\n+};\n+\n+&xhci4{\n+\tvbus-supply = <&usb_p4_vbus>;\n+\tstatus = \"okay\";\n+};\ndiff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts/mediatek/mt8189.dtsi\nnew file mode 100644\nindex 000000000000..2f2648f43f34\n--- /dev/null\n+++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi\n@@ -0,0 +1,3310 @@\n+// SPDX-License-Identifier: (GPL-2.0 OR MIT)\n+/*\n+ * Copyright (c) 2025 MediaTek Inc.\n+ */\n+\n+#include <dt-bindings/clock/mediatek,mt8189-clk.h>\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+#include <dt-bindings/interrupt-controller/irq.h>\n+#include <dt-bindings/memory/mediatek,mt8189-memory-port.h>\n+#include <dt-bindings/phy/phy.h>\n+#include <dt-bindings/power/mediatek,mt8189-power.h>\n+#include <dt-bindings/reset/ti-syscon.h>\n+#include <dt-bindings/spmi/spmi.h>\n+#include <dt-bindings/thermal/mediatek,lvts-thermal.h>\n+#include <dt-bindings/thermal/thermal.h>\n+#include \"mt8189-gce.h\"\n+\n+/ {\n+\tcompatible = \"mediatek,mt8189\";\n+\tinterrupt-parent = <&gic>;\n+\t#address-cells = <2>;\n+\t#size-cells = <2>;\n+\n+\taliases {\n+\t\tdvo0 = &disp_dvo0;\n+\t\tdvo1 = &disp_dvo1;\n+\t\tdsc0 = &disp_dsc_wrap0;\n+\t\tgce0 = &gce;\n+\t\tgce1 = &gce_m;\n+\t\ti2c0 = &i2c0;\n+\t\ti2c1 = &i2c1;\n+\t\ti2c2 = &i2c2;\n+\t\ti2c3 = &i2c3;\n+\t\ti2c4 = &i2c4;\n+\t\ti2c5 = &i2c5;\n+\t\ti2c6 = &i2c6;\n+\t\ti2c7 = &i2c7;\n+\t\ti2c8 = &i2c8;\n+\t\tmmc0 = &mmc0;\n+\t\tmmc1 = &mmc1;\n+\t\tmutex0 = &disp_mutex0;\n+\t\tovl0 = &disp_ovl0_4l;\n+\t\tovl1 = &disp_ovl1_4l;\n+\t\trdma0 = &disp_rdma0;\n+\t\trdma1 = &disp_rdma1;\n+\t\tserial0 = &uart0;\n+\t};\n+\n+\tclk32k: oscillator-clk32k {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <32000>;\n+\t\tclock-output-names = \"clk32k\";\n+\t};\n+\n+\tclk13m: oscillator-clk13m {\n+\t\tcompatible = \"fixed-factor-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclocks = <&clk26m>;\n+\t\tclock-mult = <1>;\n+\t\tclock-div = <2>;\n+\t\tclock-output-names = \"clk13m\";\n+\t};\n+\n+\tclk26m: oscillator-clk26m {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <26000000>;\n+\t\tclock-output-names = \"clk26m\";\n+\t};\n+\n+\tclk104m: oscillator-clk104m {\n+\t\tcompatible = \"fixed-factor-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclocks = <&clk26m>;\n+\t\tclock-mult = <4>;\n+\t\tclock-div = <1>;\n+\t\tclock-output-names = \"clk104m\";\n+\t};\n+\n+\tulposc: oscillator-ulposc {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <520000000>;\n+\t\tclock-output-names = \"ulposc\";\n+\t};\n+\n+\tulposc3: oscillator-ulposc3 {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <26000000>;\n+\t\tclock-output-names = \"ulposc3\";\n+\t};\n+\n+\tvowpll: oscillator-vowpll {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <26000000>;\n+\t\tclock-output-names = \"vowpll\";\n+\t};\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tcpu0: cpu@0 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a55\";\n+\t\t\treg = <0x000>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tclock-frequency = <2000000000>;\n+\t\t\tcapacity-dmips-mhz = <358>;\n+\t\t\tcpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;\n+\t\t\ti-cache-size = <32768>;\n+\t\t\ti-cache-line-size = <64>;\n+\t\t\ti-cache-sets = <128>;\n+\t\t\td-cache-size = <32768>;\n+\t\t\td-cache-line-size = <64>;\n+\t\t\td-cache-sets = <128>;\n+\t\t\tnext-level-cache = <&l2_0>;\n+\t\t\tperformance-domains = <&performance 0>;\n+\t\t\t#cooling-cells = <2>;\n+\t\t};\n+\n+\t\tcpu1: cpu@100 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a55\";\n+\t\t\treg = <0x100>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tclock-frequency = <2000000000>;\n+\t\t\tcapacity-dmips-mhz = <358>;\n+\t\t\tcpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;\n+\t\t\ti-cache-size = <32768>;\n+\t\t\ti-cache-line-size = <64>;\n+\t\t\ti-cache-sets = <128>;\n+\t\t\td-cache-size = <32768>;\n+\t\t\td-cache-line-size = <64>;\n+\t\t\td-cache-sets = <128>;\n+\t\t\tnext-level-cache = <&l2_0>;\n+\t\t\tperformance-domains = <&performance 0>;\n+\t\t\t#cooling-cells = <2>;\n+\t\t};\n+\n+\t\tcpu2: cpu@200 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a55\";\n+\t\t\treg = <0x200>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tclock-frequency = <2000000000>;\n+\t\t\tcapacity-dmips-mhz = <358>;\n+\t\t\tcpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;\n+\t\t\ti-cache-size = <32768>;\n+\t\t\ti-cache-line-size = <64>;\n+\t\t\ti-cache-sets = <128>;\n+\t\t\td-cache-size = <32768>;\n+\t\t\td-cache-line-size = <64>;\n+\t\t\td-cache-sets = <128>;\n+\t\t\tnext-level-cache = <&l2_0>;\n+\t\t\tperformance-domains = <&performance 0>;\n+\t\t\t#cooling-cells = <2>;\n+\t\t};\n+\n+\t\tcpu3: cpu@300 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a55\";\n+\t\t\treg = <0x300>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tclock-frequency = <2000000000>;\n+\t\t\tcapacity-dmips-mhz = <358>;\n+\t\t\tcpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;\n+\t\t\ti-cache-size = <32768>;\n+\t\t\ti-cache-line-size = <64>;\n+\t\t\ti-cache-sets = <128>;\n+\t\t\td-cache-size = <32768>;\n+\t\t\td-cache-line-size = <64>;\n+\t\t\td-cache-sets = <128>;\n+\t\t\tnext-level-cache = <&l2_0>;\n+\t\t\tperformance-domains = <&performance 0>;\n+\t\t\t#cooling-cells = <2>;\n+\t\t};\n+\n+\t\tcpu4: cpu@400 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a55\";\n+\t\t\treg = <0x400>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tclock-frequency = <2000000000>;\n+\t\t\tcapacity-dmips-mhz = <358>;\n+\t\t\tcpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;\n+\t\t\ti-cache-size = <32768>;\n+\t\t\ti-cache-line-size = <64>;\n+\t\t\ti-cache-sets = <128>;\n+\t\t\td-cache-size = <32768>;\n+\t\t\td-cache-line-size = <64>;\n+\t\t\td-cache-sets = <128>;\n+\t\t\tnext-level-cache = <&l2_0>;\n+\t\t\tperformance-domains = <&performance 0>;\n+\t\t\t#cooling-cells = <2>;\n+\t\t};\n+\n+\t\tcpu5: cpu@500 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a55\";\n+\t\t\treg = <0x500>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tclock-frequency = <2000000000>;\n+\t\t\tcapacity-dmips-mhz = <358>;\n+\t\t\tcpu-idle-states = <&cpu_off_l>, <&cpu_s2idle>;\n+\t\t\ti-cache-size = <32768>;\n+\t\t\ti-cache-line-size = <64>;\n+\t\t\ti-cache-sets = <128>;\n+\t\t\td-cache-size = <32768>;\n+\t\t\td-cache-line-size = <64>;\n+\t\t\td-cache-sets = <128>;\n+\t\t\tnext-level-cache = <&l2_0>;\n+\t\t\tperformance-domains = <&performance 0>;\n+\t\t\t#cooling-cells = <2>;\n+\t\t};\n+\n+\t\tcpu6: cpu@600 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a78\";\n+\t\t\treg = <0x600>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tclock-frequency = <3000000000>;\n+\t\t\tcapacity-dmips-mhz = <1024>;\n+\t\t\tcpu-idle-states = <&cpu_off_b>, <&cpu_s2idle>;\n+\t\t\ti-cache-size = <65536>;\n+\t\t\ti-cache-line-size = <64>;\n+\t\t\ti-cache-sets = <256>;\n+\t\t\td-cache-size = <65536>;\n+\t\t\td-cache-line-size = <64>;\n+\t\t\td-cache-sets = <256>;\n+\t\t\tnext-level-cache = <&l2_1>;\n+\t\t\tperformance-domains = <&performance 1>;\n+\t\t\t#cooling-cells = <2>;\n+\t\t};\n+\n+\t\tcpu7: cpu@700 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a78\";\n+\t\t\treg = <0x700>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tclock-frequency = <3000000000>;\n+\t\t\tcapacity-dmips-mhz = <1024>;\n+\t\t\tcpu-idle-states = <&cpu_off_b>, <&cpu_s2idle>;\n+\t\t\ti-cache-size = <65536>;\n+\t\t\ti-cache-line-size = <64>;\n+\t\t\ti-cache-sets = <256>;\n+\t\t\td-cache-size = <65536>;\n+\t\t\td-cache-line-size = <64>;\n+\t\t\td-cache-sets = <256>;\n+\t\t\tnext-level-cache = <&l2_1>;\n+\t\t\tperformance-domains = <&performance 1>;\n+\t\t\t#cooling-cells = <2>;\n+\t\t};\n+\n+\t\tcpu-map {\n+\t\t\tcluster0 {\n+\t\t\t\tcore0 {\n+\t\t\t\t\tcpu = <&cpu0>;\n+\t\t\t\t};\n+\t\t\t\tcore1 {\n+\t\t\t\t\tcpu = <&cpu1>;\n+\t\t\t\t};\n+\t\t\t\tcore2 {\n+\t\t\t\t\tcpu = <&cpu2>;\n+\t\t\t\t};\n+\t\t\t\tcore3 {\n+\t\t\t\t\tcpu = <&cpu3>;\n+\t\t\t\t};\n+\t\t\t\tcore4 {\n+\t\t\t\t\tcpu = <&cpu4>;\n+\t\t\t\t};\n+\t\t\t\tcore5 {\n+\t\t\t\t\tcpu = <&cpu5>;\n+\t\t\t\t};\n+\t\t\t\tcore6 {\n+\t\t\t\t\tcpu = <&cpu6>;\n+\t\t\t\t};\n+\t\t\t\tcore7 {\n+\t\t\t\t\tcpu = <&cpu7>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\tidle-states {\n+\t\t\tentry-method = \"psci\";\n+\n+\t\t\tcpu_off_l: cpu-off-l {\n+\t\t\t\tcompatible = \"arm,idle-state\";\n+\t\t\t\tarm,psci-suspend-param = <0x00010000>;\n+\t\t\t\tlocal-timer-stop;\n+\t\t\t\tentry-latency-us = <25>;\n+\t\t\t\texit-latency-us = <57>;\n+\t\t\t\tmin-residency-us = <5700>;\n+\t\t\t};\n+\n+\t\t\tcpu_off_b: cpu-off-b {\n+\t\t\t\tcompatible = \"arm,idle-state\";\n+\t\t\t\tarm,psci-suspend-param = <0x00010000>;\n+\t\t\t\tlocal-timer-stop;\n+\t\t\t\tentry-latency-us = <35>;\n+\t\t\t\texit-latency-us = <82>;\n+\t\t\t\tmin-residency-us = <1890>;\n+\t\t\t};\n+\n+\t\t\tcpu_s2idle: cpu-s2idle {\n+\t\t\t\tcompatible = \"arm,idle-state\";\n+\t\t\t\tarm,psci-suspend-param = <0x020180ff>;\n+\t\t\t\tlocal-timer-stop;\n+\t\t\t\tentry-latency-us = <10000>;\n+\t\t\t\texit-latency-us = <10000>;\n+\t\t\t\tmin-residency-us = <4294967295>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tl2_0: l2-cache0 {\n+\t\t\tcompatible = \"cache\";\n+\t\t\tcache-level = <2>;\n+\t\t\tcache-size = <131072>;\n+\t\t\tcache-line-size = <64>;\n+\t\t\tcache-sets = <512>;\n+\t\t\tnext-level-cache = <&l3_0>;\n+\t\t\tcache-unified;\n+\t\t};\n+\n+\t\tl2_1: l2-cache1 {\n+\t\t\tcompatible = \"cache\";\n+\t\t\tcache-level = <2>;\n+\t\t\tcache-size = <262144>;\n+\t\t\tcache-line-size = <64>;\n+\t\t\tcache-sets = <512>;\n+\t\t\tnext-level-cache = <&l3_0>;\n+\t\t\tcache-unified;\n+\t\t};\n+\n+\t\tl3_0: l3-cache {\n+\t\t\tcompatible = \"cache\";\n+\t\t\tcache-level = <3>;\n+\t\t\tcache-size = <1048576>;\n+\t\t\tcache-line-size = <64>;\n+\t\t\tcache-sets = <2048>;\n+\t\t\tcache-unified;\n+\t\t};\n+\t};\n+\n+\tfirmware: firmware {\n+\t\tscmi: scmi {\n+\t\t\tcompatible = \"arm,scmi\";\n+\t\t\tmboxes = <&tinysys_mbox 0>, <&tinysys_mbox 1>;\n+\t\t\tshmem = <&scmi_tx_shmem>, <&scmi_rx_shmem>;\n+\t\t\tmbox-names = \"tx\", \"rx\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tscmi_tinysys: protocol@80 {\n+\t\t\t\treg = <0x80>;\n+\t\t\t\tmediatek,scmi-mminfra = <5>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tmemory: memory@40000000 {\n+\t\tdevice_type = \"memory\";\n+\t\t/* This memory size is filled in by the bootloader */\n+\t\treg = <0 0x40000000 0 0>;\n+\t};\n+\n+\tpmu-a55 {\n+\t\tcompatible = \"arm,cortex-a55-pmu\";\n+\t\tinterrupt-parent = <&gic>;\n+\t\tinterrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;\n+\t};\n+\n+\tpmu-a78 {\n+\t\tcompatible = \"arm,cortex-a78-pmu\";\n+\t\tinterrupt-parent = <&gic>;\n+\t\tinterrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;\n+\t};\n+\n+\tpsci {\n+\t\tcompatible = \"arm,psci-1.0\";\n+\t\tmethod = \"smc\";\n+\t};\n+\n+\treserved-memory {\n+\t\t/*TODO: add reserved memory node here*/\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tranges;\n+\n+\t\tafe_dma_mem_reserved: snd-dma-mem-region@60000000 {\n+\t\t\tcompatible = \"shared-dma-pool\";\n+\t\t\treg = <0 0x60000000 0 0x300000>;\n+\t\t\tno-map;\n+\t\t};\n+\t};\n+\n+\ttimer: timer {\n+\t\tcompatible = \"arm,armv8-timer\";\n+\t\tinterrupt-parent = <&gic>;\n+\t\tinterrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,\n+\t\t\t <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,\n+\t\t\t <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,\n+\t\t\t <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t};\n+\n+\twl_info: wl-info@c2bf090 {\n+\t\tcompatible = \"mediatek,wl-info\";\n+\t\twl-support = <0>;\n+\t\treg = <0 0x0c2bf090 0 0x10>, /*tcm sram base*/\n+\t\t\t<0 0x0c2c2f10 0 0x1520>; /*tcm wl-base sram*/\n+\t\treg-names = \"wl_sram_base\", \"wl_tbl_base\";\n+\t};\n+\n+\tsoc {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tranges;\n+\t\tdma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;\n+\n+\t\tcpuhvfs: cpuhvfs@100a00 {\n+\t\t\tcompatible = \"mediatek,cpufreq-hybrid\";\n+\t\t\treg = <0 0x00100a00 0 0xc00>,\n+\t\t\t <0 0x00108d68 0 0x1400>,\n+\t\t\t <0 0x0010a168 0 0x1800>,\n+\t\t\t <0 0x00103640 0 0xc0>;\n+\t\t\treg-names = \"USRAM\", \"CSRAM\", \"ESRAM\", \"FREQ_HW_STATE\";\n+\n+\t\t\t/* pll mcucfg */\n+\t\t\tmcucfg-ver = <0>;\n+\t\t};\n+\n+\t\tperformance: performance-controller@108d68 {\n+\t\t\tcompatible = \"mediatek,cpufreq-hw\";\n+\t\t\treg = <0 0x00108d78 0 0x120>,\n+\t\t\t <0 0x00108e98 0 0x120>;\n+\t\t\treg-names = \"performance-domain0\",\n+\t\t\t\t \"performance-domain1\";\n+\t\t\t#performance-domain-cells = <1>;\n+\t\t};\n+\n+\t\tgic: interrupt-controller@c000000 {\n+\t\t\tcompatible = \"arm,gic-v3\";\n+\t\t\t#interrupt-cells = <4>;\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tinterrupt-parent = <&gic>;\n+\t\t\tinterrupt-controller;\n+\t\t\treg = <0 0xc000000 0 0x40000>, /* distributor */\n+\t\t\t <0 0xc040000 0 0x200000>; /* redistributor */\n+\t\t\tinterrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;\n+\n+\t\t\tppi-partitions {\n+\t\t\t\tppi_cluster0: interrupt-partition-0 {\n+\t\t\t\t\taffinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;\n+\t\t\t\t};\n+\n+\t\t\t\tppi_cluster1: interrupt-partition-1 {\n+\t\t\t\t\taffinity = <&cpu6 &cpu7>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\tdbgao_clk: syscon@d01a000 {\n+\t\t\tcompatible = \"mediatek,mt8189-dbg-ao\", \"syscon\";\n+\t\t\treg = <0 0xd01a000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tsoc_dbg_error_flag: soc-dbg-error-flag@d01a000 {\n+\t\t\tcompatible = \"mediatek, soc-dbg-error-flag\";\n+\t\t\treg = <0 0x0d01a000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tinterrupt-names = \"dbg-error-flag\";\n+\t\t\t/* error flag mask description */\n+\t\t\tmcu2sub-emi-m1-parity-mask = <0x1>;\n+\t\t\tmcu2sub-emi-m0-parity-mask = <0x2>;\n+\t\t\tmcu2emi-m1-parity-mask = <0x4>;\n+\t\t\tmcu2emi-m0-parity-mask = <0x8>;\n+\t\t\tmcu2infra-reg-parity-mask = <0x10>;\n+\t\t\tinfra-l3-cache2mcu-parity-mask = <0x20>;\n+\t\t\temi-parity-cen-mask = <0x40>;\n+\t\t\temi-parity-sub-cen-mask = <0x80>;\n+\t\t\temi-parity-chan1-mask = <0x100>;\n+\t\t\temi-parity-chan2-mask = <0x200>;\n+\t\t\temi-parity-chan3-mask = <0x400>;\n+\t\t\temi-parity-chan4-mask = <0x800>;\n+\t\t\tdramc-error-flag-ch-a-mask = <0x1000>;\n+\t\t\tdramc-error-flag-ch-b-mask = <0x2000>;\n+\t\t\tdramc-error-flag-ch-c-mask = <0x4000>;\n+\t\t\tdramc-error-flag-ch-d-mask = <0x8000>;\n+\t\t\tap-tracker-timeout-mask = <0x10000>;\n+\t\t\tinfra-tracker-timeout-mask = <0x20000>;\n+\t\t\tinfra-lastbus-timeout-mask = <0x1000000>;\n+\t\t\tperi-lastbus-timeout-mask = <0x2000000>;\n+\t\t\tdram-md32-wdt-event-ch-a-mask = <0x8000000>;\n+\t\t\tdram-md32-wdt-event-ch-b-mask = <0x10000000>;\n+\t\t\tdram-md32-wdt-event-ch-c-mask = <0x20000000>;\n+\t\t};\n+\n+\t\tdem_clk: syscon@d0a0000 {\n+\t\t\tcompatible = \"mediatek,mt8189-dem\", \"syscon\";\n+\t\t\treg = <0 0xd0a0000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\ttopckgen_clk: syscon@10000000 {\n+\t\t\tcompatible = \"mediatek,mt8189-topckgen\", \"syscon\";\n+\t\t\treg = <0 0x10000000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tinfracfg_ao_clk: syscon@10001000 {\n+\t\t\tcompatible = \"mediatek,mt8189-infra-ao\", \"syscon\";\n+\t\t\treg = <0 0x10001000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tpio: pinctrl@10005000 {\n+\t\t\tcompatible = \"mediatek,mt8189-pinctrl\";\n+\t\t\treg = <0 0x10005000 0 0x1000>,\n+\t\t\t <0 0x11b50000 0 0x1000>,\n+\t\t\t <0 0x11c50000 0 0x1000>,\n+\t\t\t <0 0x11c60000 0 0x1000>,\n+\t\t\t <0 0x11d20000 0 0x1000>,\n+\t\t\t <0 0x11d30000 0 0x1000>,\n+\t\t\t <0 0x11d40000 0 0x1000>,\n+\t\t\t <0 0x11e20000 0 0x1000>,\n+\t\t\t <0 0x11e30000 0 0x1000>,\n+\t\t\t <0 0x11f20000 0 0x1000>,\n+\t\t\t <0 0x11ce0000 0 0x1000>,\n+\t\t\t <0 0x11de0000 0 0x1000>,\n+\t\t\t <0 0x11e60000 0 0x1000>,\n+\t\t\t <0 0x1c01e000 0 0x1000>,\n+\t\t\t <0 0x11f00000 0 0x1000>;\n+\t\t\treg-names = \"base\",\n+\t\t\t\t \"lm\",\n+\t\t\t\t \"rb0\",\n+\t\t\t\t \"rb1\",\n+\t\t\t\t \"bm0\",\n+\t\t\t\t \"bm1\",\n+\t\t\t\t \"bm2\",\n+\t\t\t\t \"lt0\",\n+\t\t\t\t \"lt1\",\n+\t\t\t\t \"rt\",\n+\t\t\t\t \"eint0\",\n+\t\t\t\t \"eint1\",\n+\t\t\t\t \"eint2\",\n+\t\t\t\t \"eint3\",\n+\t\t\t\t \"eint4\";\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <2>;\n+\t\t\tgpio-ranges = <&pio 0 0 182>;\n+\t\t\tinterrupt-controller;\n+\t\t\tinterrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t#interrupt-cells = <2>;\n+\t\t};\n+\n+\t\tapmixedsys_clk: syscon@1000c000 {\n+\t\t\tcompatible = \"mediatek,mt8189-apmixedsys\", \"syscon\";\n+\t\t\treg = <0 0x1000c000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tdevapc_infra: devapc@10207000 {\n+\t\t\tcompatible = \"mediatek,mt8189-devapc\";\n+\t\t\treg = <0 0x10207000 0 0x1000>,\n+\t\t\t <0 0x10030000 0 0x1000>; /* infra ao/pd */\n+\t\t\tvio-idx-num = <105>;\n+\t\t\tinterrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;/* infra irq */\n+\t\t};\n+\n+\t\temicen: emicen@10219000 {\n+\t\t\tcompatible = \"mediatek,mt8189-emicen\";\n+\t\t\treg = <0 0x10219000 0 0x1000>;\n+\t\t\tmediatek,emi-reg = <&emichn>;\n+\t\t};\n+\n+\t\temichn: emichn@10235000 {\n+\t\t\tcompatible = \"mediatek,common-emichn\";\n+\t\t\treg = <0 0x10235000 0 0x1000>,\n+\t\t\t\t<0 0x10245000 0 0x1000>;\n+\t\t};\n+\n+\t\temicfg_ao_mem_clk: syscon@10270000 {\n+\t\t\tcompatible = \"mediatek,mt8189-emicfg-ao-mem\", \"syscon\";\n+\t\t\treg = <0 0x10270000 0 0x1000>;\n+\t\t};\n+\n+\t\tdevapc_infra1: devapc@10274000 {\n+\t\t\tcompatible = \"mediatek,mt8189-devapc\";\n+\t\t\treg = <0 0x10274000 0 0x1000>,\n+\t\t\t <0 0x10034000 0 0x1000>; /* infra1 ao/pd */\n+\t\t\tvio-idx-num = <132>;\n+\t\t\tinterrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;/* infra irq */\n+\t\t};\n+\n+\t\tlvts_ap: lvts@10315000 {\n+\t\t\tcompatible = \"mediatek,mt8189-lvts-ap\";\n+\t\t\treg = <0 0x10315000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t#thermal-sensor-cells = <1>;\n+\t\t\tnvmem-cells = <&lvts_e_data1>, <&lvts_e_data2>;\n+\t\t\tnvmem-cell-names = \"lvts-calib-data-1\", \"lvts-calib-data-2\";\n+\t\t};\n+\n+\t\tlvts_mcu: lvts@10316000 {\n+\t\t\tcompatible = \"mediatek,mt8189-lvts-mcu\";\n+\t\t\treg = <0 0x10316000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t#thermal-sensor-cells = <1>;\n+\t\t\tnvmem-cells = <&lvts_e_data1>, <&lvts_e_data2>;\n+\t\t\tnvmem-cell-names = \"lvts-calib-data-1\", \"lvts-calib-data-2\";\n+\t\t};\n+\n+\t\tinfra_iommu_m4: iommu@10330000 {\n+\t\t\tcompatible = \"mediatek,mt8189-iommu-infra\";\n+\t\t\treg = <0 0x10330000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t#iommu-cells = <1>;\n+\t\t};\n+\n+\t\tinfra_iommu_m7: iommu@1033a000 {\n+\t\t\tcompatible = \"mediatek,mt8189-iommu-infra\";\n+\t\t\treg = <0 0x1033a000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t#iommu-cells = <1>;\n+\t\t};\n+\n+\t\tuart0: serial@11001000 {\n+\t\t\tcompatible = \"mediatek,mt8189-uart\", \"mediatek,mt6577-uart\";\n+\t\t\treg = <0 0x11001000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&clk26m>, <&pericfg_ao_clk CLK_PERAO_UART0>;\n+\t\t\tclock-names = \"baud\", \"bus\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tafe: mt8189-afe-pcm@11050000 {\n+\t\t\tcompatible = \"mediatek,mt8189-afe-pcm\";\n+\t\t\treg = <0 0x11050000 0 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_AUDIO>;\n+\t\t\tmemory-region = <&afe_dma_mem_reserved>;\n+\t\t\tclocks = <&topckgen_clk CLK_TOP_AUD_INTBUS_SEL>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_AUD_ENGEN1_SEL>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_AUD_ENGEN2_SEL>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_AUDIO_H_SEL>,\n+\t\t\t\t <&apmixedsys_clk CLK_APMIXED_APLL1>,\n+\t\t\t\t <&apmixedsys_clk CLK_APMIXED_APLL2>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_APLL1_D4>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_APLL2_D4>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_APLL12_CK_DIV_I2SIN0>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_APLL12_CK_DIV_I2SIN1>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_APLL12_CK_DIV_I2SOUT0>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_APLL12_CK_DIV_I2SOUT1>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_APLL12_CK_DIV_FMI2S>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_APLL12_CK_DIV_TDMOUT_M>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_APLL12_CK_DIV_TDMOUT_B>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_AUD_1_SEL>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_AUD_2_SEL>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_APLL_I2SIN0_MCK_SEL>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_APLL_I2SIN1_MCK_SEL>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_APLL_I2SOUT0_MCK_SEL>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_APLL_I2SOUT1_MCK_SEL>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_APLL_FMI2S_MCK_SEL>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_APLL_TDMOUT_MCK_SEL>,\n+\t\t\t\t <&clk26m>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_AUDIO0>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_AUDIO1>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_AUDIO2>;\n+\t\t\tclock-names = \"top_aud_intbus\",\n+\t\t\t\t \"top_aud_eng1\",\n+\t\t\t\t \"top_aud_eng2\",\n+\t\t\t\t \"top_aud_h\",\n+\t\t\t\t \"apll1\",\n+\t\t\t\t \"apll2\",\n+\t\t\t\t \"apll1_d4\",\n+\t\t\t\t \"apll2_d4\",\n+\t\t\t\t \"apll12_div_i2sin0\",\n+\t\t\t\t \"apll12_div_i2sin1\",\n+\t\t\t\t \"apll12_div_i2sout0\",\n+\t\t\t\t \"apll12_div_i2sout1\",\n+\t\t\t\t \"apll12_div_fmi2s\",\n+\t\t\t\t \"apll12_div_tdmout_m\",\n+\t\t\t\t \"apll12_div_tdmout_b\",\n+\t\t\t\t \"top_apll1\",\n+\t\t\t\t \"top_apll2\",\n+\t\t\t\t \"top_i2sin0\",\n+\t\t\t\t \"top_i2sin1\",\n+\t\t\t\t \"top_i2sout0\",\n+\t\t\t\t \"top_i2sout1\",\n+\t\t\t\t \"top_fmi2s\",\n+\t\t\t\t \"top_dptx\",\n+\t\t\t\t \"clk26m\",\n+\t\t\t\t \"aud_slv_ck_peri\",\n+\t\t\t\t \"aud_mst_ck_peri\",\n+\t\t\t\t \"aud_intbus_ck_peri\";\n+\t\t\tmediatek,apmixedsys = <&apmixedsys_clk>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tsound: sound {\n+\t\t\tmediatek,platform = <&afe>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tdisp_pwm0: pwm@1100e000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-pwm\", \"mediatek,mt8183-disp-pwm\";\n+\t\t\treg = <0 0x1100e000 0 0x1000>;\n+\t\t\tclocks = <&pericfg_ao_clk CLK_PERAO_DISP_PWM0>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_DISP_PWM_SEL>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_OSC_D4>;\n+\t\t\tclock-names = \"main\", \"mm\", \"pwm_src\";\n+\t\t\tinterrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t#pwm-cells = <2>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tspi0: spi@11010800 {\n+\t\t\tcompatible = \"mediatek,mt8189-spi\";\n+\t\t\treg = <0 0x11010800 0 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_SPI0_SEL>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SPI0_B>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SPI0_H>;\n+\t\t\tclock-names = \"parent-clk\", \"sel-clk\", \"spi-clk\", \"hclk\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tmediatek,pad-select = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tspi1: spi@11011800 {\n+\t\t\tcompatible = \"mediatek,mt8189-spi\";\n+\t\t\treg = <0 0x11011800 0 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_SPI1_SEL>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SPI1_B>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SPI1_H>;\n+\t\t\tclock-names = \"parent-clk\", \"sel-clk\", \"spi-clk\", \"hclk\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tmediatek,pad-select = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tspi2: spi@11012800 {\n+\t\t\tcompatible = \"mediatek,mt8189-spi\";\n+\t\t\treg = <0 0x11012800 0 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_SPI2_SEL>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SPI2_B>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SPI2_H>;\n+\t\t\tclock-names = \"parent-clk\", \"sel-clk\", \"spi-clk\", \"hclk\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tmediatek,pad-select = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tspi3: spi@11013800 {\n+\t\t\tcompatible = \"mediatek,mt8189-spi\";\n+\t\t\treg = <0 0x11013800 0 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_SPI3_SEL>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SPI3_B>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SPI3_H>;\n+\t\t\tclock-names = \"parent-clk\", \"sel-clk\", \"spi-clk\", \"hclk\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tmediatek,pad-select = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tspi4: spi@11014800 {\n+\t\t\tcompatible = \"mediatek,mt8189-spi\";\n+\t\t\treg = <0 0x11014800 0 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_SPI4_SEL>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SPI4_B>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SPI4_H>;\n+\t\t\tclock-names = \"parent-clk\", \"sel-clk\", \"spi-clk\", \"hclk\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tmediatek,pad-select = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tspi5: spi@11015800 {\n+\t\t\tcompatible = \"mediatek,mt8189-spi\";\n+\t\t\treg = <0 0x11015800 0 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_SPI5_SEL>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SPI5_B>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SPI5_H>;\n+\t\t\tclock-names = \"parent-clk\", \"sel-clk\", \"spi-clk\", \"hclk\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tmediatek,pad-select = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tnor_flash: spi@11018000 {\n+\t\t\tcompatible = \"mediatek,mt8189-nor\",\"mediatek,mt8186-nor\";\n+\t\t\treg = <0 0x11018000 0 0x1000>;\n+\t\t\tclocks = <&topckgen_clk CLK_TOP_SFLASH_SEL>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SFLASH>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SFLASH_F>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SFLASH_H>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SFLASH_P>;\n+\t\t\tclock-names = \"spi\", \"sf\", \"axi_f\", \"axi_h\", \"axi_p\";\n+\t\t\tassigned-clocks = <&topckgen_clk CLK_TOP_SFLASH_SEL>;\n+\t\t\tassigned-clock-parents = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D8>;\n+\t\t\tinterrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tauxadc: adc@11019000 {\n+\t\t\tcompatible = \"mediatek,mt8189-auxadc\", \"mediatek,mt8173-auxadc\";\n+\t\t\treg = <0 0x11019000 0 0x1000>;\n+\t\t\tclocks = <&pericfg_ao_clk CLK_PERAO_AUXADC_26M>;\n+\t\t\tclock-names = \"main\";\n+\t\t\t#io-channel-cells = <1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tdevapc_peri: devapc@11020000 {\n+\t\t\tcompatible = \"mediatek,mt8189-devapc\";\n+\t\t\treg = <0 0x11020000 0 0x1000>,\n+\t\t\t <0 0x1103c000 0 0x1000>; /* peri ao/pd */\n+\t\t\tvio-idx-num = <62>;\n+\t\t\tinterrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING 0>; /* peri irq */\n+\t\t};\n+\n+\t\tpericfg_ao_clk: syscon@11036000 {\n+\t\t\tcompatible = \"mediatek,mt8189-peri-ao\", \"syscon\", \"simple-mfd\";\n+\t\t\treg = <0 0x11036000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t\tusb_rst: reset-controller {\n+\t\t\t\tcompatible = \"ti,syscon-reset\";\n+\t\t\t\t#reset-cells = <1>;\n+\t\t\t\treset-duration-us = <100>;\n+\t\t\t\tti,reset-bits = <\n+\t\t\t\t\t/* xhci mac reset */\n+\t\t\t\t\t/* 22: xhci */\n+\t\t\t\t\t0x0 22 0x0 22 0 0\n+\t\t\t\t\t(ASSERT_SET|ASSERT_CLEAR|STATUS_NONE)\n+\t\t\t\t>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tafe_clk: syscon@11050000 {\n+\t\t\tcompatible = \"mediatek,mt8189-audiosys\", \"syscon\";\n+\t\t\treg = <0 0x11050000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\txhci0: usb@11200000 {\n+\t\t\tcompatible = \"mediatek,mt8189-xhci\", \"mediatek,mtk-xhci\";\n+\t\t\treg = <0 0x11200000 0 0x1000>,\n+\t\t\t <0 0x11203e00 0 0x0100>;\n+\t\t\treg-names = \"mac\", \"ippc\";\n+\t\t\tinterrupts-extended = <&gic GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH 0>,\n+\t\t\t\t\t <&pio 207 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"host\",\"wakeup\";\n+\t\t\tphys = <&u2port0 PHY_TYPE_USB2>,\n+\t\t\t <&u3port0 PHY_TYPE_USB3>;\n+\t\t\tclocks = <&pericfg_ao_clk CLK_PERAO_SSUSB0_SYS>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB0_REF>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB0_H>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB0_F>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB0_XHCI>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB0_FRMCNT>;\n+\t\t\tclock-names = \"sys_ck\", \"ref_ck\", \"mcu_ck\",\n+\t\t\t\t \"dma_ck\", \"xhci_ck\", \"frmcnt_ck\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tresets = <&usb_rst 0>;\n+\t\t\twakeup-source;\n+\t\t\tmediatek,syscon-wakeup = <&pericfg_ao_clk 0x214 110>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\txhci1: usb@11210000 {\n+\t\t\tcompatible = \"mediatek,mt8189-xhci\", \"mediatek,mtk-xhci\";\n+\t\t\treg = <0 0x11210000 0 0x1000>,\n+\t\t\t <0 0x11213e00 0 0x0100>;\n+\t\t\treg-names = \"mac\", \"ippc\";\n+\t\t\tinterrupts-extended = <&gic GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,\n+\t\t\t\t\t <&pio 203 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"host\",\"wakeup\";\n+\t\t\tphys = <&u2port1 PHY_TYPE_USB2>;\n+\t\t\tclocks = <&pericfg_ao_clk CLK_PERAO_SSUSB1_SYS>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB1_REF>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB1_H>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB1_F>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB1_XHCI>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB1_FRMCNT>;\n+\t\t\tclock-names = \"sys_ck\", \"ref_ck\",\"mcu_ck\",\n+\t\t\t\t \"dma_ck\", \"xhci_ck\", \"frmcnt_ck\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_SSUSB>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\twakeup-source;\n+\t\t\tmediatek,syscon-wakeup = <&pericfg_ao_clk 0x21c 110>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\txhci2: usb@11220000 {\n+\t\t\tcompatible = \"mediatek,mt8189-xhci\", \"mediatek,mtk-xhci\";\n+\t\t\treg = <0 0x11220000 0 0x1000>,\n+\t\t\t <0 0x11223e00 0 0x0100>;\n+\t\t\treg-names = \"mac\", \"ippc\";\n+\t\t\tinterrupts-extended = <&gic GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH 0>,\n+\t\t\t\t\t <&pio 193 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"host\",\"wakeup\";\n+\t\t\tphys = <&u2port2 PHY_TYPE_USB2>;\n+\t\t\tclocks = <&pericfg_ao_clk CLK_PERAO_SSUSB2_SYS>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB2_REF>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB2_H>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB2_F>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB2_XHCI>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB2_FRMCNT>;\n+\t\t\tclock-names = \"sys_ck\", \"ref_ck\",\"mcu_ck\",\n+\t\t\t\t \"dma_ck\", \"xhci_ck\", \"frmcnt_ck\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_SSUSB>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\twakeup-source;\n+\t\t\tmediatek,syscon-wakeup = <&pericfg_ao_clk 0x27c 110>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tmmc0: mmc@11230000 {\n+\t\t\tcompatible = \"mediatek,mt8189-mmc\";\n+\t\t\treg = <0 0x11230000 0 0x10000>,\n+\t\t\t <0 0x11e70000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&topckgen_clk CLK_TOP_MSDC50_0_SEL>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_MSDC0_H>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_MSDC0>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_MSDC50_0_HCLK_SEL>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_MSDC0_SLV_H>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_MSDC0_MST_F>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_MSDC50_0_SEL>;\n+\t\t\tclock-names = \"source\", \"hclk\", \"source_cg\", \"bus_clk\",\n+\t\t\t\t \"pclk_cg\", \"axi_cg\", \"crypto\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tmmc1: mmc@11240000 {\n+\t\t\tcompatible = \"mediatek,mt8189-mmc\";\n+\t\t\treg = <0 0x11240000 0 0x1000>,\n+\t\t\t <0 0x11d80000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&topckgen_clk CLK_TOP_MSDC30_1_SEL>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_MSDC1_H>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_MSDC1>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_MSDC30_1_HCLK_SEL>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_MSDC1_SLV_H>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_MSDC1_MST_F>;\n+\t\t\tclock-names = \"source\", \"hclk\", \"source_cg\", \"bus_clk\",\n+\t\t\t\t \"pclk_cg\", \"axi_cg\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\txhci3: usb@11260000 {\n+\t\t\tcompatible = \"mediatek,mt8189-xhci\", \"mediatek,mtk-xhci\";\n+\t\t\treg = <0 0x11260000 0 0x2e00>,\n+\t\t\t <0 0x11263e00 0 0x0100>;\n+\t\t\treg-names = \"mac\", \"ippc\";\n+\t\t\tinterrupts-extended = <&gic GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH 0>,\n+\t\t\t\t\t <&pio 188 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"host\",\"wakeup\";\n+\t\t\tphys = <&u2port3 PHY_TYPE_USB2>,\n+\t\t\t <&u3port3 PHY_TYPE_USB3>;\n+\t\t\tclocks = <&pericfg_ao_clk CLK_PERAO_SSUSB3_SYS>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB3_REF>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB3_H>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB3_F>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB3_XHCI>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB3_FRMCNT>;\n+\t\t\tclock-names = \"sys_ck\", \"ref_ck\", \"mcu_ck\",\n+\t\t\t\t \"dma_ck\", \"xhci_ck\", \"frmcnt_ck\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_SSUSB>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\twakeup-source;\n+\t\t\tmediatek,syscon-wakeup = <&pericfg_ao_clk 0x284 110>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\txhci4: usb@11270000 {\n+\t\t\tcompatible = \"mediatek,mt8189-xhci\", \"mediatek,mtk-xhci\";\n+\t\t\treg = <0 0x11270000 0 0x1000>,\n+\t\t\t <0 0x11273e00 0 0x0100>;\n+\t\t\treg-names = \"mac\", \"ippc\";\n+\t\t\tinterrupts-extended = <&gic GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH 0>,\n+\t\t\t\t\t <&pio 184 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"host\",\"wakeup\";\n+\t\t\tphys = <&u2port4 PHY_TYPE_USB2>;\n+\t\t\tclocks = <&pericfg_ao_clk CLK_PERAO_SSUSB4_SYS>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB4_REF>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB4_H>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB4_F>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB4_XHCI>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_SSUSB4_FRMCNT>;\n+\t\t\tclock-names = \"sys_ck\", \"ref_ck\", \"mcu_ck\",\n+\t\t\t\t \"dma_ck\", \"xhci_ck\", \"frmcnt_ck\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\twakeup-source;\n+\t\t\tmediatek,syscon-wakeup = <&pericfg_ao_clk 0x28c 110>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tufshci: ufshci@112b0000 {\n+\t\t\tcompatible = \"mediatek,mt8183-ufshci\";\n+\t\t\treg = <0 0x112b0000 0 0x2300>;\n+\t\t\tinterrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;\n+\n+\t\t\tclocks = <&topckgen_clk CLK_TOP_U_SEL>,\n+\t\t\t\t <&clk26m>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_MSDCPLL_D2>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_AES_UFSFDE_SEL>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_U_MBIST_SEL>,\n+\t\t\t\t <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM>,\n+\t\t\t\t <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0>,\n+\t\t\t\t <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1>,\n+\t\t\t\t <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_SYS>,\n+\t\t\t\t <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_U_SAP_CFG>,\n+\t\t\t\t <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS>,\n+\t\t\t\t <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_UFS>,\n+\t\t\t\t <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_AES>,\n+\t\t\t\t <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_U_AHB>,\n+\t\t\t\t <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_U_AXI>;\n+\n+\t\t\tclock-names = \"ufs_sel\",\n+\t\t\t\t \"ufs_sel_min_src\",\n+\t\t\t\t \"ufs_sel_max_src\",\n+\t\t\t\t \"ufs_fde\",\n+\t\t\t\t \"ufs_mbist\",\n+\t\t\t\t \"unipro_tx_sym\",\n+\t\t\t\t \"unipro_rx_sym0\",\n+\t\t\t\t \"unipro_rx_sym1\",\n+\t\t\t\t \"unipro_sys\",\n+\t\t\t\t \"unipro_phy_sap\",\n+\t\t\t\t \"phy_top_ahb_s_bus\",\n+\t\t\t\t \"ufshci_ufs\",\n+\t\t\t\t \"ufshci_aes\",\n+\t\t\t\t \"ufshci_ufs_ahb\",\n+\t\t\t\t \"ufshci_aes_axi\";\n+\n+\t\t\tfreq-table-hz = <26000000 208000000>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>,\n+\t\t\t\t\t<0 0>;\n+\n+\t\t\tvcc-supply = <&mt6359_vemc_1_ldo_reg>;\n+\t\t\tvccq-supply = <&mt6359_vio18_ldo_reg>;\n+\t\t\tvccq2-supply = <&mt6359_vufs_ldo_reg>;\n+\n+\t\t\tresets = <&ufscfgpdn_rst 0>,\n+\t\t\t\t <&ufscfgpdn_rst 1>,\n+\t\t\t\t <&ufscfgpdn_rst 2>;\n+\n+\t\t\treset-names = \"unipro_rst\",\n+\t\t\t\t \"crypto_rst\",\n+\t\t\t\t \"hci_rst\";\n+\n+\t\t\tmediatek,ufs-disable-mcq;\n+\t\t\tmediatek,ufs-rtff-mtcmos;\n+\t\t\tmediatek,ufs-broken-vcc;\n+\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tufscfg_ao_reg_clk: syscon@112b8000 {\n+\t\t\tcompatible = \"mediatek,mt8189-ufscfg-ao\", \"syscon\", \"simple-mfd\";\n+\t\t\treg = <0 0x112b8000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\n+\t\t\tufscfgao_rst: reset-controller {\n+\t\t\t\tcompatible = \"ti,syscon-reset\";\n+\t\t\t\t#reset-cells = <1>;\n+\n+\t\t\t\tti,reset-bits = <\n+\t\t\t\t\t/* ufs mphy reset */\n+\t\t\t\t\t/* 8: mphy */\n+\t\t\t\t\t0x48 8 0x4c 8 0 0\n+\t\t\t\t\t(ASSERT_SET | DEASSERT_SET | STATUS_NONE)\n+\t\t\t\t>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tufscfg_pdn_reg_clk: syscon@112bb000 {\n+\t\t\tcompatible = \"mediatek,mt8189-ufscfg-pdn\", \"syscon\", \"simple-mfd\";\n+\t\t\treg = <0 0x112bb000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\n+\t\t\tufscfgpdn_rst: reset-controller {\n+\t\t\t\tcompatible = \"ti,syscon-reset\";\n+\t\t\t\t#reset-cells = <1>;\n+\n+\t\t\t\tti,reset-bits = <\n+\t\t\t\t\t/* ufs ufschi/crypto/unipro reset */\n+\t\t\t\t\t/* 0: unipro */\n+\t\t\t\t\t0x48 0 0x4c 0 0 0\n+\t\t\t\t\t(ASSERT_SET | DEASSERT_SET | STATUS_NONE)\n+\t\t\t\t\t/* 1: ufs-crypto */\n+\t\t\t\t\t0x48 1 0x4c 1 0 0\n+\t\t\t\t\t(ASSERT_SET | DEASSERT_SET | STATUS_NONE)\n+\t\t\t\t\t/* 2: ufshci */\n+\t\t\t\t\t0x48 2 0x4c 2 0 0\n+\t\t\t\t\t(ASSERT_SET | DEASSERT_SET | STATUS_NONE)\n+\t\t\t\t>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tpcie: pcie@112f0000 {\n+\t\t\tcompatible = \"mediatek,mt8189-pcie\",\n+\t\t\t\t \"mediatek,mt8192-pcie\";\n+\t\t\treg = <0 0x112f0000 0 0x4000>;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\treg-names = \"pcie-mac\";\n+\t\t\tlinux,pci-domain = <0>;\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tinterrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tbus-range = <0x00 0xff>;\n+\t\t\tranges = <0x82000000 0 0x30000000\n+\t\t\t\t 0x0 0x30000000 0 0x04000000>;\n+\n+\t\t\tclocks = <&pericfg_ao_clk CLK_PERAO_AXI>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_AHB_APB>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_TL>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_REF>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_F26M_CK_EN>;\n+\n+\t\t\tphys = <&pcieport PHY_TYPE_PCIE>;\n+\t\t\tphy-names = \"pcie-phy\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_PCIE>;\n+\n+\t\t\t#interrupt-cells = <1>;\n+\t\t\tinterrupt-map-mask = <0 0 0 7>;\n+\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc 0>,\n+\t\t\t\t\t<0 0 0 2 &pcie_intc 1>,\n+\t\t\t\t\t<0 0 0 3 &pcie_intc 2>,\n+\t\t\t\t\t<0 0 0 4 &pcie_intc 3>;\n+\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tpcie_intc: interrupt-controller {\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#address-cells = <0>;\n+\t\t\t\t#interrupt-cells = <1>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tu3phy3: t-phy@11b00000 {\n+\t\t\tcompatible = \"mediatek,mt8189-tphy\",\n+\t\t\t\t \"mediatek,generic-tphy-v2\";\n+\t\t\treg = <0 0x11b00000 0 0x700>;\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\n+\t\t\tu2port3: usb-phy@11b00000 {\n+\t\t\t\treg = <0 0x11b00000 0 0x700>;\n+\t\t\t\tclocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P3_EN>;\n+\t\t\t\tclock-names = \"ref\";\n+\t\t\t\t#phy-cells = <1>;\n+\t\t\t};\n+\n+\t\t\tu3port3: usb-phy@11b00700 {\n+\t\t\t\treg = <0 0x11b00700 0 0x700>;\n+\t\t\t\tclocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P3_EN>;\n+\t\t\t\tclock-names = \"ref\";\n+\t\t\t\t#phy-cells = <1>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tu2phy4: xs-phy@11b10000 {\n+\t\t\tcompatible = \"mediatek,mt8189-xsphy\", \"mediatek,xsphy\";\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\n+\t\t\tu2port4: usb-phy@11b10000 {\n+\t\t\t\treg = <0 0x11b10000 0 0x700>;\n+\t\t\t\tclocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P4_EN>;\n+\t\t\t\tclock-names = \"ref\";\n+\t\t\t\t#phy-cells = <1>;\n+\t\t\t};\n+\t\t};\n+\n+\t\ti2c2: i2c@11b20000 {\n+\t\t\tcompatible = \"mediatek,mt8188-i2c\";\n+\t\t\treg = <0 0x11b20000 0 0x1000>,\n+\t\t\t <0 0x11300400 0 0x80>;\n+\t\t\tinterrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&imp_iic_wrap_ws_clk CLK_IMPWS_I2C2>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_DMA_B>;\n+\t\t\tclock-names = \"main\", \"dma\";\n+\t\t\tclock-div = <1>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\timp_iic_wrap_ws_clk: syscon@11b21e00 {\n+\t\t\tcompatible = \"mediatek,mt8189-iic-wrap-ws\", \"syscon\";\n+\t\t\treg = <0 0x11b21e00 0 0x10>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tmipi_tx_config0: mipi-tx-config@11b40000 {\n+\t\t\tcompatible = \"mediatek,mt8189-mipi-tx\";\n+\t\t\treg = <0 0x11b40000 0 0x1000>;\n+\t\t\tclocks = <&clk26m>;\n+\t\t\t#clock-cells = <0>;\n+\t\t\t#phy-cells = <0>;\n+\t\t\tclock-output-names = \"mipi_tx0_pll\";\n+\t\t\tdispsys-sel-offset = <0x170 0x174>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tdp_tx: dp-tx@11b60000 {\n+\t\t\tcompatible = \"mediatek,mt8189-dp-tx\";\n+\t\t\treg = <0 0x11b60000 0 0x5000>,\n+\t\t\t <0 0x11c10000 0 0x1500>,\n+\t\t\t <0 0x10011018 0 0x4>,\n+\t\t\t <0 0x1c001e80 0 0x4>;\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_DP_TX>,\n+\t\t\t\t\t<&spm MT8189_POWER_DOMAIN_SSUSB>;\n+\t\t\tpower-domain-names = \"pd_dp_tx\", \"pd_dp_phy\";\n+\t\t\tinterrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t#phy-cells = <0>;\n+\t\t\tclocks = <&topckgen_clk CLK_TOP_DP_SEL>,\n+\t\t\t\t <&clk26m>;\n+\t\t\tclock-names = \"mux_dp\", \"ck_26m\";\n+\t\t};\n+\n+\t\tedp_tx: edp-tx@11b70000 {\n+\t\t\tcompatible = \"mediatek,mt8189-edp-tx\";\n+\t\t\treg = <0 0x11b70000 0 0x14000>,\n+\t\t\t <0 0x11e10000 0 0x1500>;\n+\t\t\tinterrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_EDP_TX_DORMANT>;\n+\t\t\tclocks = <&topckgen_clk CLK_TOP_EDP_SEL>;\n+\t\t\tclock-names = \"power\";\n+\t\t};\n+\n+\t\ti2c0: i2c@11c20000 {\n+\t\t\tcompatible = \"mediatek,mt8188-i2c\";\n+\t\t\treg = <0 0x11c20000 0 0x1000>,\n+\t\t\t <0 0x11300200 0 0x80>;\n+\t\t\tinterrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&imp_iic_wrap_e_clk CLK_IMPE_I2C0>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_DMA_B>;\n+\t\t\tclock-names = \"main\", \"dma\";\n+\t\t\tclock-div = <1>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\ti2c1: i2c@11c21000 {\n+\t\t\tcompatible = \"mediatek,mt8188-i2c\";\n+\t\t\treg = <0 0x11c21000 0 0x1000>,\n+\t\t\t <0 0x11300300 0 0x80>;\n+\t\t\tinterrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&imp_iic_wrap_e_clk CLK_IMPE_I2C1>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_DMA_B>;\n+\t\t\tclock-names = \"main\", \"dma\";\n+\t\t\tclock-div = <1>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\timp_iic_wrap_e_clk: syscon@11c22e00 {\n+\t\t\tcompatible = \"mediatek,mt8189-iic-wrap-e\", \"syscon\";\n+\t\t\treg = <0 0x11c22e00 0 0x10>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\ti2c3: i2c@11d70000 {\n+\t\t\tcompatible = \"mediatek,mt8188-i2c\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0 0x11d70000 0 0x1000>,\n+\t\t\t <0 0x11300500 0 0x80>;\n+\t\t\tinterrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&imp_iic_wrap_s_clk CLK_IMPS_I2C3>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_DMA_B>;\n+\t\t\tclock-names = \"main\", \"dma\";\n+\t\t\tclock-div = <1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\ti2c4: i2c@11d71000 {\n+\t\t\tcompatible = \"mediatek,mt8188-i2c\";\n+\t\t\treg = <0 0x11d71000 0 0x1000>,\n+\t\t\t <0 0x11300600 0 0x80>;\n+\t\t\tinterrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&imp_iic_wrap_s_clk CLK_IMPS_I2C4>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_DMA_B>;\n+\t\t\tclock-names = \"main\", \"dma\";\n+\t\t\tclock-div = <1>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\ti2c5: i2c@11d72000 {\n+\t\t\tcompatible = \"mediatek,mt8188-i2c\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0 0x11d72000 0 0x1000>,\n+\t\t\t <0 0x11300700 0 0x80>;\n+\t\t\tinterrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&imp_iic_wrap_s_clk CLK_IMPS_I2C5>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_DMA_B>;\n+\t\t\tclock-names = \"main\", \"dma\";\n+\t\t\tclock-div = <1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\ti2c6: i2c@11d73000 {\n+\t\t\tcompatible = \"mediatek,mt8188-i2c\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0 0x11d73000 0 0x1000>,\n+\t\t\t <0 0x11300800 0 0x80>;\n+\t\t\tinterrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&imp_iic_wrap_s_clk CLK_IMPS_I2C6>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_DMA_B>;\n+\t\t\tclock-names = \"main\", \"dma\";\n+\t\t\tclock-div = <1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\timp_iic_wrap_s_clk: syscon@11d74e00 {\n+\t\t\tcompatible = \"mediatek,mt8189-iic-wrap-s\", \"syscon\";\n+\t\t\treg = <0 0x11d74e00 0 0x10>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tpciephy: t-phy@11e50700 {\n+\t\t\tcompatible = \"mediatek,mt8189-tphy\",\n+\t\t\t\t \"mediatek,generic-tphy-v2\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0x0 0x0 0x11e50700 0x700>;\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_PCIE_PHY>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tpcieport: pcie-phy@0 {\n+\t\t\t\treg = <0 0x700>;\n+\t\t\t\t#phy-cells = <1>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tu3phy0: xs-phy@11e80000 {\n+\t\t\tcompatible = \"mediatek,mt8189-xsphy\", \"mediatek,xsphy\";\n+\t\t\treg = <0 0x11e83000 0 0x200>;\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\n+\t\t\tu2port0: usb-phy@11e80000 {\n+\t\t\t\treg = <0 0x11e80000 0 0x700>;\n+\t\t\t\tclocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P0_EN>;\n+\t\t\t\tclock-names = \"ref\";\n+\t\t\t\t#phy-cells = <1>;\n+\t\t\t};\n+\n+\t\t\tu3port0: usb-phy@11e83000 {\n+\t\t\t\treg = <0 0x11e83400 0 0x500>;\n+\t\t\t\tclocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P0_EN>;\n+\t\t\t\tclock-names = \"ref\";\n+\t\t\t\t#phy-cells = <1>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tu2phy1: xs-phy@11e90000 {\n+\t\t\tcompatible = \"mediatek,mt8189-xsphy\", \"mediatek,xsphy\";\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\n+\t\t\tu2port1: usb-phy@11e90000 {\n+\t\t\t\treg = <0 0x11e90000 0 0x700>;\n+\t\t\t\tclocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P1_EN>;\n+\t\t\t\tclock-names = \"ref\";\n+\t\t\t\t#phy-cells = <1>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tu2phy2: xs-phy@11ef0000 {\n+\t\t\tcompatible = \"mediatek,mt8189-xsphy\", \"mediatek,xsphy\";\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\n+\t\t\tu2port2: usb-phy@11ef0000 {\n+\t\t\t\treg = <0 0x11ef0000 0 0x700>;\n+\t\t\t\tclocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P2_EN>;\n+\t\t\t\tclock-names = \"ref\";\n+\t\t\t\t#phy-cells = <1>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tefuse: efuse@11f10000 {\n+\t\t\tcompatible = \"mediatek,mt8189-efuse\", \"mediatek,efuse\";\n+\t\t\treg = <0 0x11f10000 0 0x1000>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tlvts_e_data1: data1@1a4 {\n+\t\t\t\treg = <0x1a4 0x54>;\n+\t\t\t};\n+\n+\t\t\tlvts_e_data2: data2@1f8 {\n+\t\t\t\treg = <0x1f8 0x8>;\n+\t\t\t};\n+\n+\t\t\tgpu_avs0: gpu-avs0@308 {\n+\t\t\t\treg = <0x308 0x4>;\n+\t\t\t};\n+\n+\t\t\tgpu_avs1: gpu-avs1@30c {\n+\t\t\t\treg = <0x30c 0x4>;\n+\t\t\t};\n+\n+\t\t\tgpu_avs2: gpu-avs2@310 {\n+\t\t\t\treg = <0x310 0x4>;\n+\t\t\t};\n+\n+\t\t\tsocinfo-data1@7a0 {\n+\t\t\t\treg = <0x7a0 0x4>;\n+\t\t\t};\n+\n+\t\t\tsocinfo-data2@7e0 {\n+\t\t\t\treg = <0x7e0 0x4>;\n+\t\t\t};\n+\t\t};\n+\n+\t\ti2c7: i2c@11f30000 {\n+\t\t\tcompatible = \"mediatek,mt8188-i2c\";\n+\t\t\treg = <0 0x11f30000 0 0x1000>,\n+\t\t\t <0 0x11300900 0 0x80>;\n+\t\t\tinterrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&imp_iic_wrap_en_clk CLK_IMPEN_I2C7>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_DMA_B>;\n+\t\t\tclock-names = \"main\", \"dma\";\n+\t\t\tclock-div = <1>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\ti2c8: i2c@11f31000 {\n+\t\t\tcompatible = \"mediatek,mt8188-i2c\";\n+\t\t\treg = <0 0x11f31000 0 0x1000>,\n+\t\t\t <0 0x11300a00 0 0x80>;\n+\t\t\tinterrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&imp_iic_wrap_en_clk CLK_IMPEN_I2C8>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_DMA_B>;\n+\t\t\tclock-names = \"main\", \"dma\";\n+\t\t\tclock-div = <1>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\timp_iic_wrap_en_clk: syscon@11f32e00 {\n+\t\t\tcompatible = \"mediatek,mt8189-iic-wrap-en\", \"syscon\";\n+\t\t\treg = <0 0x11f32e00 0 0x10>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tgpu: gpu@13000000 {\n+\t\t\tcompatible = \"mediatek,mt8189-mali\",\n+\t\t\t\t \"arm,mali-valhall-jm\";\n+\t\t\treg = <0 0x13000000 0 0x4000>;\n+\n+\t\t\tnvmem-cells = <&gpu_avs0>, <&gpu_avs1>, <&gpu_avs2>;\n+\t\t\tnvmem-cell-names = \"avs-bin-0\", \"avs-bin-1\", \"avs-bin-2\";\n+\n+\t\t\tinterrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>,\n+\t\t\t\t <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>,\n+\t\t\t\t <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tinterrupt-names = \"job\", \"mmu\", \"gpu\";\n+\n+\t\t\toperating-points-v2 = <&gpu_opp_table>;\n+\n+\t\t\tclocks = <&mfg_clk CLK_MFG_BG3D>;\n+\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_MFG2>,\n+\t\t\t\t\t<&spm MT8189_POWER_DOMAIN_MFG3>;\n+\t\t\tpower-domain-names = \"core0\", \"core1\";\n+\n+\t\t\t#cooling-cells = <2>;\n+\t\t\tdynamic-power-coefficient = <1427>;\n+\n+\t\t\tpower-model@0 {\n+\t\t\t\tcompatible = \"arm,mali-simple-power-model\";\n+\t\t\t\tdynamic-coefficient = <1427>;\n+\t\t\t\tstatic-coefficient = <118279>;\n+\t\t\t\tthermal-zone = \"gpu1-thermal\";\n+\t\t\t\tts = <6 (-238) 20283 32499>;\n+\t\t\t};\n+\t\t\tpower-model@1 {\n+\t\t\t\tcompatible = \"arm,mali-tnax-power-model\";\n+\t\t\t\tscale = <5>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tgpu_opp_table: opp-table-gpu {\n+\t\t\tcompatible = \"operating-points-v2\";\n+\t\t\topp-shared;\n+\n+\t\t\topp-390000000 {\n+\t\t\t\topp-hz = /bits/ 64 <390000000>;\n+\t\t\t\topp-microvolt = <675000>;\n+\t\t\t};\n+\n+\t\t\topp-424000000 {\n+\t\t\t\topp-hz = /bits/ 64 <424000000>;\n+\t\t\t\topp-microvolt = <681250>;\n+\t\t\t};\n+\n+\t\t\topp-458000000 {\n+\t\t\t\topp-hz = /bits/ 64 <458000000>;\n+\t\t\t\topp-microvolt = <681250>;\n+\t\t\t};\n+\n+\t\t\topp-492000000 {\n+\t\t\t\topp-hz = /bits/ 64 <492000000>;\n+\t\t\t\topp-microvolt = <687500>;\n+\t\t\t};\n+\n+\t\t\topp-526000000 {\n+\t\t\t\topp-hz = /bits/ 64 <526000000>;\n+\t\t\t\topp-microvolt = <687500>;\n+\t\t\t};\n+\n+\t\t\topp-560000000 {\n+\t\t\t\topp-hz = /bits/ 64 <560000000>;\n+\t\t\t\topp-microvolt = <693750>;\n+\t\t\t};\n+\n+\t\t\topp-595000000 {\n+\t\t\t\topp-hz = /bits/ 64 <595000000>;\n+\t\t\t\topp-microvolt = <693750>;\n+\t\t\t};\n+\n+\t\t\topp-630000000 {\n+\t\t\t\topp-hz = /bits/ 64 <630000000>;\n+\t\t\t\topp-microvolt = <700000>;\n+\t\t\t};\n+\n+\t\t\topp-665000000 {\n+\t\t\t\topp-hz = /bits/ 64 <665000000>;\n+\t\t\t\topp-microvolt = <700000>;\n+\t\t\t};\n+\n+\t\t\topp-700000000 {\n+\t\t\t\topp-hz = /bits/ 64 <700000000>;\n+\t\t\t\topp-microvolt = <700000>;\n+\t\t\t};\n+\n+\t\t\topp-736000000 {\n+\t\t\t\topp-hz = /bits/ 64 <736000000>;\n+\t\t\t\topp-microvolt = <718750>;\n+\t\t\t};\n+\n+\t\t\topp-772000000 {\n+\t\t\t\topp-hz = /bits/ 64 <772000000>;\n+\t\t\t\topp-microvolt = <737500>;\n+\t\t\t};\n+\n+\t\t\topp-808000000 {\n+\t\t\t\topp-hz = /bits/ 64 <808000000>;\n+\t\t\t\topp-microvolt = <756250>;\n+\t\t\t};\n+\n+\t\t\topp-844000000 {\n+\t\t\t\topp-hz = /bits/ 64 <844000000>;\n+\t\t\t\topp-microvolt = <775000>;\n+\t\t\t};\n+\n+\t\t\topp-880000000 {\n+\t\t\t\topp-hz = /bits/ 64 <880000000>;\n+\t\t\t\topp-microvolt = <793750>;\n+\t\t\t};\n+\n+\t\t\topp-935000000 {\n+\t\t\t\topp-hz = /bits/ 64 <935000000>;\n+\t\t\t\topp-microvolt = <818750>;\n+\t\t\t};\n+\n+\t\t\topp-990000000 {\n+\t\t\t\topp-hz = /bits/ 64 <990000000>;\n+\t\t\t\topp-microvolt = <850000>;\n+\t\t\t};\n+\n+\t\t\topp-1045000000 {\n+\t\t\t\topp-hz = /bits/ 64 <1045000000>;\n+\t\t\t\topp-microvolt = <875000>;\n+\t\t\t};\n+\n+\t\t\topp-1100000000 {\n+\t\t\t\topp-hz = /bits/ 64 <1100000000>;\n+\t\t\t\topp-microvolt = <900000>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tmfg_clk: syscon@13fbf000 {\n+\t\t\tcompatible = \"mediatek,mt8189-mfgcfg\", \"syscon\";\n+\t\t\treg = <0 0x13fbf000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tdispsys_config: syscon@14000000 {\n+\t\t\tcompatible = \"mediatek,mt8189-mmsys\", \"syscon\";\n+\t\t\treg = <0 0x14000000 0 0x1000>;\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\t\t\t#clock-cells = <1>;\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_DISP>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_MUTEX0>,\n+\t\t\t\t <&dispsys_config_clk CLK_MM_DIPSYS_CONFIG>;\n+\t\t\tmboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,\n+\t\t\t\t <&gce 1 CMDQ_THR_PRIO_HIGHEST>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;\n+\t\t};\n+\n+\t\tdispsys_config_clk: syscon@14000100 {\n+\t\t\tcompatible = \"mediatek,mt8189-dispsys\", \"syscon\";\n+\t\t\treg = <0 0x14000100 0 0x20>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tdisp_mutex0: mutex@14001000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-mutex\";\n+\t\t\treg = <0 0x14001000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_MUTEX0>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;\n+\t\t\tmediatek,gce-events = <CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_0>,\n+\t\t\t\t\t <CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_1>;\n+\t\t};\n+\n+\t\tdisp_ovl0_4l: ovl@14002000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-ovl\";\n+\t\t\treg = <0 0x14002000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tiommus = <&mm_iommu M4U_L0_P1_DISP_OVL0_4L_RDMA0>,\n+\t\t\t\t <&mm_iommu M4U_L1_P2_DISP_OVL0_4L_RDMA1>,\n+\t\t\t\t <&mm_iommu M4U_L0_P3_DISP_OVL0_4L_RDMA2>,\n+\t\t\t\t <&mm_iommu M4U_L1_P4_DISP_OVL0_4L_RDMA3>,\n+\t\t\t\t <&mm_iommu M4U_L0_P0_DISP_OVL0_4L_HDR>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_OVL0_4L>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x2000 0x1000>;\n+\t\t};\n+\n+\t\tdisp_ovl1_4l: ovl@14003000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-ovl\";\n+\t\t\treg = <0 0x14003000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tiommus = <&mm_iommu M4U_L1_P1_DISP_OVL1_4L_RDMA0>,\n+\t\t\t\t <&mm_iommu M4U_L0_P2_DISP_OVL1_4L_RDMA1>,\n+\t\t\t\t <&mm_iommu M4U_L1_P3_DISP_OVL1_4L_RDMA2>,\n+\t\t\t\t <&mm_iommu M4U_L0_P4_DISP_OVL1_4L_RDMA3>,\n+\t\t\t\t <&mm_iommu M4U_L1_P0_DISP_OVL1_4L_HDR>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_OVL1_4L>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;\n+\t\t};\n+\n+\t\tdisp_rdma0: rdma@14006000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-rdma\";\n+\t\t\treg = <0 0x14006000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_RDMA0>;\n+\t\t\tiommus = <&mm_iommu M4U_L0_P5_DISP_RDMA0>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;\n+\t\t};\n+\n+\t\tdisp_rdma1: rdma@14007000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-rdma\";\n+\t\t\treg = <0 0x14007000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_RDMA1>;\n+\t\t\tiommus = <&mm_iommu M4U_L1_P5_DISP_RDMA1>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;\n+\t\t};\n+\n+\t\tdisp_color0: color@14008000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-color\";\n+\t\t\treg = <0 0x14008000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_COLOR0>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;\n+\t\t};\n+\n+\t\tdisp_color1: color@14009000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-color\";\n+\t\t\treg = <0 0x14009000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_COLOR1>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;\n+\t\t};\n+\n+\t\tdisp_ccorr0: ccorr@1400a000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-ccorr\";\n+\t\t\treg = <0 0x1400a000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_CCORR0>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;\n+\t\t};\n+\n+\t\tdisp_ccorr1: ccorr@1400b000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-ccorr\";\n+\t\t\treg = <0 0x1400b000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_CCORR1>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;\n+\t\t};\n+\n+\t\tdisp_ccorr2: ccorr@1400c000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-ccorr\";\n+\t\t\treg = <0 0x1400c000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_CCORR2>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;\n+\t\t};\n+\n+\t\tdisp_ccorr3: ccorr@1400d000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-ccorr\";\n+\t\t\treg = <0 0x1400d000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_CCORR3>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;\n+\t\t};\n+\n+\t\tdisp_aal0: aal@1400e000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-aal\";\n+\t\t\treg = <0 0x1400e000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_AAL0>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;\n+\t\t};\n+\n+\t\tdisp_aal1: aal@1400f000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-aal\";\n+\t\t\treg = <0 0x1400f000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_AAL1>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;\n+\t\t};\n+\n+\t\tdisp_gamma0: gamma@14010000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-gamma\";\n+\t\t\treg = <0 0x14010000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_GAMMA0>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;\n+\t\t};\n+\n+\t\tdisp_gamma1: gamma@14011000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-gamma\";\n+\t\t\treg = <0 0x14011000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_GAMMA1>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;\n+\t\t};\n+\n+\t\tdisp_dither0: dither@14012000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-dither\";\n+\t\t\treg = <0 0x14012000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_DITHER0>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;\n+\t\t};\n+\n+\t\tdisp_dither1: dither@14013000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-dither\";\n+\t\t\treg = <0 0x14013000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_DITHER1>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;\n+\t\t};\n+\n+\t\tdisp_dsc_wrap0: dsc@14014000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-dsc\";\n+\t\t\treg = <0 0x14014000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DISP_DSC_WRAP0>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;\n+\t\t};\n+\n+\t\tdisp_merge0: merge@14015000 {\n+\t\t\tcompatible = \"mediatek,mt8189-disp-merge\";\n+\t\t\treg = <0 0x14015000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_VPP_MERGE0>;\n+\t\t\tmediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;\n+\t\t};\n+\n+\t\tdsi0: dsi@14016000 {\n+\t\t\tcompatible = \"mediatek,mt8189-dsi\";\n+\t\t\treg = <0 0x14016000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tphys = <&mipi_tx_config0>;\n+\t\t\tphy-names = \"dphy\";\n+\t\t\tclocks = <&dispsys_config_clk CLK_MMSYS_0_DISP_DSI0>,\n+\t\t\t\t <&dispsys_config_clk CLK_MMSYS_1_DISP_DSI0>,\n+\t\t\t\t <&mipi_tx_config0>;\n+\t\t\tclock-names = \"engine\", \"digital\", \"hs\";\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tport {\n+\t\t\t\tdsi_out: endpoint { };\n+\t\t\t};\n+\t\t};\n+\n+\t\tdisp_dvo0: dvo@14017000 {\n+\t\t\tcompatible = \"mediatek,mt8189-edp-dvo\";\n+\t\t\treg = <0 0x14017000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MMSYS_1_DISP_DVO>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_EDP_SEL>,\n+\t\t\t\t <&apmixedsys_clk CLK_APMIXED_TVDPLL2>,\n+\t\t\t\t <&clk26m>,\n+\t\t\t\t <&dispsys_config_clk CLK_MMSYS_0_DISP_DVO>;\n+\t\t\tclock-names = \"engine\",\n+\t\t\t\t \"pixel\",\n+\t\t\t\t \"pll\",\n+\t\t\t\t \"dvo_clk\",\n+\t\t\t\t \"hf_fdvo_clk\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tdisp_dvo1: dvo@14018000 {\n+\t\t\tcompatible = \"mediatek,mt8189-dp-dvo\";\n+\t\t\treg = <0 0x14018000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_DP_INTF>,\n+\t\t\t\t <&topckgen_clk CLK_TOP_DP_SEL>,\n+\t\t\t\t <&apmixedsys_clk CLK_APMIXED_TVDPLL1>,\n+\t\t\t\t <&clk26m>,\n+\t\t\t\t <&dispsys_config_clk CLK_MM_DP_INTF0>;\n+\t\t\tclock-names = \"engine\",\n+\t\t\t\t \"pixel\",\n+\t\t\t\t \"pll\",\n+\t\t\t\t \"dvo_clk\",\n+\t\t\t\t \"hf_fdvo_clk\";\n+\t\t\tphys = <&dp_tx>;\n+\t\t\tphy-names = \"dp_tx\";\n+\t\t};\n+\n+\t\tsmi_larb0: larb@1401c000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-larb\";\n+\t\t\treg = <0 0x1401c000 0 0x1000>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_SMI_LARB>,\n+\t\t\t\t <&dispsys_config_clk CLK_MM_SMI_LARB>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_DISP>;\n+\t\t\tmediatek,larb-id = <SMI_L0_ID>;\n+\t\t\tmediatek,smi = <&smi_disp_common>;\n+\t\t};\n+\n+\t\tsmi_larb1: larb@1401d000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-larb\";\n+\t\t\treg = <0 0x1401d000 0 0x1000>;\n+\t\t\tclocks = <&dispsys_config_clk CLK_MM_SMI_LARB>,\n+\t\t\t\t <&dispsys_config_clk CLK_MM_SMI_LARB>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_DISP>;\n+\t\t\tmediatek,larb-id = <SMI_L1_ID>;\n+\t\t\tmediatek,smi = <&smi_disp_common>;\n+\t\t};\n+\n+\t\timgsys1_clk: syscon@15020000 {\n+\t\t\tcompatible = \"mediatek,mt8189-imgsys1\", \"syscon\";\n+\t\t\treg = <0 0x15020000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tsmi_larb9: larb@1502e000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-larb\";\n+\t\t\treg = <0 0x1502e000 0 0x1000>;\n+\t\t\tclocks = <&imgsys1_clk CLK_IMGSYS1_LARB9>,\n+\t\t\t\t <&imgsys1_clk CLK_IMGSYS1_LARB9>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_ISP_IMG1>;\n+\t\t\tmediatek,larb-id = <SMI_L9_ID>;\n+\t\t\tmediatek,smi = <&smi_img_2x1_sub_comm>;\n+\t\t};\n+\n+\t\tsmi_img_2x1_sub_comm: smi@1502f000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-sub-common\";\n+\t\t\treg = <0 0x1502f000 0 0x1000>;\n+\t\t\tclocks = <&imgsys1_clk CLK_IMGSYS1_LARB9>,\n+\t\t\t\t <&imgsys1_clk CLK_IMGSYS1_LARB11>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_ISP_IMG1>;\n+\t\t\tmediatek,smi = <&smi_disp_common>;\n+\t\t};\n+\n+\t\timgsys2_clk: syscon@15820000 {\n+\t\t\tcompatible = \"mediatek,mt8189-imgsys2\", \"syscon\";\n+\t\t\treg = <0 0x15820000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tsmi_larb11: larb@1582e000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-larb\";\n+\t\t\treg = <0 0x1582e000 0 0x1000>;\n+\t\t\t/* larb11 uses larb9's clk */\n+\t\t\tclocks = <&imgsys2_clk CLK_IMGSYS2_LARB9>,\n+\t\t\t\t <&imgsys2_clk CLK_IMGSYS2_LARB9>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_ISP_IMG2>;\n+\t\t\tmediatek,larb-id = <SMI_L11_ID>;\n+\t\t\tmediatek,smi = <&smi_img_2x1_sub_comm>;\n+\t\t};\n+\n+\t\tvdec: video-codec@16000000 {\n+\t\t\tcompatible = \"mediatek,mt8189-vcodec-dec\";\n+\t\t\treg = <0 0x16000000 0 0x1000>;\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges = <0 0 0 0x16000000 0 0x26000>;\n+\t\t\tdma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;\n+\t\t\tiommus = <&mm_iommu M4U_L4_P0_HW_VDEC_MC_EXT>;\n+\t\t\tmediatek,scp = <&scp>;\n+\n+\t\t\tvcodec_core: video-codec@16025000 {\n+\t\t\t\tcompatible = \"mediatek,mtk-vcodec-core\";\n+\t\t\t\treg = <0 0x25000 0 0x1000>;\n+\t\t\t\tiommus = <&mm_iommu M4U_L4_P0_HW_VDEC_MC_EXT>,\n+\t\t\t\t\t <&mm_iommu M4U_L4_P1_HW_VDEC_UFO_EXT>,\n+\t\t\t\t\t <&mm_iommu M4U_L4_P2_HW_VDEC_PP_EXT>,\n+\t\t\t\t\t <&mm_iommu M4U_L4_P3_HW_VDEC_PRED_RD_EXT>,\n+\t\t\t\t\t <&mm_iommu M4U_L4_P4_HW_VDEC_PRED_WR_EXT>,\n+\t\t\t\t\t <&mm_iommu M4U_L4_P5_HW_VDEC_PPWRAP_EXT>,\n+\t\t\t\t\t <&mm_iommu M4U_L4_P6_HW_VDEC_TILE_EXT>,\n+\t\t\t\t\t <&mm_iommu M4U_L4_P7_HW_VDEC_VLD_EXT>,\n+\t\t\t\t\t <&mm_iommu M4U_L4_P8_HW_VDEC_VLD2_EXT>,\n+\t\t\t\t\t <&mm_iommu M4U_L4_P9_HW_VDEC_AVC_MV_EXT>,\n+\t\t\t\t\t <&mm_iommu M4U_L4_P10_HW_VDEC_RG_CTRL_DMA_EXT>,\n+\t\t\t\t\t <&mm_iommu M4U_L4_P11_HW_VDEC_UFO_ENC_EXT>;\n+\t\t\t\tinterrupts = <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t\tclocks = <&vdec_core_clk CLK_VDEC_CORE_VDEC_CKEN>,\n+\t\t\t\t\t <&vdec_core_clk CLK_VDEC_CORE_LARB_CKEN>;\n+\t\t\t\tclock-names = \"soc-vdec\", \"vdec\";\n+\t\t\t\tassigned-clocks = <&topckgen_clk CLK_TOP_VDEC_SEL>;\n+\t\t\t\tassigned-clock-parents = <&topckgen_clk CLK_TOP_UNIVPLL_D4>;\n+\t\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_VDE0>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tsmi_larb4: larb@1602e000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-larb\";\n+\t\t\treg = <0 0x1602e000 0 0x1000>;\n+\t\t\tclocks = <&vdec_core_clk CLK_VDEC_CORE_LARB_CKEN>,\n+\t\t\t\t <&vdec_core_clk CLK_VDEC_CORE_LARB_CKEN>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_VDE0>;\n+\t\t\tmediatek,larb-id = <SMI_L4_ID>;\n+\t\t\tmediatek,smi = <&smi_disp_common>;\n+\t\t};\n+\n+\t\tvdec_core_clk: syscon@1602f000 {\n+\t\t\tcompatible = \"mediatek,mt8189-vdec-core\", \"syscon\";\n+\t\t\treg = <0 0x1602f000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tvenc_gcon_clk: syscon@17000000 {\n+\t\t\tcompatible = \"mediatek,mt8189-venc\", \"syscon\";\n+\t\t\treg = <0 0x17000000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tsmi_larb7: larb@17010000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-larb\";\n+\t\t\treg = <0 0x17010000 0 0x1000>;\n+\t\t\tclocks = <&venc_gcon_clk CLK_VEN1_CKE0_LARB>,\n+\t\t\t\t <&venc_gcon_clk CLK_VEN1_CKE0_LARB>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_VEN0>;\n+\t\t\tmediatek,larb-id = <SMI_L7_ID>;\n+\t\t\tmediatek,smi = <&smi_disp_common>;\n+\t\t};\n+\n+\t\tvenc: video-codec@17020000 {\n+\t\t\tcompatible = \"mediatek,mt8189-vcodec-enc\";\n+\t\t\treg = <0 0x17020000 0 0x6000>;\n+\t\t\tinterrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tiommus = <&mm_iommu M4U_L7_P0_VENC_RCPU>,\n+\t\t\t\t <&mm_iommu M4U_L7_P1_VENC_REC>,\n+\t\t\t\t <&mm_iommu M4U_L7_P2_VENC_BSDMA>,\n+\t\t\t\t <&mm_iommu M4U_L7_P3_VENC_SV_COMV>,\n+\t\t\t\t <&mm_iommu M4U_L7_P4_VENC_RD_COMV>,\n+\t\t\t\t <&mm_iommu M4U_L7_P8_VENC_SUB_W_LUMA>,\n+\t\t\t\t <&mm_iommu M4U_L7_P10_VENC_CUR_LUMA>,\n+\t\t\t\t <&mm_iommu M4U_L7_P11_VENC_CUR_CHROMA>,\n+\t\t\t\t <&mm_iommu M4U_L7_P12_VENC_REF_LUMA>,\n+\t\t\t\t <&mm_iommu M4U_L7_P13_VENC_REF_CHROMA>,\n+\t\t\t\t <&mm_iommu M4U_L7_P14_VENC_SUB_R_LUMA>;\n+\t\t\tclocks = <&venc_gcon_clk CLK_VEN1_CKE1_VENC>;\n+\t\t\tclock-names = \"venc_sel\";\n+\t\t\tassigned-clocks = <&topckgen_clk CLK_TOP_VENC_SEL>;\n+\t\t\tassigned-clock-parents = <&topckgen_clk CLK_TOP_UNIVPLL_D4>;\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_VEN0>;\n+\t\t\tmediatek,scp = <&scp>;\n+\t\t};\n+\n+\t\tjpeg_encoder: jpeg-encoder@17030000 {\n+\t\t\tcompatible = \"mediatek,mt8189-jpgenc\", \"mediatek,mtk-jpgenc\";\n+\t\t\treg = <0 0x17030000 0 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&venc_gcon_clk CLK_VEN1_CKE2_JPGENC>;\n+\t\t\tclock-names = \"jpgenc\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_VEN0>;\n+\t\t\tmediatek,larb = <&smi_larb7>;\n+\t\t\tiommus = <&mm_iommu M4U_L7_P5_JPGENC_Y_RDMA>,\n+\t\t\t\t <&mm_iommu M4U_L7_P6_JPGENC_C_RDMA>,\n+\t\t\t\t <&mm_iommu M4U_L7_P7_JPGENC_Q_RDMA>,\n+\t\t\t\t <&mm_iommu M4U_L7_P9_JPGENC_BSDMA>;\n+\t\t};\n+\n+\t\tjpeg_decoder: jpeg-decoder@17040000 {\n+\t\t\tcompatible = \"mediatek,mt8189-jpgdec\", \"mediatek,mt2701-jpgdec\";\n+\t\t\treg = <0 0x17040000 0 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&venc_gcon_clk CLK_VEN1_CKE3_JPGDEC>;\n+\t\t\tclock-names = \"jpgdec\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_VEN0>;\n+\t\t\tmediatek,larb = <&smi_larb7>;\n+\t\t\tiommus = <&mm_iommu M4U_L7_P15_JPGDEC_WDMA>,\n+\t\t\t\t <&mm_iommu M4U_L7_P16_JPGDEC_BSDMA>,\n+\t\t\t\t <&mm_iommu M4U_L7_P17_JPGDEC_HUFF_OFFSET>;\n+\t\t};\n+\n+\t\tapu_iommu: iommu@19010000 {\n+\t\t\tcompatible = \"mediatek,mt8189-iommu-apu\";\n+\t\t\treg = <0 0x19010000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&clk26m>;\n+\t\t\tclock-names = \"bclk\";\n+\t\t\t#iommu-cells = <1>;\n+\t\t};\n+\n+\t\tcamsys_main_clk: syscon@1a000000 {\n+\t\t\tcompatible = \"mediatek,mt8189-camsys-main\", \"syscon\";\n+\t\t\treg = <0 0x1a000000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tsmi_larb13: larb@1a001000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-larb\";\n+\t\t\treg = <0 0x1a001000 0 0x1000>;\n+\t\t\tclocks = <&camsys_main_clk CLK_CAM_M_LARB13>,\n+\t\t\t\t <&camsys_main_clk CLK_CAM_M_LARB13>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_CAM_MAIN>;\n+\t\t\tmediatek,larb-id = <SMI_L13_ID>;\n+\t\t\tmediatek,smi = <&smi_cam_4x1_sub_comm>;\n+\t\t};\n+\n+\t\tsmi_larb14: larb@1a002000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-larb\";\n+\t\t\treg = <0 0x1a002000 0 0x1000>;\n+\t\t\tclocks = <&camsys_main_clk CLK_CAM_M_LARB14>,\n+\t\t\t\t <&camsys_main_clk CLK_CAM_M_LARB14>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_CAM_MAIN>;\n+\t\t\tmediatek,larb-id = <SMI_L14_ID>;\n+\t\t\tmediatek,smi = <&smi_cam_3x1_sub_comm>;\n+\t\t};\n+\n+\t\tsmi_cam_3x1_sub_comm: smi@1a00c000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-sub-common\";\n+\t\t\treg = <0 0x1a00c000 0 0x1000>;\n+\t\t\tclocks = <&camsys_main_clk CLK_CAM_M_CAM2MM_GALS>,\n+\t\t\t\t <&camsys_main_clk CLK_CAM_M_CAM2MM_GALS>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_CAM_MAIN>;\n+\t\t\tmediatek,smi = <&smi_disp_common>;\n+\t\t};\n+\n+\t\tsmi_cam_4x1_sub_comm: smi@1a00d000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-sub-common\";\n+\t\t\treg = <0 0x1a00d000 0 0x1000>;\n+\t\t\tclocks = <&camsys_main_clk CLK_CAM_M_CAM2MM_GALS>,\n+\t\t\t\t <&camsys_main_clk CLK_CAM_M_CAM2MM_GALS>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_CAM_MAIN>;\n+\t\t\tmediatek,smi = <&smi_disp_common>;\n+\t\t};\n+\n+\t\tsmi_larb16: larb@1a00f000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-larb\";\n+\t\t\treg = <0 0x1a00f000 0 0x1000>;\n+\t\t\tclocks = <&camsys_rawa_clk CLK_CAM_RA_CAMSYS_RAWA_LARBX>,\n+\t\t\t\t <&camsys_rawa_clk CLK_CAM_RA_CAMSYS_RAWA_LARBX>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_CAM_SUBA>;\n+\t\t\tmediatek,larb-id = <SMI_L16_ID>;\n+\t\t\tmediatek,smi = <&smi_cam_3x1_sub_comm>;\n+\t\t};\n+\n+\t\tsmi_larb17: larb@1a010000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-larb\";\n+\t\t\treg = <0 0x1a010000 0 0x1000>;\n+\t\t\tclocks = <&camsys_rawb_clk CLK_CAM_RB_CAMSYS_RAWB_LARBX>,\n+\t\t\t\t <&camsys_rawb_clk CLK_CAM_RB_CAMSYS_RAWB_LARBX>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_CAM_SUBB>;\n+\t\t\tmediatek,larb-id = <SMI_L17_ID>;\n+\t\t\tmediatek,smi = <&smi_cam_4x1_sub_comm>;\n+\t\t};\n+\n+\t\tcamsys_rawa_clk: syscon@1a04f000 {\n+\t\t\tcompatible = \"mediatek,mt8189-camsys-rawa\", \"syscon\";\n+\t\t\treg = <0 0x1a04f000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tcamsys_rawb_clk: syscon@1a06f000 {\n+\t\t\tcompatible = \"mediatek,mt8189-camsys-rawb\", \"syscon\";\n+\t\t\treg = <0 0x1a06f000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tipesys_clk: syscon@1b000000 {\n+\t\t\tcompatible = \"mediatek,mt8189-ipesys\", \"syscon\";\n+\t\t\treg = <0 0x1b000000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tsmi_ipe_2x1_sub_comm: smi@1b00e000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-sub-common\";\n+\t\t\treg = <0 0x1b00e000 0 0x1000>;\n+\t\t\tclocks = <&ipesys_clk CLK_IPE_SMI_SUBCOM>,\n+\t\t\t\t <&ipesys_clk CLK_IPESYS_GALS>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_ISP_IPE>;\n+\t\t\tmediatek,smi = <&smi_disp_common>;\n+\t\t};\n+\n+\t\tsmi_larb19: larb@1b10f000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-larb\";\n+\t\t\treg = <0 0x1b10f000 0 0x1000>;\n+\t\t\tclocks = <&ipesys_clk CLK_IPE_LARB19>,\n+\t\t\t\t <&ipesys_clk CLK_IPE_LARB19>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_ISP_IPE>;\n+\t\t\tmediatek,larb-id = <SMI_L19_ID>;\n+\t\t\tmediatek,smi = <&smi_ipe_2x1_sub_comm>;\n+\t\t};\n+\n+\t\tsmi_larb20: larb@1b00f000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-larb\";\n+\t\t\treg = <0 0x1b00f000 0 0x1000>;\n+\t\t\tclocks = <&ipesys_clk CLK_IPE_LARB20>,\n+\t\t\t\t <&ipesys_clk CLK_IPE_LARB20>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_ISP_IPE>;\n+\t\t\tmediatek,larb-id = <SMI_L20_ID>;\n+\t\t\tmediatek,smi = <&smi_ipe_2x1_sub_comm>;\n+\t\t};\n+\n+\t\tvlpcfg_ao_reg_clk: syscon@1c000800 {\n+\t\t\tcompatible = \"mediatek,mt8189-vlp-ao\", \"syscon\";\n+\t\t\treg = <0 0x1c000800 0 0x10>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tscpsys: syscon@1c001000 {\n+\t\t\tcompatible = \"mediatek,mt8189-scpsys\", \"syscon\", \"simple-mfd\";\n+\t\t\treg = <0 0x1c001000 0 0x1000>;\n+\n+\t\t\t/* System Power Manager */\n+\t\t\tspm: power-controller {\n+\t\t\t\tcompatible = \"mediatek,mt8189-power-controller\";\n+\t\t\t\tmfg0-supply = <&mt6359_vproc1_buck_reg>;\n+\t\t\t\tmfg1-supply = <&mt6359_vsram_proc1_ldo_reg>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t#power-domain-cells = <1>;\n+\n+\t\t\t\t/* power domain of the SoC */\n+\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_CONN {\n+\t\t\t\t\treg = <MT8189_POWER_DOMAIN_CONN>;\n+\t\t\t\t\tmediatek,infracfg = <&infracfg_ao_clk>;\n+\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t};\n+\n+\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_AUDIO {\n+\t\t\t\t\treg = <MT8189_POWER_DOMAIN_AUDIO>;\n+\t\t\t\t\tclocks = <&topckgen_clk CLK_TOP_AUD_INTBUS_SEL>;\n+\t\t\t\t\tclock-names = \"audio\";\n+\t\t\t\t\tmediatek,infracfg = <&infracfg_ao_clk>;\n+\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t};\n+\n+\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_ADSP_AO {\n+\t\t\t\t\treg = <MT8189_POWER_DOMAIN_ADSP_AO>;\n+\t\t\t\t\tclocks = <&vlp_cksys_clk CLK_VLP_CK_VADSP_SEL>;\n+\t\t\t\t\tclock-names = \"vadsp\";\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\t#power-domain-cells = <1>;\n+\n+\t\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_ADSP_INFRA {\n+\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_ADSP_INFRA>;\n+\t\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\t\t#power-domain-cells = <1>;\n+\n+\t\t\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT {\n+\t\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT>;\n+\t\t\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_MM_INFRA {\n+\t\t\t\t\treg = <MT8189_POWER_DOMAIN_MM_INFRA>;\n+\t\t\t\t\tclocks = <&topckgen_clk CLK_TOP_MMINFRA_SEL>,\n+\t\t\t\t\t\t <&mminfra_config_clk CLK_MMINFRA_SMI>;\n+\t\t\t\t\tclock-names = \"mminfra\", \"ss-mminfra\";\n+\t\t\t\t\tmediatek,infracfg = <&infracfg_ao_clk>;\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\t#power-domain-cells = <1>;\n+\n+\t\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_ISP_IMG1 {\n+\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_ISP_IMG1>;\n+\t\t\t\t\t\tclocks = <&topckgen_clk CLK_TOP_IMG1_SEL>,\n+\t\t\t\t\t\t\t <&imgsys1_clk CLK_IMGSYS1_LARB9>,\n+\t\t\t\t\t\t\t <&imgsys1_clk CLK_IMGSYS1_LARB11>,\n+\t\t\t\t\t\t\t <&imgsys1_clk CLK_IMGSYS1_GALS>;\n+\t\t\t\t\t\tclock-names = \"img1\", \"ss-img1-0\", \"ss-img1-1\", \"ss-img1-2\";\n+\t\t\t\t\t\tmediatek,infracfg = <&infracfg_ao_clk>;\n+\t\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\t\t#power-domain-cells = <1>;\n+\n+\t\t\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_ISP_IMG2 {\n+\t\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_ISP_IMG2>;\n+\t\t\t\t\t\t\tclocks = <&imgsys2_clk CLK_IMGSYS2_LARB9>,\n+\t\t\t\t\t\t\t\t <&imgsys2_clk CLK_IMGSYS2_LARB11>,\n+\t\t\t\t\t\t\t\t <&imgsys2_clk CLK_IMGSYS2_GALS>;\n+\t\t\t\t\t\t\tclock-names = \"ss-img2-0\", \"ss-img2-1\", \"ss-img2-2\";\n+\t\t\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_ISP_IPE {\n+\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_ISP_IPE>;\n+\t\t\t\t\t\tclocks = <&topckgen_clk CLK_TOP_IPE_SEL>,\n+\t\t\t\t\t\t\t <&ipesys_clk CLK_IPE_LARB19>,\n+\t\t\t\t\t\t\t <&ipesys_clk CLK_IPE_LARB20>,\n+\t\t\t\t\t\t\t <&ipesys_clk CLK_IPE_SMI_SUBCOM>,\n+\t\t\t\t\t\t\t <&ipesys_clk CLK_IPESYS_GALS>;\n+\t\t\t\t\t\tclock-names = \"ipe\", \"ss-ipe0\", \"ss-ipe1\", \"ss-ipe2\", \"ss-ipe3\";\n+\t\t\t\t\t\tmediatek,infracfg = <&infracfg_ao_clk>;\n+\t\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_VDE0 {\n+\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_VDE0>;\n+\t\t\t\t\t\tclocks = <&topckgen_clk CLK_TOP_VDEC_SEL>,\n+\t\t\t\t\t\t\t <&vdec_core_clk CLK_VDEC_CORE_LARB_CKEN>;\n+\t\t\t\t\t\tclock-names = \"vdec\", \"ss-vdec\";\n+\t\t\t\t\t\tmediatek,infracfg = <&infracfg_ao_clk>;\n+\t\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_VEN0 {\n+\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_VEN0>;\n+\t\t\t\t\t\tclocks = <&topckgen_clk CLK_TOP_VENC_SEL>,\n+\t\t\t\t\t\t\t <&venc_gcon_clk CLK_VEN1_CKE0_LARB>;\n+\t\t\t\t\t\tclock-names = \"venc\", \"ss-venc\";\n+\t\t\t\t\t\tmediatek,infracfg = <&infracfg_ao_clk>;\n+\t\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_CAM_MAIN {\n+\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_CAM_MAIN>;\n+\t\t\t\t\t\tclocks = <&topckgen_clk CLK_TOP_CAM_SEL>,\n+\t\t\t\t\t\t\t <&camsys_main_clk CLK_CAM_M_LARB13>,\n+\t\t\t\t\t\t\t <&camsys_main_clk CLK_CAM_M_LARB14>,\n+\t\t\t\t\t\t\t <&camsys_main_clk CLK_CAM_M_CAM2MM_GALS>;\n+\t\t\t\t\t\tclock-names = \"cam\", \"ss-cam0\", \"ss-cam1\", \"ss-cam2\";\n+\t\t\t\t\t\tmediatek,infracfg = <&infracfg_ao_clk>;\n+\t\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\t\t#power-domain-cells = <1>;\n+\n+\t\t\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_CAM_SUBA {\n+\t\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_CAM_SUBA>;\n+\t\t\t\t\t\t\tclocks = <&camsys_rawa_clk CLK_CAM_RA_CAMSYS_RAWA_LARBX>;\n+\t\t\t\t\t\t\tclock-names = \"ss-cam-suba\";\n+\t\t\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t\t\t};\n+\n+\t\t\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_CAM_SUBB {\n+\t\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_CAM_SUBB>;\n+\t\t\t\t\t\t\tclocks = <&camsys_rawb_clk CLK_CAM_RB_CAMSYS_RAWB_LARBX>;\n+\t\t\t\t\t\t\tclock-names = \"ss-cam-subb\";\n+\t\t\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_MDP0 {\n+\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_MDP0>;\n+\t\t\t\t\t\tclocks = <&topckgen_clk CLK_TOP_MDP0_SEL>,\n+\t\t\t\t\t\t\t <&mdpsys_config_clk CLK_MDP_SMI0>;\n+\t\t\t\t\t\tclock-names = \"mdp\", \"ss-mdp\";\n+\t\t\t\t\t\tmediatek,infracfg = <&infracfg_ao_clk>;\n+\t\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_DISP {\n+\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_DISP>;\n+\t\t\t\t\t\tclocks = <&topckgen_clk CLK_TOP_DISP0_SEL>,\n+\t\t\t\t\t\t\t <&dispsys_config_clk CLK_MM_SMI_LARB>;\n+\t\t\t\t\t\tclock-names = \"disp\", \"ss-disp\";\n+\t\t\t\t\t\tmediatek,infracfg = <&infracfg_ao_clk>;\n+\t\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\t\t#power-domain-cells = <1>;\n+\n+\t\t\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_DP_TX {\n+\t\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_DP_TX>;\n+\t\t\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\t\t\t#power-domain-cells = <1>;\n+\n+\t\t\t\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_EDP_TX_DORMANT {\n+\t\t\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_EDP_TX_DORMANT>;\n+\t\t\t\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t\t\t\t};\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_CSI_RX {\n+\t\t\t\t\treg = <MT8189_POWER_DOMAIN_CSI_RX>;\n+\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t};\n+\n+\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_SSUSB {\n+\t\t\t\t\treg = <MT8189_POWER_DOMAIN_SSUSB>;\n+\t\t\t\t\tmediatek,infracfg = <&infracfg_ao_clk>;\n+\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t};\n+\n+\t\t\t\tmfg0: power-domain@MT8189_POWER_DOMAIN_MFG0 {\n+\t\t\t\t\treg = <MT8189_POWER_DOMAIN_MFG0>;\n+\t\t\t\t\tclocks = <&apmixedsys_clk CLK_APMIXED_MFGPLL>;\n+\t\t\t\t\tclock-names = \"mfg_top\";\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\t#power-domain-cells = <1>;\n+\n+\t\t\t\t\tmfg1: power-domain@MT8189_POWER_DOMAIN_MFG1 {\n+\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_MFG1>;\n+\t\t\t\t\t\tclocks = <&topckgen_clk CLK_TOP_MFG_REF_SEL>;\n+\t\t\t\t\t\tclock-names = \"mfg\";\n+\t\t\t\t\t\tmediatek,infracfg = <&infracfg_ao_clk>;\n+\t\t\t\t\t\tmediatek,smi = <&emicfg_ao_mem_clk>;\n+\t\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\t\t#power-domain-cells = <1>;\n+\n+\t\t\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_MFG2 {\n+\t\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_MFG2>;\n+\t\t\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t\t\t};\n+\n+\t\t\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_MFG3 {\n+\t\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_MFG3>;\n+\t\t\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_PCIE {\n+\t\t\t\t\treg = <MT8189_POWER_DOMAIN_PCIE>;\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\t#power-domain-cells = <1>;\n+\n+\t\t\t\t\tpower-domain@MT8189_POWER_DOMAIN_PCIE_PHY {\n+\t\t\t\t\t\treg = <MT8189_POWER_DOMAIN_PCIE_PHY>;\n+\t\t\t\t\t\t#power-domain-cells = <0>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\twatchdog: watchdog@1c00a000 {\n+\t\t\tcompatible = \"mediatek,mt8188-wdt\", \"mediatek,mt6589-wdt\";\n+\t\t\treg = <0 0x1c00a000 0 0x1000>;\n+\t\t\t#reset-cells = <1>;\n+\t\t};\n+\n+\t\tvlpcfg_reg_bus_clk: syscon@1c00c000 {\n+\t\t\tcompatible = \"mediatek,mt8189-vlpcfg-ao\", \"syscon\";\n+\t\t\treg = <0 0x1c00c000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tdvfsrc_top_clk: syscon@1c00f000 {\n+\t\t\tcompatible = \"mediatek,mt8189-dvfsrc-top\", \"syscon\";\n+\t\t\treg = <0 0x1c00f000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tvlp_cksys_clk: syscon@1c012000 {\n+\t\t\tcompatible = \"mediatek,mt8189-vlpckgen\", \"syscon\";\n+\t\t\treg = <0 0x1c012000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tdevapc_vlp: devapc@1c01c000 {\n+\t\t\tcompatible = \"mediatek,mt8189-devapc\";\n+\t\t\treg = <0 0x1c01c000 0 0x1000>,\n+\t\t\t <0 0x1c018000 0 0x1000>; /* vlp ao/pd */\n+\t\t\tvio-idx-num = <62>;\n+\t\t\tinterrupts = <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH 0>; /* vlp irq */\n+\t\t};\n+\n+\t\tsram@1c350000 {\n+\t\t\tcompatible = \"mmio-sram\";\n+\t\t\treg = <0x0 0x1c350000 0x0 0x80>;\n+\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0 0x0 0x1c350000 0x80>;\n+\n+\t\t\tscmi_tx_shmem: mailbox-sram@0 {\n+\t\t\t\tcompatible = \"arm,scmi-shmem\";\n+\t\t\t\treg = <0x0 0x80>;\n+\t\t\t};\n+\t\t};\n+\n+\t\ttinysys_mbox: mailbox@1c351000 {\n+\t\t\tcompatible = \"mediatek,tinysys_mbox\";\n+\t\t\treg = <0 0x1c351000 0 0x1000>,\n+\t\t\t <0 0x1c361000 0 0x1000>;\n+\t\t\t/* for profiling */\n+\t\t\tshmem = <&scmi_tx_shmem>, <&scmi_rx_shmem>;\n+\t\t\tinterrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH 0>,\n+\t\t\t\t <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t#mbox-cells = <1>;\n+\t\t\t/* notify spm clr */\n+\t\t\tsecure-sspm-md2spm-clr = <1>;\n+\t\t};\n+\n+\t\tsram@1c360000 {\n+\t\t\tcompatible = \"mmio-sram\";\n+\t\t\treg = <0x0 0x1c360000 0x0 0x80>;\n+\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0 0x0 0x1c360000 0x80>;\n+\n+\t\t\tscmi_rx_shmem: mailbox-sram@0 {\n+\t\t\t\tcompatible = \"arm,scmi-shmem\";\n+\t\t\t\treg = <0x0 0x80>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tscp: scp@1c400000 {\n+\t\t\tcompatible = \"mediatek,mt8189-scp\";\n+\t\t\treg = <0 0x1c400000 0 0x60000>,\n+\t\t\t <0 0x1cb20000 0 0xe0000>;\n+\t\t\treg-names = \"sram\", \"cfg\";\n+\t\t\tinterrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&vlp_cksys_clk CLK_VLP_CK_SCP_SEL>;\n+\t\t\tclock-names = \"scp_sel\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tscp_iic_clk: syscon@1c80ae10 {\n+\t\t\tcompatible = \"mediatek,mt8189-scp-i2c-clk\", \"syscon\";\n+\t\t\treg = <0 0x1c80ae10 0 0x10>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tscp_clk: syscon@1cb21150 {\n+\t\t\tcompatible = \"mediatek,mt8189-scp-clk\", \"syscon\";\n+\t\t\treg = <0 0x1cb21150 0 0x10>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tpwrap: pwrap@1cc04000 {\n+\t\t\tcompatible = \"mediatek,mt8189-pwrap\", \"mediatek,mt8195-pwrap\", \"syscon\";\n+\t\t\treg = <0 0x1cc04000 0 0x1000>;\n+\t\t\treg-names = \"pwrap\";\n+\t\t\tinterrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&vlpcfg_reg_bus_clk CLK_VLPCFG_REG_PMIF_SPMI_M_SYS>,\n+\t\t\t\t <&vlpcfg_reg_bus_clk CLK_VLPCFG_REG_PMIF_SPMI_M_TMR>;\n+\t\t\tclock-names = \"spi\", \"wrap\";\n+\t\t\tassigned-clocks = <&vlp_cksys_clk CLK_VLP_CK_PWRAP_ULPOSC_SEL>;\n+\t\t\tassigned-clock-parents = <&topckgen_clk CLK_TOP_OSC_D10>;\n+\t\t};\n+\n+\t\tspmi: spmi@1cc06000 {\n+\t\t\tcompatible = \"mediatek,mt8189-spmi\", \"mediatek,mt8195-spmi\";\n+\t\t\treg = <0 0x1cc06000 0 0x0008ff>,\n+\t\t\t <0 0x1cc00000 0 0x000100>;\n+\t\t\treg-names = \"pmif\", \"spmimst\";\n+\t\t\tclocks = <&vlpcfg_reg_bus_clk CLK_VLPCFG_REG_PMIF_SPMI_P_SYS>,\n+\t\t\t\t <&vlpcfg_reg_bus_clk CLK_VLPCFG_REG_PMIF_SPMI_P_TMR>,\n+\t\t\t\t <&vlp_cksys_clk CLK_VLP_CK_SPMI_P_MST_SEL>;\n+\t\t\tclock-names = \"pmif_sys_ck\", \"pmif_tmr_ck\", \"spmimst_clk_mux\";\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <0>;\n+\t\t};\n+\n+\t\tsystimer: timer@1cc10000 {\n+\t\t\tcompatible = \"mediatek,mt8189-timer\",\"mediatek,mt6765-timer\";\n+\t\t\treg = <0 0x1cc10000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&clk13m>;\n+\t\t};\n+\n+\t\tvadsys_clk: syscon@1e010000 {\n+\t\t\tcompatible = \"mediatek,mt8189-vadsys\", \"syscon\";\n+\t\t\treg = <0 0x1e010000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tdevapc_adsp: devapc@1e019000 {\n+\t\t\tcompatible = \"mediatek,mt8189-devapc\";\n+\t\t\treg = <0 0x1e019000 0 0x1000>,\n+\t\t\t <0 0x1e340000 0 0x1000>; /* adsp ao/pd */\n+\t\t\tvio-idx-num = <44>;\n+\t\t\tinterrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>; /* adsp irq */\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tmminfra {\n+\t\t\tcompatible = \"mediatek,mt8189-mminfra\";\n+\t\t\tclocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>,\n+\t\t\t\t <&mminfra_config_clk CLK_MMINFRA_GCE_M>,\n+\t\t\t\t <&mminfra_config_clk CLK_MMINFRA_GCE_26M>;\n+\t\t\tclock-names = \"gce_d\", \"gce_m\", \"gce_26m\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_MM_INFRA>;\n+\t\t\tmediatek,mminfra = <&mminfra_config_clk>;\n+\t\t};\n+\n+\t\tmminfra_config_clk: syscon@1e800000 {\n+\t\t\tcompatible = \"mediatek,mt8189-mm-infra\", \"syscon\";\n+\t\t\treg = <0 0x1e800000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tsmi_disp_common: smi@1e801000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-common\";\n+\t\t\treg = <0 0x1e801000 0 0x1000>;\n+\t\t\tclocks = <&mminfra_config_clk CLK_MMINFRA_SMI>,\n+\t\t\t\t <&mminfra_config_clk CLK_MMINFRA_SMI>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_MM_INFRA>;\n+\t\t};\n+\n+\t\tmm_iommu: iommu@1e802000 {\n+\t\t\tcompatible = \"mediatek,mt8189-iommu-mm\";\n+\t\t\treg = <0 0x1e802000 0 0x5000>;\n+\t\t\tinterrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&mminfra_config_clk CLK_MMINFRA_SMI>;\n+\t\t\tclock-names = \"bclk\";\n+\t\t\t#iommu-cells = <1>;\n+\t\t\tmediatek,larbs = <&smi_larb0 &smi_larb1 &smi_larb2 &smi_larb4 &smi_larb7\n+\t\t\t\t\t &smi_larb9 &smi_larb11 &smi_larb13 &smi_larb14\n+\t\t\t\t\t &smi_larb16 &smi_larb17 &smi_larb19 &smi_larb20>;\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_MM_INFRA>;\n+\t\t};\n+\n+\t\tdisp_ssc0_smi_2x1_sub_comm: smi@1e807000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-common\";\n+\t\t\treg = <0 0x1e807000 0 0x1000>;\n+\t\t\tclocks = <&mminfra_config_clk CLK_MMINFRA_SMI>,\n+\t\t\t\t <&mminfra_config_clk CLK_MMINFRA_SMI>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_MM_INFRA>;\n+\t\t};\n+\n+\t\tdisp_ssc1_smi_2x1_sub_comm: smi@1e808000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-common\";\n+\t\t\treg = <0 0x1e808000 0 0x1000>;\n+\t\t\tclocks = <&mminfra_config_clk CLK_MMINFRA_SMI>,\n+\t\t\t\t <&mminfra_config_clk CLK_MMINFRA_SMI>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_MM_INFRA>;\n+\t\t};\n+\n+\t\tmminfra_smi_3x1_sub_comm: smi@1e809000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-sub-common\";\n+\t\t\treg = <0 0x1e809000 0 0x1000>;\n+\t\t\tclocks = <&mminfra_config_clk CLK_MMINFRA_SMI>,\n+\t\t\t\t <&mminfra_config_clk CLK_MMINFRA_SMI>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_MM_INFRA>;\n+\t\t\tmediatek,smi = <&smi_disp_common>;\n+\t\t};\n+\n+\t\tmminfra_smi_2x1_sub_comm: smi@1e80a000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-sub-common\";\n+\t\t\treg = <0 0x1e80a000 0 0x1000>;\n+\t\t\tclocks = <&mminfra_config_clk CLK_MMINFRA_SMI>,\n+\t\t\t\t <&mminfra_config_clk CLK_MMINFRA_SMI>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_MM_INFRA>;\n+\t\t\tmediatek,smi = <&smi_disp_common>;\n+\t\t};\n+\n+\t\tdevapc_mminfra: devapc@1e826000 {\n+\t\t\tcompatible = \"mediatek,mt8189-devapc\";\n+\t\t\treg = <0 0x1e826000 0 0x1000>,\n+\t\t\t <0 0x1e820000 0 0x1000>; /* mminfra ao/pd */\n+\t\t\tvio-idx-num = <304>;\n+\t\t\tinterrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH 0>; /* mminfra irq */\n+\t\t};\n+\n+\t\tgce: gce@1e980000 {\n+\t\t\tcompatible = \"mediatek,mt8189-gce\";\n+\t\t\treg = <0 0x1e980000 0 0x4000>;\n+\t\t\tinterrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t#mbox-cells = <2>;\n+\t\t\tclocks = <&mminfra_config_clk CLK_MMINFRA_GCE_D>,\n+\t\t\t\t <&mminfra_config_clk CLK_MMINFRA_GCE_26M>;\n+\t\t\tclock-names = \"gce0\", \"gce-timer\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_MM_INFRA>;\n+\t\t};\n+\n+\t\tgce_d_clk: syscon@1e9800f0 {\n+\t\t\tcompatible = \"mediatek,mt8189-gce-d\", \"syscon\";\n+\t\t\treg = <0 0x1e9800f0 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tgce_m: gce@1e990000 {\n+\t\t\tcompatible = \"mediatek,mt8189-gce\";\n+\t\t\treg = <0 0x1e990000 0 0x4000>;\n+\t\t\tinterrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t#mbox-cells = <2>;\n+\t\t\tclocks = <&mminfra_config_clk CLK_MMINFRA_GCE_M>,\n+\t\t\t\t <&mminfra_config_clk CLK_MMINFRA_GCE_26M>;\n+\t\t\tclock-names = \"gce1\", \"gce-timer\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_MM_INFRA>;\n+\t\t};\n+\n+\t\tgce_m_clk: syscon@1e9900f0 {\n+\t\t\tcompatible = \"mediatek,mt8189-gce-m\", \"syscon\";\n+\t\t\treg = <0 0x1e9900f0 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tmdpsys_config_clk: syscon@1f000100 {\n+\t\t\tcompatible = \"mediatek,mt8189-mdpsys\", \"syscon\";\n+\t\t\treg = <0 0x1f000100 0 0x20>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tsmi_larb2: larb@1f002000 {\n+\t\t\tcompatible = \"mediatek,mt8189-smi-larb\";\n+\t\t\treg = <0 0x1f002000 0 0x1000>;\n+\t\t\tclocks = <&mdpsys_config_clk CLK_MDP_SMI0>,\n+\t\t\t\t <&mdpsys_config_clk CLK_MDP_SMI0>;\n+\t\t\tclock-names = \"apb\", \"smi\";\n+\t\t\tpower-domains = <&spm MT8189_POWER_DOMAIN_MDP0>;\n+\t\t\tmediatek,larb-id = <SMI_L2_ID>;\n+\t\t\tmediatek,smi = <&smi_disp_common>;\n+\t\t};\n+\n+\t\tthermal_zones: thermal-zones {\n+\n+\t\t\tcpu0-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_mcu MT8189_MCU_BIG_CPU1>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tcpu0_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu0_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <85000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu0_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <115000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t\tcooling-maps {\n+\t\t\t\t\tmap0 {\n+\t\t\t\t\t\ttrip = <&cpu0_alert>;\n+\t\t\t\t\t\tcooling-device =\n+\t\t\t\t\t\t\t<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n+\t\t\t\t\t\tcontribution = <1024>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tcpu1-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_mcu MT8189_MCU_BIG_CPU2>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tcpu1_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu1_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <85000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu1_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <119000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t\tcooling-maps {\n+\t\t\t\t\tmap0 {\n+\t\t\t\t\t\ttrip = <&cpu1_alert>;\n+\t\t\t\t\t\tcooling-device =\n+\t\t\t\t\t\t\t<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n+\t\t\t\t\t\tcontribution = <1024>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tcpu2-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_mcu MT8189_MCU_BIG_CPU3>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tcpu2_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu2_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <85000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu2_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <119000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t\tcooling-maps {\n+\t\t\t\t\tmap0 {\n+\t\t\t\t\t\ttrip = <&cpu2_alert>;\n+\t\t\t\t\t\tcooling-device =\n+\t\t\t\t\t\t\t<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n+\t\t\t\t\t\tcontribution = <1024>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tcpu3-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_mcu MT8189_MCU_BIG_CPU4>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tcpu3_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu3_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <85000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu3_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <119000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t\tcooling-maps {\n+\t\t\t\t\tmap0 {\n+\t\t\t\t\t\ttrip = <&cpu3_alert>;\n+\t\t\t\t\t\tcooling-device =\n+\t\t\t\t\t\t\t<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n+\t\t\t\t\t\tcontribution = <1024>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tcpu4-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_mcu MT8189_MCU_LITTLE_CPU1>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tcpu4_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu4_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <85000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu4_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <119000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t\tcooling-maps {\n+\t\t\t\t\tmap0 {\n+\t\t\t\t\t\ttrip = <&cpu4_alert>;\n+\t\t\t\t\t\tcooling-device =\n+\t\t\t\t\t\t\t<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n+\t\t\t\t\t\tcontribution = <1024>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tcpu5-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_mcu MT8189_MCU_LITTLE_CPU2>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tcpu5_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu5_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu5_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <119000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t\tcooling-maps {\n+\t\t\t\t\tmap0 {\n+\t\t\t\t\t\ttrip = <&cpu5_alert>;\n+\t\t\t\t\t\tcooling-device =\n+\t\t\t\t\t\t\t<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n+\t\t\t\t\t\tcontribution = <2345>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tcpu6-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_mcu MT8189_MCU_LITTLE_CPU3>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tcpu6_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu6_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu6_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <119000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t\tcooling-maps {\n+\t\t\t\t\tmap0 {\n+\t\t\t\t\t\ttrip = <&cpu6_alert>;\n+\t\t\t\t\t\tcooling-device =\n+\t\t\t\t\t\t\t<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n+\t\t\t\t\t\tcontribution = <2345>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tcpu7-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_mcu MT8189_MCU_LITTLE_CPU4>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tcpu7_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu7_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu7_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <119000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t\tcooling-maps {\n+\t\t\t\t\tmap0 {\n+\t\t\t\t\t\ttrip = <&cpu7_alert>;\n+\t\t\t\t\t\tcooling-device =\n+\t\t\t\t\t\t\t<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n+\t\t\t\t\t\tcontribution = <2345>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tcpu8-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_mcu MT8189_MCU_LITTLE_CPU5>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tcpu8_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu8_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu8_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <119000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tcooling-maps {\n+\t\t\t\t\tmap0 {\n+\t\t\t\t\t\ttrip = <&cpu8_alert>;\n+\t\t\t\t\t\tcooling-device =\n+\t\t\t\t\t\t\t<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n+\t\t\t\t\t\tcontribution = <2345>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tcpu9-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_mcu MT8189_MCU_LITTLE_CPU6>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tcpu_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu9_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu9_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <119000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tcooling-maps {\n+\t\t\t\t\tmap0 {\n+\t\t\t\t\t\ttrip = <&cpu9_alert>;\n+\t\t\t\t\t\tcooling-device =\n+\t\t\t\t\t\t\t<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n+\t\t\t\t\t\tcontribution = <2345>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tcpu10-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_mcu MT8189_MCU_LITTLE_CPU7>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tcpu10_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu10_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu10_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <119000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tcooling-maps {\n+\t\t\t\t\tmap0 {\n+\t\t\t\t\t\ttrip = <&cpu10_alert>;\n+\t\t\t\t\t\tcooling-device =\n+\t\t\t\t\t\t\t<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n+\t\t\t\t\t\tcontribution = <2345>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tcpu11-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_mcu MT8189_MCU_LITTLE_CPU8>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tcpu11_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu11_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tcpu11_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <119000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tcooling-maps {\n+\t\t\t\t\tmap0 {\n+\t\t\t\t\t\ttrip = <&cpu11_alert>;\n+\t\t\t\t\t\tcooling-device =\n+\t\t\t\t\t\t\t<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,\n+\t\t\t\t\t\t\t<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n+\t\t\t\t\t\tcontribution = <2345>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tsoc1-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_ap MT8189_AP_SOC1>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tsoc1_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tsoc1_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <85000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tsoc1_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <119000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tsoc2-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_ap MT8189_AP_SOC2>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tsoc2_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tsoc2_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <85000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tsoc2_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <119000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tsoc3-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_ap MT8189_AP_SOC3>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tsoc3_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tsoc3_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <85000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tsoc3_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <119000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tapu-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_ap MT8189_AP_APU>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tapu_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tapu_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <85000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tapu_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <119000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tgpu1-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_ap MT8189_AP_GPU1>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tgpu1_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tgpu1_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <85000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tgpu1_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <119000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t\tcooling-maps {\n+\t\t\t\t\tmap0 {\n+\t\t\t\t\t\ttrip = <&gpu1_alert>;\n+\t\t\t\t\t\tcooling-device =\n+\t\t\t\t\t\t\t<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n+\t\t\t\t\t\tcontribution = <1134>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tgpu2-thermal {\n+\t\t\t\tpolling-delay = <200>; /* milliseconds */\n+\t\t\t\tpolling-delay-passive = <100>; /* milliseconds */\n+\t\t\t\tthermal-sensors = <&lvts_ap MT8189_AP_GPU2>;\n+\t\t\t\tsustainable-power = <1200>;\n+\t\t\t\ttrips {\n+\t\t\t\t\tgpu2_threshold: trip-point@0 {\n+\t\t\t\t\t\ttemperature = <68000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tgpu2_alert: target@1 {\n+\t\t\t\t\t\ttemperature = <85000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"passive\";\n+\t\t\t\t\t};\n+\t\t\t\t\tgpu2_crit: trip-crit {\n+\t\t\t\t\t\ttemperature = <119000>;\n+\t\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t\tcooling-maps {\n+\t\t\t\t\tmap0 {\n+\t\t\t\t\t\ttrip = <&gpu2_alert>;\n+\t\t\t\t\t\tcooling-device =\n+\t\t\t\t\t\t\t<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n+\t\t\t\t\t\tcontribution = <1134>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\temiisu {\n+\t\t\tcompatible = \"mediatek,common-emiisu\";\n+\t\t\tctrl-intf = <1>;\n+\t\t};\n+\t};\n+};\n", "prefixes": [ "v7", "9/9" ] }