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GET /api/patches/2148245/?format=api
{ "id": 2148245, "url": "http://patchwork.ozlabs.org/api/patches/2148245/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20251010134424.3835757-7-anshuld@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20251010134424.3835757-7-anshuld@ti.com>", "list_archive_url": null, "date": "2025-10-10T13:44:12", "name": "[v10,06/11] mach-k3: map all banks using mem_map_from_dram_banks", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "2edc06105cfb529c56cf8b7e57b5ad8caba48835", "submitter": { "id": 90324, "url": "http://patchwork.ozlabs.org/api/people/90324/?format=api", "name": "Anshul Dalal", "email": "anshuld@ti.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20251010134424.3835757-7-anshuld@ti.com/mbox/", "series": [ { "id": 477111, "url": "http://patchwork.ozlabs.org/api/series/477111/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=477111", "date": "2025-10-10T13:44:06", "name": "Add support for dynamic MMU configuration", "version": 10, "mbox": "http://patchwork.ozlabs.org/series/477111/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2148245/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2148245/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", 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"", "X-Spam-Status": "No, score=-2.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,\n RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,\n RCVD_IN_VALIDITY_RPBL_BLOCKED,SPF_HELO_PASS,SPF_PASS autolearn=ham\n autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com;\n s=ti-com-17Q1; t=1760103883;\n bh=wD/4FvEm1t8qMpsx5JMgTQBJ8j1NVP1u7WgpbkM6Jgc=;\n h=From:To:CC:Subject:Date:In-Reply-To:References;\n b=jC43pYHHOO/tMxbd7TkI6hipHYqn1IQNk3NpUjlKuucVS9b5vaHWZQ9/I+2QHABQS\n JBqFF07K8BZ1QSnNKNqZZcMUsT4BqHlOIv3tHChyX2pN2JsdT5g8iv36+icldWmL29\n ryTN9KtEYDzcsN9O/BrDKqds21SfCErbza7RtEjM=", "From": "Anshul Dalal <anshuld@ti.com>", "To": "<u-boot@lists.denx.de>", "CC": "Anshul Dalal <anshuld@ti.com>, <d-gole@ti.com>, <b-padhi@ti.com>,\n <vigneshr@ti.com>, <trini@konsulko.com>, <nm@ti.com>,\n <robertcnelson@gmail.com>, <w.egorov@phytec.de>,\n <francesco.dolcini@toradex.com>, <ggiordano@phytec.com>,\n <m-chawdhry@ti.com>, <afd@ti.com>, <bb@ti.com>, <u-kumar1@ti.com>,\n <devarsht@ti.com>, <ilias.apalodimas@linaro.org>, <xypron.glpk@gmx.de>", "Subject": "[PATCH v10 06/11] mach-k3: map all banks using\n mem_map_from_dram_banks", "Date": "Fri, 10 Oct 2025 19:14:12 +0530", "Message-ID": "<20251010134424.3835757-7-anshuld@ti.com>", "X-Mailer": "git-send-email 2.51.0", "In-Reply-To": "<20251010134424.3835757-1-anshuld@ti.com>", "References": "<20251010134424.3835757-1-anshuld@ti.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-C2ProcessedOrg": "333ef613-75bf-4e12-a4b1-8e3623f5dcea", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "The static memory map for K3 (k3_mem_map) only maps the first DRAM bank\nand therefore doesn't scale for platforms with multiple memory banks.\n\nThis patch modifies enable_caches to add mem_map_from_dram_banks which\nappends all the memory banks to k3_mem_map before calling mmu_setup.\n\nSigned-off-by: Anshul Dalal <anshuld@ti.com>\nTested-by: Wadim Egorov <w.egorov@phytec.de>\n---\n arch/arm/mach-k3/arm64/arm64-mmu.c | 5 +++--\n arch/arm/mach-k3/common.c | 9 +++++++++\n arch/arm/mach-k3/include/mach/k3-ddr.h | 6 ++++++\n 3 files changed, 18 insertions(+), 2 deletions(-)", "diff": "diff --git a/arch/arm/mach-k3/arm64/arm64-mmu.c b/arch/arm/mach-k3/arm64/arm64-mmu.c\nindex 79650a7e346..479451452a2 100644\n--- a/arch/arm/mach-k3/arm64/arm64-mmu.c\n+++ b/arch/arm/mach-k3/arm64/arm64-mmu.c\n@@ -12,8 +12,9 @@\n #include <asm/system.h>\n #include <asm/armv8/mmu.h>\n #include <linux/sizes.h>\n+#include <mach/k3-ddr.h>\n \n-struct mm_region k3_mem_map[] = {\n+struct mm_region k3_mem_map[K3_MEM_MAP_LEN] = {\n \t{ /* SoC Peripherals */\n \t\t.virt = 0x0UL,\n \t\t.phys = 0x0UL,\n@@ -28,7 +29,7 @@ struct mm_region k3_mem_map[] = {\n \t\t.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n \t\t\t PTE_BLOCK_NON_SHARE |\n \t\t\t PTE_BLOCK_PXN | PTE_BLOCK_UXN\n-\t}, { /* First DRAM Bank of size 2G */\n+\t}, [K3_MEM_MAP_FIRST_BANK_IDX] = { /* First DRAM Bank of size 2G */\n \t\t.virt = CFG_SYS_SDRAM_BASE,\n \t\t.phys = CFG_SYS_SDRAM_BASE,\n \t\t.size = SZ_2G,\ndiff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c\nindex ea287ba1226..30ad98a68a2 100644\n--- a/arch/arm/mach-k3/common.c\n+++ b/arch/arm/mach-k3/common.c\n@@ -31,6 +31,7 @@\n #include <dm/uclass-internal.h>\n #include <dm/device-internal.h>\n #include <asm/armv8/mmu.h>\n+#include <mach/k3-ddr.h>\n \n #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT\t0x00000001\n #define PROC_BOOT_STATUS_FLAG_R5_WFI\t\t0x00000002\n@@ -262,6 +263,14 @@ void board_prep_linux(struct bootm_headers *images)\n \n void enable_caches(void)\n {\n+\tint ret;\n+\n+\tret = mem_map_from_dram_banks(K3_MEM_MAP_FIRST_BANK_IDX, K3_MEM_MAP_LEN,\n+\t\t\t\t PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n+\t\t\t\t\t PTE_BLOCK_INNER_SHARE);\n+\tif (ret)\n+\t\tdebug(\"%s: Failed to setup dram banks\\n\", __func__);\n+\n \tmmu_setup();\n \n \ticache_enable();\ndiff --git a/arch/arm/mach-k3/include/mach/k3-ddr.h b/arch/arm/mach-k3/include/mach/k3-ddr.h\nindex 39e6725bb9b..207e60b2763 100644\n--- a/arch/arm/mach-k3/include/mach/k3-ddr.h\n+++ b/arch/arm/mach-k3/include/mach/k3-ddr.h\n@@ -8,6 +8,12 @@\n \n #include <spl.h>\n \n+/* We need 3 extra entries for:\n+ * SoC peripherals, flash and the sentinel value.\n+ */\n+#define K3_MEM_MAP_LEN\t\t\t((CONFIG_NR_DRAM_BANKS) + 3)\n+#define K3_MEM_MAP_FIRST_BANK_IDX\t2\n+\n int dram_init(void);\n int dram_init_banksize(void);\n \n", "prefixes": [ "v10", "06/11" ] }