Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2148240/?format=api
{ "id": 2148240, "url": "http://patchwork.ozlabs.org/api/patches/2148240/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20251010134424.3835757-4-anshuld@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20251010134424.3835757-4-anshuld@ti.com>", "list_archive_url": null, "date": "2025-10-10T13:44:09", "name": "[v10,03/11] arm: armv8: mmu: export mmu_setup", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "6d612c405b8641a166bf328857eb1b16b5fd9379", "submitter": { "id": 90324, "url": "http://patchwork.ozlabs.org/api/people/90324/?format=api", "name": "Anshul Dalal", "email": "anshuld@ti.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20251010134424.3835757-4-anshuld@ti.com/mbox/", "series": [ { "id": 477111, "url": "http://patchwork.ozlabs.org/api/series/477111/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=477111", "date": "2025-10-10T13:44:06", "name": "Add support for dynamic MMU configuration", "version": 10, "mbox": "http://patchwork.ozlabs.org/series/477111/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2148240/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2148240/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256\n header.s=ti-com-17Q1 header.b=KyIWKINc;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=quarantine dis=none) header.from=ti.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ti.com header.i=@ti.com header.b=\"KyIWKINc\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=quarantine dis=none) header.from=ti.com", "phobos.denx.de; spf=pass smtp.mailfrom=anshuld@ti.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cjp056r1pz1y1V\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 11 Oct 2025 00:45:09 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 48D63843B7;\n\tFri, 10 Oct 2025 15:44:45 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 583EC843C5; Fri, 10 Oct 2025 15:44:44 +0200 (CEST)", "from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n bits)) (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 4497E843B6\n for <u-boot@lists.denx.de>; Fri, 10 Oct 2025 15:44:42 +0200 (CEST)", "from fllvem-sh04.itg.ti.com ([10.64.41.54])\n by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 59ADibom326603;\n Fri, 10 Oct 2025 08:44:37 -0500", "from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32])\n by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 59ADibfu829863\n (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL);\n Fri, 10 Oct 2025 08:44:37 -0500", "from DLEE203.ent.ti.com (157.170.170.78) by DLEE102.ent.ti.com\n (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 10\n Oct 2025 08:44:36 -0500", "from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE203.ent.ti.com\n (157.170.170.78) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend\n Transport; Fri, 10 Oct 2025 08:44:36 -0500", "from localhost (dhcp-172-24-233-105.dhcp.ti.com [172.24.233.105])\n by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 59ADiZXD1957404;\n Fri, 10 Oct 2025 08:44:36 -0500" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,\n RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,\n RCVD_IN_VALIDITY_RPBL_BLOCKED,SPF_HELO_PASS,SPF_PASS autolearn=ham\n autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com;\n s=ti-com-17Q1; t=1760103877;\n bh=/TsTgUJWonwNdxUt3rrYagHlRE1AJH4qcPN28IN4sWw=;\n h=From:To:CC:Subject:Date:In-Reply-To:References;\n b=KyIWKINc1aTSkXZ6+CGvogOv2+6+7q5/WgDFOmv4YFqLvIzUIxaCXSOWH5J9Keeze\n pvwiiaRRzA8DwNe2WG77jWwl2TXeT6TGgEWg1BLpB0jgCjDoW83rokyBuExH8YnilQ\n 9LwcGXU7r/ycqY8KxQxL+O1ML68+Mnt7G9AGKt5s=", "From": "Anshul Dalal <anshuld@ti.com>", "To": "<u-boot@lists.denx.de>", "CC": "Anshul Dalal <anshuld@ti.com>, <d-gole@ti.com>, <b-padhi@ti.com>,\n <vigneshr@ti.com>, <trini@konsulko.com>, <nm@ti.com>,\n <robertcnelson@gmail.com>, <w.egorov@phytec.de>,\n <francesco.dolcini@toradex.com>, <ggiordano@phytec.com>,\n <m-chawdhry@ti.com>, <afd@ti.com>, <bb@ti.com>, <u-kumar1@ti.com>,\n <devarsht@ti.com>, <ilias.apalodimas@linaro.org>, <xypron.glpk@gmx.de>", "Subject": "[PATCH v10 03/11] arm: armv8: mmu: export mmu_setup", "Date": "Fri, 10 Oct 2025 19:14:09 +0530", "Message-ID": "<20251010134424.3835757-4-anshuld@ti.com>", "X-Mailer": "git-send-email 2.51.0", "In-Reply-To": "<20251010134424.3835757-1-anshuld@ti.com>", "References": "<20251010134424.3835757-1-anshuld@ti.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-C2ProcessedOrg": "333ef613-75bf-4e12-a4b1-8e3623f5dcea", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "The mmu_setup function configures the page tables based on the board\nsupplied mem_map struct array. It is called implicitly as part of\ndcache_enable but this limits us to only be able to use APIs such as\nmmu_change_region_attr only after caches are enabled.\n\nThis might lead to speculative accesses before we can unmap a region\nthat is marked as cacheable in the static memory map.\n\nTherefore this patch exports the mmu_setup function in mmu.h allowing\nusers to have more control over when the mmu is configured.\n\nFor K3 specifically this allows for the following configuration sequence\nas part of enable_caches:\n\nstatic mem_map fixups (TODO) -> mmu_setup -> carveouts using\nmmu_change_region_attr (TODO) -> icache/dcache enable\n\nReviewed-by: Dhruva Gole <d-gole@ti.com>\nReviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>\nSigned-off-by: Anshul Dalal <anshuld@ti.com>\nTested-by: Wadim Egorov <w.egorov@phytec.de>\n---\n arch/arm/include/asm/armv8/mmu.h | 5 +++++\n arch/arm/mach-k3/common.c | 3 +++\n 2 files changed, 8 insertions(+)", "diff": "diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h\nindex 6af8cd111a4..3807c702fb6 100644\n--- a/arch/arm/include/asm/armv8/mmu.h\n+++ b/arch/arm/include/asm/armv8/mmu.h\n@@ -197,6 +197,11 @@ struct mm_region {\n extern struct mm_region *mem_map;\n void setup_pgtables(void);\n u64 get_tcr(u64 *pips, u64 *pva_bits);\n+\n+/**\n+ * mmu_setup() - Sets up the mmu page tables as per mem_map\n+ */\n+void mmu_setup(void);\n #endif\n \n #endif /* _ASM_ARMV8_MMU_H_ */\ndiff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c\nindex 7f2a4e6260e..ea287ba1226 100644\n--- a/arch/arm/mach-k3/common.c\n+++ b/arch/arm/mach-k3/common.c\n@@ -30,6 +30,7 @@\n #include <soc.h>\n #include <dm/uclass-internal.h>\n #include <dm/device-internal.h>\n+#include <asm/armv8/mmu.h>\n \n #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT\t0x00000001\n #define PROC_BOOT_STATUS_FLAG_R5_WFI\t\t0x00000002\n@@ -261,6 +262,8 @@ void board_prep_linux(struct bootm_headers *images)\n \n void enable_caches(void)\n {\n+\tmmu_setup();\n+\n \ticache_enable();\n \tdcache_enable();\n }\n", "prefixes": [ "v10", "03/11" ] }