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GET /api/patches/2148237/?format=api
{ "id": 2148237, "url": "http://patchwork.ozlabs.org/api/patches/2148237/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20251010134424.3835757-3-anshuld@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20251010134424.3835757-3-anshuld@ti.com>", "list_archive_url": null, "date": "2025-10-10T13:44:08", "name": "[v10,02/11] mach-k3: use custom enable_cache", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "fbad95de3c96c8deb7f2c62e2622699836f2e3b7", "submitter": { "id": 90324, "url": "http://patchwork.ozlabs.org/api/people/90324/?format=api", "name": "Anshul Dalal", "email": "anshuld@ti.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20251010134424.3835757-3-anshuld@ti.com/mbox/", "series": [ { "id": 477111, "url": "http://patchwork.ozlabs.org/api/series/477111/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=477111", "date": "2025-10-10T13:44:06", "name": "Add support for dynamic MMU configuration", "version": 10, "mbox": "http://patchwork.ozlabs.org/series/477111/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2148237/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2148237/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256\n header.s=ti-com-17Q1 header.b=QBvYPErC;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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Fri, 10 Oct 2025 08:44:34 -0500", "from localhost (dhcp-172-24-233-105.dhcp.ti.com [172.24.233.105])\n by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 59ADiXqb1957378;\n Fri, 10 Oct 2025 08:44:34 -0500" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,\n RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,\n RCVD_IN_VALIDITY_RPBL_BLOCKED,SPF_HELO_PASS,SPF_PASS autolearn=ham\n autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com;\n s=ti-com-17Q1; t=1760103875;\n bh=g7TK7VmUJnhH5OPpjnLRJDv02B0k9ljpO6bXG9UPgXk=;\n h=From:To:CC:Subject:Date:In-Reply-To:References;\n b=QBvYPErC4FZQ+ERrUZs2LBxVVN4gwx9o9BbmaU8m0nFWE2EVJK+hZypZiX7oo0jew\n ioaHzaW8VWlmmKyu4hhLx2vre0JVaOnJs/NKsrpsE0GmawvTd2OjzaBHEXmoCFhfZH\n LJlUax+vUJwXX50pDDFfsLPp26yzdBv7s76JPOrE=", "From": "Anshul Dalal <anshuld@ti.com>", "To": "<u-boot@lists.denx.de>", "CC": "Anshul Dalal <anshuld@ti.com>, <d-gole@ti.com>, <b-padhi@ti.com>,\n <vigneshr@ti.com>, <trini@konsulko.com>, <nm@ti.com>,\n <robertcnelson@gmail.com>, <w.egorov@phytec.de>,\n <francesco.dolcini@toradex.com>, <ggiordano@phytec.com>,\n <m-chawdhry@ti.com>, <afd@ti.com>, <bb@ti.com>, <u-kumar1@ti.com>,\n <devarsht@ti.com>, <ilias.apalodimas@linaro.org>, <xypron.glpk@gmx.de>", "Subject": "[PATCH v10 02/11] mach-k3: use custom enable_cache", "Date": "Fri, 10 Oct 2025 19:14:08 +0530", "Message-ID": "<20251010134424.3835757-3-anshuld@ti.com>", "X-Mailer": "git-send-email 2.51.0", "In-Reply-To": "<20251010134424.3835757-1-anshuld@ti.com>", "References": "<20251010134424.3835757-1-anshuld@ti.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-C2ProcessedOrg": "333ef613-75bf-4e12-a4b1-8e3623f5dcea", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "U-Boot's provided enable_caches enforces the following sequence:\nicache_enable -> mmu_setup (as part of dcache_enable) -> dcache_enable\n\nWhereas for K3 devices, we would like to add entries to the provided\nstatic array (k3_mem_map) as per gd->bd->bi_dram and then call mmu_setup\nto configure the MMU but also create carveouts for TFA/TEE before we\nenable caches to prevent speculative accesses to the region. Thus the\nfollowing desired sequence:\n\nadd dram banks -> mmu_setup -> carveout TFA/TEE -> icache/dcache enable\n\nTherefore this patch adds K3's own implementation of enable_cache for\nARM64, allowing for greater control over the cache enablement sequence.\n\nReviewed-by: Dhruva Gole <d-gole@ti.com>\nSigned-off-by: Anshul Dalal <anshuld@ti.com>\nTested-by: Wadim Egorov <w.egorov@phytec.de>\n---\n arch/arm/mach-k3/common.c | 6 ++++++\n 1 file changed, 6 insertions(+)", "diff": "diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c\nindex 5483ac9906c..7f2a4e6260e 100644\n--- a/arch/arm/mach-k3/common.c\n+++ b/arch/arm/mach-k3/common.c\n@@ -258,6 +258,12 @@ void board_prep_linux(struct bootm_headers *images)\n \t\t\t\t ROUND(images->os.end,\n \t\t\t\t CONFIG_SYS_CACHELINE_SIZE));\n }\n+\n+void enable_caches(void)\n+{\n+\ticache_enable();\n+\tdcache_enable();\n+}\n #endif\n \n void spl_enable_cache(void)\n", "prefixes": [ "v10", "02/11" ] }