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GET /api/patches/2148235/?format=api
{ "id": 2148235, "url": "http://patchwork.ozlabs.org/api/patches/2148235/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20251010134424.3835757-2-anshuld@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20251010134424.3835757-2-anshuld@ti.com>", "list_archive_url": null, "date": "2025-10-10T13:44:07", "name": "[v10,01/11] mach-k3: use minimal memory map for all K3", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "cbb0aa014e03fc9a7877e766452a03d807580d63", "submitter": { "id": 90324, "url": "http://patchwork.ozlabs.org/api/people/90324/?format=api", "name": "Anshul Dalal", "email": "anshuld@ti.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20251010134424.3835757-2-anshuld@ti.com/mbox/", "series": [ { "id": 477111, "url": "http://patchwork.ozlabs.org/api/series/477111/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=477111", "date": "2025-10-10T13:44:06", "name": "Add support for dynamic MMU configuration", "version": 10, "mbox": "http://patchwork.ozlabs.org/series/477111/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2148235/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2148235/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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"X-Spam-Level": "", "X-Spam-Status": "No, score=-2.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,\n RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,\n RCVD_IN_VALIDITY_RPBL_BLOCKED,SPF_HELO_PASS,SPF_PASS autolearn=ham\n autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com;\n s=ti-com-17Q1; t=1760103873;\n bh=wbbuxHplBS08EPZUGXzcNtjZchZH2D3DKkU0e96Q+DU=;\n h=From:To:CC:Subject:Date:In-Reply-To:References;\n b=sl9i4lLar78B2Je/BHkZwNDqT053Gnm813rPNNxhyZvO7S+pSITbl5x3YmI/Az30h\n crLQLVNs9OOM4opdQNfNew9N6ys0qUNMNf5fb1NIxqdxLk4B0UG1U5/eY7UWXHDipD\n AtFDPbwXb2aq7Wt7MKmeVJqiP2uJ4QAhuEXuvR4A=", "From": "Anshul Dalal <anshuld@ti.com>", "To": "<u-boot@lists.denx.de>", "CC": "Anshul Dalal <anshuld@ti.com>, <d-gole@ti.com>, <b-padhi@ti.com>,\n <vigneshr@ti.com>, <trini@konsulko.com>, <nm@ti.com>,\n <robertcnelson@gmail.com>, <w.egorov@phytec.de>,\n <francesco.dolcini@toradex.com>, <ggiordano@phytec.com>,\n <m-chawdhry@ti.com>, <afd@ti.com>, <bb@ti.com>, <u-kumar1@ti.com>,\n <devarsht@ti.com>, <ilias.apalodimas@linaro.org>, <xypron.glpk@gmx.de>", "Subject": "[PATCH v10 01/11] mach-k3: use minimal memory map for all K3", "Date": "Fri, 10 Oct 2025 19:14:07 +0530", "Message-ID": "<20251010134424.3835757-2-anshuld@ti.com>", "X-Mailer": "git-send-email 2.51.0", "In-Reply-To": "<20251010134424.3835757-1-anshuld@ti.com>", "References": "<20251010134424.3835757-1-anshuld@ti.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-C2ProcessedOrg": "333ef613-75bf-4e12-a4b1-8e3623f5dcea", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "The K3 family of SoCs encompasses a wide variety of devices with varying\nDDR configurations and memory carveout requirements, the current static\nmemory map provides basic support for TI EVMs but does not scale well\nfor newer platforms (such as AM62SiP with 512MiB of RAM).\n\nTherefore this patch replaces the existing memory map with a minimal\none, that could be more easily modified at runtime.\n\nReviewed-by: Dhruva Gole <d-gole@ti.com>\nSigned-off-by: Anshul Dalal <anshuld@ti.com>\nTested-by: Wadim Egorov <w.egorov@phytec.de>\n---\n arch/arm/mach-k3/arm64/arm64-mmu.c | 32 ++++++++++--------------------\n 1 file changed, 10 insertions(+), 22 deletions(-)", "diff": "diff --git a/arch/arm/mach-k3/arm64/arm64-mmu.c b/arch/arm/mach-k3/arm64/arm64-mmu.c\nindex 0e07b1b7ce0..79650a7e346 100644\n--- a/arch/arm/mach-k3/arm64/arm64-mmu.c\n+++ b/arch/arm/mach-k3/arm64/arm64-mmu.c\n@@ -11,42 +11,30 @@\n \n #include <asm/system.h>\n #include <asm/armv8/mmu.h>\n+#include <linux/sizes.h>\n \n struct mm_region k3_mem_map[] = {\n-\t{\n+\t{ /* SoC Peripherals */\n \t\t.virt = 0x0UL,\n \t\t.phys = 0x0UL,\n \t\t.size = 0x80000000UL,\n \t\t.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n \t\t\t PTE_BLOCK_NON_SHARE |\n \t\t\t PTE_BLOCK_PXN | PTE_BLOCK_UXN\n-\t}, {\n-\t\t.virt = 0x80000000UL,\n-\t\t.phys = 0x80000000UL,\n-\t\t.size = 0x1e780000UL,\n-\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n-\t\t\t PTE_BLOCK_INNER_SHARE\n-\t}, {\n-\t\t.virt = 0xa0000000UL,\n-\t\t.phys = 0xa0000000UL,\n-\t\t.size = 0x60000000UL,\n-\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n-\t\t\t PTE_BLOCK_INNER_SHARE\n-\t}, {\n-\t\t.virt = 0x880000000UL,\n-\t\t.phys = 0x880000000UL,\n-\t\t.size = 0x80000000UL,\n-\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n-\t\t\t PTE_BLOCK_INNER_SHARE\n-\t}, {\n+\t}, { /* Flash Peripherals */\n \t\t.virt = 0x500000000UL,\n \t\t.phys = 0x500000000UL,\n \t\t.size = 0x380000000UL,\n \t\t.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n \t\t\t PTE_BLOCK_NON_SHARE |\n \t\t\t PTE_BLOCK_PXN | PTE_BLOCK_UXN\n-\t}, {\n-\t\t/* List terminator */\n+\t}, { /* First DRAM Bank of size 2G */\n+\t\t.virt = CFG_SYS_SDRAM_BASE,\n+\t\t.phys = CFG_SYS_SDRAM_BASE,\n+\t\t.size = SZ_2G,\n+\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n+\t\t\t PTE_BLOCK_INNER_SHARE\n+\t}, { /* List terminator */\n \t\t0,\n \t}\n };\n", "prefixes": [ "v10", "01/11" ] }