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GET /api/patches/2140027/?format=api
{ "id": 2140027, "url": "http://patchwork.ozlabs.org/api/patches/2140027/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20250920161013.31799-5-ansuelsmth@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20250920161013.31799-5-ansuelsmth@gmail.com>", "list_archive_url": null, "date": "2025-09-20T16:09:44", "name": "[v2,4/5] net: mediatek: move MT7531 MMIO MDIO to dedicated driver", "commit_ref": "b24268d151a0c28772785e14703491364becda5b", "pull_url": null, "state": "accepted", "archived": false, "hash": "5b5589cba443d274fd6381f7952e768d915a129e", "submitter": { "id": 71108, "url": "http://patchwork.ozlabs.org/api/people/71108/?format=api", "name": "Christian Marangi", "email": "ansuelsmth@gmail.com" }, "delegate": { "id": 157425, "url": "http://patchwork.ozlabs.org/api/users/157425/?format=api", "username": "jforissier", "first_name": "Jerome", "last_name": "Forissier", "email": "jerome.forissier@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20250920161013.31799-5-ansuelsmth@gmail.com/mbox/", "series": [ { "id": 474528, "url": "http://patchwork.ozlabs.org/api/series/474528/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=474528", "date": "2025-09-20T16:09:40", "name": "net: mediatek: mt7988: various fixup + MDIO detach", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/474528/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2140027/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2140027/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=IDkG6nrJ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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The MT7988 code is updated to make use of the external driver.\n\nThis permits Airoha driver to make use of DM_MDIO to bind for the MT7531\ndriver that have the same exact register.\n\nSigned-off-by: Christian Marangi <ansuelsmth@gmail.com>\n---\n drivers/net/Kconfig | 3 +\n drivers/net/Makefile | 1 +\n drivers/net/mdio-mt7531-mmio.c | 168 +++++++++++++++++++++++++++++++++\n drivers/net/mdio-mt7531-mmio.h | 9 ++\n drivers/net/mtk_eth/Kconfig | 1 +\n drivers/net/mtk_eth/mt7988.c | 85 ++++++++++++++---\n 6 files changed, 254 insertions(+), 13 deletions(-)\n create mode 100644 drivers/net/mdio-mt7531-mmio.c\n create mode 100644 drivers/net/mdio-mt7531-mmio.h", "diff": "diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig\nindex d1cb69f85ad..cee4a3fc9bd 100644\n--- a/drivers/net/Kconfig\n+++ b/drivers/net/Kconfig\n@@ -966,6 +966,9 @@ config TSEC_ENET\n \t This driver implements support for the (Enhanced) Three-Speed\n \t Ethernet Controller found on Freescale SoCs.\n \n+config MDIO_MT7531_MMIO\n+\tbool\n+\n source \"drivers/net/mtk_eth/Kconfig\"\n \n config HIFEMAC_ETH\ndiff --git a/drivers/net/Makefile b/drivers/net/Makefile\nindex f8f9a71f815..a3c3420898c 100644\n--- a/drivers/net/Makefile\n+++ b/drivers/net/Makefile\n@@ -63,6 +63,7 @@ obj-$(CONFIG_MACB) += macb.o\n obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o\n obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o\n obj-$(CONFIG_MDIO_GPIO_BITBANG) += mdio_gpio.o\n+obj-$(CONFIG_MDIO_MT7531_MMIO) += mdio-mt7531-mmio.o\n obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o\n obj-$(CONFIG_MDIO_MUX_MESON_G12A) += mdio_mux_meson_g12a.o\n obj-$(CONFIG_MDIO_MUX_MESON_GXL) += mdio_mux_meson_gxl.o\ndiff --git a/drivers/net/mdio-mt7531-mmio.c b/drivers/net/mdio-mt7531-mmio.c\nnew file mode 100644\nindex 00000000000..3e325ca58da\n--- /dev/null\n+++ b/drivers/net/mdio-mt7531-mmio.c\n@@ -0,0 +1,168 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+\n+#include <asm/io.h>\n+#include <dm.h>\n+#include <linux/bitfield.h>\n+#include <linux/iopoll.h>\n+#include <miiphy.h>\n+\n+#define MT7531_PHY_IAC\t\t\t0x701c\n+#define MT7531_PHY_ACS_ST\t\tBIT(31)\n+#define MT7531_MDIO_REG_ADDR_CL22\tGENMASK(29, 25)\n+#define MT7531_MDIO_DEV_ADDR\t\tMT7531_MDIO_REG_ADDR_CL22\n+#define MT7531_MDIO_PHY_ADDR\t\tGENMASK(24, 20)\n+#define MT7531_MDIO_CMD\t\tGENMASK(19, 18)\n+#define MT7531_MDIO_CMD_READ_CL45\tFIELD_PREP_CONST(MT7531_MDIO_CMD, 0x3)\n+#define MT7531_MDIO_CMD_READ_CL22\tFIELD_PREP_CONST(MT7531_MDIO_CMD, 0x2)\n+#define MT7531_MDIO_CMD_WRITE\t\tFIELD_PREP_CONST(MT7531_MDIO_CMD, 0x1)\n+#define MT7531_MDIO_CMD_ADDR\t\tFIELD_PREP_CONST(MT7531_MDIO_CMD, 0x0)\n+#define MT7531_MDIO_ST\t\tGENMASK(17, 16)\n+#define MT7531_MDIO_ST_CL22\t\tFIELD_PREP_CONST(MT7531_MDIO_ST, 0x1)\n+#define MT7531_MDIO_ST_CL45\t\tFIELD_PREP_CONST(MT7531_MDIO_ST, 0x0)\n+#define MT7531_MDIO_RW_DATA\t\tGENMASK(15, 0)\n+#define MT7531_MDIO_REG_ADDR_CL45\tMT7531_MDIO_RW_DATA\n+\n+#define MT7531_MDIO_TIMEOUT\t\t100000\n+#define MT7531_MDIO_SLEEP\t\t20\n+\n+struct mt7531_mdio_priv {\n+\tphys_addr_t switch_regs;\n+};\n+\n+static int mt7531_mdio_wait_busy(struct mt7531_mdio_priv *priv)\n+{\n+\tunsigned int busy;\n+\n+\treturn readl_poll_sleep_timeout(priv->switch_regs + MT7531_PHY_IAC,\n+\t\t\t\t\tbusy, (busy & MT7531_PHY_ACS_ST) == 0,\n+\t\t\t\t\tMT7531_MDIO_SLEEP, MT7531_MDIO_TIMEOUT);\n+}\n+\n+static int mt7531_mdio_read(struct mt7531_mdio_priv *priv, int addr, int devad, int reg)\n+{\n+\tu32 val;\n+\n+\tif (devad != MDIO_DEVAD_NONE) {\n+\t\tif (mt7531_mdio_wait_busy(priv))\n+\t\t\treturn -ETIMEDOUT;\n+\n+\t\tval = MT7531_PHY_ACS_ST |\n+\t\t MT7531_MDIO_ST_CL45 | MT7531_MDIO_CMD_ADDR |\n+\t\t FIELD_PREP(MT7531_MDIO_PHY_ADDR, addr) |\n+\t\t FIELD_PREP(MT7531_MDIO_DEV_ADDR, devad) |\n+\t\t FIELD_PREP(MT7531_MDIO_REG_ADDR_CL45, reg);\n+\n+\t\twritel(val, priv->switch_regs + MT7531_PHY_IAC);\n+\t}\n+\n+\tif (mt7531_mdio_wait_busy(priv))\n+\t\treturn -ETIMEDOUT;\n+\n+\tval = MT7531_PHY_ACS_ST | FIELD_PREP(MT7531_MDIO_PHY_ADDR, addr);\n+\tif (devad != MDIO_DEVAD_NONE)\n+\t\tval |= MT7531_MDIO_ST_CL45 | MT7531_MDIO_CMD_READ_CL45 |\n+\t\t FIELD_PREP(MT7531_MDIO_DEV_ADDR, devad);\n+\telse\n+\t\tval |= MT7531_MDIO_ST_CL22 | MT7531_MDIO_CMD_READ_CL22 |\n+\t\t FIELD_PREP(MT7531_MDIO_REG_ADDR_CL22, reg);\n+\n+\twritel(val, priv->switch_regs + MT7531_PHY_IAC);\n+\n+\tif (mt7531_mdio_wait_busy(priv))\n+\t\treturn -ETIMEDOUT;\n+\n+\tval = readl(priv->switch_regs + MT7531_PHY_IAC);\n+\treturn val & MT7531_MDIO_RW_DATA;\n+}\n+\n+static int mt7531_mdio_write(struct mt7531_mdio_priv *priv, int addr, int devad,\n+\t\t\t int reg, u16 value)\n+{\n+\tu32 val;\n+\n+\tif (devad != MDIO_DEVAD_NONE) {\n+\t\tif (mt7531_mdio_wait_busy(priv))\n+\t\t\treturn -ETIMEDOUT;\n+\n+\t\tval = MT7531_PHY_ACS_ST |\n+\t\t MT7531_MDIO_ST_CL45 | MT7531_MDIO_CMD_ADDR |\n+\t\t FIELD_PREP(MT7531_MDIO_PHY_ADDR, addr) |\n+\t\t FIELD_PREP(MT7531_MDIO_DEV_ADDR, devad) |\n+\t\t FIELD_PREP(MT7531_MDIO_REG_ADDR_CL45, reg);\n+\n+\t\twritel(val, priv->switch_regs + MT7531_PHY_IAC);\n+\t}\n+\n+\tif (mt7531_mdio_wait_busy(priv))\n+\t\treturn -ETIMEDOUT;\n+\n+\tval = MT7531_PHY_ACS_ST | FIELD_PREP(MT7531_MDIO_PHY_ADDR, addr) |\n+\t MT7531_MDIO_CMD_WRITE | FIELD_PREP(MT7531_MDIO_RW_DATA, value);\n+\tif (devad != MDIO_DEVAD_NONE)\n+\t\tval |= MT7531_MDIO_ST_CL45 |\n+\t\t FIELD_PREP(MT7531_MDIO_DEV_ADDR, devad);\n+\telse\n+\t\tval |= MT7531_MDIO_ST_CL22 |\n+\t\t FIELD_PREP(MT7531_MDIO_REG_ADDR_CL22, reg);\n+\n+\twritel(val, priv->switch_regs + MT7531_PHY_IAC);\n+\n+\tif (mt7531_mdio_wait_busy(priv))\n+\t\treturn -ETIMEDOUT;\n+\n+\treturn 0;\n+}\n+\n+int mt7531_mdio_mmio_read(struct mii_dev *bus, int addr, int devad, int reg)\n+{\n+\tstruct mt7531_mdio_priv *priv = bus->priv;\n+\n+\treturn mt7531_mdio_read(priv, addr, devad, reg);\n+}\n+\n+int mt7531_mdio_mmio_write(struct mii_dev *bus, int addr, int devad,\n+\t\t\t int reg, u16 value)\n+{\n+\tstruct mt7531_mdio_priv *priv = bus->priv;\n+\n+\treturn mt7531_mdio_write(priv, addr, devad, reg, value);\n+}\n+\n+static int dm_mt7531_mdio_read(struct udevice *dev, int addr, int devad, int reg)\n+{\n+\tstruct mt7531_mdio_priv *priv = dev_get_priv(dev);\n+\n+\treturn mt7531_mdio_read(priv, addr, devad, reg);\n+}\n+\n+static int dm_mt7531_mdio_write(struct udevice *dev, int addr, int devad,\n+\t\t\t\tint reg, u16 value)\n+{\n+\tstruct mt7531_mdio_priv *priv = dev_get_priv(dev);\n+\n+\treturn mt7531_mdio_write(priv, addr, devad, reg, value);\n+}\n+\n+static const struct mdio_ops mt7531_mdio_ops = {\n+\t.read = dm_mt7531_mdio_read,\n+\t.write = dm_mt7531_mdio_write,\n+};\n+\n+static int mt7531_mdio_probe(struct udevice *dev)\n+{\n+\tstruct mt7531_mdio_priv *priv = dev_get_priv(dev);\n+\n+\tpriv->switch_regs = dev_read_addr(dev);\n+\tif (priv->switch_regs == FDT_ADDR_T_NONE)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+U_BOOT_DRIVER(mt7531_mdio) = {\n+\t.name = \"mt7531-mdio-mmio\",\n+\t.id = UCLASS_MDIO,\n+\t.probe = mt7531_mdio_probe,\n+\t.ops = &mt7531_mdio_ops,\n+\t.priv_auto\t = sizeof(struct mt7531_mdio_priv),\n+};\ndiff --git a/drivers/net/mdio-mt7531-mmio.h b/drivers/net/mdio-mt7531-mmio.h\nnew file mode 100644\nindex 00000000000..f98102cb939\n--- /dev/null\n+++ b/drivers/net/mdio-mt7531-mmio.h\n@@ -0,0 +1,9 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+\n+struct mt7531_mdio_mmio_priv {\n+\tphys_addr_t switch_regs;\n+};\n+\n+int mt7531_mdio_mmio_read(struct mii_dev *bus, int addr, int devad, int reg);\n+int mt7531_mdio_mmio_write(struct mii_dev *bus, int addr, int devad,\n+\t\t\t int reg, u16 value);\ndiff --git a/drivers/net/mtk_eth/Kconfig b/drivers/net/mtk_eth/Kconfig\nindex e8cdf408237..8716eb86064 100644\n--- a/drivers/net/mtk_eth/Kconfig\n+++ b/drivers/net/mtk_eth/Kconfig\n@@ -30,6 +30,7 @@ config MTK_ETH_SWITCH_MT7531\n config MTK_ETH_SWITCH_MT7988\n \tbool \"Support for MediaTek MT7988 built-in ethernet switch\"\n \tdepends on TARGET_MT7988\n+\tselect MDIO_MT7531_MMIO\n \tdefault y\n \n config MTK_ETH_SWITCH_AN8855\ndiff --git a/drivers/net/mtk_eth/mt7988.c b/drivers/net/mtk_eth/mt7988.c\nindex b77660be55c..29b6363cbd7 100644\n--- a/drivers/net/mtk_eth/mt7988.c\n+++ b/drivers/net/mtk_eth/mt7988.c\n@@ -6,6 +6,7 @@\n * Author: Mark Lee <mark-mc.lee@mediatek.com>\n */\n \n+#include <malloc.h>\n #include <miiphy.h>\n #include <linux/delay.h>\n #include <linux/mdio.h>\n@@ -14,6 +15,8 @@\n #include \"mtk_eth.h\"\n #include \"mt753x.h\"\n \n+#include \"../mdio-mt7531-mmio.h\"\n+\n static int mt7988_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data)\n {\n \t*data = readl(priv->epriv.ethsys_base + GSW_BASE + reg);\n@@ -30,25 +33,34 @@ static int mt7988_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data)\n \n static void mt7988_phy_setting(struct mt753x_switch_priv *priv)\n {\n+\tstruct mii_dev *mdio_bus = priv->mdio_bus;\n \tu16 val;\n \tu32 i;\n \n \tfor (i = 0; i < MT753X_NUM_PHYS; i++) {\n+\t\tu16 addr = MT753X_PHY_ADDR(priv->phy_base, i);\n+\n \t\t/* Set PHY to PHY page 1 */\n-\t\tmt7531_mii_write(priv, i, 0x1f, 0x1);\n+\t\tmt7531_mdio_mmio_write(mdio_bus, addr, MDIO_DEVAD_NONE,\n+\t\t\t\t 0x1f, 0x1);\n \n \t\t/* Enable HW auto downshift */\n-\t\tval = mt7531_mii_read(priv, i, PHY_EXT_REG_14);\n+\t\tval = mt7531_mdio_mmio_read(mdio_bus, addr, MDIO_DEVAD_NONE,\n+\t\t\t\t\t PHY_EXT_REG_14);\n \t\tval |= PHY_EN_DOWN_SHFIT;\n-\t\tmt7531_mii_write(priv, i, PHY_EXT_REG_14, val);\n+\t\tmt7531_mdio_mmio_write(mdio_bus, addr, MDIO_DEVAD_NONE,\n+\t\t\t\t PHY_EXT_REG_14, val);\n \n \t\t/* PHY link down power saving enable */\n-\t\tval = mt7531_mii_read(priv, i, PHY_EXT_REG_17);\n+\t\tval = mt7531_mdio_mmio_read(mdio_bus, addr, MDIO_DEVAD_NONE,\n+\t\t\t\t\t PHY_EXT_REG_17);\n \t\tval |= PHY_LINKDOWN_POWER_SAVING_EN;\n-\t\tmt7531_mii_write(priv, i, PHY_EXT_REG_17, val);\n+\t\tmt7531_mdio_mmio_write(mdio_bus, addr, MDIO_DEVAD_NONE,\n+\t\t\t\t PHY_EXT_REG_17, val);\n \n \t\t/* Restore PHY to PHY page 0 */\n-\t\tmt7531_mii_write(priv, i, 0x1f, 0x0);\n+\t\tmt7531_mdio_mmio_write(mdio_bus, addr, MDIO_DEVAD_NONE,\n+\t\t\t\t 0x1f, 0x0);\n \t}\n }\n \n@@ -63,23 +75,66 @@ static void mt7988_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable)\n \tmt7988_reg_write(priv, PMCR_REG(6), pmcr);\n }\n \n+static int mt7988_mdio_register(struct mt753x_switch_priv *priv)\n+{\n+\tstruct mt7531_mdio_mmio_priv *mdio_priv;\n+\tstruct mii_dev *mdio_bus = mdio_alloc();\n+\tint ret;\n+\n+\tif (!mdio_bus)\n+\t\treturn -ENOMEM;\n+\n+\tmdio_priv = malloc(sizeof(*mdio_priv));\n+\tif (!mdio_priv)\n+\t\treturn -ENOMEM;\n+\n+\tmdio_priv->switch_regs = (phys_addr_t)priv->epriv.ethsys_base + GSW_BASE;\n+\n+\tmdio_bus->read = mt7531_mdio_mmio_read;\n+\tmdio_bus->write = mt7531_mdio_mmio_write;\n+\tsnprintf(mdio_bus->name, sizeof(mdio_bus->name), priv->epriv.sw->name);\n+\n+\tmdio_bus->priv = mdio_priv;\n+\n+\tret = mdio_register(mdio_bus);\n+\tif (ret) {\n+\t\tfree(mdio_bus->priv);\n+\t\tmdio_free(mdio_bus);\n+\t\treturn ret;\n+\t}\n+\n+\tpriv->mdio_bus = mdio_bus;\n+\n+\treturn 0;\n+}\n+\n static int mt7988_setup(struct mtk_eth_switch_priv *swpriv)\n {\n \tstruct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv;\n-\tu16 phy_val;\n+\tstruct mii_dev *mdio_bus;\n+\tu16 phy_addr, phy_val;\n+\tint ret, i;\n \tu32 pmcr;\n-\tint i;\n \n \tpriv->smi_addr = MT753X_DFL_SMI_ADDR;\n \tpriv->phy_base = (priv->smi_addr + 1) & MT753X_SMI_ADDR_MASK;\n \tpriv->reg_read = mt7988_reg_read;\n \tpriv->reg_write = mt7988_reg_write;\n \n+\tret = mt7988_mdio_register(priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tmdio_bus = priv->mdio_bus;\n+\n \t/* Turn off PHYs */\n \tfor (i = 0; i < MT753X_NUM_PHYS; i++) {\n-\t\tphy_val = mt7531_mii_read(priv, i, MII_BMCR);\n+\t\tphy_addr = MT753X_PHY_ADDR(priv->phy_base, i);\n+\t\tphy_val = mt7531_mdio_mmio_read(mdio_bus, phy_addr,\n+\t\t\t\t\t\tMDIO_DEVAD_NONE, MII_BMCR);\n \t\tphy_val |= BMCR_PDOWN;\n-\t\tmt7531_mii_write(priv, i, MII_BMCR, phy_val);\n+\t\tmt7531_mdio_mmio_write(mdio_bus, phy_addr, MDIO_DEVAD_NONE,\n+\t\t\t\t MII_BMCR, phy_val);\n \t}\n \n \tswitch (priv->epriv.phy_interface) {\n@@ -132,14 +187,17 @@ static int mt7988_setup(struct mtk_eth_switch_priv *swpriv)\n \n \t/* Turn on PHYs */\n \tfor (i = 0; i < MT753X_NUM_PHYS; i++) {\n-\t\tphy_val = mt7531_mii_read(priv, i, MII_BMCR);\n+\t\tphy_addr = MT753X_PHY_ADDR(priv->phy_base, i);\n+\t\tphy_val = mt7531_mdio_mmio_read(mdio_bus, phy_addr,\n+\t\t\t\t\t\tMDIO_DEVAD_NONE, MII_BMCR);\n \t\tphy_val &= ~BMCR_PDOWN;\n-\t\tmt7531_mii_write(priv, i, MII_BMCR, phy_val);\n+\t\tmt7531_mdio_mmio_write(mdio_bus, phy_addr, MDIO_DEVAD_NONE,\n+\t\t\t\t MII_BMCR, phy_val);\n \t}\n \n \tmt7988_phy_setting(priv);\n \n-\treturn mt7531_mdio_register(priv);\n+\treturn 0;\n }\n \n static int mt7988_cleanup(struct mtk_eth_switch_priv *swpriv)\n@@ -148,6 +206,7 @@ static int mt7988_cleanup(struct mtk_eth_switch_priv *swpriv)\n \tstruct mii_dev *mdio_bus = priv->mdio_bus;\n \n \tmdio_unregister(mdio_bus);\n+\tfree(mdio_bus->priv);\n \tmdio_free(mdio_bus);\n \n \treturn 0;\n", "prefixes": [ "v2", "4/5" ] }