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GET /api/patches/2137030/?format=api
{ "id": 2137030, "url": "http://patchwork.ozlabs.org/api/patches/2137030/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250915080157.28195-6-clamor95@gmail.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20250915080157.28195-6-clamor95@gmail.com>", "list_archive_url": null, "date": "2025-09-15T08:01:51", "name": "[v3,05/11] dt-bindings: memory: Add Tegra114 memory client IDs", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "d802a3b550d977ea42f0e610b4db8f2c4922fd4b", "submitter": { "id": 84146, "url": "http://patchwork.ozlabs.org/api/people/84146/?format=api", "name": "Svyatoslav Ryhel", "email": "clamor95@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250915080157.28195-6-clamor95@gmail.com/mbox/", "series": [ { "id": 473641, "url": "http://patchwork.ozlabs.org/api/series/473641/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=473641", "date": "2025-09-15T08:01:46", "name": "Tegra114: implement EMC support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/473641/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2137030/comments/", "check": "success", "checks": "http://patchwork.ozlabs.org/api/patches/2137030/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <devicetree+bounces-217258-incoming-dt=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming-dt@patchwork.ozlabs.org", "devicetree@vger.kernel.org" ], "Delivered-To": "patchwork-incoming-dt@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=FpA8AWJD;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2604:1380:45d1:ec00::1; helo=ny.mirrors.kernel.org;\n envelope-from=devicetree+bounces-217258-incoming-dt=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"FpA8AWJD\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.167.46", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com" ], "Received": [ "from ny.mirrors.kernel.org (ny.mirrors.kernel.org\n [IPv6:2604:1380:45d1:ec00::1])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cQHbs2fffz1y1Y\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n Mon, 15 Sep 2025 18:03:53 +1000 (AEST)", "from smtp.subspace.kernel.org (relay.kernel.org [52.25.139.140])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ny.mirrors.kernel.org (Postfix) with ESMTPS id 8DE0617E027\n\tfor <incoming-dt@patchwork.ozlabs.org>; Mon, 15 Sep 2025 08:03:48 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 42D812EC56F;\n\tMon, 15 Sep 2025 08:02:34 +0000 (UTC)", "from mail-lf1-f46.google.com (mail-lf1-f46.google.com\n [209.85.167.46])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D7492EBBB4\n\tfor <devicetree@vger.kernel.org>; Mon, 15 Sep 2025 08:02:30 +0000 (UTC)", "by mail-lf1-f46.google.com with SMTP id\n 2adb3069b0e04-55f716e25d9so3956353e87.1\n for <devicetree@vger.kernel.org>;\n Mon, 15 Sep 2025 01:02:30 -0700 (PDT)", "from xeon.. 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Gaikwad <pgaikwad@nvidia.com>,\n\tMikko Perttunen <mperttunen@nvidia.com>,\n\tMichael Turquette <mturquette@baylibre.com>,\n\tStephen Boyd <sboyd@kernel.org>,\n\tDmitry Osipenko <digetx@gmail.com>,\n\tMyungJoo Ham <myungjoo.ham@samsung.com>,\n\tKyungmin Park <kyungmin.park@samsung.com>,\n\tChanwoo Choi <cw00.choi@samsung.com>,\n\tSvyatoslav Ryhel <clamor95@gmail.com>", "Cc": "linux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org,\n\tlinux-clk@vger.kernel.org,\n\tlinux-pm@vger.kernel.org", "Subject": "[PATCH v3 05/11] dt-bindings: memory: Add Tegra114 memory client IDs", "Date": "Mon, 15 Sep 2025 11:01:51 +0300", "Message-ID": "<20250915080157.28195-6-clamor95@gmail.com>", "X-Mailer": "git-send-email 2.48.1", "In-Reply-To": "<20250915080157.28195-1-clamor95@gmail.com>", "References": "<20250915080157.28195-1-clamor95@gmail.com>", "Precedence": "bulk", "X-Mailing-List": "devicetree@vger.kernel.org", "List-Id": "<devicetree.vger.kernel.org>", "List-Subscribe": "<mailto:devicetree+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:devicetree+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Each memory client has unique hardware ID, add these IDs.\n\nSigned-off-by: Svyatoslav Ryhel <clamor95@gmail.com>\nAcked-by: Rob Herring (Arm) <robh@kernel.org>\n---\n include/dt-bindings/memory/tegra114-mc.h | 67 ++++++++++++++++++++++++\n 1 file changed, 67 insertions(+)", "diff": "diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h\nindex dfe99c8a5ba5..5e0d6a1b91f2 100644\n--- a/include/dt-bindings/memory/tegra114-mc.h\n+++ b/include/dt-bindings/memory/tegra114-mc.h\n@@ -40,4 +40,71 @@\n #define TEGRA114_MC_RESET_VDE\t\t14\n #define TEGRA114_MC_RESET_VI\t\t15\n \n+#define TEGRA114_MC_PTCR\t\t0\n+#define TEGRA114_MC_DISPLAY0A\t\t1\n+#define TEGRA114_MC_DISPLAY0AB\t\t2\n+#define TEGRA114_MC_DISPLAY0B\t\t3\n+#define TEGRA114_MC_DISPLAY0BB\t\t4\n+#define TEGRA114_MC_DISPLAY0C\t\t5\n+#define TEGRA114_MC_DISPLAY0CB\t\t6\n+#define TEGRA114_MC_DISPLAY1B\t\t7\n+#define TEGRA114_MC_DISPLAY1BB\t\t8\n+#define TEGRA114_MC_EPPUP\t\t9\n+#define TEGRA114_MC_G2PR\t\t10\n+#define TEGRA114_MC_G2SR\t\t11\n+#define TEGRA114_MC_MPEUNIFBR\t\t12\n+#define TEGRA114_MC_VIRUV\t\t13\n+#define TEGRA114_MC_AFIR\t\t14\n+#define TEGRA114_MC_AVPCARM7R\t\t15\n+#define TEGRA114_MC_DISPLAYHC\t\t16\n+#define TEGRA114_MC_DISPLAYHCB\t\t17\n+#define TEGRA114_MC_FDCDRD\t\t18\n+#define TEGRA114_MC_FDCDRD2\t\t19\n+#define TEGRA114_MC_G2DR\t\t20\n+#define TEGRA114_MC_HDAR\t\t21\n+#define TEGRA114_MC_HOST1XDMAR\t\t22\n+#define TEGRA114_MC_HOST1XR\t\t23\n+#define TEGRA114_MC_IDXSRD\t\t24\n+#define TEGRA114_MC_IDXSRD2\t\t25\n+#define TEGRA114_MC_MPE_IPRED\t\t26\n+#define TEGRA114_MC_MPEAMEMRD\t\t27\n+#define TEGRA114_MC_MPECSRD\t\t28\n+#define TEGRA114_MC_PPCSAHBDMAR\t\t29\n+#define TEGRA114_MC_PPCSAHBSLVR\t\t30\n+#define TEGRA114_MC_SATAR\t\t31\n+#define TEGRA114_MC_TEXSRD\t\t32\n+#define TEGRA114_MC_TEXSRD2\t\t33\n+#define TEGRA114_MC_VDEBSEVR\t\t34\n+#define TEGRA114_MC_VDEMBER\t\t35\n+#define TEGRA114_MC_VDEMCER\t\t36\n+#define TEGRA114_MC_VDETPER\t\t37\n+#define TEGRA114_MC_MPCORELPR\t\t38\n+#define TEGRA114_MC_MPCORER\t\t39\n+#define TEGRA114_MC_EPPU\t\t40\n+#define TEGRA114_MC_EPPV\t\t41\n+#define TEGRA114_MC_EPPY\t\t42\n+#define TEGRA114_MC_MPEUNIFBW\t\t43\n+#define TEGRA114_MC_VIWSB\t\t44\n+#define TEGRA114_MC_VIWU\t\t45\n+#define TEGRA114_MC_VIWV\t\t46\n+#define TEGRA114_MC_VIWY\t\t47\n+#define TEGRA114_MC_G2DW\t\t48\n+#define TEGRA114_MC_AFIW\t\t49\n+#define TEGRA114_MC_AVPCARM7W\t\t50\n+#define TEGRA114_MC_FDCDWR\t\t51\n+#define TEGRA114_MC_FDCDWR2\t\t52\n+#define TEGRA114_MC_HDAW\t\t53\n+#define TEGRA114_MC_HOST1XW\t\t54\n+#define TEGRA114_MC_ISPW\t\t55\n+#define TEGRA114_MC_MPCORELPW\t\t56\n+#define TEGRA114_MC_MPCOREW\t\t57\n+#define TEGRA114_MC_MPECSWR\t\t58\n+#define TEGRA114_MC_PPCSAHBDMAW\t\t59\n+#define TEGRA114_MC_PPCSAHBSLVW\t\t60\n+#define TEGRA114_MC_SATAW\t\t61\n+#define TEGRA114_MC_VDEBSEVW\t\t62\n+#define TEGRA114_MC_VDEDBGW\t\t63\n+#define TEGRA114_MC_VDEMBEW\t\t64\n+#define TEGRA114_MC_VDETPMW\t\t65\n+\n #endif\n", "prefixes": [ "v3", "05/11" ] }