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GET /api/patches/2137028/?format=api
{ "id": 2137028, "url": "http://patchwork.ozlabs.org/api/patches/2137028/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250915080157.28195-4-clamor95@gmail.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20250915080157.28195-4-clamor95@gmail.com>", "list_archive_url": null, "date": "2025-09-15T08:01:49", "name": "[v3,03/11] dt-bindings: memory: Document Tegra114 Memory Controller", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "084a9be62d785910281986e46fd630682097b206", "submitter": { "id": 84146, "url": "http://patchwork.ozlabs.org/api/people/84146/?format=api", "name": "Svyatoslav Ryhel", "email": "clamor95@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250915080157.28195-4-clamor95@gmail.com/mbox/", "series": [ { "id": 473641, "url": "http://patchwork.ozlabs.org/api/series/473641/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=473641", "date": "2025-09-15T08:01:46", "name": "Tegra114: implement EMC support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/473641/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2137028/comments/", "check": "success", "checks": "http://patchwork.ozlabs.org/api/patches/2137028/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <devicetree+bounces-217256-incoming-dt=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming-dt@patchwork.ozlabs.org", "devicetree@vger.kernel.org" ], "Delivered-To": "patchwork-incoming-dt@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=EkhM5i9L;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2604:1380:45d1:ec00::1; helo=ny.mirrors.kernel.org;\n envelope-from=devicetree+bounces-217256-incoming-dt=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"EkhM5i9L\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.167.52", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com" ], "Received": [ "from ny.mirrors.kernel.org (ny.mirrors.kernel.org\n [IPv6:2604:1380:45d1:ec00::1])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cQHbF2bCnz1y1Y\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n Mon, 15 Sep 2025 18:03:21 +1000 (AEST)", "from smtp.subspace.kernel.org (relay.kernel.org [52.25.139.140])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ny.mirrors.kernel.org (Postfix) with ESMTPS id 1D0DC17DF67\n\tfor <incoming-dt@patchwork.ozlabs.org>; Mon, 15 Sep 2025 08:03:15 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id E645B2EACE9;\n\tMon, 15 Sep 2025 08:02:29 +0000 (UTC)", "from mail-lf1-f52.google.com (mail-lf1-f52.google.com\n [209.85.167.52])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id AF4E32EAD0B\n\tfor <devicetree@vger.kernel.org>; Mon, 15 Sep 2025 08:02:27 +0000 (UTC)", "by mail-lf1-f52.google.com with SMTP id\n 2adb3069b0e04-5720a18b137so1599394e87.2\n for <devicetree@vger.kernel.org>;\n Mon, 15 Sep 2025 01:02:27 -0700 (PDT)", "from xeon.. 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<jonathanh@nvidia.com>,\n\tPrashant Gaikwad <pgaikwad@nvidia.com>,\n\tMikko Perttunen <mperttunen@nvidia.com>,\n\tMichael Turquette <mturquette@baylibre.com>,\n\tStephen Boyd <sboyd@kernel.org>,\n\tDmitry Osipenko <digetx@gmail.com>,\n\tMyungJoo Ham <myungjoo.ham@samsung.com>,\n\tKyungmin Park <kyungmin.park@samsung.com>,\n\tChanwoo Choi <cw00.choi@samsung.com>,\n\tSvyatoslav Ryhel <clamor95@gmail.com>", "Cc": "linux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org,\n\tlinux-clk@vger.kernel.org,\n\tlinux-pm@vger.kernel.org", "Subject": "[PATCH v3 03/11] dt-bindings: memory: Document Tegra114 Memory\n Controller", "Date": "Mon, 15 Sep 2025 11:01:49 +0300", "Message-ID": "<20250915080157.28195-4-clamor95@gmail.com>", "X-Mailer": "git-send-email 2.48.1", "In-Reply-To": "<20250915080157.28195-1-clamor95@gmail.com>", "References": "<20250915080157.28195-1-clamor95@gmail.com>", "Precedence": "bulk", "X-Mailing-List": "devicetree@vger.kernel.org", "List-Id": "<devicetree.vger.kernel.org>", "List-Subscribe": "<mailto:devicetree+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:devicetree+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Add Tegra114 support into existing Tegra124 MC schema with the most\nnotable difference in the amount of EMEM timings.\n\nSigned-off-by: Svyatoslav Ryhel <clamor95@gmail.com>\n---\n .../nvidia,tegra124-mc.yaml | 97 ++++++++++++++-----\n 1 file changed, 74 insertions(+), 23 deletions(-)", "diff": "diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\nindex 7b18b4d11e0a..9cc9360d3bd0 100644\n--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n@@ -19,7 +19,9 @@ description: |\n \n properties:\n compatible:\n- const: nvidia,tegra124-mc\n+ enum:\n+ - nvidia,tegra114-mc\n+ - nvidia,tegra124-mc\n \n reg:\n maxItems: 1\n@@ -64,29 +66,10 @@ patternProperties:\n \n nvidia,emem-configuration:\n $ref: /schemas/types.yaml#/definitions/uint32-array\n- description: |\n+ description:\n Values to be written to the EMEM register block. See section\n- \"15.6.1 MC Registers\" in the TRM.\n- items:\n- - description: MC_EMEM_ARB_CFG\n- - description: MC_EMEM_ARB_OUTSTANDING_REQ\n- - description: MC_EMEM_ARB_TIMING_RCD\n- - description: MC_EMEM_ARB_TIMING_RP\n- - description: MC_EMEM_ARB_TIMING_RC\n- - description: MC_EMEM_ARB_TIMING_RAS\n- - description: MC_EMEM_ARB_TIMING_FAW\n- - description: MC_EMEM_ARB_TIMING_RRD\n- - description: MC_EMEM_ARB_TIMING_RAP2PRE\n- - description: MC_EMEM_ARB_TIMING_WAP2PRE\n- - description: MC_EMEM_ARB_TIMING_R2R\n- - description: MC_EMEM_ARB_TIMING_W2W\n- - description: MC_EMEM_ARB_TIMING_R2W\n- - description: MC_EMEM_ARB_TIMING_W2R\n- - description: MC_EMEM_ARB_DA_TURNS\n- - description: MC_EMEM_ARB_DA_COVERS\n- - description: MC_EMEM_ARB_MISC0\n- - description: MC_EMEM_ARB_MISC1\n- - description: MC_EMEM_ARB_RING1_THROTTLE\n+ \"20.11.1 MC Registers\" in the Tegea114 TRM or\n+ \"15.6.1 MC Registers\" in the Tegra124 TRM.\n \n required:\n - clock-frequency\n@@ -109,6 +92,74 @@ required:\n - \"#iommu-cells\"\n - \"#interconnect-cells\"\n \n+allOf:\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ enum:\n+ - nvidia,tegra114-mc\n+ then:\n+ patternProperties:\n+ \"^emc-timings-[0-9]+$\":\n+ patternProperties:\n+ \"^timing-[0-9]+$\":\n+ properties:\n+ nvidia,emem-configuration:\n+ items:\n+ - description: MC_EMEM_ARB_CFG\n+ - description: MC_EMEM_ARB_OUTSTANDING_REQ\n+ - description: MC_EMEM_ARB_TIMING_RCD\n+ - description: MC_EMEM_ARB_TIMING_RP\n+ - description: MC_EMEM_ARB_TIMING_RC\n+ - description: MC_EMEM_ARB_TIMING_RAS\n+ - description: MC_EMEM_ARB_TIMING_FAW\n+ - description: MC_EMEM_ARB_TIMING_RRD\n+ - description: MC_EMEM_ARB_TIMING_RAP2PRE\n+ - description: MC_EMEM_ARB_TIMING_WAP2PRE\n+ - description: MC_EMEM_ARB_TIMING_R2R\n+ - description: MC_EMEM_ARB_TIMING_W2W\n+ - description: MC_EMEM_ARB_TIMING_R2W\n+ - description: MC_EMEM_ARB_TIMING_W2R\n+ - description: MC_EMEM_ARB_DA_TURNS\n+ - description: MC_EMEM_ARB_DA_COVERS\n+ - description: MC_EMEM_ARB_MISC0\n+ - description: MC_EMEM_ARB_RING1_THROTTLE\n+\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ enum:\n+ - nvidia,tegra124-mc\n+ then:\n+ patternProperties:\n+ \"^emc-timings-[0-9]+$\":\n+ patternProperties:\n+ \"^timing-[0-9]+$\":\n+ properties:\n+ nvidia,emem-configuration:\n+ items:\n+ - description: MC_EMEM_ARB_CFG\n+ - description: MC_EMEM_ARB_OUTSTANDING_REQ\n+ - description: MC_EMEM_ARB_TIMING_RCD\n+ - description: MC_EMEM_ARB_TIMING_RP\n+ - description: MC_EMEM_ARB_TIMING_RC\n+ - description: MC_EMEM_ARB_TIMING_RAS\n+ - description: MC_EMEM_ARB_TIMING_FAW\n+ - description: MC_EMEM_ARB_TIMING_RRD\n+ - description: MC_EMEM_ARB_TIMING_RAP2PRE\n+ - description: MC_EMEM_ARB_TIMING_WAP2PRE\n+ - description: MC_EMEM_ARB_TIMING_R2R\n+ - description: MC_EMEM_ARB_TIMING_W2W\n+ - description: MC_EMEM_ARB_TIMING_R2W\n+ - description: MC_EMEM_ARB_TIMING_W2R\n+ - description: MC_EMEM_ARB_DA_TURNS\n+ - description: MC_EMEM_ARB_DA_COVERS\n+ - description: MC_EMEM_ARB_MISC0\n+ - description: MC_EMEM_ARB_MISC1\n+ - description: MC_EMEM_ARB_RING1_THROTTLE\n+\n additionalProperties: false\n \n examples:\n", "prefixes": [ "v3", "03/11" ] }