Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2137021/?format=api
{ "id": 2137021, "url": "http://patchwork.ozlabs.org/api/patches/2137021/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20250915080157.28195-7-clamor95@gmail.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20250915080157.28195-7-clamor95@gmail.com>", "list_archive_url": null, "date": "2025-09-15T08:01:52", "name": "[v3,06/11] clk: tegra: remove EMC to MC clock mux in Tegra114", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "e0c0ba3554dd22487563d2ff0cb6101a00ece7bc", "submitter": { "id": 84146, "url": "http://patchwork.ozlabs.org/api/people/84146/?format=api", "name": "Svyatoslav Ryhel", "email": "clamor95@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20250915080157.28195-7-clamor95@gmail.com/mbox/", "series": [ { "id": 473640, "url": "http://patchwork.ozlabs.org/api/series/473640/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=473640", "date": "2025-09-15T08:01:46", "name": "Tegra114: implement EMC support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/473640/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2137021/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2137021/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-9251-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=H0/FzE6s;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2604:1380:45d1:ec00::1; helo=ny.mirrors.kernel.org;\n envelope-from=linux-tegra+bounces-9251-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"H0/FzE6s\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.167.52", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com" ], "Received": [ "from ny.mirrors.kernel.org (ny.mirrors.kernel.org\n [IPv6:2604:1380:45d1:ec00::1])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cQHZP6ghQz1y1p\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 15 Sep 2025 18:02:37 +1000 (AEST)", "from smtp.subspace.kernel.org (relay.kernel.org [52.25.139.140])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ny.mirrors.kernel.org (Postfix) with ESMTPS id AA9D417DBD1\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 15 Sep 2025 08:02:35 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 463712EC576;\n\tMon, 15 Sep 2025 08:02:34 +0000 (UTC)", "from mail-lf1-f52.google.com (mail-lf1-f52.google.com\n [209.85.167.52])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 01CC62EBB8A\n\tfor <linux-tegra@vger.kernel.org>; Mon, 15 Sep 2025 08:02:31 +0000 (UTC)", "by mail-lf1-f52.google.com with SMTP id\n 2adb3069b0e04-55f720ffe34so4393022e87.1\n for <linux-tegra@vger.kernel.org>;\n Mon, 15 Sep 2025 01:02:31 -0700 (PDT)", "from xeon.. ([188.163.112.70])\n by smtp.gmail.com with ESMTPSA id\n 2adb3069b0e04-56e6460dec4sm3392381e87.103.2025.09.15.01.02.28\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 15 Sep 2025 01:02:29 -0700 (PDT)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1757923353; cv=none;\n b=B5REVdmQBPtBbUE/4MvY1VzDaotiJV31Gja7/984+Cdkbv8Z+n4gRlLCRN+7XIIRvgwpcX32foRcRLf+tO27O9xbPtclrd3bYVoXBAuqCr6b7bBIhqlqp8c6H6fa76RKHSV5n1EIQ29kgg71BGhvcGECp+dYN3Os+Au7KdqoNss=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1757923353; c=relaxed/simple;\n\tbh=Gobe3gcacEzjxq3TiZSj8gVH+MTvaW0vF7gQs/h1xFo=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=Xvc2FtKLFRuNIDzARvyYbYRmOSmTCbpYVW2IXOaqLLx6nvwy5wfBbZNE86hHjjBLtA3eHfzBd1NbLU66KcopAcRSSedUx+4EpNQoXr7WYfllQd6K+RMryc/UZldYc2DyM+uoRkJM6F3IZMXKobUXQ8YiWSH4mHgTjqpnFzccfWg=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com;\n spf=pass smtp.mailfrom=gmail.com;\n dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=H0/FzE6s; arc=none smtp.client-ip=209.85.167.52", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20230601; t=1757923350; x=1758528150;\n darn=vger.kernel.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=APj+Tgp0XTk3Jgg5edx6R/2oZ09b0NwwwSYAX8oTvFc=;\n b=H0/FzE6sP7XpqfcsLHeYLJAX9HJasJ6mkQFq7bkji3BAioW4ahioKjZjbjup7vOUBx\n gfEDXBDDw3Ow1HwAscoS0BM5jWzQhaDjDCy9WVamx/O4hpsgnepRPaqEDUdr8yPj1HgI\n 7o8skaG42cawg5Y9BRK+5VTDiEAhGoOfSCIifuqaQ07+pthF+ArmK2TQ+D1pdVOhqFLH\n O8qCzmGpUQAtibD1Fg9kkjbECnqZeJ9KncaCNxPLNQXsC685b5GFkJ20QxbQFHeIQdhQ\n 5C3JKOo09mG7U/bPrWUHYGogX8GwRgHyaW3Gff8ZX9tvwqO/q8Zr+Hx+sOZ446QECORH\n 7SRw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1757923350; x=1758528150;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc\n :subject:date:message-id:reply-to;\n bh=APj+Tgp0XTk3Jgg5edx6R/2oZ09b0NwwwSYAX8oTvFc=;\n b=E6JSJrtdcOEonYDp3IB2YhSxWd9uKd40Nl8DwPxzo9SeTzfQMHGxXH4EGPAr/8nVRJ\n TTqhFysspGfTH62dwhBbG7txW3eZx2q8cAykCJNEcLdvx4E1GCgQiylxIVflae1lDwWD\n a97UQ72XXEmfp+VZV/hMR+CyvbPO94oAP3A8FYpldNwLvyaPMPdSmpR5ZlJ29nRDymVi\n VT+tHmMGp5RqSMe05hXx2L96cXZ6K4eKoLhBJAQw/fmNBovg7sYlQKEgNh1QmfZ8j+K1\n UDYwAzJTL06sSF69GFi3th+5FUnIkLvjuI7JGPUqkFnrSp1voYb8YM3IBFhTQLH3DDPi\n 5kFg==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCUtQK5CZa9IIMZ7+lBfU+8/CYoLVI5l7U62Uefr4nen0dclTFjwPILzRVP+4zxfzSz6jI3cqqKrtG8bIA==@vger.kernel.org", "X-Gm-Message-State": "AOJu0YwbCUcna67JWCHCjhKQkVb9lmX2ycDI7jx6ox9N78W26wCv6BJp\n\tBf/xaHOZzht/21tIH3qjdbY8/a4cPOTWQW/2NKurJPfJ9kwru7E1CGRH", "X-Gm-Gg": "ASbGnctatNngLSC9GQsX3oZ9l4nVdRHiLxPhw3/ow+DEeWpY2RJ0eRf7H7grJs3xvix\n\t4kW+Y+MLLl6KqPOKqbnxoqdxLH2Xm9YR9gcux2XBmmDtvaIZO35/y64rcAPjkHV52HD3Dr8iF5P\n\tpRDykkpka8ScjTtvTChfQHkmW38J3rJ9tiUR6a4vLqlZpHpcl+JoO4cvmPWqSXo6B1E1sEkyq2V\n\tzf+7I+CUf1vpT+aVr5HF1/Bod4OeEh3DT42YOH10PhT72ijY0SUfZGydxUddZv8lszozC7VnSLB\n\tzkmWWn1CLhWRMAIQi4culSOX+sDNEuEYqmLJKjHn5aEnMTtfSJd6LzZabxA8YZyY87IxWeUvASW\n\tLPCAWKZHrjzQBJA==", "X-Google-Smtp-Source": "\n AGHT+IFETlinsBZ9CIzysT7U/mhptSzIvIHcUfuvSzk7UV0WFcZE8DHw3DchmG7FGhfUAhPjJIeVsQ==", "X-Received": "by 2002:a05:6512:ad4:b0:55f:702c:ff1d with SMTP id\n 2adb3069b0e04-570601d3e20mr4030976e87.13.1757923349733;\n Mon, 15 Sep 2025 01:02:29 -0700 (PDT)", "From": "Svyatoslav Ryhel <clamor95@gmail.com>", "To": "Krzysztof Kozlowski <krzk@kernel.org>,\n\tRob Herring <robh@kernel.org>,\n\tConor Dooley <conor+dt@kernel.org>,\n\tThierry Reding <treding@nvidia.com>,\n\tThierry Reding <thierry.reding@gmail.com>,\n\tJonathan Hunter <jonathanh@nvidia.com>,\n\tPrashant Gaikwad <pgaikwad@nvidia.com>,\n\tMikko Perttunen <mperttunen@nvidia.com>,\n\tMichael Turquette <mturquette@baylibre.com>,\n\tStephen Boyd <sboyd@kernel.org>,\n\tDmitry Osipenko <digetx@gmail.com>,\n\tMyungJoo Ham <myungjoo.ham@samsung.com>,\n\tKyungmin Park <kyungmin.park@samsung.com>,\n\tChanwoo Choi <cw00.choi@samsung.com>,\n\tSvyatoslav Ryhel <clamor95@gmail.com>", "Cc": "linux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org,\n\tlinux-clk@vger.kernel.org,\n\tlinux-pm@vger.kernel.org", "Subject": "[PATCH v3 06/11] clk: tegra: remove EMC to MC clock mux in Tegra114", "Date": "Mon, 15 Sep 2025 11:01:52 +0300", "Message-ID": "<20250915080157.28195-7-clamor95@gmail.com>", "X-Mailer": "git-send-email 2.48.1", "In-Reply-To": "<20250915080157.28195-1-clamor95@gmail.com>", "References": "<20250915080157.28195-1-clamor95@gmail.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Configure EMC without mux for correct EMC driver support.\n\nSigned-off-by: Svyatoslav Ryhel <clamor95@gmail.com>\n---\n drivers/clk/tegra/clk-tegra114.c | 48 ++++++++++++++++++++++----------\n 1 file changed, 33 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c\nindex 8bde72aa5e68..6b3a140772c2 100644\n--- a/drivers/clk/tegra/clk-tegra114.c\n+++ b/drivers/clk/tegra/clk-tegra114.c\n@@ -622,10 +622,6 @@ static const char *mux_plld_out0_plld2_out0[] = {\n };\n #define mux_plld_out0_plld2_out0_idx NULL\n \n-static const char *mux_pllmcp_clkm[] = {\n-\t\"pll_m_out0\", \"pll_c_out0\", \"pll_p_out0\", \"clk_m\", \"pll_m_ud\",\n-};\n-\n static const struct clk_div_table pll_re_div_table[] = {\n \t{ .val = 0, .div = 1 },\n \t{ .val = 1, .div = 2 },\n@@ -672,7 +668,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {\n \t[tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },\n \t[tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },\n \t[tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },\n-\t[tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },\n \t[tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },\n \t[tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },\n \t[tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },\n@@ -1048,14 +1043,7 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,\n \t\t\t\t\t 0, 82, periph_clk_enb_refcnt);\n \tclks[TEGRA114_CLK_DSIB] = clk;\n \n-\t/* emc mux */\n-\tclk = clk_register_mux(NULL, \"emc_mux\", mux_pllmcp_clkm,\n-\t\t\t ARRAY_SIZE(mux_pllmcp_clkm),\n-\t\t\t CLK_SET_RATE_NO_REPARENT,\n-\t\t\t clk_base + CLK_SOURCE_EMC,\n-\t\t\t 29, 3, 0, &emc_lock);\n-\n-\tclk = tegra_clk_register_mc(\"mc\", \"emc_mux\", clk_base + CLK_SOURCE_EMC,\n+\tclk = tegra_clk_register_mc(\"mc\", \"emc\", clk_base + CLK_SOURCE_EMC,\n \t\t\t\t &emc_lock);\n \tclks[TEGRA114_CLK_MC] = clk;\n \n@@ -1321,6 +1309,28 @@ static int tegra114_reset_deassert(unsigned long id)\n \treturn 0;\n }\n \n+#ifdef CONFIG_TEGRA124_CLK_EMC\n+static struct clk *tegra114_clk_src_onecell_get(struct of_phandle_args *clkspec,\n+\t\t\t\t\t\tvoid *data)\n+{\n+\tstruct clk_hw *hw;\n+\tstruct clk *clk;\n+\n+\tclk = of_clk_src_onecell_get(clkspec, data);\n+\tif (IS_ERR(clk))\n+\t\treturn clk;\n+\n+\thw = __clk_get_hw(clk);\n+\n+\tif (clkspec->args[0] == TEGRA114_CLK_EMC) {\n+\t\tif (!tegra124_clk_emc_driver_available(hw))\n+\t\t\treturn ERR_PTR(-EPROBE_DEFER);\n+\t}\n+\n+\treturn clk;\n+}\n+#endif\n+\n static void __init tegra114_clock_init(struct device_node *np)\n {\n \tstruct device_node *node;\n@@ -1362,16 +1372,24 @@ static void __init tegra114_clock_init(struct device_node *np)\n \ttegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,\n \t\t\t tegra114_audio_plls,\n \t\t\t ARRAY_SIZE(tegra114_audio_plls), 24000000);\n+\n+\ttegra_clk_apply_init_table = tegra114_clock_apply_init_table;\n+\n \ttegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,\n \t\t\t\t\t&pll_x_params);\n \n \ttegra_init_special_resets(1, tegra114_reset_assert,\n \t\t\t\t tegra114_reset_deassert);\n \n+#ifdef CONFIG_TEGRA124_CLK_EMC\n+\ttegra_add_of_provider(np, tegra114_clk_src_onecell_get);\n+\tclks[TEGRA114_CLK_EMC] = tegra124_clk_register_emc(clk_base, np,\n+\t\t\t\t\t\t\t &emc_lock);\n+#else\n \ttegra_add_of_provider(np, of_clk_src_onecell_get);\n-\ttegra_register_devclks(devclks, ARRAY_SIZE(devclks));\n+#endif\n \n-\ttegra_clk_apply_init_table = tegra114_clock_apply_init_table;\n+\ttegra_register_devclks(devclks, ARRAY_SIZE(devclks));\n \n \ttegra_cpu_car_ops = &tegra114_cpu_car_ops;\n }\n", "prefixes": [ "v3", "06/11" ] }