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GET /api/patches/2132483/?format=api
{ "id": 2132483, "url": "http://patchwork.ozlabs.org/api/patches/2132483/?format=api", "web_url": "http://patchwork.ozlabs.org/project/ubuntu-kernel/patch/d6fa0f745f7876ebe2d71b239f25cb11c4e9ab1c.1756973061.git.massimiliano.pellizzer@canonical.com/", "project": { "id": 15, "url": "http://patchwork.ozlabs.org/api/projects/15/?format=api", "name": "Ubuntu Kernel", "link_name": "ubuntu-kernel", "list_id": "kernel-team.lists.ubuntu.com", "list_email": "kernel-team@lists.ubuntu.com", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<d6fa0f745f7876ebe2d71b239f25cb11c4e9ab1c.1756973061.git.massimiliano.pellizzer@canonical.com>", "list_archive_url": null, "date": "2025-09-04T08:11:34", "name": "[SRU,J,09/12] perf list: fix short description for some cache events", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "78bb04b9ed6bccee4179c9baf0e11142c2a66dbf", "submitter": { "id": 89057, "url": "http://patchwork.ozlabs.org/api/people/89057/?format=api", "name": "Massimiliano Pellizzer", "email": "massimiliano.pellizzer@canonical.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/ubuntu-kernel/patch/d6fa0f745f7876ebe2d71b239f25cb11c4e9ab1c.1756973061.git.massimiliano.pellizzer@canonical.com/mbox/", "series": [ { "id": 472179, "url": "http://patchwork.ozlabs.org/api/series/472179/?format=api", "web_url": "http://patchwork.ozlabs.org/project/ubuntu-kernel/list/?series=472179", "date": "2025-09-04T08:11:25", "name": "CPU-MF Counters for new IBM Z hardware - perf part (LP: #2103415)", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/472179/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2132483/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2132483/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<kernel-team-bounces@lists.ubuntu.com>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ubuntu.com\n (client-ip=185.125.189.65; helo=lists.ubuntu.com;\n envelope-from=kernel-team-bounces@lists.ubuntu.com;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.ubuntu.com (lists.ubuntu.com [185.125.189.65])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cHXL508QTz1y0M\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 4 Sep 2025 18:13:33 +1000 (AEST)", "from localhost ([127.0.0.1] helo=lists.ubuntu.com)\n\tby lists.ubuntu.com with esmtp (Exim 4.86_2)\n\t(envelope-from <kernel-team-bounces@lists.ubuntu.com>)\n\tid 1uu55x-0002oj-6P; Thu, 04 Sep 2025 08:13:25 +0000", "from smtp-relay-internal-1.internal ([10.131.114.114]\n helo=smtp-relay-internal-1.canonical.com)\n by lists.ubuntu.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.86_2) (envelope-from <massimiliano.pellizzer@canonical.com>)\n id 1uu55a-0001hP-Np\n for kernel-team@lists.ubuntu.com; Thu, 04 Sep 2025 08:13:02 +0000", "from mail-ej1-f69.google.com (mail-ej1-f69.google.com\n [209.85.218.69])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id 678063F6FD\n for <kernel-team@lists.ubuntu.com>; Thu, 4 Sep 2025 08:13:01 +0000 (UTC)", "by mail-ej1-f69.google.com with SMTP id\n a640c23a62f3a-afe6216085aso56127566b.1\n for <kernel-team@lists.ubuntu.com>; Thu, 04 Sep 2025 01:13:01 -0700 (PDT)", "from framework-canonical.lan\n (net-31-156-181-205.cust.vodafonedsl.it. [31.156.181.205])\n by smtp.gmail.com with ESMTPSA id\n a640c23a62f3a-b041565ca98sm1131743766b.86.2025.09.04.01.12.59\n for <kernel-team@lists.ubuntu.com>\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 04 Sep 2025 01:12:59 -0700 (PDT)" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1756973580; x=1757578380;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-message-state:from:to:cc\n :subject:date:message-id:reply-to;\n bh=2HSGpzZ/8JGwZUD0pR9iALwFtQxsQk1v2UPohFSItSk=;\n b=KGOKFjdYAnCfk3J+l0zYGJHmsDBgrIBEN/G0/rqy3+0Nzr6GqGwBPyZPtsESTFwJxu\n cZbiB7EUfJOahNY6RhHuATulR0TXBU+Qx4cqy0b/cQBTYeYYcyJjGvKK2Mjdm3sLpB7E\n lJeRKfb+nyOb4m7RHTt96WZnaMX5WvyLM+itMWmwEiVXfQD/lpnsyo8e8Z05lx/aT4zY\n 2etNy893RnCadrnjuXwUeao+MhOLvlCqzEEwdndFMuogfGOCp9ms9wvXvcWsJ0mQY3dg\n CnY27Im2VvpxWz8Rr4csBGa23zj7XFZKxIcjJLJkEVZFVyzo9MA+NmalDMCqXoHyny9Y\n 0t5A==", "X-Gm-Message-State": "AOJu0Yzdwi30c0YkjeJEnP4KLRamvs2BwOu4TiRowJyHltz0YgRB/WJg\n DRjgMnK9mgJpnyNV63r2IsPGWI/saqTuNKMavn647LIE+CtOahUzRVBN7T76sDoVnv2gzMshsvP\n Jl46BaOp+meiULpJrvG/oY2OUnhK1XvemqbzMNDtOjEfbbyfBxvPpqZXF44KKlsQurdny54Zxyo\n JeuK3cqYs9E/sPCQ==", "X-Gm-Gg": "ASbGncs6HVd4+0TbSxZmf5no35vLOEHsg3b0Br+xSYmpp+XSOVhM8IpdgVYdL5Z8J4u\n za0o+0ZaVdjTaQw855JJ3FaAEj97EWcY9vwzH3vg2jIlulCprCiLMRUGu4ph88h5BVu2MwloEua\n 1XEaGAYnZn2K//VB76voGcAUgXN73CIW5EgA+bpNGzEcwYWdFE5b6ShqknSW+C5NIo6cmKW2ofo\n II0i+weUYFfnQbIXPT1degwEy2ZZHJkiY4xYnhuJP9P9iFC4O+lgsB5lC8c7S26nZ8zWZywpGt3\n gwJ+nWqzRYf1PL+BgNkVBUVurV57Wk/UlrWuF41ZQCNdOVtmHam+ngPTU1H2kJVry+IbugyhfV8\n fjNcCLPoUhniswuI8bkEGbObl68XH5fVcnkJ1hOkepL6b", "X-Received": [ "by 2002:a17:907:724c:b0:afe:764d:6b22 with SMTP id\n a640c23a62f3a-b01d8a32756mr1556636666b.9.1756973580232;\n Thu, 04 Sep 2025 01:13:00 -0700 (PDT)", "by 2002:a17:907:724c:b0:afe:764d:6b22 with SMTP id\n a640c23a62f3a-b01d8a32756mr1556633766b.9.1756973579713;\n Thu, 04 Sep 2025 01:12:59 -0700 (PDT)" ], "X-Google-Smtp-Source": "\n AGHT+IF53qlZq+gyJkTLVzZPm2kmaqCOtF6A9hbb6ge4wWKZ0xO/1u9HRsDHOCpIW1M1Tv4C5uy3hw==", "From": "Massimiliano Pellizzer <massimiliano.pellizzer@canonical.com>", "To": "kernel-team@lists.ubuntu.com", "Subject": "[SRU][J][PATCH 09/12] perf list: fix short description for some cache\n events", "Date": "Thu, 4 Sep 2025 10:11:34 +0200", "Message-ID": "\n <d6fa0f745f7876ebe2d71b239f25cb11c4e9ab1c.1756973061.git.massimiliano.pellizzer@canonical.com>", "X-Mailer": "git-send-email 2.48.1", "In-Reply-To": "<cover.1756973061.git.massimiliano.pellizzer@canonical.com>", "References": "\n <175697071248.21594.2440727989420834998@framework-canonical.public>\n <cover.1756973061.git.massimiliano.pellizzer@canonical.com>", "MIME-Version": "1.0", "X-BeenThere": "kernel-team@lists.ubuntu.com", "X-Mailman-Version": "2.1.20", "Precedence": "list", "List-Id": "Kernel team discussions <kernel-team.lists.ubuntu.com>", "List-Unsubscribe": "<https://lists.ubuntu.com/mailman/options/kernel-team>,\n <mailto:kernel-team-request@lists.ubuntu.com?subject=unsubscribe>", "List-Archive": "<https://lists.ubuntu.com/archives/kernel-team>", "List-Post": "<mailto:kernel-team@lists.ubuntu.com>", "List-Help": "<mailto:kernel-team-request@lists.ubuntu.com?subject=help>", "List-Subscribe": "<https://lists.ubuntu.com/mailman/listinfo/kernel-team>,\n <mailto:kernel-team-request@lists.ubuntu.com?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "kernel-team-bounces@lists.ubuntu.com", "Sender": "\"kernel-team\" <kernel-team-bounces@lists.ubuntu.com>" }, "content": "From: Thomas Richter <tmricht@linux.ibm.com>\n\nBugLink: https://bugs.launchpad.net/bugs/2103415\n\nCorrect the short description of the following events:\nDCW_REQ, DCW_REQ_CHIP_HIT, DCW_REQ_DRAWER_HIT, DCW_REQ_IV,\nDCW_ON_CHIP, DCW_ON_CHIP_IV, DCW_ON_CHIP_CHIP_HIT,\nDCW_ON_CHIP_DRAWER_HIT, CW_ON_MODULE, DCW_ON_DRAWER,\nDCW_OFF_DRAWER, IDCW_ON_MODULE_IV, IDCW_ON_MODULE_CHIP_HIT,\nIDCW_ON_MODULE_DRAWER_HIT, IDCW_ON_DRAWER_IV, IDCW_ON_DRAWER_CHIP_HIT,\nIDCW_ON_DRAWER_DRAWER_HIT, IDCW_OFF_DRAWER_IV, IDCW_OFF_DRAWER_CHIP_HIT,\nIDCW_OFF_DRAWER_DRAWER_HIT, ICW_REQ, ICW_REQ_IV, CW_REQ_CHIP_HIT,\nICW_REQ_DRAWER_HIT, ICW_ON_CHIP, ICW_ON_CHIP_IV, ICW_ON_CHIP_CHIP_HIT,\nICW_ON_CHIP_DRAWER_HIT, ICW_ON_MODULE and ICW_OFF_DRAWER.\n\nThe second Cache should be L2-Cache.\n\nOutput before (display diff of the first four events)\n # perf list -d\n DCW_REQ\n [Directory Write Level 1 Data Cache from Cache. Unit: cpum_cf]\n DCW_REQ_CHIP_HIT\n [Directory Write Level 1 Data Cache from Cache with Chip HP \\\n\t Hit. Unit: cpum_cf]\n DCW_REQ_DRAWER_HIT\n [Directory Write Level 1 Data Cache from Cache with Drawer \\\n\t HP Hit. Unit: cpum_cf]\n DCW_REQ_IV\n [Directory Write Level 1 Data Cache from Cache with Intervention. \\\n\t Unit: cpum_cf]\n\nOutput after:\n # perf list -d\n DCW_REQ\n [Directory Write Level 1 Data Cache from L2-Cache. Unit: cpum_cf]\n DCW_REQ_CHIP_HIT\n [Directory Write Level 1 Data Cache from L2-Cache with Chip HP \\\n\t Hit. Unit: cpum_cf]\n DCW_REQ_DRAWER_HIT\n [Directory Write Level 1 Data Cache from L2-Cache with Drawer \\\n\t HP Hit. Unit: cpum_cf]\n DCW_REQ_IV\n [Directory Write Level 1 Data Cache from L2-Cache with \\\n\t Intervention. Unit: cpum_cf]\n\nFixes: 7f76b3113068 (\"perf list: Add IBM z16 event description for s390\")\nReported-by: Andreas Krebbel <krebbel@linux.ibm.com>\nSigned-off-by: Thomas Richter <tmricht@linux.ibm.com>\nAcked-by: Andreas Krebbel <krebbel@linux.ibm.com>\nReviewed-by: Ian Rogers <irogers@google.com>\nCc: gor@linux.ibm.com\nCc: hca@linux.ibm.com\nCc: sumanthk@linux.ibm.com\nCc: svens@linux.ibm.com\nSigned-off-by: Namhyung Kim <namhyung@kernel.org>\nLink: https://lore.kernel.org/r/20240221091908.1759083-1-tmricht@linux.ibm.com\n(cherry picked from commit b6968f9b5035e8e5a74a83209853f274345c74a2)\nSigned-off-by: Massimiliano Pellizzer <massimiliano.pellizzer@canonical.com>\n---\n .../pmu-events/arch/s390/cf_z16/extended.json | 62 +++++++++----------\n 1 file changed, 31 insertions(+), 31 deletions(-)", "diff": "diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/extended.json b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json\nindex c2b10ec1c6e0..02cce3a629cb 100644\n--- a/tools/perf/pmu-events/arch/s390/cf_z16/extended.json\n+++ b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json\n@@ -94,77 +94,77 @@\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"145\",\n \t\t\"EventName\": \"DCW_REQ\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from Cache\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from L2-Cache\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"146\",\n \t\t\"EventName\": \"DCW_REQ_IV\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from Cache with Intervention\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from L2-Cache with Intervention\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"147\",\n \t\t\"EventName\": \"DCW_REQ_CHIP_HIT\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from Cache with Chip HP Hit\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from L2-Cache with Chip HP Hit\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"148\",\n \t\t\"EventName\": \"DCW_REQ_DRAWER_HIT\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from Cache with Drawer HP Hit\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from L2-Cache with Drawer HP Hit\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"149\",\n \t\t\"EventName\": \"DCW_ON_CHIP\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Chip Cache\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Chip L2-Cache\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"150\",\n \t\t\"EventName\": \"DCW_ON_CHIP_IV\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Chip Cache with Intervention\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Chip L2-Cache with Intervention\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache with intervention.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"151\",\n \t\t\"EventName\": \"DCW_ON_CHIP_CHIP_HIT\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Chip Cache with Chip HP Hit\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Chip L2-Cache with Chip HP Hit\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"152\",\n \t\t\"EventName\": \"DCW_ON_CHIP_DRAWER_HIT\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Chip Cache with Drawer HP Hit\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Chip L2-Cache with Drawer HP Hit\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using drawer level horizontal persistence, Drawer-HP hit.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"153\",\n \t\t\"EventName\": \"DCW_ON_MODULE\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Module Cache\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Module L2-Cache\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Module Level-2 cache.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"154\",\n \t\t\"EventName\": \"DCW_ON_DRAWER\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Drawer Cache\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Drawer L2-Cache\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"155\",\n \t\t\"EventName\": \"DCW_OFF_DRAWER\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from Off-Drawer Cache\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from Off-Drawer L2-Cache\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache.\"\n \t},\n \t{\n@@ -199,140 +199,140 @@\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"160\",\n \t\t\"EventName\": \"IDCW_ON_MODULE_IV\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Intervention\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Intervention\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache with intervention.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"161\",\n \t\t\"EventName\": \"IDCW_ON_MODULE_CHIP_HIT\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Chip Hit\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Chip Hit\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using chip horizontal persistence, Chip-HP hit.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"162\",\n \t\t\"EventName\": \"IDCW_ON_MODULE_DRAWER_HIT\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Drawer Hit\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Drawer Hit\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using drawer level horizontal persistence, Drawer-HP hit.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"163\",\n \t\t\"EventName\": \"IDCW_ON_DRAWER_IV\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Intervention\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Intervention\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache with intervention.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"164\",\n \t\t\"EventName\": \"IDCW_ON_DRAWER_CHIP_HIT\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Chip Hit\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Chip Hit\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"165\",\n \t\t\"EventName\": \"IDCW_ON_DRAWER_DRAWER_HIT\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Drawer Hit\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Drawer Hit\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"166\",\n \t\t\"EventName\": \"IDCW_OFF_DRAWER_IV\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Intervention\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Intervention\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache with intervention.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"167\",\n \t\t\"EventName\": \"IDCW_OFF_DRAWER_CHIP_HIT\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Chip Hit\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Chip Hit\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"168\",\n \t\t\"EventName\": \"IDCW_OFF_DRAWER_DRAWER_HIT\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Drawer Hit\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Drawer Hit\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"169\",\n \t\t\"EventName\": \"ICW_REQ\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from Cache\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from L2-Cache\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced the requestors Level-2 cache.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"170\",\n \t\t\"EventName\": \"ICW_REQ_IV\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from Cache with Intervention\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from L2-Cache with Intervention\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"171\",\n \t\t\"EventName\": \"ICW_REQ_CHIP_HIT\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from Cache with Chip HP Hit\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from L2-Cache with Chip HP Hit\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using chip level horizontal persistence, Chip-HP hit.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"172\",\n \t\t\"EventName\": \"ICW_REQ_DRAWER_HIT\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from Cache with Drawer HP Hit\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from L2-Cache with Drawer HP Hit\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using drawer level horizontal persistence, Drawer-HP hit.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"173\",\n \t\t\"EventName\": \"ICW_ON_CHIP\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Chip Cache\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Chip L2-Cache\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"174\",\n \t\t\"EventName\": \"ICW_ON_CHIP_IV\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Chip Cache with Intervention\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Intervention\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Chip Level-2 cache with intervention.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"175\",\n \t\t\"EventName\": \"ICW_ON_CHIP_CHIP_HIT\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Chip Cache with Chip HP Hit\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Chip HP Hit\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using chip level horizontal persistence, Chip-HP hit.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"176\",\n \t\t\"EventName\": \"ICW_ON_CHIP_DRAWER_HIT\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Chip Cache with Drawer HP Hit\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Drawer HP Hit\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip level 2 cache using drawer level horizontal persistence, Drawer-HP hit.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"177\",\n \t\t\"EventName\": \"ICW_ON_MODULE\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Module Cache\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Module L2-Cache\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"178\",\n \t\t\"EventName\": \"ICW_ON_DRAWER\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Drawer Cache\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Drawer L2-Cache\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Drawer Level-2 cache.\"\n \t},\n \t{\n \t\t\"Unit\": \"CPU-M-CF\",\n \t\t\"EventCode\": \"179\",\n \t\t\"EventName\": \"ICW_OFF_DRAWER\",\n-\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from Off-Drawer Cache\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from Off-Drawer L2-Cache\",\n \t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an Off-Drawer Level-2 cache.\"\n \t},\n \t{\n", "prefixes": [ "SRU", "J", "09/12" ] }