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GET /api/patches/2132478/?format=api
{ "id": 2132478, "url": "http://patchwork.ozlabs.org/api/patches/2132478/?format=api", "web_url": "http://patchwork.ozlabs.org/project/ubuntu-kernel/patch/283c18ac1bfcfaa511e3c0b8910a3a46be85bb67.1756973061.git.massimiliano.pellizzer@canonical.com/", "project": { "id": 15, "url": "http://patchwork.ozlabs.org/api/projects/15/?format=api", "name": "Ubuntu Kernel", "link_name": "ubuntu-kernel", "list_id": "kernel-team.lists.ubuntu.com", "list_email": "kernel-team@lists.ubuntu.com", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<283c18ac1bfcfaa511e3c0b8910a3a46be85bb67.1756973061.git.massimiliano.pellizzer@canonical.com>", "list_archive_url": null, "date": "2025-09-04T08:11:32", "name": "[SRU,J,07/12] perf vendor events s390: Add metric for TLB and cache", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7bb016f3cc47873162e35076cf973dfe26a68369", "submitter": { "id": 89057, "url": "http://patchwork.ozlabs.org/api/people/89057/?format=api", "name": "Massimiliano Pellizzer", "email": "massimiliano.pellizzer@canonical.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/ubuntu-kernel/patch/283c18ac1bfcfaa511e3c0b8910a3a46be85bb67.1756973061.git.massimiliano.pellizzer@canonical.com/mbox/", "series": [ { "id": 472179, "url": "http://patchwork.ozlabs.org/api/series/472179/?format=api", "web_url": "http://patchwork.ozlabs.org/project/ubuntu-kernel/list/?series=472179", "date": "2025-09-04T08:11:25", "name": "CPU-MF Counters for new IBM Z hardware - perf part (LP: #2103415)", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/472179/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2132478/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2132478/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<kernel-team-bounces@lists.ubuntu.com>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ubuntu.com\n (client-ip=185.125.189.65; helo=lists.ubuntu.com;\n envelope-from=kernel-team-bounces@lists.ubuntu.com;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.ubuntu.com (lists.ubuntu.com [185.125.189.65])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cHXKy4fJ0z1y1P\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 4 Sep 2025 18:13:26 +1000 (AEST)", "from localhost ([127.0.0.1] helo=lists.ubuntu.com)\n\tby lists.ubuntu.com with esmtp (Exim 4.86_2)\n\t(envelope-from <kernel-team-bounces@lists.ubuntu.com>)\n\tid 1uu55q-0002PY-0O; Thu, 04 Sep 2025 08:13:18 +0000", "from smtp-relay-internal-0.internal ([10.131.114.225]\n helo=smtp-relay-internal-0.canonical.com)\n by lists.ubuntu.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.86_2) (envelope-from <massimiliano.pellizzer@canonical.com>)\n id 1uu55a-0001bv-Ff\n for kernel-team@lists.ubuntu.com; Thu, 04 Sep 2025 08:13:02 +0000", "from mail-ej1-f72.google.com (mail-ej1-f72.google.com\n [209.85.218.72])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id D76663F657\n for <kernel-team@lists.ubuntu.com>; Thu, 4 Sep 2025 08:12:59 +0000 (UTC)", "by mail-ej1-f72.google.com with SMTP id\n a640c23a62f3a-afe81959e5cso67957866b.1\n for <kernel-team@lists.ubuntu.com>; Thu, 04 Sep 2025 01:12:59 -0700 (PDT)", "from framework-canonical.lan\n (net-31-156-181-205.cust.vodafonedsl.it. [31.156.181.205])\n by smtp.gmail.com with ESMTPSA id\n a640c23a62f3a-b041565ca98sm1131743766b.86.2025.09.04.01.12.57\n for <kernel-team@lists.ubuntu.com>\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 04 Sep 2025 01:12:57 -0700 (PDT)" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1756973579; x=1757578379;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-message-state:from:to:cc\n :subject:date:message-id:reply-to;\n bh=nFJQVLXEPgQDBe6uqcZX6+MYdtnVtP7GgcQssAKYQYE=;\n b=IZ46dPNGdsvkg7cYmqoeCdaeQNe+3BJumZDNgE2Ic0Ijgu7BlEGBqsfCeDhu0ItKqp\n oqTSvU9bKs1blzY8ctTP0x4vKjclhDB4TQ7Atyxfs3ZpPTxKm8wToig01LIPfp2oJzr+\n boVA/NHpndJ7C3Y+o93VeJusVTPDwU/xRvN5r1c88/gkq7N7nh0vZZYfYoLDMpQXVBNN\n uDpz0Eiu9bev0nr0TaaIFFjM0mxWOpND3uBUvKJ3gFWPNdb2aJvv+tLF0y6oLU9bGG8x\n 1WEb1l+ts/VRoaePpPBkkTj3xCrJ5pMz8ZwIUISDVhnLauRdvnS5FS2qFosrPNXXdlYD\n wXHg==", "X-Gm-Message-State": "AOJu0Yyjlj81fImGFSp7+dTE931PTtmF32MG84bBePh8d0tHPwxvWWc4\n tum7oEVwuMMys31WQnmpoFO8v3M7rg3XN2OKfchHPDC8WIPtpCyBBXVm0hnqrFhGbldI+70+7Bl\n mVgQifHofo6S+N0/ud+6DixNpNwxhmJvSlYjYCoEavX9JYPcNonnwtaCDE3XH1AMIj4cuTdxAgx\n JGLXVycy7h7S9paQ==", "X-Gm-Gg": "ASbGncuEG8SJbtrZl4OChYZSudK8bgT4Efoa8+eiC9L0RqHXlNRtPdrvlJQEM4PHhY4\n Q9yTPUu/vDTPB4kpF//mysAL6gpJJS3TpG4SN0hy5R12jc6wjPqpdq1kIyOFX6RqJSDqOneeFPw\n ebRZqZl2obimGlSeK1NQnEgvn0Ti28ROtGq7RCo1oOAJXlpn4S5ePp2OghyOIBQYuzb86Vfdeld\n u9lJWRWTHhpF51UsszpmJzzi+O+mTLZNDJ89xfMem7u7+0Qfxj6SbN8UdQEGHh6XJOv0mn30IGq\n F4q3cmnRqLKTqOcanH5TRi/Y1xkOM5nphpGq/Xsb6oMcY16Wp+jg6aSfjRqOYRR1K4PsZ6X6/fe\n EC/Ffe4Q/ZtnkRX9Zd+P7Vxzm3xZPv8L0+SkqaPqXmWT7", "X-Received": [ "by 2002:a17:907:9409:b0:b04:74d1:a575 with SMTP id\n a640c23a62f3a-b0474d1b166mr386999566b.62.1756973578727;\n Thu, 04 Sep 2025 01:12:58 -0700 (PDT)", "by 2002:a17:907:9409:b0:b04:74d1:a575 with SMTP id\n a640c23a62f3a-b0474d1b166mr386995366b.62.1756973578142;\n Thu, 04 Sep 2025 01:12:58 -0700 (PDT)" ], "X-Google-Smtp-Source": "\n AGHT+IGChoCY5snf87Rv4Ja6c45Mt88v1xhRyqGFbsd/uHTjeL5ivgEvd59KMo3EiHQJ8o+Ffjkisw==", "From": "Massimiliano Pellizzer <massimiliano.pellizzer@canonical.com>", "To": "kernel-team@lists.ubuntu.com", "Subject": "[SRU][J][PATCH 07/12] perf vendor events s390: Add metric for TLB and\n cache", "Date": "Thu, 4 Sep 2025 10:11:32 +0200", "Message-ID": "\n <283c18ac1bfcfaa511e3c0b8910a3a46be85bb67.1756973061.git.massimiliano.pellizzer@canonical.com>", "X-Mailer": "git-send-email 2.48.1", "In-Reply-To": "<cover.1756973061.git.massimiliano.pellizzer@canonical.com>", "References": "\n <175697071248.21594.2440727989420834998@framework-canonical.public>\n <cover.1756973061.git.massimiliano.pellizzer@canonical.com>", "MIME-Version": "1.0", "X-BeenThere": "kernel-team@lists.ubuntu.com", "X-Mailman-Version": "2.1.20", "Precedence": "list", "List-Id": "Kernel team discussions <kernel-team.lists.ubuntu.com>", "List-Unsubscribe": "<https://lists.ubuntu.com/mailman/options/kernel-team>,\n <mailto:kernel-team-request@lists.ubuntu.com?subject=unsubscribe>", "List-Archive": "<https://lists.ubuntu.com/archives/kernel-team>", "List-Post": "<mailto:kernel-team@lists.ubuntu.com>", "List-Help": "<mailto:kernel-team-request@lists.ubuntu.com?subject=help>", "List-Subscribe": "<https://lists.ubuntu.com/mailman/listinfo/kernel-team>,\n <mailto:kernel-team-request@lists.ubuntu.com?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "kernel-team-bounces@lists.ubuntu.com", "Sender": "\"kernel-team\" <kernel-team-bounces@lists.ubuntu.com>" }, "content": "From: Thomas Richter <tmricht@linux.ibm.com>\n\nBugLink: https://bugs.launchpad.net/bugs/2103415\n\nAdd metrics for tlb and cache statistics:\n\n- finite_cpi: Cycles per Instructions from Finite cache/memory\n- est_cpi: Estimated Instruction Complexity CPI infinite Level 1\n- scpl1m: Estimated Sourcing Cycles per Level 1 Miss\n- tlb_percent: Estimated TLB CPU percentage of Total CPU\n- tlb_miss: Estimated Cycles per TLB Miss\n\nFor details about the formulas see this documentation:\n\n https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf\n\nOutput after:\n\n # ./perf stat -M tlb_miss -- dd if=/dev/zero of=/dev/null bs=1M count=10K\n ... dd output removed\n\n Performance counter stats for 'dd if=/dev/zero of=/dev/null bs=1M count=10K':\n\n 667,726 DTLB2_MISSES # 440.96 tlb_miss\n 198 ITLB2_WRITES\n 795,170,260 L1C_TLB2_MISSES\n 9,478 ITLB2_MISSES\n 820 DTLB2_WRITES\n 1,197,126,869 L1D_PENALTY_CYCLES\n 2,457,447 L1I_PENALTY_CYCLES\n\n 1.249342187 seconds time elapsed\n\n 0.001030000 seconds user\n 1.248105000 seconds sys\n\n #\n\nSigned-off-by: Thomas Richter <tmricht@linux.ibm.com>\nAcked-by: Ian Rogers <irogers@google.com>\nAcked-By: Sumanth Korikkar <sumanthk@linux.ibm.com>\nCc: Heiko Carstens <hca@linux.ibm.com>\nCc: Sven Schnelle <svens@linux.ibm.com>\nCc: Vasily Gorbik <gor@linux.ibm.com>\nLink: https://lore.kernel.org/r/20230313080201.2440201-3-tmricht@linux.ibm.com\nSigned-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>\n(cherry picked from commit 4c290d4fa3aeed74e37637acaa1a787f194fe43d)\nSigned-off-by: Massimiliano Pellizzer <massimiliano.pellizzer@canonical.com>\n---\n .../arch/s390/cf_z13/transaction.json | 30 +++++++++++++++++++\n .../arch/s390/cf_z14/transaction.json | 25 ++++++++++++++++\n .../arch/s390/cf_z15/transaction.json | 25 ++++++++++++++++\n .../arch/s390/cf_z16/transaction.json | 25 ++++++++++++++++\n 4 files changed, 105 insertions(+)", "diff": "diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json\nindex 71e2c7fa734c..b941a7212a4d 100644\n--- a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json\n+++ b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json\n@@ -43,5 +43,35 @@\n \"BriefDescription\": \"Percentage sourced from memory\",\n \"MetricName\": \"memp\",\n \"MetricExpr\": \"((L1D_ONNODE_MEM_SOURCED_WRITES + L1D_ONDRAWER_MEM_SOURCED_WRITES + L1D_OFFDRAWER_MEM_SOURCED_WRITES + L1D_ONCHIP_MEM_SOURCED_WRITES + L1I_ONNODE_MEM_SOURCED_WRITES + L1I_ONDRAWER_MEM_SOURCED_WRITES + L1I_OFFDRAWER_MEM_SOURCED_WRITES + L1I_ONCHIP_MEM_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Cycles per Instructions from Finite cache/memory\",\n+ \"MetricName\": \"finite_cpi\",\n+ \"MetricExpr\": \"L1C_TLB1_MISSES / INSTRUCTIONS\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Instruction Complexity CPI infinite Level 1\",\n+ \"MetricName\": \"est_cpi\",\n+ \"MetricExpr\": \"(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB1_MISSES / INSTRUCTIONS)\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Sourcing Cycles per Level 1 Miss\",\n+ \"MetricName\": \"scpl1m\",\n+ \"MetricExpr\": \"L1C_TLB1_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated TLB CPU percentage of Total CPU\",\n+ \"MetricName\": \"tlb_percent\",\n+ \"MetricExpr\": \"((DTLB1_MISSES + ITLB1_MISSES) / CPU_CYCLES) * (L1C_TLB1_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Cycles per TLB Miss\",\n+ \"MetricName\": \"tlb_miss\",\n+ \"MetricExpr\": \"((DTLB1_MISSES + ITLB1_MISSES) / (DTLB1_WRITES + ITLB1_WRITES)) * (L1C_TLB1_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))\"\n+ },\n+ {\n+ \"BriefDescription\": \"Page Table Entry misses\",\n+ \"MetricName\": \"pte_miss\",\n+ \"MetricExpr\": \"(TLB2_PTE_WRITES / (DTLB1_WRITES + ITLB1_WRITES)) * 100\"\n }\n ]\ndiff --git a/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json\nindex cca237bdb7ba..ce814ea93396 100644\n--- a/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json\n+++ b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json\n@@ -43,5 +43,30 @@\n \"BriefDescription\": \"Percentage sourced from memory\",\n \"MetricName\": \"memp\",\n \"MetricExpr\": \"((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Cycles per Instructions from Finite cache/memory\",\n+ \"MetricName\": \"finite_cpi\",\n+ \"MetricExpr\": \"L1C_TLB2_MISSES / INSTRUCTIONS\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Instruction Complexity CPI infinite Level 1\",\n+ \"MetricName\": \"est_cpi\",\n+ \"MetricExpr\": \"(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Sourcing Cycles per Level 1 Miss\",\n+ \"MetricName\": \"scpl1m\",\n+ \"MetricExpr\": \"L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated TLB CPU percentage of Total CPU\",\n+ \"MetricName\": \"tlb_percent\",\n+ \"MetricExpr\": \"((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Cycles per TLB Miss\",\n+ \"MetricName\": \"tlb_miss\",\n+ \"MetricExpr\": \"((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))\"\n }\n ]\ndiff --git a/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json\nindex cca237bdb7ba..ce814ea93396 100644\n--- a/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json\n+++ b/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json\n@@ -43,5 +43,30 @@\n \"BriefDescription\": \"Percentage sourced from memory\",\n \"MetricName\": \"memp\",\n \"MetricExpr\": \"((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Cycles per Instructions from Finite cache/memory\",\n+ \"MetricName\": \"finite_cpi\",\n+ \"MetricExpr\": \"L1C_TLB2_MISSES / INSTRUCTIONS\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Instruction Complexity CPI infinite Level 1\",\n+ \"MetricName\": \"est_cpi\",\n+ \"MetricExpr\": \"(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Sourcing Cycles per Level 1 Miss\",\n+ \"MetricName\": \"scpl1m\",\n+ \"MetricExpr\": \"L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated TLB CPU percentage of Total CPU\",\n+ \"MetricName\": \"tlb_percent\",\n+ \"MetricExpr\": \"((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Cycles per TLB Miss\",\n+ \"MetricName\": \"tlb_miss\",\n+ \"MetricExpr\": \"((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))\"\n }\n ]\ndiff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json\nindex dde0735a7d22..ec2ff78e2b5f 100644\n--- a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json\n+++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json\n@@ -43,5 +43,30 @@\n \"BriefDescription\": \"Percentage sourced from memory\",\n \"MetricName\": \"memp\",\n \"MetricExpr\": \"((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Cycles per Instructions from Finite cache/memory\",\n+ \"MetricName\": \"finite_cpi\",\n+ \"MetricExpr\": \"L1C_TLB2_MISSES / INSTRUCTIONS\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Instruction Complexity CPI infinite Level 1\",\n+ \"MetricName\": \"est_cpi\",\n+ \"MetricExpr\": \"(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Sourcing Cycles per Level 1 Miss\",\n+ \"MetricName\": \"scpl1m\",\n+ \"MetricExpr\": \"L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated TLB CPU percentage of Total CPU\",\n+ \"MetricName\": \"tlb_percent\",\n+ \"MetricExpr\": \"((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100\"\n+ },\n+ {\n+ \"BriefDescription\": \"Estimated Cycles per TLB Miss\",\n+ \"MetricName\": \"tlb_miss\",\n+ \"MetricExpr\": \"((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))\"\n }\n ]\n", "prefixes": [ "SRU", "J", "07/12" ] }