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GET /api/patches/2132469/?format=api
{ "id": 2132469, "url": "http://patchwork.ozlabs.org/api/patches/2132469/?format=api", "web_url": "http://patchwork.ozlabs.org/project/ubuntu-kernel/patch/642d28565104aa687215a1123e0f402355d17770.1756973061.git.massimiliano.pellizzer@canonical.com/", "project": { "id": 15, "url": "http://patchwork.ozlabs.org/api/projects/15/?format=api", "name": "Ubuntu Kernel", "link_name": "ubuntu-kernel", "list_id": "kernel-team.lists.ubuntu.com", "list_email": "kernel-team@lists.ubuntu.com", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<642d28565104aa687215a1123e0f402355d17770.1756973061.git.massimiliano.pellizzer@canonical.com>", "list_archive_url": null, "date": "2025-09-04T08:11:26", "name": "[SRU,J,01/12] perf list: Add IBM z16 event description for s390", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bbbce35d4e86be0cf24318e27b8cd92a9308321e", "submitter": { "id": 89057, "url": "http://patchwork.ozlabs.org/api/people/89057/?format=api", "name": "Massimiliano Pellizzer", "email": "massimiliano.pellizzer@canonical.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/ubuntu-kernel/patch/642d28565104aa687215a1123e0f402355d17770.1756973061.git.massimiliano.pellizzer@canonical.com/mbox/", "series": [ { "id": 472179, "url": "http://patchwork.ozlabs.org/api/series/472179/?format=api", "web_url": "http://patchwork.ozlabs.org/project/ubuntu-kernel/list/?series=472179", "date": "2025-09-04T08:11:25", "name": "CPU-MF Counters for new IBM Z hardware - perf part (LP: #2103415)", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/472179/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2132469/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2132469/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<kernel-team-bounces@lists.ubuntu.com>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ubuntu.com\n (client-ip=185.125.189.65; helo=lists.ubuntu.com;\n envelope-from=kernel-team-bounces@lists.ubuntu.com;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.ubuntu.com (lists.ubuntu.com [185.125.189.65])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cHXKb65l9z1xyS\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 4 Sep 2025 18:13:07 +1000 (AEST)", "from localhost ([127.0.0.1] helo=lists.ubuntu.com)\n\tby lists.ubuntu.com with esmtp (Exim 4.86_2)\n\t(envelope-from <kernel-team-bounces@lists.ubuntu.com>)\n\tid 1uu55X-0001bi-V1; Thu, 04 Sep 2025 08:12:59 +0000", "from smtp-relay-internal-1.internal ([10.131.114.114]\n helo=smtp-relay-internal-1.canonical.com)\n by lists.ubuntu.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.86_2) (envelope-from <massimiliano.pellizzer@canonical.com>)\n id 1uu55U-0001VB-M6\n for kernel-team@lists.ubuntu.com; Thu, 04 Sep 2025 08:12:56 +0000", "from mail-ej1-f71.google.com (mail-ej1-f71.google.com\n [209.85.218.71])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id B592A3F6A9\n for <kernel-team@lists.ubuntu.com>; Thu, 4 Sep 2025 08:12:54 +0000 (UTC)", "by mail-ej1-f71.google.com with SMTP id\n a640c23a62f3a-b04124943bcso52630666b.2\n for <kernel-team@lists.ubuntu.com>; Thu, 04 Sep 2025 01:12:54 -0700 (PDT)", "from framework-canonical.lan\n (net-31-156-181-205.cust.vodafonedsl.it. [31.156.181.205])\n by smtp.gmail.com with ESMTPSA id\n a640c23a62f3a-b041565ca98sm1131743766b.86.2025.09.04.01.12.52\n for <kernel-team@lists.ubuntu.com>\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 04 Sep 2025 01:12:52 -0700 (PDT)" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1756973574; x=1757578374;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-message-state:from:to:cc\n :subject:date:message-id:reply-to;\n bh=zZ9VkSlfbS9BRr9qDrt3yJ9acB+tPo/SUKpTimEK9bk=;\n b=LoR7bVynpX6WSj+TwbXUaVJBw6jYBVR4EQsc52zExEUkOxgLfOhPGr2QIiRub52wJ6\n KsgDaPyvaaKSRFeDav/dwvQId89Ykk7PlM3OqGM/iMwz0+wfQiGNo31OaCEziS6GEyt6\n CdJ36ov7QrbyEbsanT/HctFa4eMomXgQX2d4elVv0SXmYCF1PlCmepZbnEpf0u17Bpqt\n gTlywprq5PwqGbDEXM+LQJhut5hVkFDmT7Rcv9LJzMBFtR4wlUiSJFNQW6Fdts8XLFV3\n +zc2a3DrQ79KVcfr3uKxEG58bOq2HOnM/o4JiTx2vTn7C+vXy6qIqJPzdkUfMLZJkgoa\n rzYQ==", "X-Gm-Message-State": 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], "X-Google-Smtp-Source": "\n AGHT+IEYqRS5z10SeEOryc1mA+pIK4y+7bFR+DuTomYnlLMVIQw6qRJQ2SUoZYpPhB7ae/ixNFNlyg==", "From": "Massimiliano Pellizzer <massimiliano.pellizzer@canonical.com>", "To": "kernel-team@lists.ubuntu.com", "Subject": "[SRU][J][PATCH 01/12] perf list: Add IBM z16 event description for\n s390", "Date": "Thu, 4 Sep 2025 10:11:26 +0200", "Message-ID": "\n <642d28565104aa687215a1123e0f402355d17770.1756973061.git.massimiliano.pellizzer@canonical.com>", "X-Mailer": "git-send-email 2.48.1", "In-Reply-To": "<cover.1756973061.git.massimiliano.pellizzer@canonical.com>", "References": "\n <175697071248.21594.2440727989420834998@framework-canonical.public>\n <cover.1756973061.git.massimiliano.pellizzer@canonical.com>", "MIME-Version": "1.0", "X-BeenThere": "kernel-team@lists.ubuntu.com", "X-Mailman-Version": "2.1.20", "Precedence": "list", "List-Id": "Kernel team discussions <kernel-team.lists.ubuntu.com>", "List-Unsubscribe": "<https://lists.ubuntu.com/mailman/options/kernel-team>,\n <mailto:kernel-team-request@lists.ubuntu.com?subject=unsubscribe>", "List-Archive": "<https://lists.ubuntu.com/archives/kernel-team>", "List-Post": "<mailto:kernel-team@lists.ubuntu.com>", "List-Help": "<mailto:kernel-team-request@lists.ubuntu.com?subject=help>", "List-Subscribe": "<https://lists.ubuntu.com/mailman/listinfo/kernel-team>,\n <mailto:kernel-team-request@lists.ubuntu.com?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "kernel-team-bounces@lists.ubuntu.com", "Sender": "\"kernel-team\" <kernel-team-bounces@lists.ubuntu.com>" }, "content": "From: Thomas Richter <tmricht@linux.ibm.com>\n\nBugLink: https://bugs.launchpad.net/bugs/2103415\n\nUpdate IBM z16 counter description using document SA23-2260-07:\n\"The Load-Program-Parameter and the CPU-Measurement Facilities\"\nreleased in May, 2022, to include counter definitions for IBM z16\ncounter sets:\n * Basic counter set\n * Problem/user counter set\n * Crypto counter set\n\nUse document SA23-2261-07:\n\"The CPU-Measurement Facility Extended Counters Definition\n for z10, z196/z114, zEC12/zBC12, z13/z13s, z14, z15 and z16\"\nreleased on April 29, 2022 to include counter definitions for IBM z16\n * Extended counter set\n * MT-Diagnostic counter set\n\nSigned-off-by: Thomas Richter <tmricht@linux.ibm.com>\nAcked-by: Sumanth Korikkar <sumanthk@linux.ibm.com>\nAcked-by: Ian Rogers <irogers@google.com>\nSigned-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>\nLink: https://lore.kernel.org/r/20220531092706.1931503-1-tmricht@linux.ibm.com\nCc: acme@kernel.org\nCc: gor@linux.ibm.com\nCc: hca@linux.ibm.com\nCc: svens@linux.ibm.com\nCc: linux-kernel@vger.kernel.org\nCc: linux-perf-users@vger.kernel.org\n(cherry picked from commit 7f76b31130680fb322b3c28563e50f1679140526)\nSigned-off-by: Massimiliano Pellizzer <massimiliano.pellizzer@canonical.com>\n---\n .../pmu-events/arch/s390/cf_z16/basic.json | 58 +++\n .../pmu-events/arch/s390/cf_z16/crypto6.json | 142 +++++\n .../pmu-events/arch/s390/cf_z16/extended.json | 492 ++++++++++++++++++\n .../arch/s390/cf_z16/transaction.json | 7 +\n tools/perf/pmu-events/arch/s390/mapfile.csv | 1 +\n 5 files changed, 700 insertions(+)\n create mode 100644 tools/perf/pmu-events/arch/s390/cf_z16/basic.json\n create mode 100644 tools/perf/pmu-events/arch/s390/cf_z16/crypto6.json\n create mode 100644 tools/perf/pmu-events/arch/s390/cf_z16/extended.json\n create mode 100644 tools/perf/pmu-events/arch/s390/cf_z16/transaction.json", "diff": "diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/basic.json b/tools/perf/pmu-events/arch/s390/cf_z16/basic.json\nnew file mode 100644\nindex 000000000000..1023d47028ce\n--- /dev/null\n+++ b/tools/perf/pmu-events/arch/s390/cf_z16/basic.json\n@@ -0,0 +1,58 @@\n+[\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"0\",\n+\t\t\"EventName\": \"CPU_CYCLES\",\n+\t\t\"BriefDescription\": \"Cycle Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"1\",\n+\t\t\"EventName\": \"INSTRUCTIONS\",\n+\t\t\"BriefDescription\": \"Instruction Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of instructions executed by the CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"2\",\n+\t\t\"EventName\": \"L1I_DIR_WRITES\",\n+\t\t\"BriefDescription\": \"Level-1 I-Cache Directory Write Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of level-1 instruction-cache or unified-cache directory writes.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"3\",\n+\t\t\"EventName\": \"L1I_PENALTY_CYCLES\",\n+\t\t\"BriefDescription\": \"Level-1 I-Cache Penalty Cycle Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"4\",\n+\t\t\"EventName\": \"L1D_DIR_WRITES\",\n+\t\t\"BriefDescription\": \"Level-1 D-Cache Directory Write Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of level-1 data-cache directory writes.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"5\",\n+\t\t\"EventName\": \"L1D_PENALTY_CYCLES\",\n+\t\t\"BriefDescription\": \"Level-1 D-Cache Penalty Cycle Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of cache penalty cycles for level-1 data cache.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"32\",\n+\t\t\"EventName\": \"PROBLEM_STATE_CPU_CYCLES\",\n+\t\t\"BriefDescription\": \"Problem-State Cycle Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"33\",\n+\t\t\"EventName\": \"PROBLEM_STATE_INSTRUCTIONS\",\n+\t\t\"BriefDescription\": \"Problem-State Instruction Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of instructions executed by the CPU while in the problem state.\"\n+\t}\n+]\ndiff --git a/tools/perf/pmu-events/arch/s390/cf_z16/crypto6.json b/tools/perf/pmu-events/arch/s390/cf_z16/crypto6.json\nnew file mode 100644\nindex 000000000000..8b4380b8e489\n--- /dev/null\n+++ b/tools/perf/pmu-events/arch/s390/cf_z16/crypto6.json\n@@ -0,0 +1,142 @@\n+[\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"64\",\n+\t\t\"EventName\": \"PRNG_FUNCTIONS\",\n+\t\t\"BriefDescription\": \"PRNG Function Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"65\",\n+\t\t\"EventName\": \"PRNG_CYCLES\",\n+\t\t\"BriefDescription\": \"PRNG Cycle Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"66\",\n+\t\t\"EventName\": \"PRNG_BLOCKED_FUNCTIONS\",\n+\t\t\"BriefDescription\": \"PRNG Blocked Function Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"67\",\n+\t\t\"EventName\": \"PRNG_BLOCKED_CYCLES\",\n+\t\t\"BriefDescription\": \"PRNG Blocked Cycle Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"68\",\n+\t\t\"EventName\": \"SHA_FUNCTIONS\",\n+\t\t\"BriefDescription\": \"SHA Function Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of the SHA functions issued by the CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"69\",\n+\t\t\"EventName\": \"SHA_CYCLES\",\n+\t\t\"BriefDescription\": \"SHA Cycle Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"70\",\n+\t\t\"EventName\": \"SHA_BLOCKED_FUNCTIONS\",\n+\t\t\"BriefDescription\": \"SHA Blocked Function Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"71\",\n+\t\t\"EventName\": \"SHA_BLOCKED_CYCLES\",\n+\t\t\"BriefDescription\": \"SHA Blocked Cycle Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"72\",\n+\t\t\"EventName\": \"DEA_FUNCTIONS\",\n+\t\t\"BriefDescription\": \"DEA Function Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of the DEA functions issued by the CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"73\",\n+\t\t\"EventName\": \"DEA_CYCLES\",\n+\t\t\"BriefDescription\": \"DEA Cycle Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"74\",\n+\t\t\"EventName\": \"DEA_BLOCKED_FUNCTIONS\",\n+\t\t\"BriefDescription\": \"DEA Blocked Function Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"75\",\n+\t\t\"EventName\": \"DEA_BLOCKED_CYCLES\",\n+\t\t\"BriefDescription\": \"DEA Blocked Cycle Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"76\",\n+\t\t\"EventName\": \"AES_FUNCTIONS\",\n+\t\t\"BriefDescription\": \"AES Function Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of the AES functions issued by the CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"77\",\n+\t\t\"EventName\": \"AES_CYCLES\",\n+\t\t\"BriefDescription\": \"AES Cycle Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"78\",\n+\t\t\"EventName\": \"AES_BLOCKED_FUNCTIONS\",\n+\t\t\"BriefDescription\": \"AES Blocked Function Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"79\",\n+\t\t\"EventName\": \"AES_BLOCKED_CYCLES\",\n+\t\t\"BriefDescription\": \"AES Blocked Cycle Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"80\",\n+\t\t\"EventName\": \"ECC_FUNCTION_COUNT\",\n+\t\t\"BriefDescription\": \"ECC Function Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of the elliptic-curve cryptography (ECC) functions issued by the CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"81\",\n+\t\t\"EventName\": \"ECC_CYCLES_COUNT\",\n+\t\t\"BriefDescription\": \"ECC Cycles Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of CPU cycles when the ECC coprocessor is busy performing the elliptic-curve cryptography (ECC) functions issued by the CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"82\",\n+\t\t\"EventName\": \"ECC_BLOCKED_FUNCTION_COUNT\",\n+\t\t\"BriefDescription\": \"Ecc Blocked Function Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of the elliptic-curve cryptography (ECC) functions that are issued by the CPU and are blocked because the ECC coprocessor is busy performing a function issued by another CPU.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"83\",\n+\t\t\"EventName\": \"ECC_BLOCKED_CYCLES_COUNT\",\n+\t\t\"BriefDescription\": \"ECC Blocked Cycles Count\",\n+\t\t\"PublicDescription\": \"This counter counts the total number of CPU cycles blocked for the elliptic-curve cryptography (ECC) functions issued by the CPU because the ECC coprocessor is busy performing a function issued by another CPU.\"\n+\t}\n+]\ndiff --git a/tools/perf/pmu-events/arch/s390/cf_z16/extended.json b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json\nnew file mode 100644\nindex 000000000000..c306190fc06f\n--- /dev/null\n+++ b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json\n@@ -0,0 +1,492 @@\n+[\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"128\",\n+\t\t\"EventName\": \"L1D_RO_EXCL_WRITES\",\n+\t\t\"BriefDescription\": \"L1D Read-only Exclusive Writes\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"129\",\n+\t\t\"EventName\": \"DTLB2_WRITES\",\n+\t\t\"BriefDescription\": \"DTLB2 Writes\",\n+\t\t\"PublicDescription\": \"A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a replacement for what was provided for the DTLB on z13 and prior machines.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"130\",\n+\t\t\"EventName\": \"DTLB2_MISSES\",\n+\t\t\"BriefDescription\": \"DTLB2 Misses\",\n+\t\t\"PublicDescription\": \"A TLB2 miss is in progress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on z13 and prior machines.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"131\",\n+\t\t\"EventName\": \"CRSTE_1MB_WRITES\",\n+\t\t\"BriefDescription\": \"One Megabyte CRSTE writes\",\n+\t\t\"PublicDescription\": \"A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"132\",\n+\t\t\"EventName\": \"DTLB2_GPAGE_WRITES\",\n+\t\t\"BriefDescription\": \"DTLB2 Two-Gigabyte Page Writes\",\n+\t\t\"PublicDescription\": \"A translation entry for a two-gigabyte page was written into the Level-2 TLB.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"134\",\n+\t\t\"EventName\": \"ITLB2_WRITES\",\n+\t\t\"BriefDescription\": \"ITLB2 Writes\",\n+\t\t\"PublicDescription\": \"A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement for what was provided for the ITLB on z13 and prior machines.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"135\",\n+\t\t\"EventName\": \"ITLB2_MISSES\",\n+\t\t\"BriefDescription\": \"ITLB2 Misses\",\n+\t\t\"PublicDescription\": \"A TLB2 miss is in progress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on z13 and prior machines.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"137\",\n+\t\t\"EventName\": \"TLB2_PTE_WRITES\",\n+\t\t\"BriefDescription\": \"TLB2 Page Table Entry Writes\",\n+\t\t\"PublicDescription\": \"A translation entry was written into the Page Table Entry array in the Level-2 TLB.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"138\",\n+\t\t\"EventName\": \"TLB2_CRSTE_WRITES\",\n+\t\t\"BriefDescription\": \"TLB2 Combined Region and Segment Entry Writes\",\n+\t\t\"PublicDescription\": \"Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"139\",\n+\t\t\"EventName\": \"TLB2_ENGINES_BUSY\",\n+\t\t\"BriefDescription\": \"TLB2 Engines Busy\",\n+\t\t\"PublicDescription\": \"The number of Level-2 TLB translation engines busy in a cycle.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"140\",\n+\t\t\"EventName\": \"TX_C_TEND\",\n+\t\t\"BriefDescription\": \"Completed TEND instructions in constrained TX mode\",\n+\t\t\"PublicDescription\": \"A TEND instruction has completed in a constrained transactional-execution mode.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"141\",\n+\t\t\"EventName\": \"TX_NC_TEND\",\n+\t\t\"BriefDescription\": \"Completed TEND instructions in non-constrained TX mode\",\n+\t\t\"PublicDescription\": \"A TEND instruction has completed in a non-constrained transactional-execution mode.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"143\",\n+\t\t\"EventName\": \"L1C_TLB2_MISSES\",\n+\t\t\"BriefDescription\": \"L1C TLB2 Misses\",\n+\t\t\"PublicDescription\": \"Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"145\",\n+\t\t\"EventName\": \"DCW_REQ\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from Cache\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"146\",\n+\t\t\"EventName\": \"DCW_REQ_IV\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from Cache with Intervention\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache with intervention.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"147\",\n+\t\t\"EventName\": \"DCW_REQ_CHIP_HIT\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from Cache with Chip HP Hit\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using chip level horizontal persistence, Chip-HP hit.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"148\",\n+\t\t\"EventName\": \"DCW_REQ_DRAWER_HIT\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from Cache with Drawer HP Hit\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"149\",\n+\t\t\"EventName\": \"DCW_ON_CHIP\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Chip Cache\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"150\",\n+\t\t\"EventName\": \"DCW_ON_CHIP_IV\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Chip Cache with Intervention\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache with intervention.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"151\",\n+\t\t\"EventName\": \"DCW_ON_CHIP_CHIP_HIT\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Chip Cache with Chip HP Hit\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"152\",\n+\t\t\"EventName\": \"DCW_ON_CHIP_DRAWER_HIT\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Chip Cache with Drawer HP Hit\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using drawer level horizontal persistence, Drawer-HP hit.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"153\",\n+\t\t\"EventName\": \"DCW_ON_MODULE\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Module Cache\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Module Level-2 cache.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"154\",\n+\t\t\"EventName\": \"DCW_ON_DRAWER\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Drawer Cache\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"155\",\n+\t\t\"EventName\": \"DCW_OFF_DRAWER\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from Off-Drawer Cache\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"156\",\n+\t\t\"EventName\": \"DCW_ON_CHIP_MEMORY\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Chip Memory\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"157\",\n+\t\t\"EventName\": \"DCW_ON_MODULE_MEMORY\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Module Memory\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Module memory.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"158\",\n+\t\t\"EventName\": \"DCW_ON_DRAWER_MEMORY\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from On-Drawer Memory\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"159\",\n+\t\t\"EventName\": \"DCW_OFF_DRAWER_MEMORY\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Data Cache from Off-Drawer Memory\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"160\",\n+\t\t\"EventName\": \"IDCW_ON_MODULE_IV\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Intervention\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache with intervention.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"161\",\n+\t\t\"EventName\": \"IDCW_ON_MODULE_CHIP_HIT\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Chip Hit\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using chip horizontal persistence, Chip-HP hit.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"162\",\n+\t\t\"EventName\": \"IDCW_ON_MODULE_DRAWER_HIT\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Drawer Hit\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using drawer level horizontal persistence, Drawer-HP hit.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"163\",\n+\t\t\"EventName\": \"IDCW_ON_DRAWER_IV\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Intervention\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache with intervention.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"164\",\n+\t\t\"EventName\": \"IDCW_ON_DRAWER_CHIP_HIT\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Chip Hit\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"165\",\n+\t\t\"EventName\": \"IDCW_ON_DRAWER_DRAWER_HIT\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Drawer Hit\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"166\",\n+\t\t\"EventName\": \"IDCW_OFF_DRAWER_IV\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Intervention\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache with intervention.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"167\",\n+\t\t\"EventName\": \"IDCW_OFF_DRAWER_CHIP_HIT\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Chip Hit\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"168\",\n+\t\t\"EventName\": \"IDCW_OFF_DRAWER_DRAWER_HIT\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Drawer Hit\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"169\",\n+\t\t\"EventName\": \"ICW_REQ\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from Cache\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced the requestors Level-2 cache.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"170\",\n+\t\t\"EventName\": \"ICW_REQ_IV\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from Cache with Intervention\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"171\",\n+\t\t\"EventName\": \"ICW_REQ_CHIP_HIT\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from Cache with Chip HP Hit\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using chip level horizontal persistence, Chip-HP hit.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"172\",\n+\t\t\"EventName\": \"ICW_REQ_DRAWER_HIT\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from Cache with Drawer HP Hit\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestor’s Level-2 cache using drawer level horizontal persistence, Drawer-HP hit.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"173\",\n+\t\t\"EventName\": \"ICW_ON_CHIP\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Chip Cache\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"174\",\n+\t\t\"EventName\": \"ICW_ON_CHIP_IV\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Chip Cache with Intervention\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Chip Level-2 cache with intervention.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"175\",\n+\t\t\"EventName\": \"ICW_ON_CHIP_CHIP_HIT\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Chip Cache with Chip HP Hit\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using chip level horizontal persistence, Chip-HP hit.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"176\",\n+\t\t\"EventName\": \"ICW_ON_CHIP_DRAWER_HIT\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Chip Cache with Drawer HP Hit\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip level 2 cache using drawer level horizontal persistence, Drawer-HP hit.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"177\",\n+\t\t\"EventName\": \"ICW_ON_MODULE\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Module Cache\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"178\",\n+\t\t\"EventName\": \"ICW_ON_DRAWER\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Drawer Cache\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Drawer Level-2 cache.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"179\",\n+\t\t\"EventName\": \"ICW_OFF_DRAWER\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from Off-Drawer Cache\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an Off-Drawer Level-2 cache.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"180\",\n+\t\t\"EventName\": \"ICW_ON_CHIP_MEMORY\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Chip Memory\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"181\",\n+\t\t\"EventName\": \"ICW_ON_MODULE_MEMORY\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Module Memory\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Module memory.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"182\",\n+\t\t\"EventName\": \"ICW_ON_DRAWER_MEMORY\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from On-Drawer Memory\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"183\",\n+\t\t\"EventName\": \"ICW_OFF_DRAWER_MEMORY\",\n+\t\t\"BriefDescription\": \"Directory Write Level 1 Instruction Cache from Off-Drawer Memory\",\n+\t\t\"PublicDescription\": \"A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"224\",\n+\t\t\"EventName\": \"BCD_DFP_EXECUTION_SLOTS\",\n+\t\t\"BriefDescription\": \"Binary Coded Decimal to Decimal Floating Point conversions\",\n+\t\t\"PublicDescription\": \"Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"225\",\n+\t\t\"EventName\": \"VX_BCD_EXECUTION_SLOTS\",\n+\t\t\"BriefDescription\": \"Count finished vector arithmetic Binary Coded Decimal instructions\",\n+\t\t\"PublicDescription\": \"Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMP, VMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOP, VCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVD, VCVDG.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"226\",\n+\t\t\"EventName\": \"DECIMAL_INSTRUCTIONS\",\n+\t\t\"BriefDescription\": \"Decimal instruction dispatched\",\n+\t\t\"PublicDescription\": \"Decimal instruction dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"232\",\n+\t\t\"EventName\": \"LAST_HOST_TRANSLATIONS\",\n+\t\t\"BriefDescription\": \"Last host translation done\",\n+\t\t\"PublicDescription\": \"Last Host Translation done\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"244\",\n+\t\t\"EventName\": \"TX_NC_TABORT\",\n+\t\t\"BriefDescription\": \"Aborted transactions in unconstrained TX mode\",\n+\t\t\"PublicDescription\": \"A transaction abort has occurred in a non-constrained transactional-execution mode.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"245\",\n+\t\t\"EventName\": \"TX_C_TABORT_NO_SPECIAL\",\n+\t\t\"BriefDescription\": \"Aborted transactions in constrained TX mode\",\n+\t\t\"PublicDescription\": \"A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"246\",\n+\t\t\"EventName\": \"TX_C_TABORT_SPECIAL\",\n+\t\t\"BriefDescription\": \"Aborted transactions in constrained TX mode using special completion logic\",\n+\t\t\"PublicDescription\": \"A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"248\",\n+\t\t\"EventName\": \"DFLT_ACCESS\",\n+\t\t\"BriefDescription\": \"Cycles CPU spent obtaining access to Deflate unit\",\n+\t\t\"PublicDescription\": \"Cycles CPU spent obtaining access to Deflate unit\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"253\",\n+\t\t\"EventName\": \"DFLT_CYCLES\",\n+\t\t\"BriefDescription\": \"Cycles CPU is using Deflate unit\",\n+\t\t\"PublicDescription\": \"Cycles CPU is using Deflate unit\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"256\",\n+\t\t\"EventName\": \"SORTL\",\n+\t\t\"BriefDescription\": \"Count SORTL instructions\",\n+\t\t\"PublicDescription\": \"Increments by one for every SORT LISTS instruction executed.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"265\",\n+\t\t\"EventName\": \"DFLT_CC\",\n+\t\t\"BriefDescription\": \"Increments DEFLATE CONVERSION CALL\",\n+\t\t\"PublicDescription\": \"Increments by one for every DEFLATE CONVERSION CALL instruction executed.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"266\",\n+\t\t\"EventName\": \"DFLT_CCFINISH\",\n+\t\t\"BriefDescription\": \"Increments completed DEFLATE CONVERSION CALL\",\n+\t\t\"PublicDescription\": \"Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"267\",\n+\t\t\"EventName\": \"NNPA_INVOCATIONS\",\n+\t\t\"BriefDescription\": \"NNPA Total invocations\",\n+\t\t\"PublicDescription\": \"Increments by one for every Neural Network Processing Assist instruction executed.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"268\",\n+\t\t\"EventName\": \"NNPA_COMPLETIONS\",\n+\t\t\"BriefDescription\": \"NNPA Total completions\",\n+\t\t\"PublicDescription\": \"Increments by one for every Neural Network Processing Assist instruction executed that ended in Condition Codes 0, 1 or 2.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"269\",\n+\t\t\"EventName\": \"NNPA_WAIT_LOCK\",\n+\t\t\"BriefDescription\": \"Cycles spent obtaining NNPA lock\",\n+\t\t\"PublicDescription\": \"Cycles CPU spent obtaining access to IBM Z Integrated Accelerator for AI.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"270\",\n+\t\t\"EventName\": \"NNPA_HOLD_LOCK\",\n+\t\t\"BriefDescription\": \"Cycles spent holding NNPA lock\",\n+\t\t\"PublicDescription\": \"Cycles CPU is using IBM Z Integrated Accelerator for AI.\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"448\",\n+\t\t\"EventName\": \"MT_DIAG_CYCLES_ONE_THR_ACTIVE\",\n+\t\t\"BriefDescription\": \"Cycle count with one thread active\",\n+\t\t\"PublicDescription\": \"Cycle count with one thread active\"\n+\t},\n+\t{\n+\t\t\"Unit\": \"CPU-M-CF\",\n+\t\t\"EventCode\": \"449\",\n+\t\t\"EventName\": \"MT_DIAG_CYCLES_TWO_THR_ACTIVE\",\n+\t\t\"BriefDescription\": \"Cycle count with two threads active\",\n+\t\t\"PublicDescription\": \"Cycle count with two threads active\"\n+\t}\n+]\ndiff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json\nnew file mode 100644\nindex 000000000000..1a0034f79f73\n--- /dev/null\n+++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json\n@@ -0,0 +1,7 @@\n+[\n+ {\n+ \"BriefDescription\": \"Transaction count\",\n+ \"MetricName\": \"transaction\",\n+ \"MetricExpr\": \"TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL\"\n+ }\n+]\ndiff --git a/tools/perf/pmu-events/arch/s390/mapfile.csv b/tools/perf/pmu-events/arch/s390/mapfile.csv\nindex 61641a3480e0..a918e1af77a5 100644\n--- a/tools/perf/pmu-events/arch/s390/mapfile.csv\n+++ b/tools/perf/pmu-events/arch/s390/mapfile.csv\n@@ -5,3 +5,4 @@ Family-model,Version,Filename,EventType\n ^IBM.296[45].*[13]\\.[1-5].[[:xdigit:]]+$,1,cf_z13,core\n ^IBM.390[67].*[13]\\.[1-5].[[:xdigit:]]+$,3,cf_z14,core\n ^IBM.856[12].*3\\.6.[[:xdigit:]]+$,3,cf_z15,core\n+^IBM.393[12].*3\\.7.[[:xdigit:]]+$,3,cf_z16,core\n", "prefixes": [ "SRU", "J", "01/12" ] }