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GET /api/patches/2112969/?format=api
{ "id": 2112969, "url": "http://patchwork.ozlabs.org/api/patches/2112969/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20250718011544.1333974-1-trini@konsulko.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20250718011544.1333974-1-trini@konsulko.com>", "list_archive_url": null, "date": "2025-07-18T01:15:44", "name": "arm: bcm281xx: Remove ethernet driver", "commit_ref": "3c1ac44caaa243acb7c3fe0aca412778b8cc28e6", "pull_url": null, "state": "accepted", "archived": false, "hash": "59b98a94452dfd5d0c27c15c0fc10f640c0ad30e", "submitter": { "id": 65875, "url": "http://patchwork.ozlabs.org/api/people/65875/?format=api", "name": "Tom Rini", "email": "trini@konsulko.com" }, "delegate": { "id": 157425, "url": "http://patchwork.ozlabs.org/api/users/157425/?format=api", "username": "jforissier", "first_name": "Jerome", "last_name": "Forissier", "email": "jerome.forissier@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20250718011544.1333974-1-trini@konsulko.com/mbox/", "series": [ { "id": 465715, "url": "http://patchwork.ozlabs.org/api/series/465715/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=465715", "date": "2025-07-18T01:15:44", "name": "arm: bcm281xx: Remove ethernet driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/465715/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2112969/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2112969/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=konsulko.com header.i=@konsulko.com header.a=rsa-sha256\n header.s=google header.b=e9l97ZzY;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=konsulko.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=konsulko.com header.i=@konsulko.com\n header.b=\"e9l97ZzY\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=konsulko.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=trini@konsulko.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4bjsLs0k34z1xrF\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 18 Jul 2025 11:16:21 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 8DC82835FE;\n\tFri, 18 Jul 2025 03:15:53 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 53E40835C7; Fri, 18 Jul 2025 03:15:52 +0200 (CEST)", "from mail-ot1-x32e.google.com (mail-ot1-x32e.google.com\n [IPv6:2607:f8b0:4864:20::32e])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 0EF9D8353A\n for <u-boot@lists.denx.de>; Fri, 18 Jul 2025 03:15:48 +0200 (CEST)", "by mail-ot1-x32e.google.com with SMTP id\n 46e09a7af769-73e57751cd9so477315a34.1\n for <u-boot@lists.denx.de>; Thu, 17 Jul 2025 18:15:47 -0700 (PDT)", "from bill-the-cat.. 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"<20250718011544.1333974-1-trini@konsulko.com>", "X-Mailer": "git-send-email 2.43.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "As no platforms enable the ethernet driver, remove it.\n\nSigned-off-by: Tom Rini <trini@konsulko.com>\n---\nCc: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>\n---\n arch/arm/cpu/armv7/bcm281xx/Makefile | 1 -\n arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c | 24 -\n arch/arm/cpu/armv7/bcm281xx/clk-eth.c | 142 ---\n drivers/net/Kconfig | 24 -\n drivers/net/Makefile | 2 -\n drivers/net/bcm-sf2-eth-gmac.c | 976 ---------------------\n drivers/net/bcm-sf2-eth-gmac.h | 222 -----\n drivers/net/bcm-sf2-eth.c | 274 ------\n drivers/net/bcm-sf2-eth.h | 65 --\n include/configs/bcm_ns3.h | 12 +-\n 10 files changed, 1 insertion(+), 1741 deletions(-)\n delete mode 100644 arch/arm/cpu/armv7/bcm281xx/clk-eth.c\n delete mode 100644 drivers/net/bcm-sf2-eth-gmac.c\n delete mode 100644 drivers/net/bcm-sf2-eth-gmac.h\n delete mode 100644 drivers/net/bcm-sf2-eth.c\n delete mode 100644 drivers/net/bcm-sf2-eth.h", "diff": "diff --git a/arch/arm/cpu/armv7/bcm281xx/Makefile b/arch/arm/cpu/armv7/bcm281xx/Makefile\nindex e5099975cba3..f6323af1d068 100644\n--- a/arch/arm/cpu/armv7/bcm281xx/Makefile\n+++ b/arch/arm/cpu/armv7/bcm281xx/Makefile\n@@ -7,5 +7,4 @@ obj-y\t+= clk-core.o\n obj-y\t+= clk-bcm281xx.o\n obj-y\t+= clk-sdio.o\n obj-y\t+= clk-bsc.o\n-obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o\n obj-y\t+= clk-usb-otg.o\ndiff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c\nindex b258fea45c8e..39eb2ca01dc5 100644\n--- a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c\n+++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c\n@@ -307,27 +307,6 @@ static struct ccu_clock kps_ccu_clk = {\n \t.freq_tbl = slave_axi_freq_tbl,\n };\n \n-#ifdef CONFIG_BCM_SF2_ETH\n-static struct ccu_clock esub_ccu_clk = {\n-\t.clk = {\n-\t\t.name = \"esub_ccu_clk\",\n-\t\t.ops = &ccu_clk_ops,\n-\t\t.ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,\n-\t},\n-\t.num_policy_masks = 1,\n-\t.policy_freq_offset = 0x00000008,\n-\t.freq_bit_shift = 8,\n-\t.policy_ctl_offset = 0x0000000c,\n-\t.policy0_mask_offset = 0x00000010,\n-\t.policy1_mask_offset = 0x00000014,\n-\t.policy2_mask_offset = 0x00000018,\n-\t.policy3_mask_offset = 0x0000001c,\n-\t.lvm_en_offset = 0x00000034,\n-\t.freq_id = 2,\n-\t.freq_tbl = esub_freq_tbl,\n-};\n-#endif\n-\n /*\n * Bus clocks\n */\n@@ -562,9 +541,6 @@ struct clk_lookup arch_clk_tbl[] = {\n \tCLK_LK(bsc1_apb),\n \tCLK_LK(bsc2_apb),\n \tCLK_LK(bsc3_apb),\n-#ifdef CONFIG_BCM_SF2_ETH\n-\tCLK_LK(esub_ccu),\n-#endif\n };\n \n /* public array size */\ndiff --git a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c\ndeleted file mode 100644\nindex 5f7cc4a102d0..000000000000\n--- a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c\n+++ /dev/null\n@@ -1,142 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0+\n-/*\n- * Copyright 2014 Broadcom Corporation.\n- */\n-\n-#include <asm/io.h>\n-#include <linux/delay.h>\n-#include <linux/errno.h>\n-#include <asm/arch/sysmap.h>\n-#include <asm/kona-common/clk.h>\n-#include \"clk-core.h\"\n-\n-#define WR_ACCESS_ADDR\t\t\tESUB_CLK_BASE_ADDR\n-#define WR_ACCESS_PASSWORD\t\t\t\t0xA5A500\n-\n-#define PLLE_POST_RESETB_ADDR\t\t(ESUB_CLK_BASE_ADDR + 0x00000C00)\n-\n-#define PLLE_RESETB_ADDR\t\t(ESUB_CLK_BASE_ADDR + 0x00000C58)\n-#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK\t\t0x00010000\n-#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK\t0x00000001\n-\n-#define PLL_LOCK_ADDR\t\t\t(ESUB_CLK_BASE_ADDR + 0x00000C38)\n-#define PLL_LOCK_PLL_LOCK_PLLE_MASK\t\t\t0x00000001\n-\n-#define ESW_SYS_DIV_ADDR\t\t(ESUB_CLK_BASE_ADDR + 0x00000A04)\n-#define ESW_SYS_DIV_PLL_SELECT_MASK\t\t\t0x00000300\n-#define ESW_SYS_DIV_DIV_MASK\t\t\t\t0x0000001C\n-#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT\t\t0x00000100\n-#define ESW_SYS_DIV_DIV_SELECT\t\t\t\t0x4\n-#define ESW_SYS_DIV_TRIGGER_MASK\t\t\t0x00000001\n-\n-#define ESUB_AXI_DIV_DEBUG_ADDR\t\t(ESUB_CLK_BASE_ADDR + 0x00000E04)\n-#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK\t\t0x0000001C\n-#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK\t0x00000040\n-#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT\t0x0\n-#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK\t\t\t0x00000001\n-\n-#define PLL_MAX_RETRY\t100\n-\n-/* Enable appropriate clocks for Ethernet */\n-int clk_eth_enable(void)\n-{\n-\tint rc = -1;\n-\tint retry_count = 0;\n-\trc = clk_get_and_enable(\"esub_ccu_clk\");\n-\n-\t/* Enable Access to CCU registers */\n-\twritel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR);\n-\n-\twritel(readl(PLLE_POST_RESETB_ADDR) &\n-\t ~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,\n-\t PLLE_POST_RESETB_ADDR);\n-\n-\t/* Take PLL out of reset and put into normal mode */\n-\twritel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK,\n-\t PLLE_RESETB_ADDR);\n-\n-\t/* Wait for PLL lock */\n-\trc = -1;\n-\twhile (retry_count < PLL_MAX_RETRY) {\n-\t\tudelay(100);\n-\t\tif (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) {\n-\t\t\trc = 0;\n-\t\t\tbreak;\n-\t\t}\n-\t\tretry_count++;\n-\t}\n-\n-\tif (rc == -1) {\n-\t\tprintf(\"%s: ETH-PLL lock timeout, Ethernet is not enabled!\\n\",\n-\t\t __func__);\n-\t\treturn -1;\n-\t}\n-\n-\twritel(readl(PLLE_POST_RESETB_ADDR) |\n-\t PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,\n-\t PLLE_POST_RESETB_ADDR);\n-\n-\t/* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */\n-\twritel((readl(ESW_SYS_DIV_ADDR) &\n-\t\t~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) |\n-\t ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT,\n-\t ESW_SYS_DIV_ADDR);\n-\n-\twritel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK,\n-\t ESW_SYS_DIV_ADDR);\n-\n-\t/* Wait for trigger complete */\n-\trc = -1;\n-\tretry_count = 0;\n-\twhile (retry_count < PLL_MAX_RETRY) {\n-\t\tudelay(100);\n-\t\tif (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) {\n-\t\t\trc = 0;\n-\t\t\tbreak;\n-\t\t}\n-\t\tretry_count++;\n-\t}\n-\n-\tif (rc == -1) {\n-\t\tprintf(\"%s: SYS CLK Trigger timeout, Ethernet is not enabled!\\n\",\n-\t\t __func__);\n-\t\treturn -1;\n-\t}\n-\n-\t/* switch Esub AXI clock to 208MHz */\n-\twritel((readl(ESUB_AXI_DIV_DEBUG_ADDR) &\n-\t\t~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK |\n-\t\t ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK |\n-\t\t ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) |\n-\t ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT |\n-\t ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK,\n-\t ESUB_AXI_DIV_DEBUG_ADDR);\n-\n-\twritel(readl(ESUB_AXI_DIV_DEBUG_ADDR) |\n-\t ESUB_AXI_DIV_DEBUG_TRIGGER_MASK,\n-\t ESUB_AXI_DIV_DEBUG_ADDR);\n-\n-\t/* Wait for trigger complete */\n-\trc = -1;\n-\tretry_count = 0;\n-\twhile (retry_count < PLL_MAX_RETRY) {\n-\t\tudelay(100);\n-\t\tif (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) &\n-\t\t ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) {\n-\t\t\trc = 0;\n-\t\t\tbreak;\n-\t\t}\n-\t\tretry_count++;\n-\t}\n-\n-\tif (rc == -1) {\n-\t\tprintf(\"%s: AXI CLK Trigger timeout, Ethernet is not enabled!\\n\",\n-\t\t __func__);\n-\t\treturn -1;\n-\t}\n-\n-\t/* Disable Access to CCU registers */\n-\twritel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR);\n-\n-\treturn rc;\n-}\ndiff --git a/drivers/net/Kconfig b/drivers/net/Kconfig\nindex 950ed0f25a9a..f8c7637f0b9c 100644\n--- a/drivers/net/Kconfig\n+++ b/drivers/net/Kconfig\n@@ -138,30 +138,6 @@ config ALTERA_TSE\n \t Please find details on the \"Triple-Speed Ethernet MegaCore Function\n \t Resource Center\" of Altera.\n \n-config BCM_SF2_ETH\n-\tbool \"Broadcom SF2 (Starfighter2) Ethernet support\"\n-\tselect PHYLIB\n-\thelp\n-\t This is an abstract framework which provides a generic interface\n-\t to MAC and DMA management for multiple Broadcom SoCs such as\n-\t Cygnus, NSP and bcm28155_ap platforms.\n-\n-config BCM_SF2_ETH_DEFAULT_PORT\n-\tint \"Broadcom SF2 (Starfighter2) Ethernet default port number\"\n-\tdepends on BCM_SF2_ETH\n-\tdefault 0\n-\thelp\n-\t Default port number for the Starfighter2 ethernet driver.\n-\n-config BCM_SF2_ETH_GMAC\n-\tbool \"Broadcom SF2 (Starfighter2) GMAC Ethernet support\"\n-\tdepends on BCM_SF2_ETH\n-\thelp\n-\t This flag enables the ethernet support for Broadcom platforms with\n-\t GMAC such as Cygnus. This driver is based on the framework provided\n-\t by the BCM_SF2_ETH driver.\n-\t Say Y to any bcmcygnus based platforms.\n-\n config BCM6348_ETH\n \tbool \"BCM6348 EMAC support\"\n \tdepends on ARCH_BMIPS\ndiff --git a/drivers/net/Makefile b/drivers/net/Makefile\nindex 67bba3a85367..0591312d17db 100644\n--- a/drivers/net/Makefile\n+++ b/drivers/net/Makefile\n@@ -11,8 +11,6 @@ obj-$(CONFIG_ASPEED_MDIO) += aspeed_mdio.o\n obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o\n obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o\n obj-$(CONFIG_BCMGENET) += bcmgenet.o\n-obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o\n-obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o\n obj-$(CONFIG_BNXT_ETH) += bnxt/\n obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o\n obj-$(CONFIG_CORTINA_NI_ENET) += cortina_ni.o\ndiff --git a/drivers/net/bcm-sf2-eth-gmac.c b/drivers/net/bcm-sf2-eth-gmac.c\ndeleted file mode 100644\nindex ba244b4a26e2..000000000000\n--- a/drivers/net/bcm-sf2-eth-gmac.c\n+++ /dev/null\n@@ -1,976 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0+\n-/*\n- * Copyright 2014-2017 Broadcom.\n- */\n-\n-#ifdef BCM_GMAC_DEBUG\n-#ifndef DEBUG\n-#define DEBUG\n-#include <linux/printk.h>\n-#endif\n-#endif\n-\n-#include <config.h>\n-#include <cpu_func.h>\n-#include <log.h>\n-#include <malloc.h>\n-#include <net.h>\n-#include <asm/cache.h>\n-#include <asm/io.h>\n-#include <phy.h>\n-#include <linux/delay.h>\n-#include <linux/bitops.h>\n-\n-#include \"bcm-sf2-eth.h\"\n-#include \"bcm-sf2-eth-gmac.h\"\n-\n-#define SPINWAIT(exp, us) { \\\n-\tuint countdown = (us) + 9; \\\n-\twhile ((exp) && (countdown >= 10)) {\\\n-\t\tudelay(10); \\\n-\t\tcountdown -= 10; \\\n-\t} \\\n-}\n-\n-#define RX_BUF_SIZE_ALIGNED\tALIGN(RX_BUF_SIZE, ARCH_DMA_MINALIGN)\n-#define TX_BUF_SIZE_ALIGNED\tALIGN(TX_BUF_SIZE, ARCH_DMA_MINALIGN)\n-#define DESCP_SIZE_ALIGNED\tALIGN(sizeof(dma64dd_t), ARCH_DMA_MINALIGN)\n-\n-static int gmac_disable_dma(struct eth_dma *dma, int dir);\n-static int gmac_enable_dma(struct eth_dma *dma, int dir);\n-\n-/* DMA Descriptor */\n-typedef struct {\n-\t/* misc control bits */\n-\tuint32_t\tctrl1;\n-\t/* buffer count and address extension */\n-\tuint32_t\tctrl2;\n-\t/* memory address of the date buffer, bits 31:0 */\n-\tuint32_t\taddrlow;\n-\t/* memory address of the date buffer, bits 63:32 */\n-\tuint32_t\taddrhigh;\n-} dma64dd_t;\n-\n-uint32_t g_dmactrlflags;\n-\n-static uint32_t dma_ctrlflags(uint32_t mask, uint32_t flags)\n-{\n-\tdebug(\"%s enter\\n\", __func__);\n-\n-\tg_dmactrlflags &= ~mask;\n-\tg_dmactrlflags |= flags;\n-\n-\t/* If trying to enable parity, check if parity is actually supported */\n-\tif (g_dmactrlflags & DMA_CTRL_PEN) {\n-\t\tuint32_t control;\n-\n-\t\tcontrol = readl(GMAC0_DMA_TX_CTRL_ADDR);\n-\t\twritel(control | D64_XC_PD, GMAC0_DMA_TX_CTRL_ADDR);\n-\t\tif (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_PD) {\n-\t\t\t/*\n-\t\t\t * We *can* disable it, therefore it is supported;\n-\t\t\t * restore control register\n-\t\t\t */\n-\t\t\twritel(control, GMAC0_DMA_TX_CTRL_ADDR);\n-\t\t} else {\n-\t\t\t/* Not supported, don't allow it to be enabled */\n-\t\t\tg_dmactrlflags &= ~DMA_CTRL_PEN;\n-\t\t}\n-\t}\n-\n-\treturn g_dmactrlflags;\n-}\n-\n-static inline void reg32_clear_bits(uint32_t reg, uint32_t value)\n-{\n-\tuint32_t v = readl(reg);\n-\tv &= ~(value);\n-\twritel(v, reg);\n-}\n-\n-static inline void reg32_set_bits(uint32_t reg, uint32_t value)\n-{\n-\tuint32_t v = readl(reg);\n-\tv |= value;\n-\twritel(v, reg);\n-}\n-\n-#ifdef BCM_GMAC_DEBUG\n-static void dma_tx_dump(struct eth_dma *dma)\n-{\n-\tdma64dd_t *descp = NULL;\n-\tuint8_t *bufp;\n-\tint i;\n-\n-\tprintf(\"TX DMA Register:\\n\");\n-\tprintf(\"control:0x%x; ptr:0x%x; addrl:0x%x; addrh:0x%x; stat0:0x%x, stat1:0x%x\\n\",\n-\t readl(GMAC0_DMA_TX_CTRL_ADDR),\n-\t readl(GMAC0_DMA_TX_PTR_ADDR),\n-\t readl(GMAC0_DMA_TX_ADDR_LOW_ADDR),\n-\t readl(GMAC0_DMA_TX_ADDR_HIGH_ADDR),\n-\t readl(GMAC0_DMA_TX_STATUS0_ADDR),\n-\t readl(GMAC0_DMA_TX_STATUS1_ADDR));\n-\n-\tprintf(\"TX Descriptors:\\n\");\n-\tfor (i = 0; i < TX_BUF_NUM; i++) {\n-\t\tdescp = (dma64dd_t *)(dma->tx_desc_aligned) + i;\n-\t\tprintf(\"ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\\n\",\n-\t\t descp->ctrl1, descp->ctrl2,\n-\t\t descp->addrhigh, descp->addrlow);\n-\t}\n-\n-\tprintf(\"TX Buffers:\\n\");\n-\t/* Initialize TX DMA descriptor table */\n-\tfor (i = 0; i < TX_BUF_NUM; i++) {\n-\t\tbufp = (uint8_t *)(dma->tx_buf + i * TX_BUF_SIZE_ALIGNED);\n-\t\tprintf(\"buf%d:0x%x; \", i, (uint32_t)bufp);\n-\t}\n-\tprintf(\"\\n\");\n-}\n-\n-static void dma_rx_dump(struct eth_dma *dma)\n-{\n-\tdma64dd_t *descp = NULL;\n-\tuint8_t *bufp;\n-\tint i;\n-\n-\tprintf(\"RX DMA Register:\\n\");\n-\tprintf(\"control:0x%x; ptr:0x%x; addrl:0x%x; addrh:0x%x; stat0:0x%x, stat1:0x%x\\n\",\n-\t readl(GMAC0_DMA_RX_CTRL_ADDR),\n-\t readl(GMAC0_DMA_RX_PTR_ADDR),\n-\t readl(GMAC0_DMA_RX_ADDR_LOW_ADDR),\n-\t readl(GMAC0_DMA_RX_ADDR_HIGH_ADDR),\n-\t readl(GMAC0_DMA_RX_STATUS0_ADDR),\n-\t readl(GMAC0_DMA_RX_STATUS1_ADDR));\n-\n-\tprintf(\"RX Descriptors:\\n\");\n-\tfor (i = 0; i < RX_BUF_NUM; i++) {\n-\t\tdescp = (dma64dd_t *)(dma->rx_desc_aligned) + i;\n-\t\tprintf(\"ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\\n\",\n-\t\t descp->ctrl1, descp->ctrl2,\n-\t\t descp->addrhigh, descp->addrlow);\n-\t}\n-\n-\tprintf(\"RX Buffers:\\n\");\n-\tfor (i = 0; i < RX_BUF_NUM; i++) {\n-\t\tbufp = dma->rx_buf + i * RX_BUF_SIZE_ALIGNED;\n-\t\tprintf(\"buf%d:0x%x; \", i, (uint32_t)bufp);\n-\t}\n-\tprintf(\"\\n\");\n-}\n-#endif\n-\n-static int dma_tx_init(struct eth_dma *dma)\n-{\n-\tdma64dd_t *descp = NULL;\n-\tuint8_t *bufp;\n-\tint i;\n-\tuint32_t ctrl;\n-\n-\tdebug(\"%s enter\\n\", __func__);\n-\n-\t/* clear descriptor memory */\n-\tmemset((void *)(dma->tx_desc_aligned), 0,\n-\t TX_BUF_NUM * DESCP_SIZE_ALIGNED);\n-\tmemset(dma->tx_buf, 0, TX_BUF_NUM * TX_BUF_SIZE_ALIGNED);\n-\n-\t/* Initialize TX DMA descriptor table */\n-\tfor (i = 0; i < TX_BUF_NUM; i++) {\n-\t\tdescp = (dma64dd_t *)(dma->tx_desc_aligned) + i;\n-\t\tbufp = dma->tx_buf + i * TX_BUF_SIZE_ALIGNED;\n-\t\t/* clear buffer memory */\n-\t\tmemset((void *)bufp, 0, TX_BUF_SIZE_ALIGNED);\n-\n-\t\tctrl = 0;\n-\t\t/* if last descr set endOfTable */\n-\t\tif (i == (TX_BUF_NUM-1))\n-\t\t\tctrl = D64_CTRL1_EOT;\n-\t\tdescp->ctrl1 = ctrl;\n-\t\tdescp->ctrl2 = 0;\n-\t\tdescp->addrlow = (uint32_t)bufp;\n-\t\tdescp->addrhigh = 0;\n-\t}\n-\n-\t/* flush descriptor and buffer */\n-\tdescp = dma->tx_desc_aligned;\n-\tbufp = dma->tx_buf;\n-\tflush_dcache_range((unsigned long)descp,\n-\t\t\t (unsigned long)descp +\n-\t\t\t DESCP_SIZE_ALIGNED * TX_BUF_NUM);\n-\tflush_dcache_range((unsigned long)bufp,\n-\t\t\t (unsigned long)bufp +\n-\t\t\t TX_BUF_SIZE_ALIGNED * TX_BUF_NUM);\n-\n-\t/* initialize the DMA channel */\n-\twritel((uint32_t)(dma->tx_desc_aligned), GMAC0_DMA_TX_ADDR_LOW_ADDR);\n-\twritel(0, GMAC0_DMA_TX_ADDR_HIGH_ADDR);\n-\n-\t/* now update the dma last descriptor */\n-\twritel(((uint32_t)(dma->tx_desc_aligned)) & D64_XP_LD_MASK,\n-\t GMAC0_DMA_TX_PTR_ADDR);\n-\n-\treturn 0;\n-}\n-\n-static int dma_rx_init(struct eth_dma *dma)\n-{\n-\tuint32_t last_desc;\n-\tdma64dd_t *descp = NULL;\n-\tuint8_t *bufp;\n-\tuint32_t ctrl;\n-\tint i;\n-\n-\tdebug(\"%s enter\\n\", __func__);\n-\n-\t/* clear descriptor memory */\n-\tmemset((void *)(dma->rx_desc_aligned), 0,\n-\t RX_BUF_NUM * DESCP_SIZE_ALIGNED);\n-\t/* clear buffer memory */\n-\tmemset(dma->rx_buf, 0, RX_BUF_NUM * RX_BUF_SIZE_ALIGNED);\n-\n-\t/* Initialize RX DMA descriptor table */\n-\tfor (i = 0; i < RX_BUF_NUM; i++) {\n-\t\tdescp = (dma64dd_t *)(dma->rx_desc_aligned) + i;\n-\t\tbufp = dma->rx_buf + i * RX_BUF_SIZE_ALIGNED;\n-\t\tctrl = 0;\n-\t\t/* if last descr set endOfTable */\n-\t\tif (i == (RX_BUF_NUM - 1))\n-\t\t\tctrl = D64_CTRL1_EOT;\n-\t\tdescp->ctrl1 = ctrl;\n-\t\tdescp->ctrl2 = RX_BUF_SIZE_ALIGNED;\n-\t\tdescp->addrlow = (uint32_t)bufp;\n-\t\tdescp->addrhigh = 0;\n-\n-\t\tlast_desc = ((uint32_t)(descp) & D64_XP_LD_MASK)\n-\t\t\t\t+ sizeof(dma64dd_t);\n-\t}\n-\n-\tdescp = dma->rx_desc_aligned;\n-\tbufp = dma->rx_buf;\n-\t/* flush descriptor and buffer */\n-\tflush_dcache_range((unsigned long)descp,\n-\t\t\t (unsigned long)descp +\n-\t\t\t DESCP_SIZE_ALIGNED * RX_BUF_NUM);\n-\tflush_dcache_range((unsigned long)(bufp),\n-\t\t\t (unsigned long)bufp +\n-\t\t\t RX_BUF_SIZE_ALIGNED * RX_BUF_NUM);\n-\n-\t/* initailize the DMA channel */\n-\twritel((uint32_t)descp, GMAC0_DMA_RX_ADDR_LOW_ADDR);\n-\twritel(0, GMAC0_DMA_RX_ADDR_HIGH_ADDR);\n-\n-\t/* now update the dma last descriptor */\n-\twritel(last_desc, GMAC0_DMA_RX_PTR_ADDR);\n-\n-\treturn 0;\n-}\n-\n-static int dma_init(struct eth_dma *dma)\n-{\n-\tdebug(\" %s enter\\n\", __func__);\n-\n-\t/*\n-\t * Default flags: For backwards compatibility both\n-\t * Rx Overflow Continue and Parity are DISABLED.\n-\t */\n-\tdma_ctrlflags(DMA_CTRL_ROC | DMA_CTRL_PEN, 0);\n-\n-\tdebug(\"rx burst len 0x%x\\n\",\n-\t (readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK)\n-\t >> D64_RC_BL_SHIFT);\n-\tdebug(\"tx burst len 0x%x\\n\",\n-\t (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_BL_MASK)\n-\t >> D64_XC_BL_SHIFT);\n-\n-\tdma_tx_init(dma);\n-\tdma_rx_init(dma);\n-\n-\t/* From end of chip_init() */\n-\t/* enable the overflow continue feature and disable parity */\n-\tdma_ctrlflags(DMA_CTRL_ROC | DMA_CTRL_PEN /* mask */,\n-\t\t DMA_CTRL_ROC /* value */);\n-\n-\treturn 0;\n-}\n-\n-static int dma_deinit(struct eth_dma *dma)\n-{\n-\tdebug(\" %s enter\\n\", __func__);\n-\n-\tgmac_disable_dma(dma, MAC_DMA_RX);\n-\tgmac_disable_dma(dma, MAC_DMA_TX);\n-\n-\tfree(dma->tx_buf);\n-\tdma->tx_buf = NULL;\n-\tfree(dma->tx_desc_aligned);\n-\tdma->tx_desc_aligned = NULL;\n-\n-\tfree(dma->rx_buf);\n-\tdma->rx_buf = NULL;\n-\tfree(dma->rx_desc_aligned);\n-\tdma->rx_desc_aligned = NULL;\n-\n-\treturn 0;\n-}\n-\n-int gmac_tx_packet(struct eth_dma *dma, void *packet, int length)\n-{\n-\tuint8_t *bufp = dma->tx_buf + dma->cur_tx_index * TX_BUF_SIZE_ALIGNED;\n-\n-\t/* kick off the dma */\n-\tsize_t len = length;\n-\tint txout = dma->cur_tx_index;\n-\tuint32_t flags;\n-\tdma64dd_t *descp = NULL;\n-\tuint32_t ctrl;\n-\tuint32_t last_desc = (((uint32_t)dma->tx_desc_aligned) +\n-\t\t\t sizeof(dma64dd_t)) & D64_XP_LD_MASK;\n-\tsize_t buflen;\n-\n-\tdebug(\"%s enter\\n\", __func__);\n-\n-\t/* load the buffer */\n-\tmemcpy(bufp, packet, len);\n-\n-\t/* Add 4 bytes for Ethernet FCS/CRC */\n-\tbuflen = len + 4;\n-\n-\tctrl = (buflen & D64_CTRL2_BC_MASK);\n-\n-\t/* the transmit will only be one frame or set SOF, EOF */\n-\t/* also set int on completion */\n-\tflags = D64_CTRL1_SOF | D64_CTRL1_IOC | D64_CTRL1_EOF;\n-\n-\t/* txout points to the descriptor to uset */\n-\t/* if last descriptor then set EOT */\n-\tif (txout == (TX_BUF_NUM - 1)) {\n-\t\tflags |= D64_CTRL1_EOT;\n-\t\tlast_desc = ((uint32_t)(dma->tx_desc_aligned)) & D64_XP_LD_MASK;\n-\t}\n-\n-\t/* write the descriptor */\n-\tdescp = ((dma64dd_t *)(dma->tx_desc_aligned)) + txout;\n-\tdescp->addrlow = (uint32_t)bufp;\n-\tdescp->addrhigh = 0;\n-\tdescp->ctrl1 = flags;\n-\tdescp->ctrl2 = ctrl;\n-\n-\t/* flush descriptor and buffer */\n-\tflush_dcache_range((unsigned long)dma->tx_desc_aligned,\n-\t\t\t (unsigned long)dma->tx_desc_aligned +\n-\t\t\t DESCP_SIZE_ALIGNED * TX_BUF_NUM);\n-\tflush_dcache_range((unsigned long)bufp,\n-\t\t\t (unsigned long)bufp + TX_BUF_SIZE_ALIGNED);\n-\n-\t/* now update the dma last descriptor */\n-\twritel(last_desc, GMAC0_DMA_TX_PTR_ADDR);\n-\n-\t/* tx dma should be enabled so packet should go out */\n-\n-\t/* update txout */\n-\tdma->cur_tx_index = (txout + 1) & (TX_BUF_NUM - 1);\n-\n-\treturn 0;\n-}\n-\n-bool gmac_check_tx_done(struct eth_dma *dma)\n-{\n-\t/* wait for tx to complete */\n-\tuint32_t intstatus;\n-\tbool xfrdone = false;\n-\n-\tdebug(\"%s enter\\n\", __func__);\n-\n-\tintstatus = readl(GMAC0_INT_STATUS_ADDR);\n-\n-\tdebug(\"int(0x%x)\\n\", intstatus);\n-\tif (intstatus & (I_XI0 | I_XI1 | I_XI2 | I_XI3)) {\n-\t\txfrdone = true;\n-\t\t/* clear the int bits */\n-\t\tintstatus &= ~(I_XI0 | I_XI1 | I_XI2 | I_XI3);\n-\t\twritel(intstatus, GMAC0_INT_STATUS_ADDR);\n-\t} else {\n-\t\tdebug(\"Tx int(0x%x)\\n\", intstatus);\n-\t}\n-\n-\treturn xfrdone;\n-}\n-\n-int gmac_check_rx_done(struct eth_dma *dma, uint8_t *buf)\n-{\n-\tvoid *bufp, *datap;\n-\tsize_t rcvlen = 0, buflen = 0;\n-\tuint32_t stat0 = 0, stat1 = 0;\n-\tuint32_t control, offset;\n-\tuint8_t statbuf[HWRXOFF*2];\n-\n-\tint index, curr, active;\n-\tdma64dd_t *descp = NULL;\n-\n-\t/* udelay(50); */\n-\n-\t/*\n-\t * this api will check if a packet has been received.\n-\t * If so it will return the address of the buffer and current\n-\t * descriptor index will be incremented to the\n-\t * next descriptor. Once done with the frame the buffer should be\n-\t * added back onto the descriptor and the lastdscr should be updated\n-\t * to this descriptor.\n-\t */\n-\tindex = dma->cur_rx_index;\n-\toffset = (uint32_t)(dma->rx_desc_aligned);\n-\tstat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR) & D64_RS0_CD_MASK;\n-\tstat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR) & D64_RS0_CD_MASK;\n-\tcurr = ((stat0 - offset) & D64_RS0_CD_MASK) / sizeof(dma64dd_t);\n-\tactive = ((stat1 - offset) & D64_RS0_CD_MASK) / sizeof(dma64dd_t);\n-\n-\t/* check if any frame */\n-\tif (index == curr)\n-\t\treturn -1;\n-\n-\tdebug(\"received packet\\n\");\n-\tdebug(\"expect(0x%x) curr(0x%x) active(0x%x)\\n\", index, curr, active);\n-\t/* remove warning */\n-\tif (index == active)\n-\t\t;\n-\n-\t/* get the packet pointer that corresponds to the rx descriptor */\n-\tbufp = dma->rx_buf + index * RX_BUF_SIZE_ALIGNED;\n-\n-\tdescp = (dma64dd_t *)(dma->rx_desc_aligned) + index;\n-\t/* flush descriptor and buffer */\n-\tflush_dcache_range((unsigned long)dma->rx_desc_aligned,\n-\t\t\t (unsigned long)dma->rx_desc_aligned +\n-\t\t\t DESCP_SIZE_ALIGNED * RX_BUF_NUM);\n-\tflush_dcache_range((unsigned long)bufp,\n-\t\t\t (unsigned long)bufp + RX_BUF_SIZE_ALIGNED);\n-\n-\tbuflen = (descp->ctrl2 & D64_CTRL2_BC_MASK);\n-\n-\tstat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR);\n-\tstat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR);\n-\n-\tdebug(\"bufp(0x%x) index(0x%x) buflen(0x%x) stat0(0x%x) stat1(0x%x)\\n\",\n-\t (uint32_t)bufp, index, buflen, stat0, stat1);\n-\n-\tdma->cur_rx_index = (index + 1) & (RX_BUF_NUM - 1);\n-\n-\t/* get buffer offset */\n-\tcontrol = readl(GMAC0_DMA_RX_CTRL_ADDR);\n-\toffset = (control & D64_RC_RO_MASK) >> D64_RC_RO_SHIFT;\n-\trcvlen = *(uint16_t *)bufp;\n-\n-\tdebug(\"Received %d bytes\\n\", rcvlen);\n-\t/* copy status into temp buf then copy data from rx buffer */\n-\tmemcpy(statbuf, bufp, offset);\n-\tdatap = (void *)((uint32_t)bufp + offset);\n-\tmemcpy(buf, datap, rcvlen);\n-\n-\t/* update descriptor that is being added back on ring */\n-\tdescp->ctrl2 = RX_BUF_SIZE_ALIGNED;\n-\tdescp->addrlow = (uint32_t)bufp;\n-\tdescp->addrhigh = 0;\n-\t/* flush descriptor */\n-\tflush_dcache_range((unsigned long)dma->rx_desc_aligned,\n-\t\t\t (unsigned long)dma->rx_desc_aligned +\n-\t\t\t DESCP_SIZE_ALIGNED * RX_BUF_NUM);\n-\n-\t/* set the lastdscr for the rx ring */\n-\twritel(((uint32_t)descp) & D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR);\n-\n-\treturn (int)rcvlen;\n-}\n-\n-static int gmac_disable_dma(struct eth_dma *dma, int dir)\n-{\n-\tint status;\n-\n-\tdebug(\"%s enter\\n\", __func__);\n-\n-\tif (dir == MAC_DMA_TX) {\n-\t\t/* address PR8249/PR7577 issue */\n-\t\t/* suspend tx DMA first */\n-\t\twritel(D64_XC_SE, GMAC0_DMA_TX_CTRL_ADDR);\n-\t\tSPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) &\n-\t\t\t\t D64_XS0_XS_MASK)) !=\n-\t\t\t D64_XS0_XS_DISABLED) &&\n-\t\t\t (status != D64_XS0_XS_IDLE) &&\n-\t\t\t (status != D64_XS0_XS_STOPPED), 10000);\n-\n-\t\t/*\n-\t\t * PR2414 WAR: DMA engines are not disabled until\n-\t\t * transfer finishes\n-\t\t */\n-\t\twritel(0, GMAC0_DMA_TX_CTRL_ADDR);\n-\t\tSPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) &\n-\t\t\t\t D64_XS0_XS_MASK)) !=\n-\t\t\t D64_XS0_XS_DISABLED), 10000);\n-\n-\t\t/* wait for the last transaction to complete */\n-\t\tudelay(2);\n-\n-\t\tstatus = (status == D64_XS0_XS_DISABLED);\n-\t} else {\n-\t\t/*\n-\t\t * PR2414 WAR: DMA engines are not disabled until\n-\t\t * transfer finishes\n-\t\t */\n-\t\twritel(0, GMAC0_DMA_RX_CTRL_ADDR);\n-\t\tSPINWAIT(((status = (readl(GMAC0_DMA_RX_STATUS0_ADDR) &\n-\t\t\t\t D64_RS0_RS_MASK)) !=\n-\t\t\t D64_RS0_RS_DISABLED), 10000);\n-\n-\t\tstatus = (status == D64_RS0_RS_DISABLED);\n-\t}\n-\n-\treturn status;\n-}\n-\n-static int gmac_enable_dma(struct eth_dma *dma, int dir)\n-{\n-\tuint32_t control;\n-\n-\tdebug(\"%s enter\\n\", __func__);\n-\n-\tif (dir == MAC_DMA_TX) {\n-\t\tdma->cur_tx_index = 0;\n-\n-\t\t/*\n-\t\t * These bits 20:18 (burstLen) of control register can be\n-\t\t * written but will take effect only if these bits are\n-\t\t * valid. So this will not affect previous versions\n-\t\t * of the DMA. They will continue to have those bits set to 0.\n-\t\t */\n-\t\tcontrol = readl(GMAC0_DMA_TX_CTRL_ADDR);\n-\n-\t\tcontrol |= D64_XC_XE;\n-\t\tif ((g_dmactrlflags & DMA_CTRL_PEN) == 0)\n-\t\t\tcontrol |= D64_XC_PD;\n-\n-\t\twritel(control, GMAC0_DMA_TX_CTRL_ADDR);\n-\n-\t\t/* initailize the DMA channel */\n-\t\twritel((uint32_t)(dma->tx_desc_aligned),\n-\t\t GMAC0_DMA_TX_ADDR_LOW_ADDR);\n-\t\twritel(0, GMAC0_DMA_TX_ADDR_HIGH_ADDR);\n-\t} else {\n-\t\tdma->cur_rx_index = 0;\n-\n-\t\tcontrol = (readl(GMAC0_DMA_RX_CTRL_ADDR) &\n-\t\t\t D64_RC_AE) | D64_RC_RE;\n-\n-\t\tif ((g_dmactrlflags & DMA_CTRL_PEN) == 0)\n-\t\t\tcontrol |= D64_RC_PD;\n-\n-\t\tif (g_dmactrlflags & DMA_CTRL_ROC)\n-\t\t\tcontrol |= D64_RC_OC;\n-\n-\t\t/*\n-\t\t * These bits 20:18 (burstLen) of control register can be\n-\t\t * written but will take effect only if these bits are\n-\t\t * valid. So this will not affect previous versions\n-\t\t * of the DMA. They will continue to have those bits set to 0.\n-\t\t */\n-\t\tcontrol &= ~D64_RC_BL_MASK;\n-\t\t/* Keep default Rx burstlen */\n-\t\tcontrol |= readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK;\n-\t\tcontrol |= HWRXOFF << D64_RC_RO_SHIFT;\n-\n-\t\twritel(control, GMAC0_DMA_RX_CTRL_ADDR);\n-\n-\t\t/*\n-\t\t * the rx descriptor ring should have\n-\t\t * the addresses set properly;\n-\t\t * set the lastdscr for the rx ring\n-\t\t */\n-\t\twritel(((uint32_t)(dma->rx_desc_aligned) +\n-\t\t\t(RX_BUF_NUM - 1) * RX_BUF_SIZE_ALIGNED) &\n-\t\t D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR);\n-\t}\n-\n-\treturn 0;\n-}\n-\n-bool gmac_mii_busywait(unsigned int timeout)\n-{\n-\tuint32_t tmp = 0;\n-\n-\twhile (timeout > 10) {\n-\t\ttmp = readl(GMAC_MII_CTRL_ADDR);\n-\t\tif (tmp & (1 << GMAC_MII_BUSY_SHIFT)) {\n-\t\t\tudelay(10);\n-\t\t\ttimeout -= 10;\n-\t\t} else {\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\treturn tmp & (1 << GMAC_MII_BUSY_SHIFT);\n-}\n-\n-int gmac_miiphy_read(struct mii_dev *bus, int phyaddr, int devad, int reg)\n-{\n-\tuint32_t tmp = 0;\n-\tu16 value = 0;\n-\n-\t/* Busy wait timeout is 1ms */\n-\tif (gmac_mii_busywait(1000)) {\n-\t\tpr_err(\"%s: Prepare MII read: MII/MDIO busy\\n\", __func__);\n-\t\treturn -1;\n-\t}\n-\n-\t/* Read operation */\n-\ttmp = GMAC_MII_DATA_READ_CMD;\n-\ttmp |= (phyaddr << GMAC_MII_PHY_ADDR_SHIFT) |\n-\t\t(reg << GMAC_MII_PHY_REG_SHIFT);\n-\tdebug(\"MII read cmd 0x%x, phy 0x%x, reg 0x%x\\n\", tmp, phyaddr, reg);\n-\twritel(tmp, GMAC_MII_DATA_ADDR);\n-\n-\tif (gmac_mii_busywait(1000)) {\n-\t\tpr_err(\"%s: MII read failure: MII/MDIO busy\\n\", __func__);\n-\t\treturn -1;\n-\t}\n-\n-\tvalue = readl(GMAC_MII_DATA_ADDR) & 0xffff;\n-\tdebug(\"MII read data 0x%x\\n\", value);\n-\treturn value;\n-}\n-\n-int gmac_miiphy_write(struct mii_dev *bus, int phyaddr, int devad, int reg,\n-\t\t u16 value)\n-{\n-\tuint32_t tmp = 0;\n-\n-\t/* Busy wait timeout is 1ms */\n-\tif (gmac_mii_busywait(1000)) {\n-\t\tpr_err(\"%s: Prepare MII write: MII/MDIO busy\\n\", __func__);\n-\t\treturn -1;\n-\t}\n-\n-\t/* Write operation */\n-\ttmp = GMAC_MII_DATA_WRITE_CMD | (value & 0xffff);\n-\ttmp |= ((phyaddr << GMAC_MII_PHY_ADDR_SHIFT) |\n-\t\t(reg << GMAC_MII_PHY_REG_SHIFT));\n-\tdebug(\"MII write cmd 0x%x, phy 0x%x, reg 0x%x, data 0x%x\\n\",\n-\t tmp, phyaddr, reg, value);\n-\twritel(tmp, GMAC_MII_DATA_ADDR);\n-\n-\tif (gmac_mii_busywait(1000)) {\n-\t\tpr_err(\"%s: MII write failure: MII/MDIO busy\\n\", __func__);\n-\t\treturn -1;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-void gmac_init_reset(void)\n-{\n-\tdebug(\"%s enter\\n\", __func__);\n-\n-\t/* set command config reg CC_SR */\n-\treg32_set_bits(UNIMAC0_CMD_CFG_ADDR, CC_SR);\n-\tudelay(GMAC_RESET_DELAY);\n-}\n-\n-void gmac_clear_reset(void)\n-{\n-\tdebug(\"%s enter\\n\", __func__);\n-\n-\t/* clear command config reg CC_SR */\n-\treg32_clear_bits(UNIMAC0_CMD_CFG_ADDR, CC_SR);\n-\tudelay(GMAC_RESET_DELAY);\n-}\n-\n-static void gmac_enable_local(bool en)\n-{\n-\tuint32_t cmdcfg;\n-\n-\tdebug(\"%s enter\\n\", __func__);\n-\n-\t/* read command config reg */\n-\tcmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);\n-\n-\t/* put mac in reset */\n-\tgmac_init_reset();\n-\n-\tcmdcfg |= CC_SR;\n-\n-\t/* first deassert rx_ena and tx_ena while in reset */\n-\tcmdcfg &= ~(CC_RE | CC_TE);\n-\t/* write command config reg */\n-\twritel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);\n-\n-\t/* bring mac out of reset */\n-\tgmac_clear_reset();\n-\n-\t/* if not enable exit now */\n-\tif (!en)\n-\t\treturn;\n-\n-\t/* enable the mac transmit and receive paths now */\n-\tudelay(2);\n-\tcmdcfg &= ~CC_SR;\n-\tcmdcfg |= (CC_RE | CC_TE);\n-\n-\t/* assert rx_ena and tx_ena when out of reset to enable the mac */\n-\twritel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);\n-\n-\treturn;\n-}\n-\n-int gmac_enable(void)\n-{\n-\tgmac_enable_local(1);\n-\n-\t/* clear interrupts */\n-\twritel(I_INTMASK, GMAC0_INT_STATUS_ADDR);\n-\treturn 0;\n-}\n-\n-int gmac_disable(void)\n-{\n-\tgmac_enable_local(0);\n-\treturn 0;\n-}\n-\n-int gmac_set_speed(int speed, int duplex)\n-{\n-\tuint32_t cmdcfg;\n-\tuint32_t hd_ena;\n-\tuint32_t speed_cfg;\n-\n-\thd_ena = duplex ? 0 : CC_HD;\n-\tif (speed == 1000) {\n-\t\tspeed_cfg = 2;\n-\t} else if (speed == 100) {\n-\t\tspeed_cfg = 1;\n-\t} else if (speed == 10) {\n-\t\tspeed_cfg = 0;\n-\t} else {\n-\t\tpr_err(\"%s: Invalid GMAC speed(%d)!\\n\", __func__, speed);\n-\t\treturn -1;\n-\t}\n-\n-\tcmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);\n-\tcmdcfg &= ~(CC_ES_MASK | CC_HD);\n-\tcmdcfg |= ((speed_cfg << CC_ES_SHIFT) | hd_ena);\n-\n-\tprintf(\"Change GMAC speed to %dMB\\n\", speed);\n-\tdebug(\"GMAC speed cfg 0x%x\\n\", cmdcfg);\n-\twritel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);\n-\n-\treturn 0;\n-}\n-\n-int gmac_set_mac_addr(unsigned char *mac)\n-{\n-\t/* set our local address */\n-\tdebug(\"GMAC: %02x:%02x:%02x:%02x:%02x:%02x\\n\",\n-\t mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);\n-\twritel(htonl(*(uint32_t *)mac), UNIMAC0_MAC_MSB_ADDR);\n-\twritew(htons(*(uint32_t *)&mac[4]), UNIMAC0_MAC_LSB_ADDR);\n-\n-\treturn 0;\n-}\n-\n-int gmac_mac_init(struct eth_device *dev)\n-{\n-\tstruct eth_info *eth = (struct eth_info *)(dev->priv);\n-\tstruct eth_dma *dma = &(eth->dma);\n-\n-\tuint32_t tmp;\n-\tuint32_t cmdcfg;\n-\tint chipid;\n-\n-\tdebug(\"%s enter\\n\", __func__);\n-\n-\t/* Always use GMAC0 */\n-\tprintf(\"Using GMAC%d\\n\", 0);\n-\n-\t/* Reset AMAC0 core */\n-\twritel(0, AMAC0_IDM_RESET_ADDR);\n-\ttmp = readl(AMAC0_IO_CTRL_DIRECT_ADDR);\n-\t/* Set clock */\n-\ttmp &= ~(1 << AMAC0_IO_CTRL_CLK_250_SEL_SHIFT);\n-\ttmp |= (1 << AMAC0_IO_CTRL_GMII_MODE_SHIFT);\n-\t/* Set Tx clock */\n-\ttmp &= ~(1 << AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT);\n-\twritel(tmp, AMAC0_IO_CTRL_DIRECT_ADDR);\n-\n-\t/* reset gmac */\n-\t/*\n-\t * As AMAC is just reset, NO need?\n-\t * set eth_data into loopback mode to ensure no rx traffic\n-\t * gmac_loopback(eth_data, TRUE);\n-\t * ET_TRACE((\"%s gmac loopback\\n\", __func__));\n-\t * udelay(1);\n-\t */\n-\n-\tcmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);\n-\tcmdcfg &= ~(CC_TE | CC_RE | CC_RPI | CC_TAI | CC_HD | CC_ML |\n-\t\t CC_CFE | CC_RL | CC_RED | CC_PE | CC_TPI |\n-\t\t CC_PAD_EN | CC_PF);\n-\tcmdcfg |= (CC_PROM | CC_NLC | CC_CFE);\n-\t/* put mac in reset */\n-\tgmac_init_reset();\n-\twritel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);\n-\tgmac_clear_reset();\n-\n-\t/* enable clear MIB on read */\n-\treg32_set_bits(GMAC0_DEV_CTRL_ADDR, DC_MROR);\n-\t/* PHY: set smi_master to drive mdc_clk */\n-\treg32_set_bits(GMAC0_PHY_CTRL_ADDR, PC_MTE);\n-\n-\t/* clear persistent sw intstatus */\n-\twritel(0, GMAC0_INT_STATUS_ADDR);\n-\n-\tif (dma_init(dma) < 0) {\n-\t\tpr_err(\"%s: GMAC dma_init failed\\n\", __func__);\n-\t\tgoto err_exit;\n-\t}\n-\n-\tchipid = CHIPID;\n-\tprintf(\"%s: Chip ID: 0x%x\\n\", __func__, chipid);\n-\n-\t/* set switch bypass mode */\n-\ttmp = readl(SWITCH_GLOBAL_CONFIG_ADDR);\n-\ttmp |= (1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT);\n-\n-\t/* Switch mode */\n-\t/* tmp &= ~(1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT); */\n-\n-\twritel(tmp, SWITCH_GLOBAL_CONFIG_ADDR);\n-\n-\ttmp = readl(CRMU_CHIP_IO_PAD_CONTROL_ADDR);\n-\ttmp &= ~(1 << CDRU_IOMUX_FORCE_PAD_IN_SHIFT);\n-\twritel(tmp, CRMU_CHIP_IO_PAD_CONTROL_ADDR);\n-\n-\t/* Set MDIO to internal GPHY */\n-\ttmp = readl(GMAC_MII_CTRL_ADDR);\n-\t/* Select internal MDC/MDIO bus*/\n-\ttmp &= ~(1 << GMAC_MII_CTRL_BYP_SHIFT);\n-\t/* select MDC/MDIO connecting to on-chip internal PHYs */\n-\ttmp &= ~(1 << GMAC_MII_CTRL_EXT_SHIFT);\n-\t/*\n-\t * give bit[6:0](MDCDIV) with required divisor to set\n-\t * the MDC clock frequency, 66MHZ/0x1A=2.5MHZ\n-\t */\n-\ttmp |= 0x1A;\n-\n-\twritel(tmp, GMAC_MII_CTRL_ADDR);\n-\n-\tif (gmac_mii_busywait(1000)) {\n-\t\tpr_err(\"%s: Configure MDIO: MII/MDIO busy\\n\", __func__);\n-\t\tgoto err_exit;\n-\t}\n-\n-\t/* Configure GMAC0 */\n-\t/* enable one rx interrupt per received frame */\n-\twritel(1 << GMAC0_IRL_FRAMECOUNT_SHIFT, GMAC0_INTR_RECV_LAZY_ADDR);\n-\n-\t/* read command config reg */\n-\tcmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);\n-\t/* enable 802.3x tx flow control (honor received PAUSE frames) */\n-\tcmdcfg &= ~CC_RPI;\n-\t/* enable promiscuous mode */\n-\tcmdcfg |= CC_PROM;\n-\t/* Disable loopback mode */\n-\tcmdcfg &= ~CC_ML;\n-\t/* set the speed */\n-\tcmdcfg &= ~(CC_ES_MASK | CC_HD);\n-\t/* Set to 1Gbps and full duplex by default */\n-\tcmdcfg |= (2 << CC_ES_SHIFT);\n-\n-\t/* put mac in reset */\n-\tgmac_init_reset();\n-\t/* write register */\n-\twritel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);\n-\t/* bring mac out of reset */\n-\tgmac_clear_reset();\n-\n-\t/* set max frame lengths; account for possible vlan tag */\n-\twritel(PKTSIZE + 32, UNIMAC0_FRM_LENGTH_ADDR);\n-\n-\treturn 0;\n-\n-err_exit:\n-\tdma_deinit(dma);\n-\treturn -1;\n-}\n-\n-int gmac_add(struct eth_device *dev)\n-{\n-\tstruct eth_info *eth = (struct eth_info *)(dev->priv);\n-\tstruct eth_dma *dma = &(eth->dma);\n-\tvoid *tmp;\n-\n-\t/*\n-\t * Desc has to be 16-byte aligned. But for dcache flush it must be\n-\t * aligned to ARCH_DMA_MINALIGN.\n-\t */\n-\ttmp = memalign(ARCH_DMA_MINALIGN, DESCP_SIZE_ALIGNED * TX_BUF_NUM);\n-\tif (tmp == NULL) {\n-\t\tprintf(\"%s: Failed to allocate TX desc Buffer\\n\", __func__);\n-\t\treturn -1;\n-\t}\n-\n-\tdma->tx_desc_aligned = (void *)tmp;\n-\tdebug(\"TX Descriptor Buffer: %p; length: 0x%x\\n\",\n-\t dma->tx_desc_aligned, DESCP_SIZE_ALIGNED * TX_BUF_NUM);\n-\n-\ttmp = memalign(ARCH_DMA_MINALIGN, TX_BUF_SIZE_ALIGNED * TX_BUF_NUM);\n-\tif (tmp == NULL) {\n-\t\tprintf(\"%s: Failed to allocate TX Data Buffer\\n\", __func__);\n-\t\tfree(dma->tx_desc_aligned);\n-\t\treturn -1;\n-\t}\n-\tdma->tx_buf = (uint8_t *)tmp;\n-\tdebug(\"TX Data Buffer: %p; length: 0x%x\\n\",\n-\t dma->tx_buf, TX_BUF_SIZE_ALIGNED * TX_BUF_NUM);\n-\n-\t/* Desc has to be 16-byte aligned */\n-\ttmp = memalign(ARCH_DMA_MINALIGN, DESCP_SIZE_ALIGNED * RX_BUF_NUM);\n-\tif (tmp == NULL) {\n-\t\tprintf(\"%s: Failed to allocate RX Descriptor\\n\", __func__);\n-\t\tfree(dma->tx_desc_aligned);\n-\t\tfree(dma->tx_buf);\n-\t\treturn -1;\n-\t}\n-\tdma->rx_desc_aligned = (void *)tmp;\n-\tdebug(\"RX Descriptor Buffer: %p, length: 0x%x\\n\",\n-\t dma->rx_desc_aligned, DESCP_SIZE_ALIGNED * RX_BUF_NUM);\n-\n-\ttmp = memalign(ARCH_DMA_MINALIGN, RX_BUF_SIZE_ALIGNED * RX_BUF_NUM);\n-\tif (tmp == NULL) {\n-\t\tprintf(\"%s: Failed to allocate RX Data Buffer\\n\", __func__);\n-\t\tfree(dma->tx_desc_aligned);\n-\t\tfree(dma->tx_buf);\n-\t\tfree(dma->rx_desc_aligned);\n-\t\treturn -1;\n-\t}\n-\tdma->rx_buf = (uint8_t *)tmp;\n-\tdebug(\"RX Data Buffer: %p; length: 0x%x\\n\",\n-\t dma->rx_buf, RX_BUF_SIZE_ALIGNED * RX_BUF_NUM);\n-\n-\tg_dmactrlflags = 0;\n-\n-\teth->phy_interface = PHY_INTERFACE_MODE_GMII;\n-\n-\tdma->tx_packet = gmac_tx_packet;\n-\tdma->check_tx_done = gmac_check_tx_done;\n-\n-\tdma->check_rx_done = gmac_check_rx_done;\n-\n-\tdma->enable_dma = gmac_enable_dma;\n-\tdma->disable_dma = gmac_disable_dma;\n-\n-\teth->miiphy_read = gmac_miiphy_read;\n-\teth->miiphy_write = gmac_miiphy_write;\n-\n-\teth->mac_init = gmac_mac_init;\n-\teth->disable_mac = gmac_disable;\n-\teth->enable_mac = gmac_enable;\n-\teth->set_mac_addr = gmac_set_mac_addr;\n-\teth->set_mac_speed = gmac_set_speed;\n-\n-\treturn 0;\n-}\ndiff --git a/drivers/net/bcm-sf2-eth-gmac.h b/drivers/net/bcm-sf2-eth-gmac.h\ndeleted file mode 100644\nindex ac5e45d4f906..000000000000\n--- a/drivers/net/bcm-sf2-eth-gmac.h\n+++ /dev/null\n@@ -1,222 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0+ */\n-/*\n- * Copyright 2014 Broadcom Corporation.\n- */\n-\n-#ifndef _BCM_SF2_ETH_GMAC_H_\n-#define _BCM_SF2_ETH_GMAC_H_\n-\n-#define BCM_SF2_ETH_MAC_NAME\t\"gmac\"\n-\n-#ifndef ETHHW_PORT_INT\n-#define ETHHW_PORT_INT\t\t8\n-#endif\n-\n-#define GMAC0_REG_BASE\t\t\t0x18042000\n-#define GMAC0_DEV_CTRL_ADDR\t\tGMAC0_REG_BASE\n-#define GMAC0_INT_STATUS_ADDR\t\t(GMAC0_REG_BASE + 0x020)\n-#define GMAC0_INTR_RECV_LAZY_ADDR\t(GMAC0_REG_BASE + 0x100)\n-#define GMAC0_PHY_CTRL_ADDR\t\t(GMAC0_REG_BASE + 0x188)\n-\n-#define GMAC_DMA_PTR_OFFSET\t\t0x04\n-#define GMAC_DMA_ADDR_LOW_OFFSET\t0x08\n-#define GMAC_DMA_ADDR_HIGH_OFFSET\t0x0c\n-#define GMAC_DMA_STATUS0_OFFSET\t\t0x10\n-#define GMAC_DMA_STATUS1_OFFSET\t\t0x14\n-\n-#define GMAC0_DMA_TX_CTRL_ADDR\t\t(GMAC0_REG_BASE + 0x200)\n-#define GMAC0_DMA_TX_PTR_ADDR \\\n-\t\t(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)\n-#define GMAC0_DMA_TX_ADDR_LOW_ADDR \\\n-\t\t(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)\n-#define GMAC0_DMA_TX_ADDR_HIGH_ADDR \\\n-\t\t(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)\n-#define GMAC0_DMA_TX_STATUS0_ADDR \\\n-\t\t(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)\n-#define GMAC0_DMA_TX_STATUS1_ADDR \\\n-\t\t(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)\n-\n-#define GMAC0_DMA_RX_CTRL_ADDR\t\t(GMAC0_REG_BASE + 0x220)\n-#define GMAC0_DMA_RX_PTR_ADDR \\\n-\t\t(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)\n-#define GMAC0_DMA_RX_ADDR_LOW_ADDR \\\n-\t\t(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)\n-#define GMAC0_DMA_RX_ADDR_HIGH_ADDR \\\n-\t\t(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)\n-#define GMAC0_DMA_RX_STATUS0_ADDR \\\n-\t\t(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)\n-#define GMAC0_DMA_RX_STATUS1_ADDR \\\n-\t\t(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)\n-\n-#define UNIMAC0_CMD_CFG_ADDR\t\t(GMAC0_REG_BASE + 0x808)\n-#define UNIMAC0_MAC_MSB_ADDR\t\t(GMAC0_REG_BASE + 0x80c)\n-#define UNIMAC0_MAC_LSB_ADDR\t\t(GMAC0_REG_BASE + 0x810)\n-#define UNIMAC0_FRM_LENGTH_ADDR\t\t(GMAC0_REG_BASE + 0x814)\n-\n-#define GMAC0_IRL_FRAMECOUNT_SHIFT\t24\n-\n-/* transmit channel control */\n-/* transmit enable */\n-#define D64_XC_XE\t\t0x00000001\n-/* transmit suspend request */\n-#define D64_XC_SE\t\t0x00000002\n-/* parity check disable */\n-#define D64_XC_PD\t\t0x00000800\n-/* BurstLen bits */\n-#define D64_XC_BL_MASK\t\t0x001C0000\n-#define D64_XC_BL_SHIFT\t\t18\n-\n-/* transmit descriptor table pointer */\n-/* last valid descriptor */\n-#define D64_XP_LD_MASK\t\t0x00001fff\n-\n-/* transmit channel status */\n-/* transmit state */\n-#define D64_XS0_XS_MASK\t\t0xf0000000\n-#define D64_XS0_XS_SHIFT\t28\n-#define D64_XS0_XS_DISABLED\t0x00000000\n-#define D64_XS0_XS_ACTIVE\t0x10000000\n-#define D64_XS0_XS_IDLE\t\t0x20000000\n-#define D64_XS0_XS_STOPPED\t0x30000000\n-#define D64_XS0_XS_SUSP\t\t0x40000000\n-\n-/* receive channel control */\n-/* receive enable */\n-#define D64_RC_RE\t\t0x00000001\n-/* address extension bits */\n-#define D64_RC_AE\t\t0x00030000\n-/* overflow continue */\n-#define D64_RC_OC\t\t0x00000400\n-/* parity check disable */\n-#define D64_RC_PD\t\t0x00000800\n-/* receive frame offset */\n-#define D64_RC_RO_MASK\t\t0x000000fe\n-#define D64_RC_RO_SHIFT\t\t1\n-/* BurstLen bits */\n-#define D64_RC_BL_MASK\t\t0x001C0000\n-#define D64_RC_BL_SHIFT\t\t18\n-\n-/* flags for dma controller */\n-/* partity enable */\n-#define DMA_CTRL_PEN\t\t(1 << 0)\n-/* rx overflow continue */\n-#define DMA_CTRL_ROC\t\t(1 << 1)\n-\n-/* receive descriptor table pointer */\n-/* last valid descriptor */\n-#define D64_RP_LD_MASK\t\t0x00001fff\n-\n-/* receive channel status */\n-/* current descriptor pointer */\n-#define D64_RS0_CD_MASK\t\t0x00001fff\n-/* receive state */\n-#define D64_RS0_RS_MASK\t\t0xf0000000\n-#define D64_RS0_RS_SHIFT\t28\n-#define D64_RS0_RS_DISABLED\t0x00000000\n-#define D64_RS0_RS_ACTIVE\t0x10000000\n-#define D64_RS0_RS_IDLE\t\t0x20000000\n-#define D64_RS0_RS_STOPPED\t0x30000000\n-#define D64_RS0_RS_SUSP\t\t0x40000000\n-\n-/* descriptor control flags 1 */\n-/* core specific flags */\n-#define D64_CTRL_COREFLAGS\t0x0ff00000\n-/* end of descriptor table */\n-#define D64_CTRL1_EOT\t\t((uint32_t)1 << 28)\n-/* interrupt on completion */\n-#define D64_CTRL1_IOC\t\t((uint32_t)1 << 29)\n-/* end of frame */\n-#define D64_CTRL1_EOF\t\t((uint32_t)1 << 30)\n-/* start of frame */\n-#define D64_CTRL1_SOF\t\t((uint32_t)1 << 31)\n-\n-/* descriptor control flags 2 */\n-/* buffer byte count. real data len must <= 16KB */\n-#define D64_CTRL2_BC_MASK\t0x00007fff\n-/* address extension bits */\n-#define D64_CTRL2_AE\t\t0x00030000\n-#define D64_CTRL2_AE_SHIFT\t16\n-/* parity bit */\n-#define D64_CTRL2_PARITY\t0x00040000\n-/* control flags in the range [27:20] are core-specific and not defined here */\n-#define D64_CTRL_CORE_MASK\t0x0ff00000\n-\n-#define DC_MROR\t\t0x00000010\n-#define PC_MTE\t\t0x00800000\n-\n-/* command config */\n-#define CC_TE\t\t0x00000001\n-#define CC_RE\t\t0x00000002\n-#define CC_ES_MASK\t0x0000000c\n-#define CC_ES_SHIFT\t2\n-#define CC_PROM\t\t0x00000010\n-#define CC_PAD_EN\t0x00000020\n-#define CC_CF\t\t0x00000040\n-#define CC_PF\t\t0x00000080\n-#define CC_RPI\t\t0x00000100\n-#define CC_TAI\t\t0x00000200\n-#define CC_HD\t\t0x00000400\n-#define CC_HD_SHIFT\t10\n-#define CC_SR\t\t0x00002000\n-#define CC_ML\t\t0x00008000\n-#define CC_AE\t\t0x00400000\n-#define CC_CFE\t\t0x00800000\n-#define CC_NLC\t\t0x01000000\n-#define CC_RL\t\t0x02000000\n-#define CC_RED\t\t0x04000000\n-#define CC_PE\t\t0x08000000\n-#define CC_TPI\t\t0x10000000\n-#define CC_AT\t\t0x20000000\n-\n-#define I_PDEE\t\t0x00000400\n-#define I_PDE\t\t0x00000800\n-#define I_DE\t\t0x00001000\n-#define I_RDU\t\t0x00002000\n-#define I_RFO\t\t0x00004000\n-#define I_XFU\t\t0x00008000\n-#define I_RI\t\t0x00010000\n-#define I_XI0\t\t0x01000000\n-#define I_XI1\t\t0x02000000\n-#define I_XI2\t\t0x04000000\n-#define I_XI3\t\t0x08000000\n-#define I_ERRORS\t(I_PDEE | I_PDE | I_DE | I_RDU | I_RFO | I_XFU)\n-#define DEF_INTMASK\t(I_XI0 | I_XI1 | I_XI2 | I_XI3 | I_RI | I_ERRORS)\n-\n-#define I_INTMASK\t0x0f01fcff\n-\n-#define CHIP_DRU_BASE\t\t\t\t0x0301d000\n-#define CRMU_CHIP_IO_PAD_CONTROL_ADDR\t\t(CHIP_DRU_BASE + 0x0bc)\n-#define SWITCH_GLOBAL_CONFIG_ADDR\t\t(CHIP_DRU_BASE + 0x194)\n-\n-#define CDRU_IOMUX_FORCE_PAD_IN_SHIFT\t\t0\n-#define CDRU_SWITCH_BYPASS_SWITCH_SHIFT\t\t13\n-\n-#define AMAC0_IDM_RESET_ADDR\t\t\t0x18110800\n-#define AMAC0_IO_CTRL_DIRECT_ADDR\t\t0x18110408\n-#define AMAC0_IO_CTRL_CLK_250_SEL_SHIFT\t\t6\n-#define AMAC0_IO_CTRL_GMII_MODE_SHIFT\t\t5\n-#define AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT\t3\n-\n-#define CHIPA_CHIP_ID_ADDR\t\t\t0x18000000\n-#define CHIPID\t\t(readl(CHIPA_CHIP_ID_ADDR) & 0xFFFF)\n-#define CHIPREV\t\t(((readl(CHIPA_CHIP_ID_ADDR) >> 16) & 0xF)\n-#define CHIPSKU\t\t(((readl(CHIPA_CHIP_ID_ADDR) >> 20) & 0xF)\n-\n-#define GMAC_MII_CTRL_ADDR\t\t0x18002000\n-#define GMAC_MII_CTRL_BYP_SHIFT\t\t10\n-#define GMAC_MII_CTRL_EXT_SHIFT\t\t9\n-#define GMAC_MII_DATA_ADDR\t\t0x18002004\n-#define GMAC_MII_DATA_READ_CMD\t\t0x60020000\n-#define GMAC_MII_DATA_WRITE_CMD\t\t0x50020000\n-#define GMAC_MII_BUSY_SHIFT\t\t8\n-#define GMAC_MII_PHY_ADDR_SHIFT\t\t23\n-#define GMAC_MII_PHY_REG_SHIFT\t\t18\n-\n-#define GMAC_RESET_DELAY\t\t2\n-#define HWRXOFF\t\t\t\t30\n-#define MAXNAMEL\t\t\t8\n-#define NUMTXQ\t\t\t\t4\n-\n-int gmac_add(struct eth_device *dev);\n-\n-#endif /* _BCM_SF2_ETH_GMAC_H_ */\ndiff --git a/drivers/net/bcm-sf2-eth.c b/drivers/net/bcm-sf2-eth.c\ndeleted file mode 100644\nindex c10719c6b510..000000000000\n--- a/drivers/net/bcm-sf2-eth.c\n+++ /dev/null\n@@ -1,274 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0+\n-/*\n- * Copyright 2014 Broadcom Corporation.\n- */\n-\n-#include <log.h>\n-#include <malloc.h>\n-#include <net.h>\n-#include <config.h>\n-#include <linux/delay.h>\n-#include <linux/printk.h>\n-\n-#include <phy.h>\n-#include <miiphy.h>\n-\n-#include <asm/io.h>\n-\n-#include <netdev.h>\n-#include \"bcm-sf2-eth.h\"\n-\n-#if defined(CONFIG_BCM_SF2_ETH_GMAC)\n-#include \"bcm-sf2-eth-gmac.h\"\n-#else\n-#error \"bcm_sf2_eth: NEED to define a MAC!\"\n-#endif\n-\n-#define BCM_NET_MODULE_DESCRIPTION\t\"Broadcom Starfighter2 Ethernet driver\"\n-#define BCM_NET_MODULE_VERSION\t\t\"0.1\"\n-#define BCM_SF2_ETH_DEV_NAME\t\t\"bcm_sf2\"\n-\n-static const char banner[] =\n-\tBCM_NET_MODULE_DESCRIPTION \" \" BCM_NET_MODULE_VERSION \"\\n\";\n-\n-static int bcm_sf2_eth_init(struct eth_device *dev)\n-{\n-\tstruct eth_info *eth = (struct eth_info *)(dev->priv);\n-\tstruct eth_dma *dma = &(eth->dma);\n-\tstruct phy_device *phydev;\n-\tint rc = 0;\n-\tint i;\n-\n-\trc = eth->mac_init(dev);\n-\tif (rc) {\n-\t\tpr_err(\"%s: Couldn't cofigure MAC!\\n\", __func__);\n-\t\treturn rc;\n-\t}\n-\n-\t/* disable DMA */\n-\tdma->disable_dma(dma, MAC_DMA_RX);\n-\tdma->disable_dma(dma, MAC_DMA_TX);\n-\n-\teth->port_num = 0;\n-\tdebug(\"Connecting PHY 0...\\n\");\n-\tphydev = phy_connect(miiphy_get_dev_by_name(dev->name),\n-\t\t\t -1, dev, eth->phy_interface);\n-\tif (phydev != NULL) {\n-\t\teth->port[0] = phydev;\n-\t\teth->port_num += 1;\n-\t} else {\n-\t\tdebug(\"No PHY found for port 0\\n\");\n-\t}\n-\n-\tfor (i = 0; i < eth->port_num; i++)\n-\t\tphy_config(eth->port[i]);\n-\n-\treturn rc;\n-}\n-\n-/*\n- * u-boot net functions\n- */\n-\n-static int bcm_sf2_eth_send(struct eth_device *dev, void *packet, int length)\n-{\n-\tstruct eth_dma *dma = &(((struct eth_info *)(dev->priv))->dma);\n-\tuint8_t *buf = (uint8_t *)packet;\n-\tint rc = 0;\n-\tint i = 0;\n-\n-\tdebug(\"%s enter\\n\", __func__);\n-\n-\t/* load buf and start transmit */\n-\trc = dma->tx_packet(dma, buf, length);\n-\tif (rc) {\n-\t\tdebug(\"ERROR - Tx failed\\n\");\n-\t\treturn rc;\n-\t}\n-\n-\twhile (!(dma->check_tx_done(dma))) {\n-\t\tudelay(100);\n-\t\tdebug(\".\");\n-\t\ti++;\n-\t\tif (i > 20) {\n-\t\t\tpr_err(\"%s: Tx timeout: retried 20 times\\n\", __func__);\n-\t\t\trc = -1;\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\tdebug(\"%s exit rc(0x%x)\\n\", __func__, rc);\n-\treturn rc;\n-}\n-\n-static int bcm_sf2_eth_receive(struct eth_device *dev)\n-{\n-\tstruct eth_dma *dma = &(((struct eth_info *)(dev->priv))->dma);\n-\tuint8_t *buf = (uint8_t *)net_rx_packets[0];\n-\tint rcvlen;\n-\tint rc = 0;\n-\tint i = 0;\n-\n-\twhile (1) {\n-\t\t/* Poll Rx queue to get a packet */\n-\t\trcvlen = dma->check_rx_done(dma, buf);\n-\t\tif (rcvlen < 0) {\n-\t\t\t/* No packet received */\n-\t\t\trc = -1;\n-\t\t\tdebug(\"\\nNO More Rx\\n\");\n-\t\t\tbreak;\n-\t\t} else if ((rcvlen == 0) || (rcvlen > RX_BUF_SIZE)) {\n-\t\t\tpr_err(\"%s: Wrong Ethernet packet size (%d B), skip!\\n\",\n-\t\t\t __func__, rcvlen);\n-\t\t\tbreak;\n-\t\t} else {\n-\t\t\tdebug(\"recieved\\n\");\n-\n-\t\t\t/* Forward received packet to uboot network handler */\n-\t\t\tnet_process_received_packet(buf, rcvlen);\n-\n-\t\t\tif (++i >= PKTBUFSRX)\n-\t\t\t\ti = 0;\n-\t\t\tbuf = net_rx_packets[i];\n-\t\t}\n-\t}\n-\n-\treturn rc;\n-}\n-\n-static int bcm_sf2_eth_write_hwaddr(struct eth_device *dev)\n-{\n-\tstruct eth_info *eth = (struct eth_info *)(dev->priv);\n-\n-\tprintf(\" ETH MAC: %02x:%02x:%02x:%02x:%02x:%02x\\n\",\n-\t dev->enetaddr[0], dev->enetaddr[1], dev->enetaddr[2],\n-\t dev->enetaddr[3], dev->enetaddr[4], dev->enetaddr[5]);\n-\n-\treturn eth->set_mac_addr(dev->enetaddr);\n-}\n-\n-static int bcm_sf2_eth_open(struct eth_device *dev, struct bd_info *bt)\n-{\n-\tstruct eth_info *eth = (struct eth_info *)(dev->priv);\n-\tstruct eth_dma *dma = &(eth->dma);\n-\tint i;\n-\n-\tdebug(\"Enabling BCM SF2 Ethernet.\\n\");\n-\n-\teth->enable_mac();\n-\n-\t/* enable tx and rx DMA */\n-\tdma->enable_dma(dma, MAC_DMA_RX);\n-\tdma->enable_dma(dma, MAC_DMA_TX);\n-\n-\t/*\n-\t * Need to start PHY here because link speed can change\n-\t * before each ethernet operation\n-\t */\n-\tfor (i = 0; i < eth->port_num; i++) {\n-\t\tif (phy_startup(eth->port[i])) {\n-\t\t\tpr_err(\"%s: PHY %d startup failed!\\n\", __func__, i);\n-\t\t\tif (i == CONFIG_BCM_SF2_ETH_DEFAULT_PORT) {\n-\t\t\t\tpr_err(\"%s: No default port %d!\\n\", __func__, i);\n-\t\t\t\treturn -1;\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\t/* Set MAC speed using default port */\n-\ti = CONFIG_BCM_SF2_ETH_DEFAULT_PORT;\n-\tdebug(\"PHY %d: speed:%d, duplex:%d, link:%d\\n\", i,\n-\t eth->port[i]->speed, eth->port[i]->duplex, eth->port[i]->link);\n-\teth->set_mac_speed(eth->port[i]->speed, eth->port[i]->duplex);\n-\n-\tdebug(\"Enable Ethernet Done.\\n\");\n-\n-\treturn 0;\n-}\n-\n-static void bcm_sf2_eth_close(struct eth_device *dev)\n-{\n-\tstruct eth_info *eth = (struct eth_info *)(dev->priv);\n-\tstruct eth_dma *dma = &(eth->dma);\n-\n-\t/* disable DMA */\n-\tdma->disable_dma(dma, MAC_DMA_RX);\n-\tdma->disable_dma(dma, MAC_DMA_TX);\n-\n-\teth->disable_mac();\n-}\n-\n-int bcm_sf2_eth_register(struct bd_info *bis, u8 dev_num)\n-{\n-\tstruct eth_device *dev;\n-\tstruct eth_info *eth;\n-\tint rc;\n-\n-\tdev = (struct eth_device *)malloc(sizeof(struct eth_device));\n-\tif (dev == NULL) {\n-\t\tpr_err(\"%s: Not enough memory!\\n\", __func__);\n-\t\treturn -1;\n-\t}\n-\n-\teth = (struct eth_info *)malloc(sizeof(struct eth_info));\n-\tif (eth == NULL) {\n-\t\tpr_err(\"%s: Not enough memory!\\n\", __func__);\n-\t\treturn -1;\n-\t}\n-\n-\tprintf(banner);\n-\n-\tmemset(dev, 0, sizeof(*dev));\n-\tsprintf(dev->name, \"%s_%s-%hu\", BCM_SF2_ETH_DEV_NAME,\n-\t\tBCM_SF2_ETH_MAC_NAME, dev_num);\n-\n-\tdev->priv = (void *)eth;\n-\tdev->iobase = 0;\n-\n-\tdev->init = bcm_sf2_eth_open;\n-\tdev->halt = bcm_sf2_eth_close;\n-\tdev->send = bcm_sf2_eth_send;\n-\tdev->recv = bcm_sf2_eth_receive;\n-\tdev->write_hwaddr = bcm_sf2_eth_write_hwaddr;\n-\n-#ifdef CONFIG_BCM_SF2_ETH_GMAC\n-\tif (gmac_add(dev)) {\n-\t\tfree(eth);\n-\t\tfree(dev);\n-\t\tpr_err(\"%s: Adding GMAC failed!\\n\", __func__);\n-\t\treturn -1;\n-\t}\n-#else\n-#error \"bcm_sf2_eth: NEED to register a MAC!\"\n-#endif\n-\n-\teth_register(dev);\n-\n-#ifdef CONFIG_CMD_MII\n-\tint retval;\n-\tstruct mii_dev *mdiodev = mdio_alloc();\n-\n-\tif (!mdiodev)\n-\t\treturn -ENOMEM;\n-\tstrlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);\n-\tmdiodev->read = eth->miiphy_read;\n-\tmdiodev->write = eth->miiphy_write;\n-\n-\tretval = mdio_register(mdiodev);\n-\tif (retval < 0)\n-\t\treturn retval;\n-#endif\n-\n-\t/* Initialization */\n-\tdebug(\"Ethernet initialization ...\");\n-\n-\trc = bcm_sf2_eth_init(dev);\n-\tif (rc != 0) {\n-\t\tpr_err(\"%s: configuration failed!\\n\", __func__);\n-\t\treturn -1;\n-\t}\n-\n-\tprintf(\"Basic ethernet functionality initialized\\n\");\n-\n-\treturn 0;\n-}\ndiff --git a/drivers/net/bcm-sf2-eth.h b/drivers/net/bcm-sf2-eth.h\ndeleted file mode 100644\nindex f4dbb4e1952d..000000000000\n--- a/drivers/net/bcm-sf2-eth.h\n+++ /dev/null\n@@ -1,65 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0+ */\n-/*\n- * Copyright 2014-2017 Broadcom.\n- */\n-\n-#ifndef _BCM_SF2_ETH_H_\n-#define _BCM_SF2_ETH_H_\n-\n-#include <phy.h>\n-\n-#define RX_BUF_SIZE\t2048\n-/* RX_BUF_NUM must be power of 2 */\n-#define RX_BUF_NUM\t32\n-\n-#define TX_BUF_SIZE\t2048\n-/* TX_BUF_NUM must be power of 2 */\n-#define TX_BUF_NUM\t2\n-\n-/* Support 2 Ethernet ports now */\n-#define BCM_ETH_MAX_PORT_NUM\t2\n-\n-enum {\n-\tMAC_DMA_TX = 1,\n-\tMAC_DMA_RX = 2\n-};\n-\n-struct eth_dma {\n-\tvoid *tx_desc_aligned;\n-\tvoid *rx_desc_aligned;\n-\n-\tuint8_t *tx_buf;\n-\tuint8_t *rx_buf;\n-\n-\tint cur_tx_index;\n-\tint cur_rx_index;\n-\n-\tint (*tx_packet)(struct eth_dma *dma, void *packet, int length);\n-\tbool (*check_tx_done)(struct eth_dma *dma);\n-\n-\tint (*check_rx_done)(struct eth_dma *dma, uint8_t *buf);\n-\n-\tint (*enable_dma)(struct eth_dma *dma, int dir);\n-\tint (*disable_dma)(struct eth_dma *dma, int dir);\n-};\n-\n-struct eth_info {\n-\tstruct eth_dma dma;\n-\tphy_interface_t phy_interface;\n-\tstruct phy_device *port[BCM_ETH_MAX_PORT_NUM];\n-\tint port_num;\n-\n-\tint (*miiphy_read)(struct mii_dev *bus, int phyaddr, int devad,\n-\t\t\t int reg);\n-\tint (*miiphy_write)(struct mii_dev *bus, int phyaddr, int devad,\n-\t\t\t int reg, u16 value);\n-\n-\tint (*mac_init)(struct eth_device *dev);\n-\tint (*enable_mac)(void);\n-\tint (*disable_mac)(void);\n-\tint (*set_mac_addr)(unsigned char *mac);\n-\tint (*set_mac_speed)(int speed, int duplex);\n-\n-};\n-\n-#endif /* _BCM_SF2_ETH_H_ */\ndiff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h\nindex 7c6e0725a6c3..8584b2b99c6e 100644\n--- a/include/configs/bcm_ns3.h\n+++ b/include/configs/bcm_ns3.h\n@@ -44,20 +44,11 @@\n \n #define PCIE_ARGS \"pcie_args=pci=pcie_bus_safe pcie_ports=native vfio_pci.disable_idle_d3=1\\0\"\n \n-#ifdef CONFIG_BCM_SF2_ETH\n-#define BCM_ETH_ADDR \"ethaddr=00:0A:F7:95:65:A4\\0\"\n-#define NET_ARGS \"bgmac_platform.ethaddr=${ethaddr} \" \\\n-\t\"ip=${ipaddr}::${gatewayip}:${netmask}::${ethif}:off\"\n-#else\n-#define BMC_ETH_ADDR\n-#define NET_ARGS\n-#endif\n-\n #define RESERVED_MEM \"reserved_mem=memmap=0xff000000$0x1000000\\0\"\n \n #define BASE_ARGS \"${console_args} ${extra_args} ${pcie_args}\" \\\n \t\t \" ${max_cpus} ${log_level} ${reserved_mem}\"\n-#define SETBOOTARGS \"setbootargs=setenv bootargs \" BASE_ARGS \" \" NET_ARGS \"\\0\"\n+#define SETBOOTARGS \"setbootargs=setenv bootargs \" BASE_ARGS \"\\0\"\n \n #define UPDATEME_FLASH_PARAMS \"bcm_compat_level=4\\0\" \\\n \t\t\t \"bcm_need_recovery_rootfs=0\\0\" \\\n@@ -749,7 +740,6 @@\n \tOS_LOG_LEVEL \\\n \tEXTRA_ARGS \\\n \tPCIE_ARGS \\\n-\tBMC_ETH_ADDR \\\n \tRESERVED_MEM \\\n \tSETBOOTARGS \\\n \tUPDATEME_FLASH_PARAMS \\\n", "prefixes": [] }