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GET /api/patches/210/?format=api
{ "id": 210, "url": "http://patchwork.ozlabs.org/api/patches/210/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/6c8102b136b709af32d5f5ceeb113b1943af29d3.1220877899.git.jwboyer@linux.vnet.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<6c8102b136b709af32d5f5ceeb113b1943af29d3.1220877899.git.jwboyer@linux.vnet.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/6c8102b136b709af32d5f5ceeb113b1943af29d3.1220877899.git.jwboyer@linux.vnet.ibm.com/", "date": "2008-09-04T14:08:20", "name": "ibm_newemac: MAL support for PowerPC 405EZ", "commit_ref": "fbcc4bacee30cad4e4a13d05492a9ed0c9c3e8c7", "pull_url": null, "state": "accepted", "archived": true, "hash": "1ab98b2337b11a55fbef9fc28432e88a652db818", "submitter": { "id": 8, "url": "http://patchwork.ozlabs.org/api/people/8/?format=api", "name": "Josh Boyer", "email": "jwboyer@linux.vnet.ibm.com" }, "delegate": { "id": 11, "url": "http://patchwork.ozlabs.org/api/users/11/?format=api", "username": "jwboyer", "first_name": "Josh", "last_name": "Boyer", "email": "jwboyer@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/6c8102b136b709af32d5f5ceeb113b1943af29d3.1220877899.git.jwboyer@linux.vnet.ibm.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/210/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/210/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork=ozlabs.org@ozlabs.org>", "X-Original-To": [ "patchwork@ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Delivered-To": [ "patchwork@ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Received": [ "from ozlabs.org (localhost [127.0.0.1])\n\tby ozlabs.org (Postfix) with ESMTP id 6721EDE207\n\tfor <patchwork@ozlabs.org>; Mon, 8 Sep 2008 23:05:39 +1000 (EST)", "from py-out-1112.google.com (py-out-1112.google.com\n\t[64.233.166.181]) by ozlabs.org (Postfix) with ESMTP id 30726DDF01\n\tfor <linuxppc-dev@ozlabs.org>; Mon, 8 Sep 2008 23:04:41 +1000 (EST)", "by py-out-1112.google.com with SMTP id a29so928307pyi.27\n\tfor <linuxppc-dev@ozlabs.org>; Mon, 08 Sep 2008 06:04:41 -0700 (PDT)", "by 10.65.215.14 with SMTP id s14mr31345455qbq.18.1220879081209;\n\tMon, 08 Sep 2008 06:04:41 -0700 (PDT)", "from ?192.168.1.101? ( [24.247.237.59])\n\tby mx.google.com with ESMTPS id s30sm5519523qbs.8.2008.09.08.06.04.38\n\t(version=TLSv1/SSLv3 cipher=RC4-MD5);\n\tMon, 08 Sep 2008 06:04:39 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; \n\th=domainkey-signature:received:received:message-id:in-reply-to\n\t:references:from:date:subject:to:cc:mime-version:x-mailer\n\t:content-transfer-encoding:sender;\n\tbh=pgMzK52z92sKGWGMrOa2TAnmL9AWVugZgoGqFmQP/wA=;\n\tb=WZlQJ8tuj7eWE+IXH6GS2VaZsrpL3sFMBiL9jmdADYj3GcUE1VZ5n8rAssGgdcoUkJ\n\tCAp2ACgIckk43OrqzsxMlWH3vx57rsUPSkkFRZgDveOJ8iAk+p9cjzowBPLn7wzXS+dM\n\tVgGveMeF3BTMJlOcoaSorDF+zkIjUpT+wiR+I=", "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=gmail.com; s=gamma;\n\th=message-id:in-reply-to:references:from:date:subject:to:cc\n\t:mime-version:x-mailer:content-transfer-encoding:sender;\n\tb=gRCEFRGQLuc5ASLW8eMZktF+JDqaD1sKOmaR1a4KOJj5HnNjJGZA49FhZfvieNb9aU\n\t+ym9LAmik9wK+cBhjQ67QDHW51/jnECLb66zJTxZ4LdArCYWRXOE4oZhDkI+Pd+BFB3y\n\tTkLJtP88ddXKvVyNC4egv4ajE2npEAKrI2jYk=", "Message-Id": "<6c8102b136b709af32d5f5ceeb113b1943af29d3.1220877899.git.jwboyer@linux.vnet.ibm.com>", "In-Reply-To": "<cover.1220877899.git.jwboyer@linux.vnet.ibm.com>", "References": "<cover.1220877899.git.jwboyer@linux.vnet.ibm.com>", "From": "Josh Boyer <jwboyer@linux.vnet.ibm.com>", "Date": "Thu, 4 Sep 2008 10:08:20 -0400", "Subject": "[PATCH 3/3 v2] ibm_newemac: MAL support for PowerPC 405EZ", "To": "benh@kernel.crashing.org, netdev@vger.kernel.org", "Mime-Version": "1.0", "X-Mailer": "Evolution 2.22.3.1 (2.22.3.1-1.fc9) ", "Cc": "linuxppc-dev@ozlabs.org", "X-BeenThere": "linuxppc-dev@ozlabs.org", "X-Mailman-Version": "2.1.11", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List <linuxppc-dev.ozlabs.org>", "List-Unsubscribe": "<https://ozlabs.org/mailman/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://ozlabs.org/pipermail/linuxppc-dev>", "List-Post": "<mailto:linuxppc-dev@ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@ozlabs.org?subject=help>", "List-Subscribe": "<https://ozlabs.org/mailman/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@ozlabs.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "linuxppc-dev-bounces+patchwork=ozlabs.org@ozlabs.org", "Errors-To": "linuxppc-dev-bounces+patchwork=ozlabs.org@ozlabs.org" }, "content": "The PowerPC 405EZ SoC has some differences in the interrupt layout and\nhandling for the MAL. The SERR, TXDE, and RXDE interrupts are OR'd into\na single interrupt. Also, due to the possibility for interrupt coalescing,\nthe TXEOB and RXEOB interrupts require an interrupt bit to be cleared in\nthe ICINTSTAT SDR.\n\nThis sets the proper MAL feature bits for 405EZ boards, and adds a common\nshared handler for SERR, TXDE, and RXDE. The defines for the ICINTSTAT DCR\nare added to the proper header file as well.\n\nThis has been adapted from code originally written by Stefan Roese.\n\nSigned-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>", "diff": "diff --git a/arch/powerpc/include/asm/dcr-regs.h b/arch/powerpc/include/asm/dcr-regs.h\nindex 29b0ece..7b833ff 100644\n--- a/arch/powerpc/include/asm/dcr-regs.h\n+++ b/arch/powerpc/include/asm/dcr-regs.h\n@@ -68,6 +68,13 @@\n #define SDR0_UART3\t\t0x0123\n #define SDR0_CUST0\t\t0x4000\n \n+/* SDR for 405EZ */\n+#define DCRN_SDR_ICINTSTAT\t0x4510\n+#define ICINTSTAT_ICRX\t0x80000000\n+#define ICINTSTAT_ICTX0\t0x40000000\n+#define ICINTSTAT_ICTX1 0x20000000\n+#define ICINTSTAT_ICTX\t0x60000000\n+\n /*\n * All those DCR register addresses are offsets from the base address\n * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is\ndiff --git a/drivers/net/ibm_newemac/mal.c b/drivers/net/ibm_newemac/mal.c\nindex 10c267b..1839d3f 100644\n--- a/drivers/net/ibm_newemac/mal.c\n+++ b/drivers/net/ibm_newemac/mal.c\n@@ -28,6 +28,7 @@\n #include <linux/delay.h>\n \n #include \"core.h\"\n+#include <asm/dcr-regs.h>\n \n static int mal_count;\n \n@@ -279,6 +280,10 @@ static irqreturn_t mal_txeob(int irq, void *dev_instance)\n \tmal_schedule_poll(mal);\n \tset_mal_dcrn(mal, MAL_TXEOBISR, r);\n \n+\tif (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT))\n+\t\tmtdcri(SDR0, DCRN_SDR_ICINTSTAT,\n+\t\t\t\t(mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICTX));\n+\n \treturn IRQ_HANDLED;\n }\n \n@@ -293,6 +298,10 @@ static irqreturn_t mal_rxeob(int irq, void *dev_instance)\n \tmal_schedule_poll(mal);\n \tset_mal_dcrn(mal, MAL_RXEOBISR, r);\n \n+\tif (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT))\n+\t\tmtdcri(SDR0, DCRN_SDR_ICINTSTAT,\n+\t\t\t\t(mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICRX));\n+\n \treturn IRQ_HANDLED;\n }\n \n@@ -336,6 +345,25 @@ static irqreturn_t mal_rxde(int irq, void *dev_instance)\n \treturn IRQ_HANDLED;\n }\n \n+static irqreturn_t mal_int(int irq, void *dev_instance)\n+{\n+\tstruct mal_instance *mal = dev_instance;\n+\tu32 esr = get_mal_dcrn(mal, MAL_ESR);\n+\n+\tif (esr & MAL_ESR_EVB) {\n+\t\t/* descriptor error */\n+\t\tif (esr & MAL_ESR_DE) {\n+\t\t\tif (esr & MAL_ESR_CIDT)\n+\t\t\t\treturn mal_rxde(irq, dev_instance);\n+\t\t\telse\n+\t\t\t\treturn mal_txde(irq, dev_instance);\n+\t\t} else { /* SERR */\n+\t\t\treturn mal_serr(irq, dev_instance);\n+\t\t}\n+\t}\n+\treturn IRQ_HANDLED;\n+}\n+\n void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac)\n {\n \t/* Spinlock-type semantics: only one caller disable poll at a time */\n@@ -493,6 +521,8 @@ static int __devinit mal_probe(struct of_device *ofdev,\n \tunsigned int dcr_base;\n \tconst u32 *prop;\n \tu32 cfg;\n+\tunsigned long irqflags;\n+\tirq_handler_t hdlr_serr, hdlr_txde, hdlr_rxde;\n \n \tmal = kzalloc(sizeof(struct mal_instance), GFP_KERNEL);\n \tif (!mal) {\n@@ -542,11 +572,21 @@ static int __devinit mal_probe(struct of_device *ofdev,\n \t\tgoto fail;\n \t}\n \n+\tif (of_device_is_compatible(ofdev->node, \"ibm,mcmal-405ez\"))\n+\t\tmal->features |= (MAL_FTR_CLEAR_ICINTSTAT |\n+\t\t\t\tMAL_FTR_COMMON_ERR_INT);\n+\n \tmal->txeob_irq = irq_of_parse_and_map(ofdev->node, 0);\n \tmal->rxeob_irq = irq_of_parse_and_map(ofdev->node, 1);\n \tmal->serr_irq = irq_of_parse_and_map(ofdev->node, 2);\n-\tmal->txde_irq = irq_of_parse_and_map(ofdev->node, 3);\n-\tmal->rxde_irq = irq_of_parse_and_map(ofdev->node, 4);\n+\n+\tif (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) {\n+\t\tmal->txde_irq = mal->rxde_irq = mal->serr_irq;\n+\t} else {\n+\t\tmal->txde_irq = irq_of_parse_and_map(ofdev->node, 3);\n+\t\tmal->rxde_irq = irq_of_parse_and_map(ofdev->node, 4);\n+\t}\n+\n \tif (mal->txeob_irq == NO_IRQ || mal->rxeob_irq == NO_IRQ ||\n \t mal->serr_irq == NO_IRQ || mal->txde_irq == NO_IRQ ||\n \t mal->rxde_irq == NO_IRQ) {\n@@ -608,16 +648,26 @@ static int __devinit mal_probe(struct of_device *ofdev,\n \t\t\t sizeof(struct mal_descriptor) *\n \t\t\t mal_rx_bd_offset(mal, i));\n \n-\terr = request_irq(mal->serr_irq, mal_serr, 0, \"MAL SERR\", mal);\n+\tif (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) {\n+\t\tirqflags = IRQF_SHARED;\n+\t\thdlr_serr = hdlr_txde = hdlr_rxde = mal_int;\n+\t} else {\n+\t\tirqflags = 0;\n+\t\thdlr_serr = mal_serr;\n+\t\thdlr_txde = mal_txde;\n+\t\thdlr_rxde = mal_rxde;\n+\t}\n+\n+\terr = request_irq(mal->serr_irq, hdlr_serr, irqflags, \"MAL SERR\", mal);\n \tif (err)\n \t\tgoto fail2;\n-\terr = request_irq(mal->txde_irq, mal_txde, 0, \"MAL TX DE\", mal);\n+\terr = request_irq(mal->txde_irq, hdlr_txde, irqflags, \"MAL TX DE\", mal);\n \tif (err)\n \t\tgoto fail3;\n \terr = request_irq(mal->txeob_irq, mal_txeob, 0, \"MAL TX EOB\", mal);\n \tif (err)\n \t\tgoto fail4;\n-\terr = request_irq(mal->rxde_irq, mal_rxde, 0, \"MAL RX DE\", mal);\n+\terr = request_irq(mal->rxde_irq, hdlr_rxde, irqflags, \"MAL RX DE\", mal);\n \tif (err)\n \t\tgoto fail5;\n \terr = request_irq(mal->rxeob_irq, mal_rxeob, 0, \"MAL RX EOB\", mal);\n", "prefixes": [] }