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GET /api/patches/2093663/?format=api
{ "id": 2093663, "url": "http://patchwork.ozlabs.org/api/patches/2093663/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20250603203241.727401-1-donalds@nvidia.com/", "project": { "id": 57, "url": "http://patchwork.ozlabs.org/api/projects/57/?format=api", "name": "Linux ASPEED SoC development", "link_name": "linux-aspeed", "list_id": "linux-aspeed.lists.ozlabs.org", "list_email": "linux-aspeed@lists.ozlabs.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20250603203241.727401-1-donalds@nvidia.com>", "list_archive_url": null, "date": "2025-06-03T20:32:41", "name": "ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b platform BMC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a08c2abd354e2efe7b439141526f07b65864567b", "submitter": { "id": 90992, "url": "http://patchwork.ozlabs.org/api/people/90992/?format=api", "name": "Donald Shannon", "email": "donalds@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20250603203241.727401-1-donalds@nvidia.com/mbox/", "series": [ { "id": 459460, "url": "http://patchwork.ozlabs.org/api/series/459460/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/list/?series=459460", "date": "2025-06-03T20:32:41", "name": "ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b platform BMC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/459460/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2093663/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2093663/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-aspeed+bounces-1299-incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-aspeed@lists.ozlabs.org" ], "Delivered-To": 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receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Donald Shannon <donalds@nvidia.com>", "To": "<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>", "CC": "<joel@jms.id.au>, <andrew@codeconstruct.com.au>,\n\t<devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,\n\t<linux-aspeed@lists.ozlabs.org>, <linux-kernel@vger.kernel.org>, \"Donald\n Shannon\" <donalds@nvidia.com>", "Subject": "[PATCH] ARM: dts: aspeed: Add device tree for Nvidia's GB200 UT3.0b\n platform BMC", "Date": "Tue, 3 Jun 2025 13:32:41 -0700", "Message-ID": "<20250603203241.727401-1-donalds@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "X-Mailing-List": "linux-aspeed@lists.ozlabs.org", "List-Id": "<linux-aspeed.lists.ozlabs.org>", "List-Help": "<mailto:linux-aspeed+help@lists.ozlabs.org>", "List-Owner": "<mailto:linux-aspeed+owner@lists.ozlabs.org>", "List-Post": "<mailto:linux-aspeed@lists.ozlabs.org>", "List-Archive": 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9vF3RseYrRk67302GPb5P8pFGxHsIvzbpy3ARM0b6aLiPwVi/pTwN2oZxSPVNkYVoJTvFblyr5gUk9nPwAWTID4s3zbQvM31Hb4C7iGHqV46gTkxuUiOBPtwJzMIw0Kjz15A/j2YWN05N9A9gw6kAUtCswL5wOKFmRNDa+siuJmfcdjA4rRlwnaDSrj54vUh2zHxf5uAy0dOL5EBGtloJV2iNgHfV9eQKWzYkB7qPW1KMSy4wP6Vt71UGOwZY4l+hya3SWC4+FvPr9rkjvW2UU+5/megEmkPu6DivH84VxUVBVa8paaw0BRZFC2lGp5mi4n/ZwoW6R5Hu17pfqFjbdzjUUckabnFKUby7Y9ohKGkYgyNxWCqErYJxbgRRaE4P1u6SDzwNHqWwJIHqEArt3QlHxBlFhEwzSMo4E25DDmwZRnuSyIpTNJd0rB0K4jXmYKmWZR500c2Sd9rePKfjaduGIBFmlBnNOh4637mlsiWnVhbnqddRpgaq9NwR3ZnDGciYAuToq0/fXrtYhiBf7cYqMDXAuWqSXB10yjVxUjAQ+CGRvcp6YXFEmm9Uocw1D6A+Xr09tOsS1WfQJP9Ie42wgNvrtR+FcIHJcdHkZM/bVq57qtg/HTx5fjUMe0ONMGxjOTN1RiSvad9dPCdTI+HLEPDAoGn4rN74qqPG/BfntwsoFf4u8VAFIf+/krsJKlzL2kulm6ampYzit9DPw3CJLybyG7KbiSNmHnTn17e+xnGJO6Q3OUMHEMpOF+26z02LXDz5y5jKXEJF2bLOaKG1y6gC1LVE3boYGmcmp6nAZZTY0S2CTxJ7fIRmlPegTIs42UTKmM/+kW2fv+MgqXllqVipW8jYd80um15vjI7zSR2urxTff2Kn7d4qLZvKLwCdGmwPm50psN2DnhBVBbJ+UHWez6NUEhOtTSRzPwUmN67MvBYC0jShrk/2ZX/ECLs6vNJgVBzfiGgci9J3LB9sB0iM4/90JPDfVi7l7nvhGWRtEgL7VwISnvVpw3/y9UO6EXp3J/WhNsLIYNWxXUKEWV5nClhXAV7zqC3/mfjzdQMsRGdpTm7k/0lKixAzWy6n8V8MoXufD68zeG4S0LNHPwRIRwRrcHyyghcyufLUyaoZZ5UfizVABTt0ST6UPU+g15Ym7aVi0VpmWwPLRSnK2OcG6xrG2XbyWZCHTbfpTveYPjzpiPRAWJPCbOL5vWUK8SBIKqd+riQWImsAdLoRwRXZnUC9psCFiGb2ua3XzETM8dESoPzZrSNz2LYbhoxIHJ5iHqJcoVLQfDeeLQcgaVtSCQISPUeBRcgOGhCp5vw33cA32ksKN2NZFR2l+uoujA8IINUYSBtyHr7rPvaOhYlHo/hDjVtgmdVLHsyLHDQWnl16e/ZxLo0N/+42/Lb9JXNbhevkcKLymzJpBEg9HrwlIHX2NpZ7cZ91xnCCzxLPdd3bVS3j7Jez9PS74nlcImyjJmhmJ7X4k3fsF8TZtY5DmHQQ8odQO4Hfr0p/DiB2iLyN0obsHUt+MRT", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "03 Jun 2025 20:32:59.6768\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 83383086-e8f7-4210-0110-08dda2ddd4d7", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBL02EPF00021F6A.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB7717", "X-Spam-Status": "No, score=-3.1 required=5.0 tests=ARC_SIGNED,ARC_VALID,\n\tDKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,\n\tSPF_HELO_PASS,SPF_PASS,WEIRD_QUOTING autolearn=disabled version=4.0.1", "X-Spam-Checker-Version": "SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org" }, "content": "The GB200NVL UT3.0b BMC is an Aspeed Ast2600 based BMC\nfor Nvidia Blackwell GB200NVL platform.\nReference to Ast2600 SOC [1].\nReference to Blackwell GB200NVL Platform [2].\n\nLink: https://www.aspeedtech.com/server_ast2600/ [1]\nLink: https://nvdam.widen.net/s/wwnsxrhm2w/blackwell-datasheet-3384703 [2]\n\nSigned-off-by: Donald Shannon <donalds@nvidia.com>\n---\n arch/arm/boot/dts/aspeed/Makefile | 1 +\n .../aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts | 1173 +++++++++++++++++\n 2 files changed, 1174 insertions(+)\n create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts", "diff": "diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile\nindex b3170fdd3096..fa09d0b61ec2 100644\n--- a/arch/arm/boot/dts/aspeed/Makefile\n+++ b/arch/arm/boot/dts/aspeed/Makefile\n@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \\\n \taspeed-bmc-lenovo-hr855xg2.dtb \\\n \taspeed-bmc-microsoft-olympus.dtb \\\n \taspeed-bmc-nvidia-gb200nvl-bmc.dtb \\\n+\taspeed-bmc-nvidia-gb200nvl-ut30b.dtb \\\n \taspeed-bmc-opp-lanyang.dtb \\\n \taspeed-bmc-opp-mowgli.dtb \\\n \taspeed-bmc-opp-nicole.dtb \\\ndiff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts\nnew file mode 100644\nindex 000000000000..e2aa33c36e71\n--- /dev/null\n+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts\n@@ -0,0 +1,1173 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/dts-v1/;\n+\n+#include \"aspeed-g6.dtsi\"\n+#include <dt-bindings/i2c/i2c.h>\n+#include <dt-bindings/gpio/aspeed-gpio.h>\n+#include <dt-bindings/leds/common.h>\n+\n+/ {\n+\tmodel = \"AST2600 GB200 UT3.0b BMC\";\n+\tcompatible = \"nvidia,gb200nvl-bmc\", \"aspeed,ast2600\";\n+\n+\taliases {\n+\t\tserial2 = &uart3;\n+\t\tserial4 = &uart5;\n+\t\ti2c16 = &imux16;\n+\t\ti2c17 = &imux17;\n+\t\ti2c18 = &imux18;\n+\t\ti2c19 = &imux19;\n+\t\ti2c20 = &imux20;\n+\t\ti2c21 = &imux21;\n+\t\ti2c22 = &imux22;\n+\t\ti2c23 = &imux23;\n+\t\ti2c24 = &imux24;\n+\t\ti2c25 = &imux25;\n+\t\ti2c26 = &imux26;\n+\t\ti2c27 = &imux27;\n+\t\ti2c28 = &imux28;\n+\t\ti2c29 = &imux29;\n+\t\ti2c30 = &imux30;\n+\t\ti2c31 = &imux31;\n+\t\ti2c32 = &imux32;\n+\t\ti2c33 = &imux33;\n+\t\ti2c34 = &imux34;\n+\t\ti2c35 = &imux35;\n+\t\ti2c36 = &imux36;\n+\t\ti2c37 = &imux37;\n+\t\ti2c38 = &imux38;\n+\t\ti2c39 = &imux39;\n+\t\ti2c40\t= &e1si2c0;\n+\t\ti2c41\t= &e1si2c1;\n+\t\ti2c42\t= &e1si2c2;\n+\t\ti2c43\t= &e1si2c3;\n+\t\ti2c44\t= &e1si2c4;\n+\t\ti2c45\t= &e1si2c5;\n+\t\ti2c46\t= &e1si2c6;\n+\t\ti2c47\t= &e1si2c7;\n+\t\ti2c48\t= &i2c17mux0;\n+\t\ti2c49\t= &i2c17mux1;\n+\t\ti2c50\t= &i2c17mux2;\n+\t\ti2c51\t= &i2c17mux3;\n+\t\ti2c52\t= &i2c25mux0;\n+\t\ti2c53\t= &i2c25mux1;\n+\t\ti2c54\t= &i2c25mux2;\n+\t\ti2c55\t= &i2c25mux3;\n+\t\ti2c56\t= &i2c29mux0;\n+\t\ti2c57\t= &i2c29mux1;\n+\t\ti2c58\t= &i2c29mux2;\n+\t\ti2c59\t= &i2c29mux3;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = &uart5;\n+\t};\n+\n+\tmemory@80000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x80000000 0x80000000>;\n+\t};\n+\n+\treserved-memory {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges;\n+\n+\t\tvga_memory: framebuffer@9f000000 {\n+\t\t\tno-map;\n+\t\t\treg = <0x9f000000 0x01000000>; /* 16M */\n+\t\t};\n+\n+\t\tramoops@a0000000 {\n+\t\t\tcompatible = \"ramoops\";\n+\t\t\treg = <0xa0000000 0x100000>; /* 1MB */\n+\t\t\trecord-size = <0x10000>; /* 64KB */\n+\t\t\tmax-reason = <2>; /* KMSG_DUMP_OOPS */\n+\t\t};\n+\n+\t\tgfx_memory: framebuffer {\n+\t\t\tsize = <0x01000000>;\n+\t\t\talignment = <0x01000000>;\n+\t\t\tcompatible = \"shared-dma-pool\";\n+\t\t\treusable;\n+\t\t};\n+\n+\t\tvideo_engine_memory: jpegbuffer {\n+\t\t\tsize = <0x02000000>;\t/* 32M */\n+\t\t\talignment = <0x01000000>;\n+\t\t\tcompatible = \"shared-dma-pool\";\n+\t\t\treusable;\n+\t\t};\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\t\tled-0 {\n+\t\t\tlabel = \"uid_led\";\n+\t\t\tgpios = <&sgpiom0 27 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t\tled-1 {\n+\t\t\tlabel = \"fault_led\";\n+\t\t\tgpios = <&sgpiom0 29 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t\tled-2 {\n+\t\t\tlabel = \"power_led\";\n+\t\t\tgpios = <&sgpiom0 31 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tbuttons {\n+\t\tbutton-power {\n+\t\t\tlabel = \"power-btn\";\n+\t\t\tgpio = <&sgpiom0 156 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t\tbutton-uid {\n+\t\t\tlabel = \"uid-btn\";\n+\t\t\tgpio = <&sgpiom0 154 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+ fixedregulator_standby_power: fixedregulator_standby_power {\n+\t\tstatus = \"okay\";\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"standby_power\";\n+\t\tgpio = <&gpio0 ASPEED_GPIO(M, 3) GPIO_ACTIVE_HIGH>;\n+\t\tregulator-min-microvolt = <1800000>;\n+\t\tregulator-max-microvolt = <1800000>;\n+\t\t//startup-delay-us = <5000000>;\n+\t\tenable-active-high;\n+\t\tregulator-always-on;\n+\t};\n+};\n+\n+// Enable Primary flash on FMC for bring up activity\n+&fmc {\n+\tstatus = \"okay\";\n+\tflash@0 {\n+\t\tstatus = \"okay\";\n+\t\tcompatible = \"jedec,spi-nor\";\n+\t\tlabel = \"bmc\";\n+\t\tspi-max-frequency = <50000000>;\n+\t\tpartitions {\n+\t\t\tcompatible = \"fixed-partitions\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tu-boot@0 {\n+\t\t\t\t// 896KB\n+\t\t\t\treg = <0x0 0xe0000>;\n+\t\t\t\tlabel = \"u-boot\";\n+\t\t\t};\n+\n+\t\t\tkernel@100000 {\n+\t\t\t\t// 9MB\n+\t\t\t\treg = <0x100000 0x900000>;\n+\t\t\t\tlabel = \"kernel\";\n+\t\t\t};\n+\n+\t\t\trofs@a00000 {\n+\t\t\t\t// 55292KB (extends to end of 64MB SPI - 4KB)\n+\t\t\t\treg = <0xa00000 0x35FF000>;\n+\t\t\t\tlabel = \"rofs\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&spi2 {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_spi2_default>;\n+\n+\t// Data SPI is 64MB in size\n+\tflash@0 {\n+\t\tstatus = \"okay\";\n+\t\tlabel = \"config\";\n+\t\tspi-max-frequency = <50000000>;\n+\t\tpartitions {\n+\t\t\tcompatible = \"fixed-partitions\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tu-boot-env@0 {\n+\t\t\t\t// 256KB\n+\t\t\t\treg = <0x0 0x40000>;\n+\t\t\t\tlabel = \"u-boot-env\";\n+\t\t\t};\n+\n+\t\t\trwfs@40000 {\n+\t\t\t\t// 16MB\n+\t\t\t\treg = <0x40000 0x1000000>;\n+\t\t\t\tlabel = \"rwfs\";\n+\t\t\t};\n+\n+\t\t\tlog@1040000 {\n+\t\t\t\t// 40MB\n+\t\t\t\treg = <0x1040000 0x2800000>;\n+\t\t\t\tlabel = \"log\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&uart1 {\n+\tstatus = \"okay\";\n+};\n+\n+&uart3 {\n+\t// Enabling SOL\n+\tstatus = \"okay\";\n+};\n+\n+&uart5 {\n+\t// BMC Debug Console\n+\tstatus = \"okay\";\n+};\n+\n+&uart_routing {\n+\tstatus = \"okay\";\n+};\n+\n+&mdio0 {\n+\tstatus = \"okay\";\n+\tethphy0: ethernet-phy@0 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <0>;\n+\t};\n+};\n+\n+&mac0 {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tphy-mode = \"rgmii-rxid\";\n+\tmax-speed = <1000>;\n+\tphy-handle = <ðphy0>;\n+\tpinctrl-0 = <&pinctrl_rgmii1_default>;\n+};\n+\n+/*\n+ * Enable USB port A as device (via the virtual hub) to host\n+ */\n+&vhub {\n+\tstatus = \"okay\";\n+};\n+\n+&video {\n+\tstatus = \"okay\";\n+\tmemory-region = <&video_engine_memory>;\n+};\n+\n+// USB 2.0 to HMC, on USB Port B\n+&ehci1 {\n+\tstatus = \"okay\";\n+};\n+\n+// USB 1.0\n+&uhci {\n+\tstatus = \"okay\";\n+};\n+\n+&sgpiom0 {\n+\tstatus=\"okay\";\n+\tngpios = <128>;\n+\tgpio-line-names =\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"RUN_POWER_FAULT_L-I\",\"SYS_RST_IN_L-O\",\n+\t\t\"RUN_POWER_PG-I\",\"PWR_BRAKE_L-O\",\n+\t\t\"SYS_RST_OUT_L-I\",\"RUN_POWER_EN-O\",\n+\t\t\"L0L1_RST_REQ_OUT_L-I\",\"SHDN_FORCE_L-O\",\n+\t\t\"L2_RST_REQ_OUT_L-I\",\"SHDN_REQ_L-O\",\n+\t\t\"SHDN_OK_L-I\",\"UID_LED_N-O\",\n+\t\t\"BMC_I2C1_FPGA_ALERT_L-I\",\"SYS_FAULT_LED_N-O\",\n+\t\t\"BMC_I2C0_FPGA_ALERT_L-I\",\"PWR_LED_N-O\",\n+\t\t\"FPGA_RSVD_FFU3-I\",\"\",\n+\t\t\"FPGA_RSVD_FFU2-I\",\"\",\n+\t\t\"FPGA_RSVD_FFU1-I\",\"\",\n+\t\t\"FPGA_RSVD_FFU0-I\",\"BMC_I2C_SSIF_ALERT_L-O\",\n+\t\t\"CPU_BOOT_DONE-I\",\"JTAG_MUX_SELECT-O\",\n+\t\t\"SPI_BMC_FPGA_INT_L-I\",\"RTC_CLR_L-O\",\n+\t\t\"THERM_BB_WARN_L-I\",\"UART_MUX_SEL-O\",\n+\t\t\"THERM_BB_OVERT_L-I\",\"\",\n+\t\t\"CPU0_UPHY3_PRSNT1_L-I\",\"IOBRD0_RUN_POWER_EN-O\",\n+\t\t\"CPU0_UPHY3_PRSNT0_L-I\",\"IOBRD1_RUN_POWER_EN-O\",\n+\t\t\"CPU0_UPHY2_PRSNT1_L-I\",\"FPGA_RSVD_FFU4-O\",\n+\t\t\"CPU0_UPHY2_PRSNT0_L-I\",\"FPGA_RSVD_FFU5-O\",\n+\t\t\"CPU0_UPHY1_PRSNT1_L-I\",\"FPGA_RSVD_FFU6-O\",\n+\t\t\"CPU0_UPHY1_PRSNT0_L-I\",\"FPGA_RSVD_FFU7-O\",\n+\t\t\"CPU0_UPHY0_PRSNT1_L-I\",\"RSVD_NV_PLT_DETECT-O\",\n+\t\t\"CPU0_UPHY0_PRSNT0_L-I\",\"SPI1_INT_L-O\",\n+\t\t\"CPU1_UPHY3_PRSNT1_L-I\",\"\",\n+\t\t\"CPU1_UPHY3_PRSNT0_L-I\",\"HMC_EROT_MUX_STATUS\",\n+\t\t\"CPU1_UPHY2_PRSNT1_L-I\",\"\",\n+\t\t\"CPU1_UPHY2_PRSNT0_L-I\",\"\",\n+\t\t\"CPU1_UPHY1_PRSNT1_L-I\",\"\",\n+\t\t\"CPU1_UPHY1_PRSNT0_L-I\",\"\",\n+\t\t\"CPU1_UPHY0_PRSNT1_L-I\",\"\",\n+\t\t\"CPU1_UPHY0_PRSNT0_L-I\",\"\",\n+\t\t\"FAN1_PRESENT_L-I\",\"\",\n+\t\t\"FAN0_PRESENT_L-I\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"IPEX_CABLE_PRSNT_L-I\",\"\",\n+\t\t\"M2_1_PRSNT_L-I\",\"\",\n+\t\t\"M2_0_PRSNT_L-I\",\"\",\n+\t\t\"CPU1_UPHY4_PRSNT1_L-I\",\"\",\n+\t\t\"CPU0_UPHY4_PRSNT0_L-I\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"I2C_RTC_ALERT_L-I\",\"\",\n+\t\t\"FAN7_PRESENT_L-I\",\"\",\n+\t\t\"FAN6_PRESENT_L-I\",\"\",\n+\t\t\"FAN5_PRESENT_L-I\",\"\",\n+\t\t\"FAN4_PRESENT_L-I\",\"\",\n+\t\t\"FAN3_PRESENT_L-I\",\"\",\n+\t\t\"FAN2_PRESENT_L-I\",\"\",\n+\t\t\"IOBRD0_IOX_INT_L-I\",\"\",\n+\t\t\"IOBRD1_PRSNT_L-I\",\"\",\n+\t\t\"IOBRD0_PRSNT_L-I\",\"\",\n+\t\t\"IOBRD1_PWR_GOOD-I\",\"\",\n+\t\t\"IOBRD0_PWR_GOOD-I\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"FAN_FAIL_IN_L-I\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"PDB_CABLE_PRESENT_L-I\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"CHASSIS_PWR_BRK_L-I\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"IOBRD1_IOX_INT_L-I\",\"\",\n+\t\t\"10GBE_SMBALRT_L-I\",\"\",\n+\t\t\"PCIE_WAKE_L-I\",\"\",\n+\t\t\"I2C_M21_ALERT_L-I\",\"\",\n+\t\t\"I2C_M20_ALERT_L-I\",\"\",\n+\t\t\"TRAY_FAST_SHDN_L-I\",\"\",\n+\t\t\"UID_BTN_N-I\",\"\",\n+\t\t\"PWR_BTN_L-I\",\"\",\n+\t\t\"PSU_SMB_ALERT_L-I\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"NODE_LOC_ID[0]-I\",\"\",\n+\t\t\"NODE_LOC_ID[1]-I\",\"\",\n+\t\t\"NODE_LOC_ID[2]-I\",\"\",\n+\t\t\"NODE_LOC_ID[3]-I\",\"\",\n+\t\t\"NODE_LOC_ID[4]-I\",\"\",\n+\t\t\"NODE_LOC_ID[5]-I\",\"\",\n+\t\t\"FAN10_PRESENT_L-I\",\"\",\n+\t\t\"FAN9_PRESENT_L-I\",\"\",\n+\t\t\"FAN8_PRESENT_L-I\",\"\",\n+\t\t\"FPGA1_READY_HMC-I\",\"\",\n+\t\t\"DP_HPD-I\",\"\",\n+\t\t\"HMC_I2C3_FPGA_ALERT_L-I\",\"\",\n+\t\t\"HMC_I2C2_FPGA_ALERT_L-I\",\"\",\n+\t\t\"FPGA0_READY_HMC-I\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"LEAK_DETECT_ALERT_L-I\",\"\",\n+\t\t\"MOD1_B2B_CABLE_PRESENT_L-I\",\"\",\n+\t\t\"MOD1_CLINK_CABLE_PRESENT_L-I\",\"\",\n+\t\t\"FAN11_PRESENT_L-I\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"\",\"\",\n+\t\t\"RSVD_SGPIO_IN_CRC[0]\",\"RSVD_SGPIO_O_CRC[7]\",\n+\t\t\"RSVD_SGPIO_IN_CRC[1]\",\"RSVD_SGPIO_O_CRC[6]\",\n+\t\t\"RSVD_SGPIO_IN_CRC[2]\",\"RSVD_SGPIO_O_CRC[5]\",\n+\t\t\"RSVD_SGPIO_IN_CRC[3]\",\"RSVD_SGPIO_O_CRC[4]\",\n+\t\t\"RSVD_SGPIO_IN_CRC[4]\",\"RSVD_SGPIO_O_CRC[3]\",\n+\t\t\"RSVD_SGPIO_IN_CRC[5]\",\"RSVD_SGPIO_O_CRC[2]\",\n+\t\t\"RSVD_SGPIO_IN_CRC[6]\",\"RSVD_SGPIO_O_CRC[1]\",\n+\t\t\"RSVD_SGPIO_IN_CRC[7]\",\"RSVD_SGPIO_O_CRC[0]\";\n+};\n+\n+// I2C1, SSIF IPMI interface\n+&i2c0 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+\n+\tssif-bmc@10 {\n+\t\tcompatible = \"ssif-bmc\";\n+\t\treg = <0x10>;\n+\t};\n+};\n+\n+// I2C2\n+// BMC_I2C1_FPGA - Secondary FPGA\n+// HMC EROT\n+&i2c1 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+\tmulti-master;\n+};\n+\n+// I2C3\n+// BMC_I2C0_FPGA - Primary FPGA\n+// HMC FRU EEPROM\n+&i2c2 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+\tmulti-master;\n+};\n+\n+// I2C4\n+&i2c3 {\n+\tstatus = \"okay\";\n+ vcc-supply = <&fixedregulator_standby_power>;\n+};\n+\n+// I2C5\n+// RTC Driver\n+// IO Expander\n+&i2c4 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\n+\t// Module 0, Expander @0x21\n+\texp4: gpio@21 {\n+\t\tcompatible = \"nxp,pca9555\";\n+\t\treg = <0x21>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\t\tgpio-line-names =\n+\t\t\t\"RTC_MUX_SEL-O\",\n+\t\t\t\"PCI_MUX_SEL-O\",\n+\t\t\t\"TPM_MUX_SEL-O\",\n+\t\t\t\"FAN_MUX-SEL-O\",\n+\t\t\t\"SGMII_MUX_SEL-O\",\n+\t\t\t\"DP_MUX_SEL-O\",\n+\t\t\t\"UPHY3_USB_SEL-O\",\n+\t\t\t\"NCSI_MUX_SEL-O\",\n+\t\t\t\"BMC_PHY_RST-O\",\n+\t\t\t\"RTC_CLR_L-O\",\n+\t\t\t\"BMC_12V_CTRL-O\",\n+\t\t\t\"PS_RUN_IO0_PG-I\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\";\n+\t};\n+};\n+\n+// I2C6\n+// Module 0/1 I2C MUX x3\n+&i2c5 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+\tmulti-master;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\n+\ti2c-mux@71 {\n+\t\tcompatible = \"nxp,pca9546\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x71>;\n+\t\ti2c-mux-idle-disconnect;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\n+\t\timux16: i2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\timux17: i2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\n+\t\t\ti2c-mux@74 {\n+\t\t\t\tcompatible = \"nxp,pca9546\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\treg = <0x74>;\n+\t\t\t\ti2c-mux-idle-disconnect;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\n+\t\t\t\ti2c17mux0: i2c@0 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <0>;\n+\t\t\t\t};\n+\n+\t\t\t\ti2c17mux1: i2c@1 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <1>;\n+\t\t\t\t};\n+\n+\t\t\t\ti2c17mux2: i2c@2 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <2>;\n+\t\t\t\t};\n+\n+\t\t\t\ti2c17mux3: i2c@3 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <3>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\timux18: i2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\timux19: i2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t};\n+\t};\n+\n+\ti2c-mux@72 {\n+\t\tcompatible = \"nxp,pca9546\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x72>;\n+\t\ti2c-mux-idle-disconnect;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\n+\t\timux20: i2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\timux21: i2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\n+\t\t\tgpio@20 {\n+\t\t\t\tcompatible = \"nxp,pca9555\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\t\t\t\tgpio-line-names =\n+\t\t\t\t\t\"RST_CX_0_L-O\",\n+\t\t\t\t\t\"RST_CX_1_L-O\",\n+\t\t\t\t\t\"CX0_SSD0_PRSNT_L-I\",\n+\t\t\t\t\t\"CX1_SSD1_PRSNT_L-I\",\n+\t\t\t\t\t\"CX_BOOT_CMPLT_CX0-I\",\n+\t\t\t\t\t\"CX_BOOT_CMPLT_CX1-I\",\n+\t\t\t\t\t\"CX_TWARN_CX0_L-I\",\n+\t\t\t\t\t\"CX_TWARN_CX1_L-I\",\n+\t\t\t\t\t\"CX_OVT_SHDN_CX0-I\",\n+\t\t\t\t\t\"CX_OVT_SHDN_CX1-I\",\n+\t\t\t\t\t\"FNP_L_CX0-O\",\n+\t\t\t\t\t\"FNP_L_CX1-O\",\n+\t\t\t\t\t\"\",\n+\t\t\t\t\t\"MCU_GPIO-I\",\n+\t\t\t\t\t\"MCU_RST_N-O\",\n+\t\t\t\t\t\"MCU_RECOVERY_N-O\";\n+\t\t\t};\n+\t\t};\n+\n+\t\timux22: i2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\timux23: i2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t};\n+\t};\n+\n+\ti2c-mux@73 {\n+\t\tcompatible = \"nxp,pca9546\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x73>;\n+\t\ti2c-mux-idle-disconnect;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\n+\t\timux24: i2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\timux25: i2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\n+\t\t\ti2c-mux@70 {\n+\t\t\t\tcompatible = \"nxp,pca9546\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\treg = <0x70>;\n+\t\t\t\ti2c-mux-idle-disconnect;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\n+\t\t\t\ti2c25mux0: i2c@0 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <0>;\n+\t\t\t\t};\n+\n+\t\t\t\ti2c25mux1: i2c@1 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <1>;\n+\t\t\t\t};\n+\n+\t\t\t\ti2c25mux2: i2c@2 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <2>;\n+\t\t\t\t};\n+\n+\t\t\t\ti2c25mux3: i2c@3 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <3>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\timux26: i2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\timux27: i2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t};\n+\t};\n+\n+\ti2c-mux@75 {\n+\t\tcompatible = \"nxp,pca9546\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x75>;\n+\t\ti2c-mux-idle-disconnect;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\n+\t\timux28: i2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\timux29: i2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\n+\t\t\ti2c-mux@74 {\n+\t\t\t\tcompatible = \"nxp,pca9546\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\treg = <0x74>;\n+\t\t\t\ti2c-mux-idle-disconnect;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\n+\t\t\t\ti2c29mux0: i2c@0 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <0>;\n+\t\t\t\t};\n+\n+\t\t\t\ti2c29mux1: i2c@1 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <1>;\n+\t\t\t\t};\n+\n+\t\t\t\ti2c29mux2: i2c@2 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <2>;\n+\t\t\t\t};\n+\n+\t\t\t\ti2c29mux3: i2c@3 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <3>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\timux30: i2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\timux31: i2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t};\n+\t};\n+\n+\ti2c-mux@76 {\n+\t\tcompatible = \"nxp,pca9546\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x76>;\n+\t\ti2c-mux-idle-disconnect;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\n+\t\timux32: i2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\timux33: i2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\n+\t\t\tgpio@21 {\n+\t\t\t\tcompatible = \"nxp,pca9555\";\n+\t\t\t\treg = <0x21>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\t\t\t\tgpio-line-names =\n+\t\t\t\t\t\"SEC_RST_CX_0_L-O\",\n+\t\t\t\t\t\"SEC_RST_CX_1_L-O\",\n+\t\t\t\t\t\"SEC_CX0_SSD0_PRSNT_L-I\",\n+\t\t\t\t\t\"SEC_CX1_SSD1_PRSNT_L-I\",\n+\t\t\t\t\t\"SEC_CX_BOOT_CMPLT_CX0-I\",\n+\t\t\t\t\t\"SEC_CX_BOOT_CMPLT_CX1-I\",\n+\t\t\t\t\t\"SEC_CX_TWARN_CX0_L-I\",\n+\t\t\t\t\t\"SEC_CX_TWARN_CX1_L-I\",\n+\t\t\t\t\t\"SEC_CX_OVT_SHDN_CX0-I\",\n+\t\t\t\t\t\"SEC_CX_OVT_SHDN_CX1-I\",\n+\t\t\t\t\t\"SEC_FNP_L_CX0-O\",\n+\t\t\t\t\t\"SEC_FNP_L_CX1-O\",\n+\t\t\t\t\t\"\",\n+\t\t\t\t\t\"SEC_MCU_GPIO-I\",\n+\t\t\t\t\t\"SEC_MCU_RST_N-O\",\n+\t\t\t\t\t\"SEC_MCU_RECOVERY_N-O\";\n+\t\t\t\t};\n+\t\t};\n+\n+\t\timux34: i2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\timux35: i2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t};\n+\t};\n+\n+\ti2c-mux@77 {\n+\t\tcompatible = \"nxp,pca9546\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x77>;\n+\t\ti2c-mux-idle-disconnect;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\n+\t\timux36: i2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\timux37: i2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\t\t};\n+\n+\t\timux38: i2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\timux39: i2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t};\n+\t};\n+};\n+\n+// I2C7\n+// Module 0/1 Leak Sensors\n+// Module 0/1 Fan Controllers\n+&i2c6 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\n+\tpmic@12 {\n+\t\tcompatible = \"ti,lm5066i\";\n+\t\treg = <0x12>;\n+\t\tshunt-resistor-micro-ohms = <190>;\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tpmic@14 {\n+\t\tcompatible = \"ti,lm5066i\";\n+\t\treg = <0x14>;\n+\t\tshunt-resistor-micro-ohms = <190>;\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tpwm@20 {\n+\t\tcompatible = \"maxim,max31790\";\n+\t\treg = <0x20>;\n+\t};\n+\n+\tpwm@23 {\n+\t\tcompatible = \"maxim,max31790\";\n+\t\treg = <0x23>;\n+\t};\n+\n+\tpwm@2c {\n+\t\tcompatible = \"maxim,max31790\";\n+\t\treg = <0x2c>;\n+\t};\n+\n+\tpwm@2f {\n+\t\tcompatible = \"maxim,max31790\";\n+\t\treg = <0x2f>;\n+\t};\n+};\n+\n+// I2C9\n+// M.2\n+&i2c8 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+\tmulti-master;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+};\n+\n+// I2C10\n+// HMC IO Expander\n+// Module 0/1 IO Expanders\n+&i2c9 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\n+\t// Module 0, Expander @0x20\n+\texp0: gpio@20 {\n+\t\tcompatible = \"nxp,pca9555\";\n+\t\treg = <0x20>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\t\tgpio-line-names =\n+\t\t\t\"FPGA_THERM_OVERT_L-I\",\n+\t\t\t\"FPGA_READY_BMC-I\",\n+\t\t\t\"HMC_BMC_DETECT-O\",\n+\t\t\t\"HMC_PGOOD-O\",\n+\t\t\t\"\",\n+\t\t\t\"BMC_STBY_CYCLE-O\",\n+\t\t\t\"FPGA_EROT_FATAL_ERROR_L-I\",\n+\t\t\t\"WP_HW_EXT_CTRL_L-O\",\n+\t\t\t\"EROT_FPGA_RST_L-O\",\n+\t\t\t\"FPGA_EROT_RECOVERY_L-O\",\n+\t\t\t\"BMC_EROT_FPGA_SPI_MUX_SEL-O\",\n+\t\t\t\"USB_HUB_RESET_L-O\",\n+\t\t\t\"NCSI_CS1_SEL-O\",\n+\t\t\t\"SGPIO_EN_L-O\",\n+\t\t\t\"B2B_IOEXP_INT_L-I\",\n+\t\t\t\"I2C_BUS_MUX_RESET_L-O\";\n+\t};\n+\n+\t// Module 1, Expander @0x21\n+\texp1: gpio@21 {\n+\t\tcompatible = \"nxp,pca9555\";\n+\t\treg = <0x21>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\t\tgpio-line-names =\n+\t\t\t\"SEC_FPGA_THERM_OVERT_L-I\",\n+\t\t\t\"SEC_FPGA_READY_BMC-I\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"SEC_FPGA_EROT_FATAL_ERROR_L-I\",\n+\t\t\t\"SEC_WP_HW_EXT_CTRL_L-O\",\n+\t\t\t\"SEC_EROT_FPGA_RST_L-O\",\n+\t\t\t\"SEC_FPGA_EROT_RECOVERY_L-O\",\n+\t\t\t\"SEC_BMC_EROT_FPGA_SPI_MUX_SEL-O\",\n+\t\t\t\"SEC_USB2_HUB_RST_L-O\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"SEC_I2C_BUS_MUX_RESET_L-O\";\n+\t};\n+\n+ // UT3.0b Expander @0x22\n+ exp2: gpio@22 {\n+\t\tcompatible = \"nxp,pca9555\";\n+\t\treg = <0x22>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <14 IRQ_TYPE_LEVEL_LOW>;\n+\t\tgpio-line-names =\n+\t\t\t\"BMC1_FANCTRL_FAIL_L-I\",\n+\t\t\t\"IOEXP_BMC_RST_12V-O\",\n+\t\t\t\"NODE_RST_STBY_H-O\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\";\n+\t};\n+\n+ // UT3.0b Expander @0x23\n+ exp3: gpio@23 {\n+\t\tcompatible = \"nxp,pca9555\";\n+\t\treg = <0x23>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <14 IRQ_TYPE_LEVEL_LOW>;\n+\t\tgpio-line-names =\n+\t\t\t\"PEXSW_FL_SPI_MUX_SEL-O\",\n+\t\t\t\"PEX_SW_FATAL_ERROR_3V3_L-I\",\n+\t\t\t\"IOEXP_PDB_NODE_EN_L-O\",\n+\t\t\t\"NODE_PWOK_ISO-I\",\n+\t\t\t\"BMC_FAN_PWR_EN-O\",\n+\t\t\t\"BMC_ETHERNET_INT-I\",\n+\t\t\t\"BMC_ENET_RST-O\",\n+\t\t\t\"IOEXP_BMC_RST_SENSE-O\",\n+\t\t\t\"BMC_ID-I\",\n+\t\t\t\"TPM_MUX_3V3_SEL_N-O\",\n+\t\t\t\"IOEXP_TPM_RST_N-O\",\n+\t\t\t\"TPM_DOWN_SPI_INT_L-I\",\n+\t\t\t\"PS_BRD_PGOOD-I\",\n+\t\t\t\"FP_BUTTON_POWER_N-I\",\n+\t\t\t\"FP_BUTTON_RESET_N-I\",\n+\t\t\t\"FP_LED_POWER_GPIOEXP_N-O\";\n+\t};\n+};\n+\n+// I2C11\n+// BMC FRU EEPROM\n+// BMC Temp Sensor\n+&i2c10 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+\n+\t// BMC FRU EEPROM - 256 bytes\n+\teeprom@50 {\n+\t\tcompatible = \"atmel,24c02\";\n+\t\treg = <0x50>;\n+\t\tpagesize = <8>;\n+\t};\n+};\n+\n+// I2C12\n+&i2c11 {\n+\tstatus = \"disabled\";\n+};\n+\n+// I2C13\n+&i2c12 {\n+\tstatus = \"disabled\";\n+};\n+\n+// I2C14\n+// Module 0 UPHY3 SMBus\n+&i2c13 {\n+\tstatus = \"disabled\";\n+};\n+\n+// I2C15\n+// Module 1 UPHY3 SMBus\n+&i2c14 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <100000>;\n+\tmulti-master;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\n+\t//E1.S drive slot 0-3\n+\ti2c-mux@77 {\n+\t\tcompatible = \"nxp,pca9546\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x77>;\n+\t\ti2c-mux-idle-disconnect;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\n+\t\te1si2c0: i2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\te1si2c1: i2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\t\t};\n+\n+\t\te1si2c2: i2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\te1si2c3: i2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t};\n+\t};\n+};\n+\n+// I2C16\n+&i2c15 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <100000>;\n+\tmulti-master;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\n+\t//E1.S drive slot 4-7\n+\ti2c-mux@77 {\n+\t\tcompatible = \"nxp,pca9546\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x77>;\n+\t\ti2c-mux-idle-disconnect;\n+ vcc-supply = <&fixedregulator_standby_power>;\n+\n+\t\te1si2c4: i2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\te1si2c5: i2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\t\t};\n+\n+\t\te1si2c6: i2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\te1si2c7: i2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t};\n+\t};\n+};\n+\n+&rng {\n+\tstatus = \"okay\";\n+};\n+\n+&gpio0 {\n+\tgpio-line-names =\n+\t\t/*A0-A7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*B0-B7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*C0-C7*/ \"SGPIO_I2C_MUX_SEL-O\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*D0-D7*/ \"\", \"\", \"\", \"UART1_MUX_SEL-O\", \"\", \"FPGA_PEX_RST_L-O\", \"\", \"\",\n+\t\t/*E0-E7*/ \"RTL8221_PHY_RST_L-O\", \"RTL8211_PHY_INT_L-I\",\t\"\", \"UART3_MUX_SEL-O\",\n+\t\t\t\t\t\"\", \"\", \"\", \"SGPIO_BMC_EN-O\",\n+\t\t/*F0-F7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*G0-G7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*H0-H7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*I0-I7*/ \"\", \"\", \"\", \"\", \"\", \"QSPI2_RST_L-O\", \"GLOBAL_WP_BMC-O\", \"BMC_DDR4_TEN-O\",\n+\t\t/*J0-J7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*K0-K7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*L0-L7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*M0-M7*/ \"PCIE_EP_RST_EN-O\", \"BMC_FRU_WP-O\", \"FPGA_RST_L-O\", \"STBY_POWER_EN-O\",\n+\t\t\t\t\t\"STBY_POWER_PG-I\", \"PCIE_EP_RST_L-O\", \"\", \"\",\n+\t\t/*N0-N7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*O0-O7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*P0-P7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*Q0-Q7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*R0-R7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*S0-S7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*T0-T7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*U0-U7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*V0-V7*/ \"AP_EROT_REQ-O\", \"EROT_AP_GNT-I\", \"\", \"\",\"PCB_TEMP_ALERT-I\", \"\",\"\", \"\",\n+\t\t/*W0-W7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*X0-X7*/ \"\", \"\", \"TPM_MUX_SEL-O\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*Y0-Y7*/ \"\", \"\", \"\", \"EMMC_RST-O\", \"\",\"\", \"\", \"\",\n+\t\t/*Z0-Z7*/ \"BMC_READY-O\",\"\", \"\", \"\", \"\", \"\", \"\", \"\";\n+};\n+\n+&gpio1 {\n+\t/* 36 1.8V GPIOs */\n+\tgpio-line-names =\n+\t\t/*A0-A7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*B0-B7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"IO_EXPANDER_INT_L-I\",\"\",\n+\t\t/*C0-C7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\t/*D0-D7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"SPI_HOST_TPM_RST_L-O\", \"SPI_BMC_FPGA_INT_L-I\",\n+\t\t/*E0-E7*/ \"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\";\n+};\n", "prefixes": [] }