Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2080613/?format=api
{ "id": 2080613, "url": "http://patchwork.ozlabs.org/api/patches/2080613/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20250503075858.277375-10-pbonzini@redhat.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20250503075858.277375-10-pbonzini@redhat.com>", "list_archive_url": null, "date": "2025-05-03T07:58:54", "name": "[PULL,09/13] target/i386: do not trigger IRQ shadow for LSS", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2022f782907f0479161610d50d4b9eca72a3205e", "submitter": { "id": 2701, "url": "http://patchwork.ozlabs.org/api/people/2701/?format=api", "name": "Paolo Bonzini", "email": "pbonzini@redhat.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20250503075858.277375-10-pbonzini@redhat.com/mbox/", "series": [ { "id": 455199, "url": "http://patchwork.ozlabs.org/api/series/455199/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=455199", "date": "2025-05-03T07:58:51", "name": "[PULL,01/13] rust/vmstate: Add support for field_exists checks", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/455199/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2080613/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2080613/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=Ov5fwjMv;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4ZqKx81WSzz1yMf\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 3 May 2025 18:01:16 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1uB7mb-00088o-FW; Sat, 03 May 2025 03:59:37 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <pbonzini@redhat.com>)\n id 1uB7mW-00086n-2Y\n for qemu-devel@nongnu.org; Sat, 03 May 2025 03:59:32 -0400", "from us-smtp-delivery-124.mimecast.com ([170.10.133.124])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <pbonzini@redhat.com>)\n id 1uB7mU-0006gN-1X\n for qemu-devel@nongnu.org; Sat, 03 May 2025 03:59:31 -0400", "from mail-wm1-f69.google.com (mail-wm1-f69.google.com\n [209.85.128.69]) by relay.mimecast.com with ESMTP with STARTTLS\n (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id\n us-mta-166-aWv9OPSxPsKE6IdWLerNrw-1; Sat, 03 May 2025 03:59:27 -0400", "by mail-wm1-f69.google.com with SMTP id\n 5b1f17b1804b1-43f405810b4so13461425e9.1\n for <qemu-devel@nongnu.org>; Sat, 03 May 2025 00:59:27 -0700 (PDT)", "from [192.168.10.48] ([151.95.54.106])\n by smtp.gmail.com with ESMTPSA id\n 5b1f17b1804b1-441b8a31695sm67646245e9.40.2025.05.03.00.59.23\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Sat, 03 May 2025 00:59:23 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;\n s=mimecast20190719; t=1746259168;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=nQ62A3MCY62mWXW1oMyGxVt/pkkUQ6ezdwuuGxH7Rf0=;\n b=Ov5fwjMva2dZ3WXGuh53eWKusamtp5MhZNwX8e7XFmkMSp6Pb8Oa0UGKiEVVA3o5jfmjVG\n zubcMHR98yHEEl7RD0kP1G3L8Bct5Ap4/bQVPTez7Yfd7RoBMbXMILrlXU0lOpcLPun7TD\n +NhbTBBkCaW3HcmEHZTIhVMdAsF64hU=", "X-MC-Unique": "aWv9OPSxPsKE6IdWLerNrw-1", "X-Mimecast-MFC-AGG-ID": "aWv9OPSxPsKE6IdWLerNrw_1746259166", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1746259165; x=1746863965;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc\n :subject:date:message-id:reply-to;\n bh=nQ62A3MCY62mWXW1oMyGxVt/pkkUQ6ezdwuuGxH7Rf0=;\n b=T+ciHMHULpVcswmWasl/fYeyxH490f75btGMWmjK4wDUK//CTkSqFG8X2tkDVmVCHV\n SbYAMsMYhlf+FqG9cutUanW18ldyXG8dKiH9Hc8lQrw5xjW71gzXcWY8jryKUB/zVaS/\n zlxluRE19/+kKUfvcgJEtB3H0S4hbe/y+WbSDI/iz1amWoTRIRTcs1e/mP/Anebhf2ua\n K0aFVKl/67ZOPj9svgdTllug6Qr9lhV/jU0Gg3qMrG5/yJDfAkd5TeqyKa1dhW+PLBek\n u5H/ldpNaD3lpoM1A619MZuSqa1MKvLvQ5zrs0nfrn5vd9cayJYP6sfBPW4+F5wvJ5WP\n o1yQ==", "X-Gm-Message-State": "AOJu0Yz5C1ViG1gtwWDWHEzjuRS362npdi00AgYM0gFWE6TGhz2Ukwoe\n ZAcrgiDEDT3BbN/uU9VeGg5q1vUD/ZEkc4rtznPD9b/GY7zPjflel5ykvhJPQuzA/6sdaNAY1B0\n bzDuhsilyZDQ4FqiPeRH5qE0rWdu9azOOmnCJPCcO5GC5ASDvRWIyducF4HFHHd2KpaKx6Lmn1Q\n 2g4H0K9xSFc1qcC5kzEbQgKNPmvlGDNCsyqNfS", "X-Gm-Gg": "ASbGncuxHD9anNQQGw82jqF+oUQhZrBflMfyXXYXrMDiLq+/KuJZ7O5d12eqUsCp33s\n bh+titeLe51bh+s1cCUmcmBxFgMgh9EVS3KzdVkd1CsGlzRoj8Dri5XT37hpCOIaDp07KiFxohQ\n FKLALiF6PAe9Kdh/tc7yUrKwR7YnFWijw3tu9NPFwarTIDB628k6GRiPw2qamE1HmgA2UxC8/Tr\n DPlFU2Hn6fYonnLemDIyzRBRh+qOf7Yj80AwYEsc/kzcgfW4sy3yadz2ANpo7Q/LzS5xbnurCPs\n 6jsUe5X8gxl3DUg=", "X-Received": [ "by 2002:a05:600c:34c3:b0:43d:a90:9f1 with SMTP id\n 5b1f17b1804b1-441c48b0404mr1998175e9.6.1746259165603;\n Sat, 03 May 2025 00:59:25 -0700 (PDT)", "by 2002:a05:600c:34c3:b0:43d:a90:9f1 with SMTP id\n 5b1f17b1804b1-441c48b0404mr1998005e9.6.1746259165170;\n Sat, 03 May 2025 00:59:25 -0700 (PDT)" ], "X-Google-Smtp-Source": "\n AGHT+IGIHvKHSSB81eDIixqHq/Zvp0mz1bwWI8osNGzApgcVe3ruCOlSZi/uTpxfNRzCQMgxPInfFw==", "From": "Paolo Bonzini <pbonzini@redhat.com>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-stable@nongnu.org", "Subject": "[PULL 09/13] target/i386: do not trigger IRQ shadow for LSS", "Date": "Sat, 3 May 2025 09:58:54 +0200", "Message-ID": "<20250503075858.277375-10-pbonzini@redhat.com>", "X-Mailer": "git-send-email 2.49.0", "In-Reply-To": "<20250503075858.277375-1-pbonzini@redhat.com>", "References": "<20250503075858.277375-1-pbonzini@redhat.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=170.10.133.124;\n envelope-from=pbonzini@redhat.com;\n helo=us-smtp-delivery-124.mimecast.com", "X-Spam_score_int": "-26", "X-Spam_score": "-2.7", "X-Spam_bar": "--", "X-Spam_report": "(-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.644,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Because LSS need not trigger an IRQ shadow, gen_movl_seg can't just use\nthe destination register to decide whether to inhibit IRQs. Add an\nargument.\n\nCc: qemu-stable@nongnu.org\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>\n---\n target/i386/tcg/translate.c | 27 ++++++++++++++++-----------\n target/i386/tcg/emit.c.inc | 4 ++--\n 2 files changed, 18 insertions(+), 13 deletions(-)", "diff": "diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c\nindex 8a641951cd1..a4e935b043b 100644\n--- a/target/i386/tcg/translate.c\n+++ b/target/i386/tcg/translate.c\n@@ -2026,27 +2026,32 @@ static void gen_op_movl_seg_real(DisasContext *s, X86Seg seg_reg, TCGv seg)\n \n /* move SRC to seg_reg and compute if the CPU state may change. Never\n call this function with seg_reg == R_CS */\n-static void gen_movl_seg(DisasContext *s, X86Seg seg_reg, TCGv src)\n+static void gen_movl_seg(DisasContext *s, X86Seg seg_reg, TCGv src, bool inhibit_irq)\n {\n if (PE(s) && !VM86(s)) {\n TCGv_i32 sel = tcg_temp_new_i32();\n \n tcg_gen_trunc_tl_i32(sel, src);\n gen_helper_load_seg(tcg_env, tcg_constant_i32(seg_reg), sel);\n- /* abort translation because the addseg value may change or\n- because ss32 may change. For R_SS, translation must always\n- stop as a special handling must be done to disable hardware\n- interrupts for the next instruction */\n- if (seg_reg == R_SS) {\n- s->base.is_jmp = DISAS_EOB_INHIBIT_IRQ;\n- } else if (CODE32(s) && seg_reg < R_FS) {\n+\n+ /* For move to DS/ES/SS, the addseg or ss32 flags may change. */\n+ if (CODE32(s) && seg_reg < R_FS) {\n s->base.is_jmp = DISAS_EOB_NEXT;\n }\n } else {\n gen_op_movl_seg_real(s, seg_reg, src);\n- if (seg_reg == R_SS) {\n- s->base.is_jmp = DISAS_EOB_INHIBIT_IRQ;\n- }\n+ }\n+\n+ /*\n+ * For MOV or POP to SS (but not LSS) translation must always\n+ * stop as a special handling must be done to disable hardware\n+ * interrupts for the next instruction.\n+ *\n+ * DISAS_EOB_INHIBIT_IRQ is a superset of DISAS_EOB_NEXT which\n+ * might have been set above.\n+ */\n+ if (inhibit_irq) {\n+ s->base.is_jmp = DISAS_EOB_INHIBIT_IRQ;\n }\n }\n \ndiff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc\nindex e3166e70a5b..1a7fab9333a 100644\n--- a/target/i386/tcg/emit.c.inc\n+++ b/target/i386/tcg/emit.c.inc\n@@ -342,7 +342,7 @@ static void gen_writeback(DisasContext *s, X86DecodedInsn *decode, int opn, TCGv\n break;\n case X86_OP_SEG:\n /* Note that gen_movl_seg takes care of interrupt shadow and TF. */\n- gen_movl_seg(s, op->n, s->T0);\n+ gen_movl_seg(s, op->n, v, op->n == R_SS);\n break;\n case X86_OP_INT:\n if (op->has_ea) {\n@@ -2382,7 +2382,7 @@ static void gen_lxx_seg(DisasContext *s, X86DecodedInsn *decode, int seg)\n gen_op_ld_v(s, MO_16, s->T1, s->A0);\n \n /* load the segment here to handle exceptions properly */\n- gen_movl_seg(s, seg, s->T1);\n+ gen_movl_seg(s, seg, s->T1, false);\n }\n \n static void gen_LDS(DisasContext *s, X86DecodedInsn *decode)\n", "prefixes": [ "PULL", "09/13" ] }