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GET /api/patches/2070361/?format=api
{ "id": 2070361, "url": "http://patchwork.ozlabs.org/api/patches/2070361/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20250409023711.2960618-5-maobibo@loongson.cn/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20250409023711.2960618-5-maobibo@loongson.cn>", "list_archive_url": null, "date": "2025-04-09T02:36:59", "name": "[v3,04/16] hw/intc/loongarch_pch: Set version information at initial stage", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "02648ecb413e9196081c0cd654d4fa3aef1a2c38", "submitter": { "id": 78914, "url": "http://patchwork.ozlabs.org/api/people/78914/?format=api", "name": "Bibo Mao", "email": "maobibo@loongson.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20250409023711.2960618-5-maobibo@loongson.cn/mbox/", "series": [ { "id": 451861, "url": "http://patchwork.ozlabs.org/api/series/451861/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=451861", "date": "2025-04-09T02:37:00", "name": "hw/intc/loongarch_pch: Cleanup with memory region ops", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/451861/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2070361/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2070361/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4ZXRvm6Btbz1yJQ\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 9 Apr 2025 12:38:28 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1u2LJh-0006Tu-DI; Tue, 08 Apr 2025 22:37:29 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <maobibo@loongson.cn>)\n id 1u2LJe-0006TM-Nk\n for qemu-devel@nongnu.org; Tue, 08 Apr 2025 22:37:26 -0400", "from mail.loongson.cn ([114.242.206.163])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <maobibo@loongson.cn>) id 1u2LJc-0007nC-3H\n for qemu-devel@nongnu.org; Tue, 08 Apr 2025 22:37:26 -0400", "from loongson.cn (unknown [10.2.10.34])\n by gateway (Coremail) with SMTP id _____8Ax3eJb3fVnFa+1AA--.1076S3;\n Wed, 09 Apr 2025 10:37:15 +0800 (CST)", "from localhost.localdomain (unknown [10.2.10.34])\n by front1 (Coremail) with SMTP id qMiowMBxLsdY3fVnnsR1AA--.28294S6;\n Wed, 09 Apr 2025 10:37:14 +0800 (CST)" ], "From": "Bibo Mao <maobibo@loongson.cn>", "To": "Song Gao <gaosong@loongson.cn>", "Cc": "Jiaxun Yang <jiaxun.yang@flygoat.com>,\n\tqemu-devel@nongnu.org", "Subject": "[PATCH v3 04/16] hw/intc/loongarch_pch: Set version information at\n initial stage", "Date": "Wed, 9 Apr 2025 10:36:59 +0800", "Message-Id": "<20250409023711.2960618-5-maobibo@loongson.cn>", "X-Mailer": "git-send-email 2.39.3", "In-Reply-To": "<20250409023711.2960618-1-maobibo@loongson.cn>", "References": "<20250409023711.2960618-1-maobibo@loongson.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "qMiowMBxLsdY3fVnnsR1AA--.28294S6", "X-CM-SenderInfo": "xpdruxter6z05rqj20fqof0/", "X-Coremail-Antispam": "1Uk129KBj93XoWxCrW3Gr45Kw13XF4xtrW7ZFc_yoW5CF4rpF\n W3CF9xtrWktrWxXrn3Zw15ZrnxJFnakryY9anIkF95AFs3Jry8XryktayDXa4Yg3yrJryq\n qrsIkayF9a1UZFcCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa\n sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU\n 0xBIdaVrnRJUUUyEb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2\n IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v\n e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI\n 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_\n GcCE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27wAqx4\n xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_WrylYx0Ex4A2jsIE14v2\n 6r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x0EwI\n xGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480\n Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vIr41lIxAIcVC0I7\n IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF04k2\n 6cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxV\n AFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU8sXo7UUUUU==", "Received-SPF": "pass client-ip=114.242.206.163;\n envelope-from=maobibo@loongson.cn;\n helo=mail.loongson.cn", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Register PCH_PIC_INT_ID constains version and supported irq number\ninformation, and it is read only register. The detailed value can\nbe set at initial stage, rather than read callback.\n\nSigned-off-by: Bibo Mao <maobibo@loongson.cn>\n---\n hw/intc/loongarch_pch_pic.c | 22 +++++++++++++++-------\n include/hw/intc/loongarch_pic_common.h | 17 +++++++++++++++--\n 2 files changed, 30 insertions(+), 9 deletions(-)", "diff": "diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c\nindex a2d9930ac9..ae2dbdfafe 100644\n--- a/hw/intc/loongarch_pch_pic.c\n+++ b/hw/intc/loongarch_pch_pic.c\n@@ -80,15 +80,10 @@ static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,\n \n switch (offset) {\n case PCH_PIC_INT_ID:\n- val = PCH_PIC_INT_ID_VAL;\n+ val = s->id.data & UINT_MAX;\n break;\n case PCH_PIC_INT_ID + 4:\n- /*\n- * With 7A1000 manual\n- * bit 0-15 pch irqchip version\n- * bit 16-31 irq number supported with pch irqchip\n- */\n- val = deposit32(PCH_PIC_INT_ID_VER, 16, 16, s->irq_num - 1);\n+ val = s->id.data >> 32;\n break;\n case PCH_PIC_INT_MASK:\n val = (uint32_t)s->int_mask;\n@@ -361,6 +356,19 @@ static void loongarch_pch_pic_reset(DeviceState *d)\n LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(d);\n int i;\n \n+ /*\n+ * With Loongson 7A1000 user manual\n+ * Chapter 5.2 \"Description of Interrupt-related Registers\"\n+ *\n+ * Interrupt controller identification register 1\n+ * Bit 24-31 Interrupt Controller ID\n+ * Interrupt controller identification register 2\n+ * Bit 0-7 Interrupt Controller version number\n+ * Bit 16-23 The number of interrupt sources supported\n+ */\n+ s->id.desc.id = PCH_PIC_INT_ID_VAL;\n+ s->id.desc.version = PCH_PIC_INT_ID_VER;\n+ s->id.desc.irq_num = s->irq_num - 1;\n s->int_mask = -1;\n s->htmsi_en = 0x0;\n s->intedge = 0x0;\ndiff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h\nindex ef6edc15bf..fb848da4b8 100644\n--- a/include/hw/intc/loongarch_pic_common.h\n+++ b/include/hw/intc/loongarch_pic_common.h\n@@ -10,9 +10,9 @@\n #include \"hw/pci-host/ls7a.h\"\n #include \"hw/sysbus.h\"\n \n-#define PCH_PIC_INT_ID_VAL 0x7000000UL\n-#define PCH_PIC_INT_ID_VER 0x1UL\n #define PCH_PIC_INT_ID 0x00\n+#define PCH_PIC_INT_ID_VAL 0x7\n+#define PCH_PIC_INT_ID_VER 0x1\n #define PCH_PIC_INT_MASK 0x20\n #define PCH_PIC_HTMSI_EN 0x40\n #define PCH_PIC_INT_EDGE 0x60\n@@ -30,10 +30,23 @@\n OBJECT_DECLARE_TYPE(LoongArchPICCommonState,\n LoongArchPICCommonClass, LOONGARCH_PIC_COMMON)\n \n+union LoongArchPIC_ID {\n+ struct {\n+ uint64_t _reserved_0:24;\n+ uint64_t id:8;\n+ uint64_t version:8;\n+ uint64_t _reserved_1:8;\n+ uint64_t irq_num:8;\n+ uint64_t _reserved_2:8;\n+ } QEMU_PACKED desc;\n+ uint64_t data;\n+};\n+\n struct LoongArchPICCommonState {\n SysBusDevice parent_obj;\n \n qemu_irq parent_irq[64];\n+ union LoongArchPIC_ID id; /* 0x00 interrupt ID register */\n uint64_t int_mask; /* 0x020 interrupt mask register */\n uint64_t htmsi_en; /* 0x040 1=msi */\n uint64_t intedge; /* 0x060 edge=1 level=0 */\n", "prefixes": [ "v3", "04/16" ] }