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GET /api/patches/2038242/?format=api
{ "id": 2038242, "url": "http://patchwork.ozlabs.org/api/patches/2038242/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250124051819.7714-1-wthai@nvidia.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20250124051819.7714-1-wthai@nvidia.com>", "list_archive_url": null, "date": "2025-01-24T05:18:19", "name": "ARM: dts: aspeed: Add device tree for Nvidia's GB200NVL BMC", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "f9eb4a0672554aa7857eba0ce9d8b62321abf365", "submitter": { "id": 90154, "url": "http://patchwork.ozlabs.org/api/people/90154/?format=api", "name": "Willie Thai", "email": "wthai@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250124051819.7714-1-wthai@nvidia.com/mbox/", "series": [ { "id": 441596, "url": "http://patchwork.ozlabs.org/api/series/441596/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=441596", "date": "2025-01-24T05:18:19", "name": "ARM: dts: aspeed: Add device tree for Nvidia's GB200NVL BMC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/441596/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2038242/comments/", "check": "warning", "checks": "http://patchwork.ozlabs.org/api/patches/2038242/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <devicetree+bounces-140678-incoming-dt=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming-dt@patchwork.ozlabs.org", "devicetree@vger.kernel.org" ], "Delivered-To": "patchwork-incoming-dt@legolas.ozlabs.org", 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216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Willie Thai <wthai@nvidia.com>", "To": "<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,\n\t<joel@jms.id.au>, <andrew@codeconstruct.com.au>, <kees@kernel.org>,\n\t<tony.luck@intel.com>, <gpiccoli@igalia.com>, <devicetree@vger.kernel.org>,\n\t<linux-arm-kernel@lists.infradead.org>, <linux-aspeed@lists.ozlabs.org>,\n\t<linux-kernel@vger.kernel.org>, <linux-hardening@vger.kernel.org>,\n\t<openbmc@lists.ozlabs.org>", "CC": "<wthai@nvidia.com>, <leohu@nvidia.com>, <tingkaic@nvidia.com>,\n\t<dkodihalli@nvidia.com>, wthai <wthai@willie-obmc-builder.nvidia.com>", "Subject": "[PATCH] ARM: dts: aspeed: Add device tree for Nvidia's GB200NVL BMC", "Date": "Fri, 24 Jan 2025 05:18:19 +0000", "Message-ID": "<20250124051819.7714-1-wthai@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "Precedence": "bulk", "X-Mailing-List": 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"X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(1800799024)(82310400026)(921020);DIR:OUT;SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Jan 2025 05:18:40.4145\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b2c6f620-d50d-4141-394e-08dd3c369078", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n MN1PEPF0000ECD8.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH2PR12MB9496" }, "content": "From: wthai <wthai@willie-obmc-builder.nvidia.com>\n\nThe GB200NVL BMC is an Aspeed Ast2600 based BMC\nfor Nvidia Blackwell GB200NVL platform.\n\nSigned-off-by: wthai <wthai@nvidia.com>\n---\n .../bindings/arm/aspeed/aspeed.yaml | 1 +\n arch/arm/boot/dts/aspeed/Makefile | 1 +\n .../aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts | 1352 +++++++++++++++++\n 3 files changed, 1354 insertions(+)\n create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts", "diff": "diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml\nindex 2f92b8ab08fa..0a6f3654dcb5 100644\n--- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml\n+++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml\n@@ -96,6 +96,7 @@ properties:\n - inventec,starscream-bmc\n - inventec,transformer-bmc\n - jabil,rbp-bmc\n+ - nvidia,gb200nvl-bmc\n - qcom,dc-scm-v1-bmc\n - quanta,s6q-bmc\n - ufispace,ncplite-bmc\ndiff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile\nindex c4f064e4b073..0dc5240866f3 100644\n--- a/arch/arm/boot/dts/aspeed/Makefile\n+++ b/arch/arm/boot/dts/aspeed/Makefile\n@@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \\\n \taspeed-bmc-lenovo-hr630.dtb \\\n \taspeed-bmc-lenovo-hr855xg2.dtb \\\n \taspeed-bmc-microsoft-olympus.dtb \\\n+\taspeed-bmc-nvidia-gb200nvl-bmc.dtb \\\n \taspeed-bmc-opp-lanyang.dtb \\\n \taspeed-bmc-opp-mowgli.dtb \\\n \taspeed-bmc-opp-nicole.dtb \\\ndiff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts\nnew file mode 100644\nindex 000000000000..91d025229aba\n--- /dev/null\n+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts\n@@ -0,0 +1,1352 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/dts-v1/;\n+\n+#include \"aspeed-g6.dtsi\"\n+#include <dt-bindings/gpio/aspeed-gpio.h>\n+#include <dt-bindings/leds/common.h>\n+\n+&gpio0 {\n+\tgpio-line-names =\n+\n+\t/* gpio-line-names are the combination of <signal>-<I/O> , \"\" is the placeholder for the unused pins\n+\t*/\n+\n+\t/* 208 (26*8) 3.3V GPIOs */\n+\n+\t/*A0-A7*/\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*B0-B7*/\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*C0-C7*/\n+\t\"SGPIO_I2C_MUX_SEL-O\",\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*D0-D7*/\n+\t\"\", \"\", \"\",\n+\t\"UART1_MUX_SEL-O\",\n+\t\"\",\n+\t\"FPGA_PEX_RST_L-O\",\n+\t\"\", \"\",\n+\n+\t/*E0-E7*/\n+\t\"RTL8221_PHY_RST_L-O\",\n+\t\"RTL8211_PHY_INT_L-I\",\n+\t\"\",\n+\t\"UART3_MUX_SEL-O\",\n+\t\"\", \"\", \"\",\n+\t\"SGPIO_BMC_EN-O\",\n+\n+\t/*F0-F7*/\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*G0-G7*/\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*H0-H7*/\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*I0-I7*/\n+\t\"\", \"\", \"\", \"\", \"\",\n+\t\"QSPI2_RST_L-O\",\n+\t\"GLOBAL_WP_BMC-O\",\n+\t\"BMC_DDR4_TEN-O\",\n+\n+\t/*J0-J7*/\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*K0-K7*/\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*L0-L7*/\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*M0-M7*/\n+\t\"PCIE_EP_RST_EN-O\",\n+\t\"BMC_FRU_WP-O\",\n+\t\"HMC_RESET_L-O\",\n+\t\"STBY_POWER_EN-O\",\n+\t\"STBY_POWER_PG-I\",\n+\t\"PCIE_EP_RST_L-O\",\n+\t\"\", \"\",\n+\n+\t/*N0-N7*/\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*O0-O7*/\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*P0-P7*/\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*Q0-Q7*/\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*R0-R7*/\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*S0-S7*/\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*T0-T7*/\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*U0-U7*/\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*V0-V7*/\n+\t\"AP_EROT_REQ-O\",\n+\t\"EROT_AP_GNT-I\",\n+\t\"\",\n+\t\"\",\n+\t\"PCB_TEMP_ALERT-I\",\n+\t\"\", \"\", \"\",\n+\n+\t/*W0-W7*/\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\n+\t/*X0-X7*/\n+\t\"\", \"\",\n+\t\"TPM_MUX_SEL-O\",\n+\t\"\", \"\", \"\", \"\", \"\",\n+\n+\t/*Y0-Y7*/\n+\t\"\", \"\", \"\",\n+\t\"EMMC_RST-O\",\n+\t\"\",\"\", \"\", \"\",\n+\n+\t/*Z0-Z7*/\n+\t\"BMC_READY-O\",\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\";\n+};\n+\n+&sgpiom0 {\n+\tstatus=\"okay\";\n+\tngpios = <128>;\n+\n+\tgpio-line-names =\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"RUN_POWER_FAULT_L-I\",\n+\t\"SYS_RST_IN_L-O\",\n+\t\"RUN_POWER_PG-I\",\n+\t\"PWR_BRAKE_L-O\",\n+\t\"SYS_RST_OUT_L-I\",\n+\t\"RUN_POWER_EN-O\",\n+\t\"L0L1_RST_REQ_OUT_L-I\",\n+\t\"SHDN_FORCE_L-O\",\n+\t\"L2_RST_REQ_OUT_L-I\",\n+\t\"SHDN_REQ_L-O\",\n+\t\"SHDN_OK_L-I\",\n+\t\"UID_LED_N-O\",\n+\t\"BMC_I2C1_FPGA_ALERT_L-I\",\n+\t\"SYS_FAULT_LED_N-O\",\n+\t\"BMC_I2C0_FPGA_ALERT_L-I\",\n+\t\"PWR_LED_N-O\",\n+\t\"FPGA_RSVD_FFU3-I\",\n+\t\"\",\n+\t\"FPGA_RSVD_FFU2-I\",\n+\t\"\",\n+\t\"FPGA_RSVD_FFU1-I\",\n+\t\"\",\n+\t\"FPGA_RSVD_FFU0-I\",\n+\t\"BMC_I2C_SSIF_ALERT_L-O\",\n+\t\"CPU_BOOT_DONE-I\",\n+\t\"JTAG_MUX_SELECT-O\",\n+\t\"SPI_BMC_FPGA_INT_L-I\",\n+\t\"RTC_CLR_L-O\",\n+\t\"THERM_BB_WARN_L-I\",\n+\t\"UART_MUX_SEL-O\",\n+\t\"THERM_BB_OVERT_L-I\",\n+\t\"\",\n+\t\"CPU0_UPHY3_PRSNT1_L-I\",\n+\t\"IOBRD0_RUN_POWER_EN-O\",\n+\t\"CPU0_UPHY3_PRSNT0_L-I\",\n+\t\"IOBRD1_RUN_POWER_EN-O\",\n+\t\"CPU0_UPHY2_PRSNT1_L-I\",\n+\t\"FPGA_RSVD_FFU4-O\",\n+\t\"CPU0_UPHY2_PRSNT0_L-I\",\n+\t\"FPGA_RSVD_FFU5-O\",\n+\t\"CPU0_UPHY1_PRSNT1_L-I\",\n+\t\"FPGA_RSVD_FFU6-O\",\n+\t\"CPU0_UPHY1_PRSNT0_L-I\",\n+\t\"FPGA_RSVD_FFU7-O\",\n+\t\"CPU0_UPHY0_PRSNT1_L-I\",\n+\t\"RSVD_NV_PLT_DETECT-O\",\n+\t\"CPU0_UPHY0_PRSNT0_L-I\",\n+\t\"SPI1_INT_L-O\",\n+\t\"CPU1_UPHY3_PRSNT1_L-I\",\n+\t\"\",\n+\t\"CPU1_UPHY3_PRSNT0_L-I\",\n+\t\"HMC_EROT_MUX_STATUS\",\n+\t\"CPU1_UPHY2_PRSNT1_L-I\",\n+\t\"\",\n+\t\"CPU1_UPHY2_PRSNT0_L-I\",\n+\t\"\",\n+\t\"CPU1_UPHY1_PRSNT1_L-I\",\n+\t\"\",\n+\t\"CPU1_UPHY1_PRSNT0_L-I\",\n+\t\"\",\n+\t\"CPU1_UPHY0_PRSNT1_L-I\",\n+\t\"\",\n+\t\"CPU1_UPHY0_PRSNT0_L-I\",\n+\t\"\",\n+\t\"FAN1_PRESENT_L-I\",\n+\t\"\",\n+\t\"FAN0_PRESENT_L-I\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"IPEX_CABLE_PRSNT_L-I\",\n+\t\"\",\n+\t\"M2_1_PRSNT_L-I\",\n+\t\"\",\n+\t\"M2_0_PRSNT_L-I\",\n+\t\"\",\n+\t\"CPU1_UPHY4_PRSNT1_L-I\",\n+\t\"\",\n+\t\"CPU0_UPHY4_PRSNT0_L-I\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"I2C_RTC_ALERT_L-I\",\n+\t\"\",\n+\t\"FAN7_PRESENT_L-I\",\n+\t\"\",\n+\t\"FAN6_PRESENT_L-I\",\n+\t\"\",\n+\t\"FAN5_PRESENT_L-I\",\n+\t\"\",\n+\t\"FAN4_PRESENT_L-I\",\n+\t\"\",\n+\t\"FAN3_PRESENT_L-I\",\n+\t\"\",\n+\t\"FAN2_PRESENT_L-I\",\n+\t\"\",\n+\t\"IOBRD0_IOX_INT_L-I\",\n+\t\"\",\n+\t\"IOBRD1_PRSNT_L-I\",\n+\t\"\",\n+\t\"IOBRD0_PRSNT_L-I\",\n+\t\"\",\n+\t\"IOBRD1_PWR_GOOD-I\",\n+\t\"\",\n+\t\"IOBRD0_PWR_GOOD-I\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"FAN_FAIL_IN_L-I\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"PDB_CABLE_PRESENT_L-I\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"CHASSIS_PWR_BRK_L-I\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"IOBRD1_IOX_INT_L-I\",\n+\t\"\",\n+\t\"10GBE_SMBALRT_L-I\",\n+\t\"\",\n+\t\"PCIE_WAKE_L-I\",\n+\t\"\",\n+\t\"I2C_M21_ALERT_L-I\",\n+\t\"\",\n+\t\"I2C_M20_ALERT_L-I\",\n+\t\"\",\n+\t\"TRAY_FAST_SHDN_L-I\",\n+\t\"\",\n+\t\"UID_BTN_N-I\",\n+\t\"\",\n+\t\"PWR_BTN_L-I\",\n+\t\"\",\n+\t\"PSU_SMB_ALERT_L-I\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"NODE_LOC_ID[0]-I\",\n+\t\"\",\n+\t\"NODE_LOC_ID[1]-I\",\n+\t\"\",\n+\t\"NODE_LOC_ID[2]-I\",\n+\t\"\",\n+\t\"NODE_LOC_ID[3]-I\",\n+\t\"\",\n+\t\"NODE_LOC_ID[4]-I\",\n+\t\"\",\n+\t\"NODE_LOC_ID[5]-I\",\n+\t\"\",\n+\t\"FAN10_PRESENT_L-I\",\n+\t\"\",\n+\t\"FAN9_PRESENT_L-I\",\n+\t\"\",\n+\t\"FAN8_PRESENT_L-I\",\n+\t\"\",\n+\t\"FPGA1_READY_HMC-I\",\n+\t\"\",\n+\t\"DP_HPD-I\",\n+\t\"\",\n+\t\"HMC_I2C3_FPGA_ALERT_L-I\",\n+\t\"\",\n+\t\"HMC_I2C2_FPGA_ALERT_L-I\",\n+\t\"\",\n+\t\"FPGA0_READY_HMC-I\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"LEAK_DETECT_ALERT_L-I\",\n+\t\"\",\n+\t\"MOD1_B2B_CABLE_PRESENT_L-I\",\n+\t\"\",\n+\t\"MOD1_CLINK_CABLE_PRESENT_L-I\",\n+\t\"\",\n+\t\"FAN11_PRESENT_L-I\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"\",\n+\t\"RSVD_SGPIO_IN_CRC[0]\",\n+\t\"RSVD_SGPIO_O_CRC[7]\",\n+\t\"RSVD_SGPIO_IN_CRC[1]\",\n+\t\"RSVD_SGPIO_O_CRC[6]\",\n+\t\"RSVD_SGPIO_IN_CRC[2]\",\n+\t\"RSVD_SGPIO_O_CRC[5]\",\n+\t\"RSVD_SGPIO_IN_CRC[3]\",\n+\t\"RSVD_SGPIO_O_CRC[4]\",\n+\t\"RSVD_SGPIO_IN_CRC[4]\",\n+\t\"RSVD_SGPIO_O_CRC[3]\",\n+\t\"RSVD_SGPIO_IN_CRC[5]\",\n+\t\"RSVD_SGPIO_O_CRC[2]\",\n+\t\"RSVD_SGPIO_IN_CRC[6]\",\n+\t\"RSVD_SGPIO_O_CRC[1]\",\n+\t\"RSVD_SGPIO_IN_CRC[7]\",\n+\t\"RSVD_SGPIO_O_CRC[0]\";\n+};\n+\n+// EMMC group that excludes WP pin\n+&pinctrl {\n+\tpinctrl_emmcg5_default: emmcg5_default {\n+\t\tfunction = \"EMMC\";\n+\t\tgroups = \"EMMCG5\";\n+\t};\n+};\n+\n+/ {\n+\tmodel = \"AST2600 GB200NVL BMC\";\n+\tcompatible = \"nvidia,gb200nvl-bmc\", \"aspeed,ast2600\";\n+\n+\taliases {\n+\t\tserial2 = &uart3;\n+\t\tserial4 = &uart5;\n+\t\ti2c16 = &imux16;\n+\t\ti2c17 = &imux17;\n+\t\ti2c18 = &imux18;\n+\t\ti2c19 = &imux19;\n+\t\ti2c20 = &imux20;\n+\t\ti2c21 = &imux21;\n+\t\ti2c22 = &imux22;\n+\t\ti2c23 = &imux23;\n+\t\ti2c24 = &imux24;\n+\t\ti2c25 = &imux25;\n+\t\ti2c26 = &imux26;\n+\t\ti2c27 = &imux27;\n+\t\ti2c28 = &imux28;\n+\t\ti2c29 = &imux29;\n+\t\ti2c30 = &imux30;\n+\t\ti2c31 = &imux31;\n+\t\ti2c32 = &imux32;\n+\t\ti2c33 = &imux33;\n+\t\ti2c34 = &imux34;\n+\t\ti2c35 = &imux35;\n+\t\ti2c36 = &imux36;\n+\t\ti2c37 = &imux37;\n+\t\ti2c38 = &imux38;\n+\t\ti2c39 = &imux39;\n+\t\ti2c40\t= &e1si2c0;\n+\t\ti2c41\t= &e1si2c1;\n+\t\ti2c42\t= &e1si2c2;\n+\t\ti2c43\t= &e1si2c3;\n+\t\ti2c44\t= &e1si2c4;\n+\t\ti2c45\t= &e1si2c5;\n+\t\ti2c46\t= &e1si2c6;\n+\t\ti2c47\t= &e1si2c7;\n+\t\ti2c48\t= &i2c5mux0;\n+\t\ti2c49 = &m2riser;\n+\t\ti2c50\t= &i2c5mux2;\n+\t\ti2c51\t= &i2c5mux3;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = &uart5;\n+\t\tbootargs = \"console=tty0 console=ttyS4,115200n8 earlyprintk\";\n+\t};\n+\n+\tmemory@80000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x80000000 0x80000000>;\n+\t};\n+\n+\treserved-memory {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges;\n+\n+\t\tvga_memory: framebuffer@9f000000 {\n+\t\t\tno-map;\n+\t\t\treg = <0x9f000000 0x01000000>; /* 16M */\n+\t\t};\n+\n+\t\tramoops@a0000000 {\n+\t\t\tcompatible = \"ramoops\";\n+\t\t\treg = <0xa0000000 0x100000>; /* 1MB */\n+\t\t\trecord-size = <0x10000>; /* 64KB */\n+\t\t\tmax-reason = <2>; /* KMSG_DUMP_OOPS */\n+\t\t};\n+\n+\t\tgfx_memory: framebuffer {\n+\t\t\tsize = <0x01000000>;\n+\t\t\talignment = <0x01000000>;\n+\t\t\tcompatible = \"shared-dma-pool\";\n+\t\t\treusable;\n+\t\t};\n+\n+\t\tvideo_engine_memory: jpegbuffer {\n+\t\t\tsize = <0x02000000>;\t/* 32M */\n+\t\t\talignment = <0x01000000>;\n+\t\t\tcompatible = \"shared-dma-pool\";\n+\t\t\treusable;\n+\t\t};\n+\t};\n+\n+\tpower-gpios{\n+\t\tn2-gpios = <&gpio0 ASPEED_GPIO(N, 2) (GPIO_ACTIVE_HIGH|GPIO_PULL_UP)>;\n+\t\tn3-gpios = <&gpio0 ASPEED_GPIO(N, 3) (GPIO_ACTIVE_HIGH|GPIO_PULL_UP)>;\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\t\tuid_led {\n+\t\t\tgpios = <&sgpiom0 27 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t\tfault_led {\n+\t\t\tgpios = <&sgpiom0 29 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t\tpower_led {\n+\t\t\tgpios = <&sgpiom0 31 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\t// Non-LEDs:\n+\t\t// BMC_READY-O GPIO pin (not an LED) is being bound to the GPIO LED driver.\n+\t\t// Notes:\n+\t\t// * This is a workaround and leverages the GPIO LED driver to enable control of\n+\t\t// reset tolerance and still allow the GPIO to be controlled from user space.\n+\t\t// * The standard Linux GPIO driver allows control of reset tolerance, however\n+\t\t// does not expose user space APIs for user space control of the GPIO pin.\n+\t\t// * GPIO_TRANSITORY = reset tolerance is disabled\n+\t\t// * Any non-leds should be added below this line.\n+\t\tbmc_ready_noled {\n+\t\t\tgpios = <&gpio0 ASPEED_GPIO(Z, 0) (GPIO_ACTIVE_HIGH|GPIO_TRANSITORY)>;\n+\t\t};\n+\t};\n+\n+\tbuttons {\n+\t\tpower-btn {\n+\t\t\tgpio = <&sgpiom0 156 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t\tuid-btn {\n+\t\t\tgpio = <&sgpiom0 154 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+};\n+\n+// Enabled Primary flash on FMC for bring up activity\n+&fmc {\n+\tstatus = \"okay\";\n+\tflash@0 {\n+\t\tstatus = \"okay\";\n+\t\tcompatible = \"jedec,spi-nor\";\n+\t\tlabel = \"bmc\";\n+\t\tspi-max-frequency = <50000000>;\n+\t\tpartitions {\n+\t\t\tcompatible = \"fixed-partitions\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tu-boot@0 {\n+\t\t\t\treg = <0x0 0xe0000>; // 896KB\n+\t\t\t\tlabel = \"u-boot\";\n+\t\t\t};\n+\n+\t\t\tkernel@100000 {\n+\t\t\t\treg = <0x100000 0x900000>; // 9MB\n+\t\t\t\tlabel = \"kernel\";\n+\t\t\t};\n+\n+\t\t\trofs@a00000 {\n+\t\t\t\treg = <0xa00000 0x35FF000>; // 55292KB (extends to end of 64MB SPI - 4KB)\n+\t\t\t\tlabel = \"rofs\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&fmcraw {\n+\tstatus = \"okay\";\n+\tspidev@0 {\n+\t\tcompatible = \"hgx,glacier\";\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&spi1raw {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_spi1_default>;\n+\tspidev@0 {\n+\t\tspi-max-frequency = <25000000>;\n+\t\tcompatible = \"hgx,glacier\";\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&spi2 {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_spi2_default>;\n+\n+\t// Data SPI is 64MB in size\n+\tflash@0 {\n+\t\tstatus = \"okay\";\n+\t\tlabel = \"config\";\n+\t\tspi-max-frequency = <50000000>;\n+\t\tpartitions {\n+\t\t\tcompatible = \"fixed-partitions\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tu-boot-env@0 {\n+\t\t\t\treg = <0x0 0x40000>; // 256KB at offset 0\n+\t\t\t\tlabel = \"u-boot-env\";\n+\t\t\t};\n+\n+\t\t\trwfs@40000 {\n+\t\t\t\treg = <0x40000 0x1000000>; // 16MB at offset 0x40000\n+\t\t\t\tlabel = \"rwfs\";\n+\t\t\t};\n+\n+\t\t\tlog@0x1040000 {\n+\t\t\t\treg = <0x1040000 0x2800000>; // 40MB at offset 0x1040000\n+\t\t\t\tlabel = \"log\"; // Move log to EMMC, make this unused\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&uart1 {\n+\tstatus = \"okay\";\n+};\n+\n+&uart3 {\n+\t//Enabling SOL\n+\tstatus = \"okay\";\n+};\n+\n+&uart5 {\n+\t// BMC Debug Console\n+\tstatus = \"okay\";\n+};\n+\n+&uart_routing {\n+\tstatus = \"okay\";\n+};\n+\n+// MAC1 (per schematics, 1-based MAC1-MAC4) of AST2600 connected to external PHY\n+// This is \"mac0\" in zero-based DTS\n+&mdio0 {\n+\tstatus = \"okay\";\n+\tethphy0: ethernet-phy@0 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <0>;\n+\t};\n+\n+};\n+\n+&mdio3 {\n+\tstatus = \"okay\";\n+\tethphy3: ethernet-phy@2 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <2>;\n+\t};\n+};\n+\n+&mac0 {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tphy-mode = \"rgmii-rxid\";\n+\tmax-speed = <1000>;\n+\tphy-handle = <ðphy3>;\n+\tpinctrl-0 = <&pinctrl_rgmii1_default>;\n+};\n+\n+&mac2 {\n+\tstatus = \"okay\";\n+\tphy-mode = \"rmii\";\n+\tuse-ncsi;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_rmii3_default>;\n+};\n+\n+// Enable emmc\n+&emmc_controller {\n+\tstatus = \"okay\";\n+};\n+\n+&emmc {\n+\tnon-removable;\n+\tpinctrl-0 = <&pinctrl_emmcg5_default>;\n+\tbus-width = <4>;\n+\tmax-frequency = <52000000>;\n+\tclk-phase-mmc-hs200 = <9>, <225>;\n+};\n+\n+/*\n+* Enable USB port A as device (via the virtual hub) to host\n+*/\n+&vhub {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\t/*\n+\tUncomment below line to enable internal EHCI controller\n+\tCurrent config uses xHCI Port1\n+\t*/\n+\t// pinctrl-0 = <&pinctrl_usb2adp_default>;\n+};\n+\n+&video {\n+\tstatus = \"okay\";\n+\tmemory-region = <&video_engine_memory>;\n+};\n+\n+// USB 2.0 to HMC, on USB Port B\n+&ehci1 {\n+\tstatus = \"okay\";\n+};\n+\n+// USB 1.0\n+&uhci {\n+\tstatus = \"okay\";\n+};\n+\n+// I2C1, SSIF IPMI interface\n+&i2c0 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+\tdisable-master = <1>;\n+\ti2c-tck-thddat-config = <0x0099EC00>;\n+\tssif-bmc@10 {\n+\t\tcompatible = \"ssif-bmc\";\n+\t\talert-gpio = <&sgpiom0 39 GPIO_ACTIVE_LOW>;\n+\t\tpulse_width_us = <5>;\n+\t\ttimeout_ms = <4995>;\n+\t\treg = <0x10>;\n+\t};\n+};\n+\n+// I2C2\n+// BMC_I2C1_FPGA - Secondary FPGA\n+// HMC EROT\n+&i2c1 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+\tmulti-master;\n+\ti2c-scl-clk-low-timeout-us = <32000>;\n+\ti2c-tck-thddat-config = <0x0099EC00>;\n+};\n+\n+// I2C4\n+&i2c3 {\n+\tstatus = \"disabled\";\n+};\n+\n+// I2C5\n+// RTC Driver\n+// IO Expander\n+&i2c4 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+\ti2c-tck-thddat-config = <0x0099EC00>;\n+\t// Module 0, Expander @0x21\n+\texp4: pca9555@21 {\n+\t\tcompatible = \"nxp,pca9555\";\n+\t\treg = <0x21>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;\n+\n+\t\tgpio-line-names =\n+\t\t\t\"RTC_MUX_SEL-O\",\n+\t\t\t\"PCI_MUX_SEL-O\",\n+\t\t\t\"TPM_MUX_SEL-O\",\n+\t\t\t\"FAN_MUX-SEL-O\",\n+\t\t\t\"SGMII_MUX_SEL-O\",\n+\t\t\t\"DP_MUX_SEL-O\",\n+\t\t\t\"UPHY3_USB_SEL-O\",\n+\t\t\t\"NCSI_MUX_SEL-O\",\n+\t\t\t\"BMC_PHY_RST-O\",\n+\t\t\t\"RTC_CLR_L-O\",\n+\t\t\t\"BMC_12V_CTRL-O\",\n+\t\t\t\"PS_RUN_IO0_PG-I\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\",\n+\t\t\t\"\";\n+\t};\n+};\n+\n+// I2C6\n+// Module 0/1 I2C MUX x3\n+&i2c5 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+\tmulti-master;\n+\ti2c-scl-clk-low-timeout-us = <32000>;\n+\ti2c-tck-thddat-config = <0x0099EC00>;\n+\n+\ti2c-switch@71 {\n+\t\tcompatible = \"nxp,pca9546\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x71>;\n+\t\ti2c-mux-idle-disconnect;\n+\n+\t\timux16: i2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\timux17: i2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\t\t};\n+\n+\t\timux18: i2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\timux19: i2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t};\n+\t};\n+\n+\ti2c-switch@72 {\n+\t\tcompatible = \"nxp,pca9546\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x72>;\n+\t\ti2c-mux-idle-disconnect;\n+\n+\t\timux20: i2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\timux21: i2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\t\t};\n+\n+\t\timux22: i2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\timux23: i2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t};\n+\t};\n+\n+\ti2c-switch@73 {\n+\t\tcompatible = \"nxp,pca9546\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x73>;\n+\t\ti2c-mux-idle-disconnect;\n+\n+\t\timux24: i2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\timux25: i2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\t\t};\n+\n+\t\timux26: i2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\timux27: i2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t};\n+\t};\n+\n+\t//A MUX for a riser with a secondary M.2 installed.\n+\ti2c-switch@74 {\n+\t\tcompatible = \"nxp,pca9546\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x74>;\n+\t\ti2c-mux-idle-disconnect;\n+\n+\t\ti2c5mux0: i2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\t//Optional/secondary M.2 drive slot\n+\t\tm2riser: i2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\t\t};\n+\n+\t\ti2c5mux2: i2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\ti2c5mux3: i2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t};\n+\t};\n+\n+\ti2c-switch@75 {\n+\t\tcompatible = \"nxp,pca9546\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x75>;\n+\t\ti2c-mux-idle-disconnect;\n+\n+\t\timux28: i2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\timux29: i2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\t\t};\n+\n+\t\timux30: i2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\timux31: i2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t};\n+\t};\n+\n+\ti2c-switch@76 {\n+\t\tcompatible = \"nxp,pca9546\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x76>;\n+\t\ti2c-mux-idle-disconnect;\n+\n+\t\timux32: i2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\timux33: i2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\t\t};\n+\n+\t\timux34: i2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\timux35: i2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t};\n+\t};\n+\n+\ti2c-switch@77 {\n+\t\tcompatible = \"nxp,pca9546\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x77>;\n+\t\ti2c-mux-idle-disconnect;\n+\n+\t\timux36: i2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\timux37: i2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\t\t};\n+\n+\t\timux38: i2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\timux39: i2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t};\n+\t};\n+};\n+\n+// I2C7\n+// Module 0/1 Leak Sensors\n+// Module 0/1 Fan Controllers\n+&i2c6 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+\ti2c-tck-thddat-config = <0x0099EC00>;\n+\thsc@12 {\n+\t\tcompatible = \"ti,lm5066i\";\n+\t\treg = <0x12>;\n+\t\tshunt-resistor-micro-ohms = <190>;\n+\t\tstatus = \"okay\";\n+\t};\n+\thsc@14 {\n+\t\tcompatible = \"ti,lm5066i\";\n+\t\treg = <0x14>;\n+\t\tshunt-resistor-micro-ohms = <190>;\n+\t\tstatus = \"okay\";\n+\t};\n+\tmax31790_1 {\n+\t\tcompatible = \"maxim,max31790\";\n+\t\treg = <0x20>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t};\n+\tmax31790_2 {\n+\t\tcompatible = \"maxim,max31790\";\n+\t\treg = <0x23>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t};\n+\tmax31790_3 {\n+\t\tcompatible = \"maxim,max31790\";\n+\t\treg = <0x2c>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t};\n+\tmax31790_4 {\n+\t\tcompatible = \"maxim,max31790\";\n+\t\treg = <0x2f>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t};\n+};\n+\n+// I2C9\n+// M.2\n+&i2c8 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+\tmulti-master;\n+\ti2c-scl-clk-low-timeout-us = <32000>;\n+\ti2c-tck-thddat-config = <0x0099EC00>;\n+};\n+\n+// I2C10\n+// HMC IO Expander\n+// Module 0/1 IO Expanders\n+&i2c9 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+\ti2c-tck-thddat-config = <0x0099EC00>;\n+\t// Module 0, Expander @0x20\n+\texp0: pca9555@20 {\n+\t\tcompatible = \"nxp,pca9555\";\n+\t\treg = <0x20>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;\n+\n+\t\tgpio-line-names =\n+\t\t\"FPGA_THERM_OVERT_L-I\",\n+\t\t\"FPGA_READY_BMC-I\",\n+\t\t\"HMC_BMC_DETECT-O\",\n+\t\t\"HMC_PGOOD-O\",\n+\t\t\"\",\n+\t\t\"BMC_STBY_CYCLE-O\",\n+\t\t\"FPGA_EROT_FATAL_ERROR_L-I\",\n+\t\t\"WP_HW_EXT_CTRL_L-O\",\n+\t\t\"EROT_FPGA_RST_L-O\",\n+\t\t\"FPGA_EROT_RECOVERY_L-O\",\n+\t\t\"BMC_EROT_FPGA_SPI_MUX_SEL-O\",\n+\t\t\"USB_HUB_RESET_L-O\",\n+\t\t\"NCSI_CS1_SEL-O\",\n+\t\t\"SGPIO_EN_L-O\",\n+\t\t\"B2B_IOEXP_INT_L-I\",\n+\t\t\"I2C_BUS_MUX_RESET_L-O\";\n+\t};\n+\n+\t// Module 1, Expander @0x21\n+\texp1: pca9555@21 {\n+\t\tcompatible = \"nxp,pca9555\";\n+\t\treg = <0x21>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;\n+\n+\t\tgpio-line-names =\n+\t\t\"SEC_FPGA_THERM_OVERT_L-I\",\n+\t\t\"SEC_FPGA_READY_BMC-I\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"SEC_FPGA_EROT_FATAL_ERROR_L-I\",\n+\t\t\"SEC_WP_HW_EXT_CTRL_L-O\",\n+\t\t\"SEC_EROT_FPGA_RST_L-O\",\n+\t\t\"SEC_FPGA_EROT_RECOVERY_L-O\",\n+\t\t\"SEC_BMC_EROT_FPGA_SPI_MUX_SEL-O\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"SEC_I2C_BUS_MUX_RESET_L-O\";\n+\t};\n+\n+\t// HMC Expander @0x27\n+\texp2: pca9555@27 {\n+\t\tcompatible = \"nxp,pca9555\";\n+\t\treg = <0x27>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;\n+\n+\t\tgpio-line-names =\n+\t\t\"HMC_PRSNT_L-I\",\n+\t\t\"HMC_READY-I\",\n+\t\t\"HMC_EROT_FATAL_ERROR_L-I\",\n+\t\t\"I2C_MUX_SEL-O\",\n+\t\t\"HMC_EROT_SPI_MUX_SEL-O\",\n+\t\t\"HMC_EROT_RECOVERY_L-O\",\n+\t\t\"HMC_EROT_RST_L-O\",\n+\t\t\"GLOBAL_WP_HMC-O\",\n+\t\t\"FPGA_RST_L-O\",\n+\t\t\"USB2_HUB_RST-O\",\n+\t\t\"CPU_UART_MUX_SEL-O\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\";\n+\t};\n+\t// HMC Expander @0x74\n+\texp3: pca9555@74 {\n+\t\tcompatible = \"nxp,pca9555\";\n+\t\treg = <0x74>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>;\n+\n+\t\tgpio-line-names =\n+\t\t\"IOB_PRSNT_L\",\n+\t\t\"IOB_DP_HPD\",\n+\t\t\"IOX_BMC_RESET\",\n+\t\t\"IOB_IOEXP_INT_L\",\n+\t\t\"IOB_UID_LED_L\",\n+\t\t\"IOB_UID_BTN_L\",\n+\t\t\"IOB_SYS_RST_BTN_L\",\n+\t\t\"IOB_PWR_LED_L\",\n+\t\t\"IOB_PWR_BTN_L\",\n+\t\t\"IOB_PHY_RST\",\n+\t\t\"CPLD_JTAG_MUX_SEL\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\",\n+\t\t\"\";\n+\t};\n+};\n+\n+// I2C11\n+// BMC FRU EEPROM\n+// BMC Temp Sensor\n+&i2c10 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <400000>;\n+\ti2c-tck-thddat-config = <0x0099EC00>;\n+\t// BMC FRU EEPROM - 256 bytes\n+\teeprom@50 {\n+\t\tcompatible = \"atmel,24c02\";\n+\t\treg = <0x50>;\n+\t\tpagesize = <8>;\n+\t};\n+};\n+\n+// I2C12\n+&i2c11 {\n+\tstatus = \"disabled\";\n+};\n+\n+// I2C13\n+&i2c12 {\n+\tstatus = \"disabled\";\n+};\n+\n+// I2C14\n+// Module 0 UPHY3 SMBus\n+&i2c13 {\n+\tstatus = \"disabled\";\n+};\n+\n+// I2C15\n+// Module 1 UPHY3 SMBus\n+&i2c14 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <100000>;\n+\tmulti-master;\n+\ti2c-scl-clk-low-timeout-us = <32000>;\n+\ti2c-tck-thddat-config = <0x00EFD000>;\n+\n+\t//E1.S drive slot 0-3\n+\ti2c-switch@77 {\n+\t\tcompatible = \"nxp,pca9546\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x77>;\n+\t\ti2c-mux-idle-disconnect;\n+\n+\t\te1si2c0: i2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\te1si2c1: i2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\t\t};\n+\n+\t\te1si2c2: i2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\te1si2c3: i2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t};\n+\t};\n+};\n+\n+// I2C16\n+&i2c15 {\n+\tstatus = \"okay\";\n+\tclock-frequency = <100000>;\n+\tmulti-master;\n+\ti2c-scl-clk-low-timeout-us = <32000>;\n+\ti2c-tck-thddat-config = <0x00EFD000>;\n+\n+\t//E1.S drive slot 4-7\n+\ti2c-switch@77 {\n+\t\tcompatible = \"nxp,pca9546\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x77>;\n+\t\ti2c-mux-idle-disconnect;\n+\n+\t\te1si2c4: i2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\te1si2c5: i2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\t\t};\n+\n+\t\te1si2c6: i2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\te1si2c7: i2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t};\n+\t};\n+};\n+\n+// PCIe RC\n+&pcie {\n+\tstatus = \"okay\";\n+\n+\tinterrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;\n+\n+\tpcie_intc0: legacy-interrupt-controller {\n+\t\tinterrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;\n+\t};\n+};\n+\n+// Bridge between AHB bus and PCIe RC.\n+&h2x {\n+\tstatus = \"okay\";\n+};\n+\n+&mctp {\n+\tstatus = \"okay\";\n+};\n+\n+&jtag0 {\n+\tstatus = \"okay\";\n+};\n+\n+&jtag1 {\n+\tmux-gpios = <&sgpiom0 41 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;\n+\tstatus = \"okay\";\n+};\n+\n+&rng {\n+\tstatus = \"okay\";\n+};\n+\n", "prefixes": [] }