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GET /api/patches/1992902/?format=api
{ "id": 1992902, "url": "http://patchwork.ozlabs.org/api/patches/1992902/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20241004163042.85922-17-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20241004163042.85922-17-philmd@linaro.org>", "list_archive_url": null, "date": "2024-10-04T16:30:32", "name": "[v2,16/25] target/riscv: Use explicit little-endian LD/ST API", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bc81a86ca16b35b9a75f62d0f6c8b9b77543aaa7", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20241004163042.85922-17-philmd@linaro.org/mbox/", "series": [ { "id": 426623, "url": "http://patchwork.ozlabs.org/api/series/426623/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=426623", "date": "2024-10-04T16:30:18", "name": "misc: Use explicit endian LD/ST API", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/426623/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1992902/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1992902/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=QPqeOSfc;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::22d;\n envelope-from=philmd@linaro.org; helo=mail-lj1-x22d.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The Risc-V architecture uses little endianness. Directly use\nthe little-endian LD/ST API.\n\nMechanical change using:\n\n $ end=le; \\\n for acc in uw w l q tul; do \\\n sed -i -e \"s/ld${acc}_p(/ld${acc}_${end}_p(/\" \\\n -e \"s/st${acc}_p(/st${acc}_${end}_p(/\" \\\n $(git grep -wlE '(ld|st)t?u?[wlq]_p' target/riscv/); \\\n done\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/riscv/gdbstub.c | 14 +++++++-------\n 1 file changed, 7 insertions(+), 7 deletions(-)", "diff": "diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c\nindex c07df972f1e..2e042f117f3 100644\n--- a/target/riscv/gdbstub.c\n+++ b/target/riscv/gdbstub.c\n@@ -84,15 +84,15 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n \n switch (mcc->misa_mxl_max) {\n case MXL_RV32:\n- tmp = (int32_t)ldl_p(mem_buf);\n+ tmp = (int32_t)ldl_le_p(mem_buf);\n length = 4;\n break;\n case MXL_RV64:\n case MXL_RV128:\n if (env->xl < MXL_RV64) {\n- tmp = (int32_t)ldq_p(mem_buf);\n+ tmp = (int32_t)ldq_le_p(mem_buf);\n } else {\n- tmp = ldq_p(mem_buf);\n+ tmp = ldq_le_p(mem_buf);\n }\n length = 8;\n break;\n@@ -130,7 +130,7 @@ static int riscv_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n)\n CPURISCVState *env = &cpu->env;\n \n if (n < 32) {\n- env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */\n+ env->fpr[n] = ldq_le_p(mem_buf); /* always 64-bit */\n return sizeof(uint64_t);\n }\n return 0;\n@@ -162,7 +162,7 @@ static int riscv_gdb_set_vector(CPUState *cs, uint8_t *mem_buf, int n)\n if (n < 32) {\n int i;\n for (i = 0; i < vlenb; i += 8) {\n- env->vreg[(n * vlenb + i) / 8] = ldq_p(mem_buf + i);\n+ env->vreg[(n * vlenb + i) / 8] = ldq_le_p(mem_buf + i);\n }\n return vlenb;\n }\n@@ -193,7 +193,7 @@ static int riscv_gdb_set_csr(CPUState *cs, uint8_t *mem_buf, int n)\n CPURISCVState *env = &cpu->env;\n \n if (n < CSR_TABLE_SIZE) {\n- target_ulong val = ldtul_p(mem_buf);\n+ target_ulong val = ldtul_le_p(mem_buf);\n int result;\n \n result = riscv_csrrw_debug(env, n, NULL, val, -1);\n@@ -226,7 +226,7 @@ static int riscv_gdb_set_virtual(CPUState *cs, uint8_t *mem_buf, int n)\n RISCVCPU *cpu = RISCV_CPU(cs);\n CPURISCVState *env = &cpu->env;\n \n- env->priv = ldtul_p(mem_buf) & 0x3;\n+ env->priv = ldtul_le_p(mem_buf) & 0x3;\n if (env->priv == PRV_RESERVED) {\n env->priv = PRV_S;\n }\n", "prefixes": [ "v2", "16/25" ] }