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GET /api/patches/1992901/?format=api
{ "id": 1992901, "url": "http://patchwork.ozlabs.org/api/patches/1992901/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20241004163042.85922-23-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20241004163042.85922-23-philmd@linaro.org>", "list_archive_url": null, "date": "2024-10-04T16:30:38", "name": "[v2,22/25] hw/s390x: Use explicit big-endian LD/ST API", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b0c90cab298b8a4433fb2650ac08e6dc3d5d7885", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20241004163042.85922-23-philmd@linaro.org/mbox/", "series": [ { "id": 426623, "url": "http://patchwork.ozlabs.org/api/series/426623/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=426623", "date": "2024-10-04T16:30:18", "name": "misc: Use explicit endian LD/ST API", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/426623/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1992901/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1992901/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=B5rA090v;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1728059774; x=1728664574;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc\n :subject:date:message-id:reply-to;\n bh=X8sRbzp8Sb06kpJ58T7p1q2wLwhmxDezE8ovGt3QAms=;\n b=rn8zZDm78ZzFEb0DuKfiKtdUIV8EmDcVG/guKtPY8SbdYiqqBKeRyaEyN9NXVKw7/d\n +jABbVY4T045W4qyeMSGltZED+/l7y/bJMjULH21asfHqPmaLhCXojHdZ1v603Jy8boO\n ietNMP/tRSo7wK893vHZQfsYoCVJ+Fd6TlQajV5izNsLqbOqPkajflKI+8Tqpm+7Xd1Y\n CenAXy4QZqDsGhDqbsUq3QchI9QuLpY/boBKFZ1BhM9LETOcLp1RU0/FSh2LBbg9rflq\n 5T/fifV5bsCl92q9GYx6YxJgq4S/i/9+peGk7Mp3wiHlHJOG632h3rtQCeGveehLgLUl\n Rabw==", "X-Gm-Message-State": "AOJu0Yyf6TemTkdbHY6EGxG6QHQeUtfdrgsvWsj9mNAyMnfwtikx34zN\n DlB7zGhe5eekdm0t42fWc8bbsjq5FV7Eh19miaNMsFIikJ7QT11NVW00yfqFPPiAiVJ+TdakVhk\n /l7hqWw==", "X-Google-Smtp-Source": "\n AGHT+IHCO7KWi92pUHCnymdqy4Dg9Yo3gQQ+7O24zk92/FzCUblVaHS41a/Vq6fU3Dn9sGlPwM1yfQ==", "X-Received": "by 2002:a05:6512:12d1:b0:539:94df:38e9 with SMTP id\n 2adb3069b0e04-539ab88af26mr2020980e87.31.1728059774064;\n Fri, 04 Oct 2024 09:36:14 -0700 (PDT)", "From": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-riscv@nongnu.org, qemu-s390x@nongnu.org,\n Thomas Huth <thuth@redhat.com>,\n Richard Henderson <richard.henderson@linaro.org>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>, qemu-ppc@nongnu.org,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>", "Subject": "[PATCH v2 22/25] hw/s390x: Use explicit big-endian LD/ST API", "Date": "Fri, 4 Oct 2024 13:30:38 -0300", "Message-ID": "<20241004163042.85922-23-philmd@linaro.org>", "X-Mailer": "git-send-email 2.45.2", "In-Reply-To": "<20241004163042.85922-1-philmd@linaro.org>", "References": "<20241004163042.85922-1-philmd@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::12e;\n envelope-from=philmd@linaro.org; helo=mail-lf1-x12e.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The S390X architecture uses big endianness. Directly use\nthe big-endian LD/ST API.\n\nMechanical change using:\n\n $ end=be; \\\n for acc in uw w l q tul; do \\\n sed -i -e \"s/ld${acc}_p(/ld${acc}_${end}_p(/\" \\\n -e \"s/st${acc}_p(/st${acc}_${end}_p(/\" \\\n $(git grep -wlE '(ld|st)t?u?[wlq]_p' hw/s390x/); \\\n done\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n hw/s390x/ipl.c | 4 +-\n hw/s390x/s390-pci-inst.c | 166 +++++++++++++++++++--------------------\n 2 files changed, 85 insertions(+), 85 deletions(-)", "diff": "diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c\nindex dd71689642b..5ab74339087 100644\n--- a/hw/s390x/ipl.c\n+++ b/hw/s390x/ipl.c\n@@ -252,8 +252,8 @@ static void s390_ipl_realize(DeviceState *dev, Error **errp)\n */\n romptr = rom_ptr(INITRD_PARM_START, 16);\n if (romptr) {\n- stq_p(romptr, initrd_offset);\n- stq_p(romptr + 1, initrd_size);\n+ stq_be_p(romptr, initrd_offset);\n+ stq_be_p(romptr + 1, initrd_size);\n }\n }\n }\ndiff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c\nindex 30149546c08..41655082dac 100644\n--- a/hw/s390x/s390-pci-inst.c\n+++ b/hw/s390x/s390-pci-inst.c\n@@ -55,26 +55,26 @@ static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc)\n uint64_t resume_token;\n \n rc = 0;\n- if (lduw_p(&rrb->request.hdr.len) != 32) {\n+ if (lduw_be_p(&rrb->request.hdr.len) != 32) {\n res_code = CLP_RC_LEN;\n rc = -EINVAL;\n goto out;\n }\n \n- if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) {\n+ if ((ldl_be_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) {\n res_code = CLP_RC_FMT;\n rc = -EINVAL;\n goto out;\n }\n \n- if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 ||\n- ldq_p(&rrb->request.reserved1) != 0) {\n+ if ((ldl_be_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 ||\n+ ldq_be_p(&rrb->request.reserved1) != 0) {\n res_code = CLP_RC_RESNOT0;\n rc = -EINVAL;\n goto out;\n }\n \n- resume_token = ldq_p(&rrb->request.resume_token);\n+ resume_token = ldq_be_p(&rrb->request.resume_token);\n \n if (resume_token) {\n pbdev = s390_pci_find_dev_by_idx(s, resume_token);\n@@ -87,13 +87,13 @@ static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc)\n pbdev = s390_pci_find_next_avail_dev(s, NULL);\n }\n \n- if (lduw_p(&rrb->response.hdr.len) < 48) {\n+ if (lduw_be_p(&rrb->response.hdr.len) < 48) {\n res_code = CLP_RC_8K;\n rc = -EINVAL;\n goto out;\n }\n \n- initial_l2 = lduw_p(&rrb->response.hdr.len);\n+ initial_l2 = lduw_be_p(&rrb->response.hdr.len);\n if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry)\n != 0) {\n res_code = CLP_RC_LEN;\n@@ -102,33 +102,33 @@ static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc)\n goto out;\n }\n \n- stl_p(&rrb->response.fmt, 0);\n- stq_p(&rrb->response.reserved1, 0);\n- stl_p(&rrb->response.mdd, FH_MASK_SHM);\n- stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS);\n+ stl_be_p(&rrb->response.fmt, 0);\n+ stq_be_p(&rrb->response.reserved1, 0);\n+ stl_be_p(&rrb->response.mdd, FH_MASK_SHM);\n+ stw_be_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS);\n rrb->response.flags = UID_CHECKING_ENABLED;\n rrb->response.entry_size = sizeof(ClpFhListEntry);\n \n i = 0;\n g_l2 = LIST_PCI_HDR_LEN;\n while (g_l2 < initial_l2 && pbdev) {\n- stw_p(&rrb->response.fh_list[i].device_id,\n+ stw_be_p(&rrb->response.fh_list[i].device_id,\n pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID));\n- stw_p(&rrb->response.fh_list[i].vendor_id,\n+ stw_be_p(&rrb->response.fh_list[i].vendor_id,\n pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID));\n /* Ignore RESERVED devices. */\n- stl_p(&rrb->response.fh_list[i].config,\n+ stl_be_p(&rrb->response.fh_list[i].config,\n pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31);\n- stl_p(&rrb->response.fh_list[i].fid, pbdev->fid);\n- stl_p(&rrb->response.fh_list[i].fh, pbdev->fh);\n+ stl_be_p(&rrb->response.fh_list[i].fid, pbdev->fid);\n+ stl_be_p(&rrb->response.fh_list[i].fh, pbdev->fh);\n \n g_l2 += sizeof(ClpFhListEntry);\n /* Add endian check for DPRINTF? */\n trace_s390_pci_list_entry(g_l2,\n- lduw_p(&rrb->response.fh_list[i].vendor_id),\n- lduw_p(&rrb->response.fh_list[i].device_id),\n- ldl_p(&rrb->response.fh_list[i].fid),\n- ldl_p(&rrb->response.fh_list[i].fh));\n+ lduw_be_p(&rrb->response.fh_list[i].vendor_id),\n+ lduw_be_p(&rrb->response.fh_list[i].device_id),\n+ ldl_be_p(&rrb->response.fh_list[i].fid),\n+ ldl_be_p(&rrb->response.fh_list[i].fh));\n pbdev = s390_pci_find_next_avail_dev(s, pbdev);\n i++;\n }\n@@ -138,13 +138,13 @@ static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc)\n } else {\n resume_token = pbdev->fh & FH_MASK_INDEX;\n }\n- stq_p(&rrb->response.resume_token, resume_token);\n- stw_p(&rrb->response.hdr.len, g_l2);\n- stw_p(&rrb->response.hdr.rsp, CLP_RC_OK);\n+ stq_be_p(&rrb->response.resume_token, resume_token);\n+ stw_be_p(&rrb->response.hdr.len, g_l2);\n+ stw_be_p(&rrb->response.hdr.rsp, CLP_RC_OK);\n out:\n if (rc) {\n trace_s390_pci_list(rc);\n- stw_p(&rrb->response.hdr.rsp, res_code);\n+ stw_be_p(&rrb->response.hdr.rsp, res_code);\n }\n return rc;\n }\n@@ -172,7 +172,7 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)\n return 0;\n }\n reqh = (ClpReqHdr *)buffer;\n- req_len = lduw_p(&reqh->len);\n+ req_len = lduw_be_p(&reqh->len);\n if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) {\n s390_program_interrupt(env, PGM_OPERAND, ra);\n return 0;\n@@ -184,7 +184,7 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)\n return 0;\n }\n resh = (ClpRspHdr *)(buffer + req_len);\n- res_len = lduw_p(&resh->len);\n+ res_len = lduw_be_p(&resh->len);\n if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) {\n s390_program_interrupt(env, PGM_OPERAND, ra);\n return 0;\n@@ -201,11 +201,11 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)\n }\n \n if (req_len != 32) {\n- stw_p(&resh->rsp, CLP_RC_LEN);\n+ stw_be_p(&resh->rsp, CLP_RC_LEN);\n goto out;\n }\n \n- switch (lduw_p(&reqh->cmd)) {\n+ switch (lduw_be_p(&reqh->cmd)) {\n case CLP_LIST_PCI: {\n ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer;\n list_pci(rrb, &cc);\n@@ -215,9 +215,9 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)\n ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh;\n ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh;\n \n- pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh));\n+ pbdev = s390_pci_find_dev_by_fh(s, ldl_be_p(&reqsetpci->fh));\n if (!pbdev) {\n- stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH);\n+ stw_be_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH);\n goto out;\n }\n \n@@ -225,17 +225,17 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)\n case CLP_SET_ENABLE_PCI_FN:\n switch (reqsetpci->ndas) {\n case 0:\n- stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS);\n+ stw_be_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS);\n goto out;\n case 1:\n break;\n default:\n- stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES);\n+ stw_be_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES);\n goto out;\n }\n \n if (pbdev->fh & FH_MASK_ENABLE) {\n- stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);\n+ stw_be_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);\n goto out;\n }\n \n@@ -249,29 +249,29 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)\n /* Take this opportunity to make sure we are sync'd with host */\n if (!s390_pci_get_host_fh(pbdev, &pbdev->fh) ||\n !(pbdev->fh & FH_MASK_ENABLE)) {\n- stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH);\n+ stw_be_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH);\n goto out;\n }\n }\n pbdev->fh |= FH_MASK_ENABLE;\n pbdev->state = ZPCI_FS_ENABLED;\n- stl_p(&ressetpci->fh, pbdev->fh);\n- stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);\n+ stl_be_p(&ressetpci->fh, pbdev->fh);\n+ stw_be_p(&ressetpci->hdr.rsp, CLP_RC_OK);\n break;\n case CLP_SET_DISABLE_PCI_FN:\n if (!(pbdev->fh & FH_MASK_ENABLE)) {\n- stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);\n+ stw_be_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);\n goto out;\n }\n device_cold_reset(DEVICE(pbdev));\n pbdev->fh &= ~FH_MASK_ENABLE;\n pbdev->state = ZPCI_FS_DISABLED;\n- stl_p(&ressetpci->fh, pbdev->fh);\n- stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);\n+ stl_be_p(&ressetpci->fh, pbdev->fh);\n+ stw_be_p(&ressetpci->hdr.rsp, CLP_RC_OK);\n break;\n default:\n trace_s390_pci_unknown(\"set-pci\", reqsetpci->oc);\n- stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);\n+ stw_be_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);\n break;\n }\n break;\n@@ -280,23 +280,23 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)\n ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh;\n ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh;\n \n- pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh));\n+ pbdev = s390_pci_find_dev_by_fh(s, ldl_be_p(&reqquery->fh));\n if (!pbdev) {\n- trace_s390_pci_nodev(\"query\", ldl_p(&reqquery->fh));\n- stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH);\n+ trace_s390_pci_nodev(\"query\", ldl_be_p(&reqquery->fh));\n+ stw_be_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH);\n goto out;\n }\n \n- stq_p(&resquery->sdma, pbdev->zpci_fn.sdma);\n- stq_p(&resquery->edma, pbdev->zpci_fn.edma);\n- stw_p(&resquery->pchid, pbdev->zpci_fn.pchid);\n- stw_p(&resquery->vfn, pbdev->zpci_fn.vfn);\n+ stq_be_p(&resquery->sdma, pbdev->zpci_fn.sdma);\n+ stq_be_p(&resquery->edma, pbdev->zpci_fn.edma);\n+ stw_be_p(&resquery->pchid, pbdev->zpci_fn.pchid);\n+ stw_be_p(&resquery->vfn, pbdev->zpci_fn.vfn);\n resquery->flags = pbdev->zpci_fn.flags;\n resquery->pfgid = pbdev->zpci_fn.pfgid;\n resquery->pft = pbdev->zpci_fn.pft;\n resquery->fmbl = pbdev->zpci_fn.fmbl;\n- stl_p(&resquery->fid, pbdev->zpci_fn.fid);\n- stl_p(&resquery->uid, pbdev->zpci_fn.uid);\n+ stl_be_p(&resquery->fid, pbdev->zpci_fn.fid);\n+ stl_be_p(&resquery->uid, pbdev->zpci_fn.uid);\n memcpy(resquery->pfip, pbdev->zpci_fn.pfip, CLP_PFIP_NR_SEGMENTS);\n memcpy(resquery->util_str, pbdev->zpci_fn.util_str, CLP_UTIL_STR_LEN);\n \n@@ -304,16 +304,16 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)\n uint32_t data = pci_get_long(pbdev->pdev->config +\n PCI_BASE_ADDRESS_0 + (i * 4));\n \n- stl_p(&resquery->bar[i], data);\n+ stl_be_p(&resquery->bar[i], data);\n resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ?\n ctz64(pbdev->pdev->io_regions[i].size) : 0;\n trace_s390_pci_bar(i,\n- ldl_p(&resquery->bar[i]),\n+ ldl_be_p(&resquery->bar[i]),\n pbdev->pdev->io_regions[i].size,\n resquery->bar_size[i]);\n }\n \n- stw_p(&resquery->hdr.rsp, CLP_RC_OK);\n+ stw_be_p(&resquery->hdr.rsp, CLP_RC_OK);\n break;\n }\n case CLP_QUERY_PCI_FNGRP: {\n@@ -326,23 +326,23 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)\n if (!group) {\n /* We do not allow access to unknown groups */\n /* The group must have been obtained with a vfio device */\n- stw_p(&resgrp->hdr.rsp, CLP_RC_QUERYPCIFG_PFGID);\n+ stw_be_p(&resgrp->hdr.rsp, CLP_RC_QUERYPCIFG_PFGID);\n goto out;\n }\n resgrp->fr = group->zpci_group.fr;\n- stq_p(&resgrp->dasm, group->zpci_group.dasm);\n- stq_p(&resgrp->msia, group->zpci_group.msia);\n- stw_p(&resgrp->mui, group->zpci_group.mui);\n- stw_p(&resgrp->i, group->zpci_group.i);\n- stw_p(&resgrp->maxstbl, group->zpci_group.maxstbl);\n+ stq_be_p(&resgrp->dasm, group->zpci_group.dasm);\n+ stq_be_p(&resgrp->msia, group->zpci_group.msia);\n+ stw_be_p(&resgrp->mui, group->zpci_group.mui);\n+ stw_be_p(&resgrp->i, group->zpci_group.i);\n+ stw_be_p(&resgrp->maxstbl, group->zpci_group.maxstbl);\n resgrp->version = group->zpci_group.version;\n resgrp->dtsm = group->zpci_group.dtsm;\n- stw_p(&resgrp->hdr.rsp, CLP_RC_OK);\n+ stw_be_p(&resgrp->hdr.rsp, CLP_RC_OK);\n break;\n }\n default:\n- trace_s390_pci_unknown(\"clp\", lduw_p(&reqh->cmd));\n- stw_p(&resh->rsp, CLP_RC_CMD);\n+ trace_s390_pci_unknown(\"clp\", lduw_be_p(&reqh->cmd));\n+ stw_be_p(&resh->rsp, CLP_RC_CMD);\n break;\n }\n \n@@ -914,7 +914,7 @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,\n \n for (i = 0; i < len / 8; i++) {\n result = memory_region_dispatch_write(mr, offset + i * 8,\n- ldq_p(buffer + i * 8),\n+ ldq_be_p(buffer + i * 8),\n MO_64, MEMTXATTRS_UNSPECIFIED);\n if (result != MEMTX_OK) {\n s390_program_interrupt(env, PGM_OPERAND, ra);\n@@ -935,13 +935,13 @@ specification_error:\n static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib)\n {\n int ret, len;\n- uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data));\n+ uint8_t isc = FIB_DATA_ISC(ldl_be_p(&fib.data));\n \n pbdev->routes.adapter.adapter_id = css_get_adapter_id(\n CSS_IO_ADAPTER_PCI, isc);\n- pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t));\n- len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long);\n- pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len);\n+ pbdev->summary_ind = get_indicator(ldq_be_p(&fib.aisb), sizeof(uint64_t));\n+ len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_be_p(&fib.data))) * sizeof(unsigned long);\n+ pbdev->indicator = get_indicator(ldq_be_p(&fib.aibv), len);\n \n ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind);\n if (ret) {\n@@ -953,13 +953,13 @@ static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib)\n goto out;\n }\n \n- pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb);\n- pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data));\n- pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv);\n- pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data));\n+ pbdev->routes.adapter.summary_addr = ldq_be_p(&fib.aisb);\n+ pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_be_p(&fib.data));\n+ pbdev->routes.adapter.ind_addr = ldq_be_p(&fib.aibv);\n+ pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_be_p(&fib.data));\n pbdev->isc = isc;\n- pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data));\n- pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data));\n+ pbdev->noi = FIB_DATA_NOI(ldl_be_p(&fib.data));\n+ pbdev->sum = FIB_DATA_SUM(ldl_be_p(&fib.data));\n \n trace_s390_pci_irqs(\"register\", pbdev->routes.adapter.adapter_id);\n return 0;\n@@ -994,9 +994,9 @@ static int reg_ioat(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib,\n uintptr_t ra)\n {\n S390PCIIOMMU *iommu = pbdev->iommu;\n- uint64_t pba = ldq_p(&fib.pba);\n- uint64_t pal = ldq_p(&fib.pal);\n- uint64_t g_iota = ldq_p(&fib.iota);\n+ uint64_t pba = ldq_be_p(&fib.pba);\n+ uint64_t pal = ldq_be_p(&fib.pal);\n+ uint64_t g_iota = ldq_be_p(&fib.iota);\n uint8_t dt = (g_iota >> 2) & 0x7;\n uint8_t t = (g_iota >> 11) & 0x1;\n \n@@ -1289,7 +1289,7 @@ int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,\n }\n break;\n case ZPCI_MOD_FC_SET_MEASURE: {\n- uint64_t fmb_addr = ldq_p(&fib.fmb_addr);\n+ uint64_t fmb_addr = ldq_be_p(&fib.fmb_addr);\n \n if (fmb_addr & FMBK_MASK) {\n cc = ZPCI_PCI_LS_ERR;\n@@ -1399,17 +1399,17 @@ int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,\n return 0;\n }\n \n- stq_p(&fib.pba, pbdev->iommu->pba);\n- stq_p(&fib.pal, pbdev->iommu->pal);\n- stq_p(&fib.iota, pbdev->iommu->g_iota);\n- stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr);\n- stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr);\n- stq_p(&fib.fmb_addr, pbdev->fmb_addr);\n+ stq_be_p(&fib.pba, pbdev->iommu->pba);\n+ stq_be_p(&fib.pal, pbdev->iommu->pal);\n+ stq_be_p(&fib.iota, pbdev->iommu->g_iota);\n+ stq_be_p(&fib.aibv, pbdev->routes.adapter.ind_addr);\n+ stq_be_p(&fib.aisb, pbdev->routes.adapter.summary_addr);\n+ stq_be_p(&fib.fmb_addr, pbdev->fmb_addr);\n \n data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) |\n ((uint32_t)pbdev->routes.adapter.ind_offset << 8) |\n ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset;\n- stl_p(&fib.data, data);\n+ stl_be_p(&fib.data, data);\n \n out:\n if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {\n", "prefixes": [ "v2", "22/25" ] }