Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1992869/?format=api
{ "id": 1992869, "url": "http://patchwork.ozlabs.org/api/patches/1992869/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20241004163042.85922-10-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20241004163042.85922-10-philmd@linaro.org>", "list_archive_url": null, "date": "2024-10-04T16:30:25", "name": "[v2,09/25] target/i386: Use explicit little-endian LD/ST API", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "818596dd7c21ca375a26b31cc33d35c709924e5b", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20241004163042.85922-10-philmd@linaro.org/mbox/", "series": [ { "id": 426623, "url": "http://patchwork.ozlabs.org/api/series/426623/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=426623", "date": "2024-10-04T16:30:18", "name": "misc: Use explicit endian LD/ST API", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/426623/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1992869/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1992869/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=sAI8EQpC;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4XKvJD3vVVz1xtH\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 5 Oct 2024 02:34:04 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1swlFJ-0007zW-Qw; Fri, 04 Oct 2024 12:33:38 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <philmd@linaro.org>) id 1swlEq-0007HL-K9\n for qemu-devel@nongnu.org; Fri, 04 Oct 2024 12:33:08 -0400", "from mail-lf1-x131.google.com ([2a00:1450:4864:20::131])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <philmd@linaro.org>) id 1swlEn-0005pQ-OY\n for qemu-devel@nongnu.org; Fri, 04 Oct 2024 12:33:08 -0400", "by mail-lf1-x131.google.com with SMTP id\n 2adb3069b0e04-5369f1c7cb8so2581146e87.1\n for <qemu-devel@nongnu.org>; Fri, 04 Oct 2024 09:33:04 -0700 (PDT)", "from localhost.localdomain ([91.223.100.150])\n by smtp.gmail.com with ESMTPSA id\n 2adb3069b0e04-539afec8255sm1950e87.83.2024.10.04.09.32.57\n (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256);\n Fri, 04 Oct 2024 09:33:01 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1728059583; x=1728664383; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=2s/tzGPg/LmnPo+rxsPQADcqJffZEpvaXgXhuXN6AeQ=;\n b=sAI8EQpCYesTCsw2GsCCQcrNrdCSx9ho3tzjWRFFR+Z9PfhiJZwNYB3qZrw6eJyY+E\n s2tVNL7nTS6yuzxKCK5TB7BJShNnDhTU4DOs3pZbRYicp/2KYbShxGJtjWjSIs9OlP+5\n oGiEidj7NwcWp5RYo5bD8mR7ECWelg1f9hRmejNg16Mpwf840eFImEdkRbQk3sVWXt9E\n iUM61x/1UhF28HcF8IP7qMPnkG+4gcOv4i486Zzgh3ZZV0vw93mk5N+0mSXxxdSgAvDs\n FEUOTltjwd9dBo/H1M/nkwi8gd8UfnfvlKH2nmBPFR95MI/BEBmAaxr/GIq15edMji0U\n Vjww==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1728059583; x=1728664383;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc\n :subject:date:message-id:reply-to;\n bh=2s/tzGPg/LmnPo+rxsPQADcqJffZEpvaXgXhuXN6AeQ=;\n b=mvHZdHRmSixA4FM2p0K0juHZqhbwFsWlX+IRzL4VbP+M5WkBroSGDpYKVYWBpqJ76T\n JtU8eGLyqX7nlqvtOW9/sPllijSg8KuYXdyM51kDBolgQ4ec346LraFq2U5Xg0FtTRoT\n EZj8FBzfpZKSh3ZiKIe14mLzKmBLzOiAHwq5UBaufx1I5scX7EtoQEUusZ++4vAtZDB6\n ZBnRLB56+DK8txsU+iTvCyY7njguz6vErPG95Lbxr6b0mPczgs1M1Z5okai13kBk8i5L\n a8fBkCuQaKgv3J/LscSxDIJ5RiOFEG+hItLClHfzUaaJIUmOBQ8GDAj23Ar9/mfVoZWO\n 8NaA==", "X-Gm-Message-State": "AOJu0YwBbvFNwlTjUHeYEZeqW/eOXtcsZ7rSIP6JzpSlxEugLdfUmtsC\n 9frW8SdiLOm8BXyoqfPDTu+aTWFR2jETo85M5ye+5acgc3tx9IOSG5p0eowlFrtfmZCLZgtmZ+s\n +lfwvxQ==", "X-Google-Smtp-Source": "\n AGHT+IGC4fHpQTA+27ggAZsNhRcHU2c/GQgEsPn+l3WUcVvbsSReakNbFECwUaxnJDpvvOqCLsru5w==", "X-Received": "by 2002:a05:6512:39c5:b0:535:6cbf:51a3 with SMTP id\n 2adb3069b0e04-539ab88a017mr2509555e87.25.1728059582806;\n Fri, 04 Oct 2024 09:33:02 -0700 (PDT)", "From": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-riscv@nongnu.org, qemu-s390x@nongnu.org,\n Thomas Huth <thuth@redhat.com>,\n Richard Henderson <richard.henderson@linaro.org>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>, qemu-ppc@nongnu.org,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>", "Subject": "[PATCH v2 09/25] target/i386: Use explicit little-endian LD/ST API", "Date": "Fri, 4 Oct 2024 13:30:25 -0300", "Message-ID": "<20241004163042.85922-10-philmd@linaro.org>", "X-Mailer": "git-send-email 2.45.2", "In-Reply-To": "<20241004163042.85922-1-philmd@linaro.org>", "References": "<20241004163042.85922-1-philmd@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::131;\n envelope-from=philmd@linaro.org; helo=mail-lf1-x131.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The x86 architecture uses little endianness. Directly use\nthe little-endian LD/ST API.\n\nMechanical change using:\n\n $ end=le; \\\n for acc in uw w l q tul; do \\\n sed -i -e \"s/ld${acc}_p(/ld${acc}_${end}_p(/\" \\\n -e \"s/st${acc}_p(/st${acc}_${end}_p(/\" \\\n $(git grep -wlE '(ld|st)t?u?[wlq]_p' target/i386/); \\\n done\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/i386/gdbstub.c | 30 +++++++++++++-------------\n target/i386/tcg/sysemu/excp_helper.c | 4 ++--\n target/i386/xsave_helper.c | 32 ++++++++++++++--------------\n 3 files changed, 33 insertions(+), 33 deletions(-)", "diff": "diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c\nindex 4acf485879e..28ccf06309d 100644\n--- a/target/i386/gdbstub.c\n+++ b/target/i386/gdbstub.c\n@@ -89,10 +89,10 @@ static int gdb_read_reg_cs64(uint32_t hflags, GByteArray *buf, target_ulong val)\n static int gdb_write_reg_cs64(uint32_t hflags, uint8_t *buf, target_ulong *val)\n {\n if (hflags & HF_CS64_MASK) {\n- *val = ldq_p(buf);\n+ *val = ldq_le_p(buf);\n return 8;\n }\n- *val = ldl_p(buf);\n+ *val = ldl_le_p(buf);\n return 4;\n }\n \n@@ -221,7 +221,7 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n static int x86_cpu_gdb_load_seg(X86CPU *cpu, X86Seg sreg, uint8_t *mem_buf)\n {\n CPUX86State *env = &cpu->env;\n- uint16_t selector = ldl_p(mem_buf);\n+ uint16_t selector = ldl_le_p(mem_buf);\n \n if (selector != env->segs[sreg].selector) {\n #if defined(CONFIG_USER_ONLY)\n@@ -262,15 +262,15 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n if (n < CPU_NB_REGS) {\n if (TARGET_LONG_BITS == 64) {\n if (env->hflags & HF_CS64_MASK) {\n- env->regs[gpr_map[n]] = ldtul_p(mem_buf);\n+ env->regs[gpr_map[n]] = ldtul_le_p(mem_buf);\n } else if (n < CPU_NB_REGS32) {\n- env->regs[gpr_map[n]] = ldtul_p(mem_buf) & 0xffffffffUL;\n+ env->regs[gpr_map[n]] = ldtul_le_p(mem_buf) & 0xffffffffUL;\n }\n return sizeof(target_ulong);\n } else if (n < CPU_NB_REGS32) {\n n = gpr_map32[n];\n env->regs[n] &= ~0xffffffffUL;\n- env->regs[n] |= (uint32_t)ldl_p(mem_buf);\n+ env->regs[n] |= (uint32_t)ldl_le_p(mem_buf);\n return 4;\n }\n } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {\n@@ -281,8 +281,8 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {\n n -= IDX_XMM_REGS;\n if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) {\n- env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf);\n- env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8);\n+ env->xmm_regs[n].ZMM_Q(0) = ldq_le_p(mem_buf);\n+ env->xmm_regs[n].ZMM_Q(1) = ldq_le_p(mem_buf + 8);\n return 16;\n }\n } else {\n@@ -290,18 +290,18 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n case IDX_IP_REG:\n if (TARGET_LONG_BITS == 64) {\n if (env->hflags & HF_CS64_MASK) {\n- env->eip = ldq_p(mem_buf);\n+ env->eip = ldq_le_p(mem_buf);\n } else {\n- env->eip = ldq_p(mem_buf) & 0xffffffffUL;\n+ env->eip = ldq_le_p(mem_buf) & 0xffffffffUL;\n }\n return 8;\n } else {\n env->eip &= ~0xffffffffUL;\n- env->eip |= (uint32_t)ldl_p(mem_buf);\n+ env->eip |= (uint32_t)ldl_le_p(mem_buf);\n return 4;\n }\n case IDX_FLAGS_REG:\n- env->eflags = ldl_p(mem_buf);\n+ env->eflags = ldl_le_p(mem_buf);\n return 4;\n \n case IDX_SEG_REGS:\n@@ -327,10 +327,10 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n return 4;\n \n case IDX_FP_REGS + 8:\n- cpu_set_fpuc(env, ldl_p(mem_buf));\n+ cpu_set_fpuc(env, ldl_le_p(mem_buf));\n return 4;\n case IDX_FP_REGS + 9:\n- tmp = ldl_p(mem_buf);\n+ tmp = ldl_le_p(mem_buf);\n env->fpstt = (tmp >> 11) & 7;\n env->fpus = tmp & ~0x3800;\n return 4;\n@@ -348,7 +348,7 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n return 4;\n \n case IDX_MXCSR_REG:\n- cpu_set_mxcsr(env, ldl_p(mem_buf));\n+ cpu_set_mxcsr(env, ldl_le_p(mem_buf));\n return 4;\n \n case IDX_CTL_CR0_REG:\ndiff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c\nindex 8fb05b1f531..de6765099f3 100644\n--- a/target/i386/tcg/sysemu/excp_helper.c\n+++ b/target/i386/tcg/sysemu/excp_helper.c\n@@ -86,7 +86,7 @@ static bool ptw_translate(PTETranslate *inout, hwaddr addr, uint64_t ra)\n static inline uint32_t ptw_ldl(const PTETranslate *in, uint64_t ra)\n {\n if (likely(in->haddr)) {\n- return ldl_p(in->haddr);\n+ return ldl_le_p(in->haddr);\n }\n return cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra);\n }\n@@ -94,7 +94,7 @@ static inline uint32_t ptw_ldl(const PTETranslate *in, uint64_t ra)\n static inline uint64_t ptw_ldq(const PTETranslate *in, uint64_t ra)\n {\n if (likely(in->haddr)) {\n- return ldq_p(in->haddr);\n+ return ldq_le_p(in->haddr);\n }\n return cpu_ldq_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra);\n }\ndiff --git a/target/i386/xsave_helper.c b/target/i386/xsave_helper.c\nindex 996e9f3bfef..fc10bfa6718 100644\n--- a/target/i386/xsave_helper.c\n+++ b/target/i386/xsave_helper.c\n@@ -43,8 +43,8 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen)\n for (i = 0; i < CPU_NB_REGS; i++) {\n uint8_t *xmm = legacy->xmm_regs[i];\n \n- stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));\n- stq_p(xmm + 8, env->xmm_regs[i].ZMM_Q(1));\n+ stq_le_p(xmm, env->xmm_regs[i].ZMM_Q(0));\n+ stq_le_p(xmm + 8, env->xmm_regs[i].ZMM_Q(1));\n }\n \n header->xstate_bv = env->xstate_bv;\n@@ -58,8 +58,8 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen)\n for (i = 0; i < CPU_NB_REGS; i++) {\n uint8_t *ymmh = avx->ymmh[i];\n \n- stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));\n- stq_p(ymmh + 8, env->xmm_regs[i].ZMM_Q(3));\n+ stq_le_p(ymmh, env->xmm_regs[i].ZMM_Q(2));\n+ stq_le_p(ymmh + 8, env->xmm_regs[i].ZMM_Q(3));\n }\n }\n \n@@ -101,10 +101,10 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen)\n for (i = 0; i < CPU_NB_REGS; i++) {\n uint8_t *zmmh = zmm_hi256->zmm_hi256[i];\n \n- stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));\n- stq_p(zmmh + 8, env->xmm_regs[i].ZMM_Q(5));\n- stq_p(zmmh + 16, env->xmm_regs[i].ZMM_Q(6));\n- stq_p(zmmh + 24, env->xmm_regs[i].ZMM_Q(7));\n+ stq_le_p(zmmh, env->xmm_regs[i].ZMM_Q(4));\n+ stq_le_p(zmmh + 8, env->xmm_regs[i].ZMM_Q(5));\n+ stq_le_p(zmmh + 16, env->xmm_regs[i].ZMM_Q(6));\n+ stq_le_p(zmmh + 24, env->xmm_regs[i].ZMM_Q(7));\n }\n \n #ifdef TARGET_X86_64\n@@ -177,8 +177,8 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen)\n for (i = 0; i < CPU_NB_REGS; i++) {\n const uint8_t *xmm = legacy->xmm_regs[i];\n \n- env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);\n- env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm + 8);\n+ env->xmm_regs[i].ZMM_Q(0) = ldq_le_p(xmm);\n+ env->xmm_regs[i].ZMM_Q(1) = ldq_le_p(xmm + 8);\n }\n \n env->xstate_bv = header->xstate_bv;\n@@ -191,8 +191,8 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen)\n for (i = 0; i < CPU_NB_REGS; i++) {\n const uint8_t *ymmh = avx->ymmh[i];\n \n- env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);\n- env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh + 8);\n+ env->xmm_regs[i].ZMM_Q(2) = ldq_le_p(ymmh);\n+ env->xmm_regs[i].ZMM_Q(3) = ldq_le_p(ymmh + 8);\n }\n }\n \n@@ -241,10 +241,10 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen)\n for (i = 0; i < CPU_NB_REGS; i++) {\n const uint8_t *zmmh = zmm_hi256->zmm_hi256[i];\n \n- env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);\n- env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh + 8);\n- env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh + 16);\n- env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh + 24);\n+ env->xmm_regs[i].ZMM_Q(4) = ldq_le_p(zmmh);\n+ env->xmm_regs[i].ZMM_Q(5) = ldq_le_p(zmmh + 8);\n+ env->xmm_regs[i].ZMM_Q(6) = ldq_le_p(zmmh + 16);\n+ env->xmm_regs[i].ZMM_Q(7) = ldq_le_p(zmmh + 24);\n }\n \n #ifdef TARGET_X86_64\n", "prefixes": [ "v2", "09/25" ] }