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GET /api/patches/1965620/?format=api
{ "id": 1965620, "url": "http://patchwork.ozlabs.org/api/patches/1965620/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20240727071742.1735703-15-patrick.rudolph@9elements.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20240727071742.1735703-15-patrick.rudolph@9elements.com>", "list_archive_url": null, "date": "2024-07-27T07:17:15", "name": "[14/17] arm: cpu: Add ACPI parking protocol support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "afdcbdf3dfd9607f2d8cf2e1d753ce538fb7a008", "submitter": { "id": 83069, "url": "http://patchwork.ozlabs.org/api/people/83069/?format=api", "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com" }, "delegate": { "id": 3184, "url": "http://patchwork.ozlabs.org/api/users/3184/?format=api", "username": "sjg", "first_name": "Simon", "last_name": "Glass", "email": "sjg@chromium.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20240727071742.1735703-15-patrick.rudolph@9elements.com/mbox/", "series": [ { "id": 416851, "url": "http://patchwork.ozlabs.org/api/series/416851/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=416851", "date": "2024-07-27T07:17:01", "name": "Implement ACPI on aarch64", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/416851/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1965620/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1965620/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=9elements.com header.i=@9elements.com header.a=rsa-sha256\n header.s=google header.b=OZX+E4bk;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=quarantine dis=none) header.from=9elements.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n secure) header.d=9elements.com header.i=@9elements.com header.b=\"OZX+E4bk\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=pass (p=quarantine dis=none)\n header.from=9elements.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=patrick.rudolph@9elements.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4WWGKw0zlVz1yY3\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 27 Jul 2024 17:22:44 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 94094887B9;\n\tSat, 27 Jul 2024 09:20:40 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id BBA2588756; Sat, 27 Jul 2024 09:20:37 +0200 (CEST)", "from mail-ej1-x635.google.com (mail-ej1-x635.google.com\n [IPv6:2a00:1450:4864:20::635])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 8696C88700\n for <u-boot@lists.denx.de>; Sat, 27 Jul 2024 09:20:35 +0200 (CEST)", "by mail-ej1-x635.google.com with SMTP id\n a640c23a62f3a-a7ac469e4c4so423701266b.0\n for <u-boot@lists.denx.de>; Sat, 27 Jul 2024 00:20:35 -0700 (PDT)", "from fedora.sec.9e.network\n (ip-037-049-067-221.um09.pools.vodafone-ip.de. [37.49.67.221])\n by smtp.gmail.com with ESMTPSA id\n a640c23a62f3a-a7acab231f2sm253102866b.7.2024.07.27.00.20.34\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Sat, 27 Jul 2024 00:20:34 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS\n autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=9elements.com; s=google; t=1722064835; x=1722669635; darn=lists.denx.de;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=efT8skWO5NIs/VnokTr3QMPx5/k2IviYeMfMGCxNzeg=;\n b=OZX+E4bkcxIxmFRcs4BVEyiyrkyxrGiAad65xswd9Q9KZwIVpLkJcqFCdLanlLXGca\n QwFC5CTpDWg/5w3s5PbPo20aEz8T2X/wQGA3QNVLEXluOf6w1eokaM2RFXlD3MW9ukFy\n NkXf2i2etwhwTL//WdbZIRoQJCN3e3BmC65Bd4Lo6LhTzJMDbs9Oesrz71oVQLMVNC8G\n VNCm9w+c+4cR07XxQxpYjzUur9BYyzCRS8rB31G4tvCDpfwjw8otYc/d8LD0qCcL2nVZ\n BhTLRAXzVIJc4GZN5PlbDY6tPmubrLyzAoSxkMggMGwckiOF5hmADyJsQH5EbX+KjY+y\n u2Qw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1722064835; x=1722669635;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc\n :subject:date:message-id:reply-to;\n bh=efT8skWO5NIs/VnokTr3QMPx5/k2IviYeMfMGCxNzeg=;\n b=V79itBAJ6v105qgc8AirAvUExEa0pDQ0ljFZKTEt4jwVmpf0g9Z3ukbKNwlKSrJn3x\n NfaVCVhc6GpPOedSwti6xI/KLXHgYatjY9IqUatCF1RgD+gDcgUc6RAw19QIA7OfREJc\n s7aGPow+ejRbDNlA5VLPO4MEHag99Osd+ektRAEMAro/V2JlwoBsmvOBBhQm/uUUtKWn\n 8aU+4E4IhvEBF3xj/wlbpIHjMS78mU+p52HfwsQ7I4qDoZkZfFvulwtqEIWLW6BRE0cq\n LaerhnlHgk3YWL2xOSJo7c1WdautCna0OwEHZ9odGenkq6YOXpMRHRZIs4VgLO6VAMAp\n 6+8g==", "X-Gm-Message-State": "AOJu0Yz2Z+xHFH+LbENr06b1MB5TsXExEAEfPpd/xIoxnRfPcQ5EOhoG\n Ny0gpMzgTgRxAqIT+VKxu2HPTJ0yzBv/U1gpOsEs87bUgIOIa7RlC/7hX8RRu25fC6QQ4hl8P6M\n ocm8=", "X-Google-Smtp-Source": "\n AGHT+IGlrT4NzYju3xmXvWOGmyRupDhhztQaqYmAx9N4VJ4rJqaPTNw3rdUviQM48EkBJ/hoqPvMKQ==", "X-Received": "by 2002:a17:907:7b8b:b0:a7a:afe8:1013 with SMTP id\n a640c23a62f3a-a7d3f81db08mr179684066b.1.1722064835030;\n Sat, 27 Jul 2024 00:20:35 -0700 (PDT)", "From": "Patrick Rudolph <patrick.rudolph@9elements.com>", "To": "u-boot@lists.denx.de,\n\tSimon Glass <sjg@chromium.org>", "Cc": "mbrugger@suse.com, pbrobinson@gmail.com, trini@konsulko.com,\n bmeng.cn@gmail.com, Patrick Rudolph <patrick.rudolph@9elements.com>", "Subject": "[PATCH 14/17] arm: cpu: Add ACPI parking protocol support", "Date": "Sat, 27 Jul 2024 09:17:15 +0200", "Message-ID": "<20240727071742.1735703-15-patrick.rudolph@9elements.com>", "X-Mailer": "git-send-email 2.45.2", "In-Reply-To": "<20240727071742.1735703-1-patrick.rudolph@9elements.com>", "References": "<20240727071742.1735703-1-patrick.rudolph@9elements.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "On Arm platforms that use ACPI they cannot rely on the \"spin-table\"\nCPU bringup usually defined in the FDT. Thus implement the\n'ACPI Multi-processor Startup for ARM Platforms', also referred to as\n'ACPI parking protocol'.\n\nThe ACPI parking protocol works similar to the spin-table mechanism, but\nthe specification also covers lots of shortcomings of the spin-table\nimplementations.\n\nEvery CPU defined in the ACPI MADT table has it's own 4K page where the\nspinloop code and the OS mailbox resides. When selected the U-Boot board\ncode must make sure that the secondary CPUs enter u-boot after relocation\nas well, so that they can enter the spinloop code residing in the ACPI\nparking protocol pages.\n\nThe OS will then write to the mailbox and generate an IPI to release the\nCPUs from the spinloop code.\n\nFor now it's only implemented on ARMv8, but can easily be extended to\nother platforms.\n\nTEST: Boots all CPUs on qemu-system-aarch64 -machine raspi4b\n\nSigned-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>\nCc: Simon Glass <sjg@chromium.org>\nCc: Tom Rini <trini@konsulko.com>\n---\n arch/arm/cpu/armv8/Makefile | 1 +\n arch/arm/cpu/armv8/parking_protocol_v8.S | 102 +++++++++++++++++++++++\n arch/arm/cpu/armv8/start.S | 4 +\n arch/arm/include/asm/acpi_table.h | 52 ++++++++++++\n arch/arm/lib/acpi_table.c | 87 +++++++++++++++++++\n include/acpi/acpi_table.h | 10 +++\n lib/Kconfig | 15 ++++\n lib/acpi/acpi_table.c | 3 +\n 8 files changed, 274 insertions(+)\n create mode 100644 arch/arm/cpu/armv8/parking_protocol_v8.S", "diff": "diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile\nindex bba4f570db..9bb07bdf12 100644\n--- a/arch/arm/cpu/armv8/Makefile\n+++ b/arch/arm/cpu/armv8/Makefile\n@@ -29,6 +29,7 @@ obj-$(CONFIG_ARM_SMCCC)\t\t+= smccc-call.o\n \n ifndef CONFIG_SPL_BUILD\n obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o\n+obj-$(CONFIG_ACPI_PARKING_PROTOCOL) += parking_protocol_v8.o\n else\n obj-$(CONFIG_ARCH_SUNXI) += fel_utils.o\n endif\ndiff --git a/arch/arm/cpu/armv8/parking_protocol_v8.S b/arch/arm/cpu/armv8/parking_protocol_v8.S\nnew file mode 100644\nindex 0000000000..b7f6abbd85\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/parking_protocol_v8.S\n@@ -0,0 +1,102 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright (C) 2024 9elements GmbH\n+ * Author: Patrick Rudolph <patrick.rudolph@9elements.com>\n+ */\n+\n+#include <linux/linkage.h>\n+#include <asm/acpi_table.h>\n+\n+__secondary_cpuif_id:\n+\t.quad 0\n+\n+__secondary_parking_protocol_tables:\n+\t.quad 0\n+\n+__secondary_parking_protocol_ncpus:\n+\t.quad 0\n+\n+.global acpi_parking_protocol_code_size\n+acpi_parking_protocol_code_size:\n+\t.word __secondary_parking_protocol_code_end - __secondary_parking_protocol_code_start\n+\n+.global acpi_parking_protocol_install\n+ENTRY(acpi_parking_protocol_install)\n+\tldr\tx2, =__secondary_parking_protocol_ncpus\n+\tstr\tx1, [x2]\n+\tldr\tx2, =__secondary_parking_protocol_tables\n+\tstr\tx0, [x2]\n+\tdsb\tishst\n+\tsev\n+\tret\n+ENDPROC(acpi_parking_protocol_install)\n+\n+.global acpi_parking_protocol_secondary_jump\n+ENTRY(acpi_parking_protocol_secondary_jump)\n+0:\n+\t/* Store a unique cpuif id in x0 */\n+\tldr\tx2, =__secondary_cpuif_id\n+\tldaxr\tw0, [x2]\n+\tadd\tw0, w0, #1 // =1\n+\tstlxr\tw1, w0, [x2]\n+\tcbnz\tw1, 0b\n+\n+0:\t/* Check if parking protocol table is ready */\n+\tldr\tx1, =__secondary_parking_protocol_tables\n+\tldr\tx2, [x1]\n+\tcbnz\tx2, 0f\n+\twfe\n+\tb\t0b\n+\n+0:\t/* Sanity check cpuif id */\n+\tldr\tx1, =__secondary_parking_protocol_ncpus\n+\tldr\tx3, [x1]\n+\tcmp\tw0, w3\n+\tb.lt\t0f\n+\n+hlt:\twfi\n+\tb\thlt\t/* Should never happen. */\n+\n+\t/* Find spinning code in ACPI parking protocol table */\n+0:\tmov\tx1, #ACPI_PP_PAGE_SIZE\n+\tmul\tx3, x0, x1\n+\tadd\tx2, x2, x3\n+\tmov\tx0, x2\t\t/* Backup ACPI page ptr for later use */\n+\n+\tmov\tx1, #ACPI_PP_CPU_CODE_OFFSET\n+\tadd\tx2, x2, x1\n+\n+\t/* Jump to spin code in own parking protocol page */\n+\tbr\tx2\n+ENDPROC(acpi_parking_protocol_secondary_jump)\n+\n+.align 8\n+__secondary_parking_protocol_code_start:\n+.global acpi_parking_protocol_code_start\n+ENTRY(acpi_parking_protocol_code_start)\n+\t/* x0 points to the 4K aligned parking protocol page */\n+\n+\t/* Prepare defines for spinning code */\n+\tmov\tw3, #ACPI_PP_CPU_ID_INVALID\n+\tmov\tx2, #ACPI_PP_JMP_ADR_INVALID\n+\n+0:\twfe\n+\tldr\tw1, [x0, #ACPI_PP_CPU_ID_OFFSET]\n+\n+\t/* Check CPU ID is not invalid */\n+\tcmp\tw1, w3\n+\tb.eq\t0b\n+\n+\t/* Check jump address not invalid */\n+\tldr\tx1, [x0, #ACPI_PP_CPU_JMP_ADDR_OFFSET]\n+\tcmp\tx1, x2\n+\tb.eq\t0b\n+\n+\t/* Clear jump address before jump */\n+\tstr\tx2, [x0, #ACPI_PP_CPU_JMP_ADDR_OFFSET]\n+\tdsb\tsy\n+\n+\tbr\tx1\n+ENDPROC(acpi_parking_protocol_code_start)\n+\t/* Secondary Boot Code ends here */\n+__secondary_parking_protocol_code_end:\ndiff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S\nindex 7461280261..32a295c832 100644\n--- a/arch/arm/cpu/armv8/start.S\n+++ b/arch/arm/cpu/armv8/start.S\n@@ -178,6 +178,10 @@ pie_fixup_done:\n \tbranch_if_master x0, master_cpu\n \tb\tspin_table_secondary_jump\n \t/* never return */\n+#elif defined(CONFIG_ACPI_PARKING_PROTOCOL) && !defined(CONFIG_SPL_BUILD)\n+\tbranch_if_master x0, master_cpu\n+\tb\tacpi_parking_protocol_secondary_jump\n+\t/* never return */\n #elif defined(CONFIG_ARMV8_MULTIENTRY)\n \tbranch_if_master x0, master_cpu\n \ndiff --git a/arch/arm/include/asm/acpi_table.h b/arch/arm/include/asm/acpi_table.h\nindex 8a25e93847..3c6736239d 100644\n--- a/arch/arm/include/asm/acpi_table.h\n+++ b/arch/arm/include/asm/acpi_table.h\n@@ -4,6 +4,7 @@\n #define __ASM_ACPI_TABLE_H__\n \n #ifndef __ACPI__\n+#ifndef __ASSEMBLY__\n \n void acpi_write_madt_gicc(struct acpi_madt_gicc *gicc, uint cpu_num,\n \t\t\t uint perf_gsiv, ulong phys_base, ulong gicv,\n@@ -13,6 +14,57 @@ void acpi_write_madt_gicc(struct acpi_madt_gicc *gicc, uint cpu_num,\n void acpi_write_madt_gicd(struct acpi_madt_gicd *gicd, uint gic_id,\n \t\t\t ulong phys_base, uint gic_version);\n \n+/* Multi-processor Startup for ARM Platforms */\n+struct acpi_parking_protocol_page {\n+\tu32 cpu_id;\n+\tu32 reserved;\n+\tu64 jumping_address;\n+\tu8 os_reserved[2032];\n+\tu8 cpu_spinning_code[2048];\n+} __packed;\n+\n+/* Architecture specific functions */\n+/**\n+ * acpi_parking_protocol_code_size - Spinloop code size *\n+ */\n+extern u32 acpi_parking_protocol_code_size;\n+\n+/**\n+ * parking_protocol_code_start() - Spinloop code\n+ *\n+ * Architectural spinloop code to be installed in each parking protocol\n+ * page. The spinloop code must be less than 2048 bytes.\n+ *\n+ * The spinloop code will be entered after calling\n+ * acpi_parking_protocol_install().\n+ *\n+ */\n+void acpi_parking_protocol_code_start(void);\n+\n+/**\n+ * acpi_parking_protocol_install() - Installs the parking protocol.\n+ *\n+ * Installs the reserved memory containing the spinloop code and the\n+ * OS mailbox as required by the ACPI Multi-processor Startup for\n+ * ARM Platforms specification.\n+ *\n+ * The secondary CPUs will wait for this function to be called in order\n+ * to enter the spinloop code residing in the tables.\n+ *\n+ * @tables: ACPI parking protocol tables.\n+ * @num_cpus: Number of allocated pages.\n+ */\n+void acpi_parking_protocol_install(uintptr_t tables, size_t num_cpus);\n+\n+#endif /* !__ASSEMBLY__ */\n #endif /* !__ACPI__ */\n \n+#define ACPI_PP_CPU_ID_INVALID\t\t0xffffffff\n+#define ACPI_PP_JMP_ADR_INVALID\t\t0\n+#define ACPI_PP_PAGE_SIZE\t\t4096\n+#define ACPI_PP_CPU_ID_OFFSET\t\t0\n+#define ACPI_PP_CPU_JMP_ADDR_OFFSET\t8\n+#define ACPI_PP_CPU_CODE_OFFSET\t\t2048\n+#define ACPI_PP_VERSION\t\t\t1\n+\n #endif /* __ASM_ACPI_TABLE_H__ */\ndiff --git a/arch/arm/lib/acpi_table.c b/arch/arm/lib/acpi_table.c\nindex ea3a6343c9..2fa25ec50e 100644\n--- a/arch/arm/lib/acpi_table.c\n+++ b/arch/arm/lib/acpi_table.c\n@@ -10,7 +10,11 @@\n #include <acpi/acpigen.h>\n #include <acpi/acpi_device.h>\n #include <acpi/acpi_table.h>\n+#include <cpu_func.h>\n+#include <efi_loader.h>\n+#include <malloc.h>\n #include <string.h>\n+#include <tables_csum.h>\n \n void acpi_write_madt_gicc(struct acpi_madt_gicc *gicc, uint cpu_num,\n \t\t\t uint perf_gsiv, ulong phys_base, ulong gicv,\n@@ -42,3 +46,86 @@ void acpi_write_madt_gicd(struct acpi_madt_gicd *gicd, uint gic_id,\n \tgicd->phys_base = phys_base;\n \tgicd->gic_version = gic_version;\n }\n+\n+void acpi_write_parking_protocol(struct acpi_madt *madt)\n+{\n+\tstruct acpi_parking_protocol_page *page;\n+\tstruct acpi_madt_gicc *gicc;\n+\tvoid *reloc_addr;\n+\tu64 start;\n+\tint ncpus = 0;\n+\n+\t/* According to the \"Multi-processor Startup for ARM Platforms\":\n+\t * - Every CPU as specified by MADT GICC has it's own 4K page\n+\t * - Every page is divided into two sections: OS and FW reserved\n+\t * - Memory occupied by \"Parking Protocol\" must be marked 'Reserved'\n+\t * - Spinloop code should reside in FW reserved 2048 bytes\n+\t * - Spinloop code will check the mailbox in OS reserved area\n+\t */\n+\n+\tif (acpi_parking_protocol_code_size > sizeof(page->cpu_spinning_code)) {\n+\t\tlog_err(\"Spinning code too big to fit: %d\\n\",\n+\t\t\tacpi_parking_protocol_code_size);\n+\t}\n+\n+\t/* Count all cores including BSP */\n+\tfor (int i = sizeof(struct acpi_madt); i < madt->header.length; ) {\n+\t\tgicc = (struct acpi_madt_gicc *)((void *)madt + i);\n+\t\tif (gicc->type != ACPI_APIC_GICC) {\n+\t\t\ti += gicc->length;\n+\t\t\tcontinue;\n+\t\t}\n+\t\tncpus++;\n+\t\ti += gicc->length;\n+\t}\n+\tdebug(\"Found %d GICCs in MADT\\n\", ncpus);\n+\n+\t/* Allocate pages linearly due to assembly code requirements */\n+\tpage = memalign(ACPI_PP_PAGE_SIZE, ACPI_PP_PAGE_SIZE * ncpus);\n+\tstart = (u64)(uintptr_t)page;\n+\n+#if CONFIG_IS_ENABLED(EFI_LOADER)\n+\tint ret = efi_add_memory_map(start, ncpus * ACPI_PP_PAGE_SIZE, EFI_RESERVED_MEMORY_TYPE);\n+\n+\tif (ret != EFI_SUCCESS)\n+\t\tlog_err(\"Reserved memory mapping failed addr %llx size %x\\n\",\n+\t\t\tstart, ncpus * ACPI_PP_PAGE_SIZE);\n+#endif\n+\n+\t/* Prepare the parking protocol pages */\n+\tfor (int i = sizeof(struct acpi_madt); i < madt->header.length; ) {\n+\t\tgicc = (struct acpi_madt_gicc *)((void *)madt + i);\n+\t\tif (gicc->type != ACPI_APIC_GICC) {\n+\t\t\ti += gicc->length;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\t/* Update GICC */\n+\t\tgicc->parking_proto = ACPI_PP_VERSION;\n+\t\tgicc->parked_addr = (uint64_t)(uintptr_t)page;\n+\n+\t\t/* Prepare parking protocol page */\n+\t\tmemset(page, 0, sizeof(struct acpi_parking_protocol_page));\n+\t\tpage->cpu_id = ACPI_PP_CPU_ID_INVALID;\n+\t\tpage->jumping_address = ACPI_PP_JMP_ADR_INVALID;\n+\n+\t\t/* Relocate spinning code */\n+\t\treloc_addr = &page->cpu_spinning_code[0];\n+\n+\t\tdebug(\"Relocating spin table from %p to %p (size %x)\\n\",\n+\t\t &acpi_parking_protocol_code_start, reloc_addr,\n+\t\t acpi_parking_protocol_code_size);\n+\t\tmemcpy(reloc_addr, &acpi_parking_protocol_code_start,\n+\t\t acpi_parking_protocol_code_size);\n+\n+\t\tif (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))\n+\t\t\tflush_dcache_range((unsigned long)page,\n+\t\t\t\t\t (unsigned long)page +\n+\t\t\t\t\t sizeof(struct acpi_parking_protocol_page));\n+\t\tpage++;\n+\t\ti += gicc->length;\n+\t}\n+\n+\t/* Point secondary CPUs to new spin loop code */\n+\tacpi_parking_protocol_install(start, ncpus);\n+}\ndiff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h\nindex 26c5e9f21a..994bfd7f8d 100644\n--- a/include/acpi/acpi_table.h\n+++ b/include/acpi/acpi_table.h\n@@ -951,6 +951,16 @@ void acpi_fill_fadt(struct acpi_fadt *fadt);\n */\n void *acpi_fill_madt(struct acpi_madt *madt, void *current);\n \n+/**\n+ * acpi_write_parking_protocol() - Installs the ACPI parking protocol.\n+ *\n+ * Sets up the ACPI parking protocol and installs the spinning code for\n+ * secondary CPUs.\n+ *\n+ * @madt: The MADT to update\n+ */\n+void acpi_write_parking_protocol(struct acpi_madt *madt);\n+\n /**\n * acpi_write_dbg2_pci_uart() - Write out a DBG2 table\n *\ndiff --git a/lib/Kconfig b/lib/Kconfig\nindex 2059219a12..43e4fa3253 100644\n--- a/lib/Kconfig\n+++ b/lib/Kconfig\n@@ -314,6 +314,21 @@ config GENERATE_ACPI_TABLE\n \t by the operating system. It defines platform-independent interfaces\n \t for configuration and power management monitoring.\n \n+config ACPI_PARKING_PROTOCOL\n+\tbool \"Support ACPI parking protocol method\"\n+\tdepends on GENERATE_ACPI_TABLE\n+\tdepends on ARMV8_MULTIENTRY\n+\tdefault y if !SEC_FIRMWARE_ARMV8_PSCI && !ARMV8_PSCI\n+\thelp\n+\t Say Y here to support \"ACPI parking protocol\" enable method\n+\t for booting Linux.\n+\n+\t To use this feature, you must do:\n+\t - Bring secondary CPUs into U-Boot proper in a board specific\n+\t manner. This must be done *after* relocation. Otherwise, the\n+\t secondary CPUs will spin in unprotected memory area because the\n+\t master CPU protects the relocated spin code.\n+\n config SPL_TINY_MEMSET\n \tbool \"Use a very small memset() in SPL\"\n \tdepends on SPL\ndiff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c\nindex eb3c83ab02..56eb4a10d0 100644\n--- a/lib/acpi/acpi_table.c\n+++ b/lib/acpi/acpi_table.c\n@@ -271,6 +271,9 @@ int acpi_write_madt(struct acpi_ctx *ctx, const struct acpi_writer *entry)\n \t/* (Re)calculate length and checksum */\n \theader->length = (uintptr_t)current - (uintptr_t)madt;\n \n+\tif (IS_ENABLED(CONFIG_ACPI_PARKING_PROTOCOL))\n+\t\tacpi_write_parking_protocol(madt);\n+\n \theader->checksum = table_compute_checksum((void *)madt, header->length);\n \tacpi_add_table(ctx, madt);\n \tacpi_inc(ctx, madt->header.length);\n", "prefixes": [ "14/17" ] }