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GET /api/patches/1965617/?format=api
{ "id": 1965617, "url": "http://patchwork.ozlabs.org/api/patches/1965617/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20240727071742.1735703-12-patrick.rudolph@9elements.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20240727071742.1735703-12-patrick.rudolph@9elements.com>", "list_archive_url": null, "date": "2024-07-27T07:17:12", "name": "[11/17] arm: mach-bcm283x: Bring in some header files from tianocore", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "964e32a65f0332e38b807957f20a929042e62f21", "submitter": { "id": 83069, "url": "http://patchwork.ozlabs.org/api/people/83069/?format=api", "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com" }, "delegate": { "id": 3184, "url": "http://patchwork.ozlabs.org/api/users/3184/?format=api", "username": "sjg", "first_name": "Simon", "last_name": "Glass", "email": "sjg@chromium.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20240727071742.1735703-12-patrick.rudolph@9elements.com/mbox/", "series": [ { "id": 416851, "url": "http://patchwork.ozlabs.org/api/series/416851/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=416851", "date": "2024-07-27T07:17:01", "name": "Implement ACPI on aarch64", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/416851/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1965617/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1965617/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=9elements.com header.i=@9elements.com header.a=rsa-sha256\n header.s=google header.b=T7PnfjdZ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=quarantine dis=none) header.from=9elements.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n secure) header.d=9elements.com header.i=@9elements.com header.b=\"T7PnfjdZ\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=pass (p=quarantine dis=none)\n header.from=9elements.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=patrick.rudolph@9elements.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4WWGKH4CPxz1yY3\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 27 Jul 2024 17:22:11 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 5840B88717;\n\tSat, 27 Jul 2024 09:20:31 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id AE39788756; Sat, 27 Jul 2024 09:20:29 +0200 (CEST)", "from mail-ej1-x636.google.com (mail-ej1-x636.google.com\n [IPv6:2a00:1450:4864:20::636])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 3614788717\n for <u-boot@lists.denx.de>; Sat, 27 Jul 2024 09:20:27 +0200 (CEST)", "by mail-ej1-x636.google.com with SMTP id\n a640c23a62f3a-a7d26c2297eso229235266b.2\n for <u-boot@lists.denx.de>; Sat, 27 Jul 2024 00:20:27 -0700 (PDT)", "from fedora.sec.9e.network\n (ip-037-049-067-221.um09.pools.vodafone-ip.de. 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For now, bring them in to get the ASL code and ACPI table\ncode to compile.\n\nSigned-off-by: Simon Glass <sjg@chromium.org>\nSigned-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>\nCc: Matthias Brugger <mbrugger@suse.com>\nCc: Peter Robinson <pbrobinson@gmail.com>\nCc: Tom Rini <trini@konsulko.com>\n---\n .../mach-bcm283x/include/mach/acpi/bcm2711.h | 152 ++++++++++++++++++\n .../mach-bcm283x/include/mach/acpi/bcm2836.h | 127 +++++++++++++++\n .../include/mach/acpi/bcm2836_gpio.h | 19 +++\n .../include/mach/acpi/bcm2836_gpu.h | 47 ++++++\n .../include/mach/acpi/bcm2836_pwm.h | 33 ++++\n .../include/mach/acpi/bcm2836_sdhost.h | 18 +++\n .../include/mach/acpi/bcm2836_sdio.h | 21 +++\n drivers/pci/pcie_brcmstb.c | 101 ++----------\n 8 files changed, 427 insertions(+), 91 deletions(-)\n create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h\n create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h\n create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h\n create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h\n create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h\n create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h\n create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h", "diff": "diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h\nnew file mode 100644\nindex 0000000000..a86875b183\n--- /dev/null\n+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h\n@@ -0,0 +1,152 @@\n+/* SPDX-License-Identifier: BSD-2-Clause-Patent */\n+/**\n+ *\n+ * Copyright (c) 2019, Jeremy Linton\n+ * Copyright (c) 2019, Pete Batard <pete@akeo.ie>.\n+ *\n+ **/\n+\n+#ifndef BCM2711_H__\n+#define BCM2711_H__\n+\n+#define BCM2711_SOC_REGISTERS 0xfc000000\n+#define BCM2711_SOC_REGISTER_LENGTH 0x02000000\n+\n+#define BCM2711_ARM_LOCAL_REGISTERS 0xfe000000\n+#define BCM2711_ARM_LOCAL_REGISTER_LENGTH 0x02000000\n+\n+/* arm local addresses */\n+#define BCM2711_ARMC_OFFSET 0x0000b000\n+#define BCM2711_ARMC_BASE_ADDRESS (BCM2711_ARM_LOCAL_REGISTERS + BCM2711_ARMC_OFFSET)\n+#define BCM2711_ARMC_LENGTH 0x00000400\n+\n+#define BCM2711_ARM_LOCAL_OFFSET 0x01800000\n+#define BCM2711_ARM_LOCAL_BASE_ADDRESS (BCM2711_ARM_LOCAL_REGISTERS + BCM2711_ARM_LOCAL_OFFSET)\n+#define BCM2711_ARM_LOCAL_LENGTH 0x00000080\n+\n+#define BCM2711_GIC400_OFFSET 0x01840000\n+#define BCM2711_GIC400_BASE_ADDRESS (BCM2711_ARM_LOCAL_REGISTERS + BCM2711_GIC400_OFFSET)\n+#define BCM2711_GIC400_LENGTH 0x00008000\n+\n+/* Generic PCI addresses */\n+#define PCIE_TOP_OF_MEM_WIN 0xf8000000\n+#define PCIE_CPU_MMIO_WINDOW 0x600000000\n+#define PCIE_BRIDGE_MMIO_LEN 0x3ffffff\n+\n+/* PCI root bridge control registers location */\n+#define PCIE_REG_BASE 0xfd500000\n+#define PCIE_REG_LIMIT 0x9310\n+\n+/* PCI root bridge control registers */\n+#define BRCM_PCIE_CAP_REGS 0x00ac\n+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188\n+#define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0\n+#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c\n+#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc\n+#define LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00\n+\n+#define PCIE_RC_DL_MDIO_ADDR 0x1100\n+#define PCIE_RC_DL_MDIO_WR_DATA 0x1104\n+#define PCIE_RC_DL_MDIO_RD_DATA 0x1108\n+\n+#define PCIE_MISC_MISC_CTRL 0x4008\n+#define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000\n+#define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000\n+#define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000\n+#define MISC_CTRL_MAX_BURST_SIZE_128 0x0\n+#define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000\n+\n+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c\n+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010\n+#define PCIE_MEM_WIN0_LO(win)\t\\\n+\t\tPCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)\n+\n+#define PCIE_MEM_WIN0_HI(win)\t\\\n+\t\tPCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)\n+#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c\n+#define RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f\n+#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034\n+#define RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f\n+#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038\n+#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c\n+#define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f\n+#define PCIE_MISC_PCIE_STATUS 0x4068\n+#define STATUS_PCIE_PORT_MASK 0x80\n+#define STATUS_PCIE_PORT_SHIFT 7\n+#define STATUS_PCIE_DL_ACTIVE_MASK 0x20\n+#define STATUS_PCIE_DL_ACTIVE_SHIFT 5\n+#define STATUS_PCIE_PHYLINKUP_MASK 0x10\n+#define STATUS_PCIE_PHYLINKUP_SHIFT 4\n+#define PCIE_MISC_REVISION 0x406c\n+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070\n+#define MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000\n+#define MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0\n+#define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12\n+#define PCIE_MEM_WIN0_BASE_LIMIT(win)\t\\\n+\t PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)\n+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080\n+#define MEM_WIN0_BASE_HI_BASE_MASK 0xff\n+#define PCIE_MEM_WIN0_BASE_HI(win)\t\\\n+\t PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)\n+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084\n+#define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff\n+#define PCIE_MEM_WIN0_LIMIT_HI(win)\t\\\n+\t PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)\n+\n+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204\n+#define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000\n+\n+#define PCIE_INTR2_CPU_STATUS 0x4300\n+#define PCIE_INTR2_CPU_SET 0x4304\n+#define PCIE_INTR2_CPU_CLR 0x4308\n+#define PCIE_INTR2_CPU_MASK_STATUS 0x430c\n+#define PCIE_INTR2_CPU_MASK_SET 0x4310\n+#define PCIE_INTR2_CPU_MASK_CLR 0x4314\n+\n+#define PCIE_MSI_INTR2_CLR 0x4508\n+#define PCIE_MSI_INTR2_MASK_SET 0x4510\n+\n+#define PCIE_RGR1_SW_INIT_1 0x9210\n+#define PCIE_EXT_CFG_INDEX 0x9000\n+/* A small window pointing at the ECAM of the device selected by CFG_INDEX */\n+#define PCIE_EXT_CFG_DATA 0x8000\n+\n+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc\n+#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff\n+\n+#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000\n+#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000\n+#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000\n+#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000\n+#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000\n+#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f\n+#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f\n+\n+#define PCIE_RGR1_SW_INIT_1_INIT_MASK 0x2\n+#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1\n+\n+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000\n+\n+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2\n+\n+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000\n+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0\n+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff\n+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff\n+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_MASK_BITS 0xc\n+\n+#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff\n+\n+#define BURST_SIZE_128 0\n+#define BURST_SIZE_256 1\n+#define BURST_SIZE_512 2\n+\n+#define BCM2711_THERM_SENSOR_OFFSET 0x015d2200\n+#define BCM2711_THERM_SENSOR_BASE_ADDRESS (BCM2711_SOC_REGISTERS + BCM2711_THERM_SENSOR_OFFSET)\n+#define BCM2711_THERM_SENSOR_LENGTH 0x00000008\n+\n+#define BCM2711_GENET_BASE_OFFSET 0x01580000\n+#define BCM2711_GENET_BASE_ADDRESS (BCM2711_SOC_REGISTERS + BCM2711_GENET_BASE_OFFSET)\n+#define BCM2711_GENET_LENGTH 0x10000\n+\n+#endif /* BCM2711_H__ */\ndiff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h\nnew file mode 100644\nindex 0000000000..64cec36a94\n--- /dev/null\n+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h\n@@ -0,0 +1,127 @@\n+/* SPDX-License-Identifier: BSD-2-Clause-Patent */\n+/**\n+ *\n+ * Copyright (c) 2019, ARM Limited. All rights reserved.\n+ * Copyright (c) 2017, Andrei Warkentin <andrey.warkentin@gmail.com>\n+ * Copyright (c) 2016, Linaro Limited. All rights reserved.\n+ *\n+ **/\n+\n+#ifndef __BCM2836_H__\n+#define __BCM2836_H__\n+\n+/*\n+ * Both \"core\" and SoC perpherals (1M each).\n+ */\n+#define BCM2836_SOC_REGISTERS 0xfe000000\n+#define BCM2836_SOC_REGISTER_LENGTH 0x02000000\n+\n+/*\n+ * Offset between the CPU's view and the VC's view of system memory.\n+ */\n+#define BCM2836_DMA_DEVICE_OFFSET 0xc0000000\n+\n+/* watchdog constants */\n+#define BCM2836_WDOG_OFFSET 0x00100000\n+#define BCM2836_WDOG_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_WDOG_OFFSET)\n+#define BCM2836_WDOG_PASSWORD 0x5a000000\n+#define BCM2836_WDOG_RSTC_OFFSET 0x0000001c\n+#define BCM2836_WDOG_WDOG_OFFSET 0x00000024\n+#define BCM2836_WDOG_RSTC_WRCFG_MASK 0x00000030\n+#define BCM2836_WDOG_RSTC_WRCFG_FULL_RESET 0x00000020\n+\n+/* clock manager constants */\n+#define BCM2836_CM_OFFSET 0x00101000\n+#define BCM2836_CM_BASE (BCM2836_SOC_REGISTERS + BCM2836_CM_OFFSET)\n+#define BCM2836_CM_GEN_CLOCK_CONTROL 0x0000\n+#define BCM2836_CM_GEN_CLOCK_DIVISOR 0x0004\n+#define BCM2836_CM_VPU_CLOCK_CONTROL 0x0008\n+#define BCM2836_CM_VPU_CLOCK_DIVISOR 0x000c\n+#define BCM2836_CM_SYSTEM_CLOCK_CONTROL 0x0010\n+#define BCM2836_CM_SYSTEM_CLOCK_DIVISOR 0x0014\n+#define BCM2836_CM_H264_CLOCK_CONTROL 0x0028\n+#define BCM2836_CM_H264_CLOCK_DIVISOR 0x002c\n+#define BCM2836_CM_PWM_CLOCK_CONTROL 0x00a0\n+#define BCM2836_CM_PWM_CLOCK_DIVISOR 0x00a4\n+#define BCM2836_CM_UART_CLOCK_CONTROL 0x00f0\n+#define BCM2836_CM_UART_CLOCK_DIVISOR 0x00f4\n+#define BCM2836_CM_SDC_CLOCK_CONTROL 0x01a8\n+#define BCM2836_CM_SDC_CLOCK_DIVISOR 0x01ac\n+#define BCM2836_CM_ARM_CLOCK_CONTROL 0x01b0\n+#define BCM2836_CM_ARM_CLOCK_DIVISOR 0x01b4\n+#define BCM2836_CM_EMMC_CLOCK_CONTROL 0x01c0\n+#define BCM2836_CM_EMMC_CLOCK_DIVISOR 0x01c4\n+\n+/* mailbox interface constants */\n+#define BCM2836_MBOX_OFFSET 0x0000b880\n+#define BCM2836_MBOX_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_MBOX_OFFSET)\n+#define BCM2836_MBOX_LENGTH 0x00000024\n+#define BCM2836_MBOX_READ_OFFSET 0x00000000\n+#define BCM2836_MBOX_STATUS_OFFSET 0x00000018\n+#define BCM2836_MBOX_CONFIG_OFFSET 0x0000001c\n+#define BCM2836_MBOX_WRITE_OFFSET 0x00000020\n+\n+#define BCM2836_MBOX_STATUS_FULL 0x1f\n+#define BCM2836_MBOX_STATUS_EMPTY 0x1e\n+\n+#define BCM2836_MBOX_NUM_CHANNELS 16\n+\n+/* interrupt controller constants */\n+#define BCM2836_INTC_TIMER_CONTROL_OFFSET 0x00000040\n+#define BCM2836_INTC_TIMER_PENDING_OFFSET 0x00000060\n+\n+/* usb constants */\n+#define BCM2836_USB_OFFSET 0x00980000\n+#define BCM2836_USB_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_USB_OFFSET)\n+#define BCM2836_USB_LENGTH 0x00010000\n+\n+/* serial based protocol constants */\n+#define BCM2836_PL011_UART_OFFSET 0x00201000\n+#define BCM2836_PL011_UART_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PL011_UART_OFFSET)\n+#define BCM2836_PL011_UART_LENGTH 0x00001000\n+\n+#define BCM2836_MINI_UART_OFFSET 0x00215000\n+#define BCM2836_MINI_UART_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_MINI_UART_OFFSET)\n+#define BCM2836_MINI_UART_LENGTH 0x00000070\n+\n+#define BCM2836_I2C0_OFFSET 0x00205000\n+#define BCM2836_I2C0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C0_OFFSET)\n+#define BCM2836_I2C0_LENGTH 0x00000020\n+\n+#define BCM2836_I2C1_OFFSET 0x00804000\n+#define BCM2836_I2C1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C1_OFFSET)\n+#define BCM2836_I2C1_LENGTH 0x00000020\n+\n+#define BCM2836_I2C2_OFFSET 0x00805000\n+#define BCM2836_I2C2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C2_OFFSET)\n+#define BCM2836_I2C2_LENGTH 0x00000020\n+\n+#define BCM2836_SPI0_OFFSET 0x00204000\n+#define BCM2836_SPI0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI0_OFFSET)\n+#define BCM2836_SPI0_LENGTH 0x00000020\n+\n+#define BCM2836_SPI1_OFFSET 0x00215080\n+#define BCM2836_SPI1_LENGTH 0x00000040\n+#define BCM2836_SPI1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI1_OFFSET)\n+\n+#define BCM2836_SPI2_OFFSET 0x002150C0\n+#define BCM2836_SPI2_LENGTH 0x00000040\n+#define BCM2836_SPI2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI2_OFFSET)\n+\n+#define BCM2836_SYSTEM_TIMER_OFFSET 0x00003000\n+#define BCM2836_SYSTEM_TIMER_LENGTH 0x00000020\n+#define BCM2836_SYSTEM_TIMER_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SYSTEM_TIMER_OFFSET)\n+\n+/* dma constants */\n+#define BCM2836_DMA0_OFFSET 0x00007000\n+#define BCM2836_DMA0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA0_OFFSET)\n+\n+#define BCM2836_DMA15_OFFSET 0x00E05000\n+#define BCM2836_DMA15_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA15_OFFSET)\n+\n+#define BCM2836_DMA_CTRL_OFFSET 0x00007FE0\n+#define BCM2836_DMA_CTRL_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA_CTRL_OFFSET)\n+\n+#define BCM2836_DMA_CHANNEL_LENGTH 0x00000100\n+\n+#endif /*__BCM2836_H__ */\ndiff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h\nnew file mode 100644\nindex 0000000000..c5b858b412\n--- /dev/null\n+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h\n@@ -0,0 +1,19 @@\n+/* SPDX-License-Identifier: BSD-2-Clause-Patent */\n+/**\n+ *\n+ * Copyright (c) 2020, Pete Batard <pete@akeo.ie>\n+ * Copyright (c) 2018, Andrei Warkentin <andrey.warkentin@gmail.com>\n+ * Copyright (c) Microsoft Corporation. All rights reserved.\n+ *\n+ **/\n+\n+#include <asm/arch/acpi/bcm2836.h>\n+\n+#ifndef __BCM2836_GPIO_H__\n+#define __BCM2836_GPIO_H__\n+\n+#define GPIO_OFFSET 0x00200000\n+#define GPIO_BASE_ADDRESS (BCM2836_SOC_REGISTERS + GPIO_OFFSET)\n+#define GPIO_LENGTH 0x000000B4\n+\n+#endif /* __BCM2836_GPIO_H__ */\ndiff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h\nnew file mode 100644\nindex 0000000000..5857d7581a\n--- /dev/null\n+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h\n@@ -0,0 +1,47 @@\n+/* SPDX-License-Identifier: BSD-2-Clause-Patent */\n+/**\n+ *\n+ * Copyright (c) 2020, Pete Batard <pete@akeo.ie>\n+ *\n+ **/\n+\n+#include <asm/arch/acpi/bcm2836.h>\n+\n+#ifndef __BCM2836_GPU_H__\n+#define __BCM2836_GPU_H__\n+\n+/* VideoCore constants */\n+\n+#define BCM2836_VCHIQ_OFFSET 0x0000B840\n+#define BCM2836_VCHIQ_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_VCHIQ_OFFSET)\n+#define BCM2836_VCHIQ_LENGTH 0x00000010\n+\n+#define BCM2836_V3D_BUS_OFFSET 0x00C00000\n+#define BCM2836_V3D_BUS_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_V3D_BUS_OFFSET)\n+#define BCM2836_V3D_BUS_LENGTH 0x00001000\n+\n+#define BCM2836_HVS_OFFSET 0x00400000\n+#define BCM2836_HVS_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HVS_OFFSET)\n+#define BCM2836_HVS_LENGTH 0x00006000\n+\n+#define BCM2836_PV0_OFFSET 0x00206000\n+#define BCM2836_PV0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV0_OFFSET)\n+#define BCM2836_PV0_LENGTH 0x00000100\n+\n+#define BCM2836_PV1_OFFSET 0x00207000\n+#define BCM2836_PV1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV1_OFFSET)\n+#define BCM2836_PV1_LENGTH 0x00000100\n+\n+#define BCM2836_PV2_OFFSET 0x00807000\n+#define BCM2836_PV2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV2_OFFSET)\n+#define BCM2836_PV2_LENGTH 0x00000100\n+\n+#define BCM2836_HDMI0_OFFSET 0x00902000\n+#define BCM2836_HDMI0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HDMI0_OFFSET)\n+#define BCM2836_HDMI0_LENGTH 0x00000600\n+\n+#define BCM2836_HDMI1_OFFSET 0x00808000\n+#define BCM2836_HDMI1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HDMI1_OFFSET)\n+#define BCM2836_HDMI1_LENGTH 0x00000100\n+\n+#endif /* __BCM2836_MISC_H__ */\ndiff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h\nnew file mode 100644\nindex 0000000000..78a8486673\n--- /dev/null\n+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h\n@@ -0,0 +1,33 @@\n+/* SPDX-License-Identifier: BSD-2-Clause-Patent */\n+/**\n+ *\n+ * Copyright (c) 2020, Pete Batard <pete@akeo.ie>\n+ *\n+ **/\n+\n+#include <asm/arch/acpi/bcm2836.h>\n+\n+#ifndef __BCM2836_PWM_H__\n+#define __BCM2836_PWM_H__\n+\n+/* PWM controller constants */\n+\n+#define BCM2836_PWM_DMA_OFFSET 0x00007B00\n+#define BCM2836_PWM_DMA_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PWM_DMA_OFFSET)\n+#define BCM2836_PWM_DMA_LENGTH 0x00000100\n+\n+#define BCM2836_PWM_CLK_OFFSET 0x001010A0\n+#define BCM2836_PWM_CLK_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PWM_CLK_OFFSET)\n+#define BCM2836_PWM_CLK_LENGTH 0x00000008\n+\n+#define BCM2836_PWM_CTRL_OFFSET 0x0020C000\n+#define BCM2836_PWM_CTRL_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PWM_CTRL_OFFSET)\n+#define BCM2836_PWM_CTRL_LENGTH 0x00000028\n+\n+#define BCM2836_PWM_BUS_BASE_ADDRESS 0x7E20C000\n+#define BCM2836_PWM_BUS_LENGTH 0x00000028\n+\n+#define BCM2836_PWM_CTRL_UNCACHED_BASE_ADDRESS 0xFF20C000\n+#define BCM2836_PWM_CTRL_UNCACHED_LENGTH 0x00000028\n+\n+#endif /* __BCM2836_PWM_H__ */\ndiff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h\nnew file mode 100644\nindex 0000000000..9b1afe8440\n--- /dev/null\n+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h\n@@ -0,0 +1,18 @@\n+/* SPDX-License-Identifier: BSD-2-Clause-Patent */\n+/**\n+ *\n+ * Copyright (c) 2017, Andrei Warkentin <andrey.warkentin@gmail.com>\n+ * Copyright (c) Microsoft Corporation. All rights reserved.\n+ *\n+ **/\n+\n+#include <asm/arch/acpi/bcm2836.h>\n+\n+#ifndef __BCM2836_SDHOST_H__\n+#define __BCM2836_SDHOST_H__\n+\n+#define SDHOST_OFFSET 0x00202000\n+#define SDHOST_BASE_ADDRESS (BCM2836_SOC_REGISTERS + SDHOST_OFFSET)\n+#define SDHOST_LENGTH 0x00000100\n+\n+#endif /*__BCM2836_SDHOST_H__ */\ndiff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h\nnew file mode 100644\nindex 0000000000..48d073d434\n--- /dev/null\n+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h\n@@ -0,0 +1,21 @@\n+/* SPDX-License-Identifier: BSD-2-Clause-Patent */\n+/**\n+ *\n+ * Copyright (c) Microsoft Corporation. All rights reserved.\n+ *\n+ **/\n+\n+#include <asm/arch/acpi/bcm2836.h>\n+\n+#ifndef __BCM2836_SDIO_H__\n+#define __BCM2836_SDIO_H__\n+\n+// MMC/SD/SDIO1 register definitions.\n+#define MMCHS1_OFFSET 0x00300000\n+#define MMCHS2_OFFSET 0x00340000\n+#define MMCHS1_BASE (BCM2836_SOC_REGISTERS + MMCHS1_OFFSET)\n+#define MMCHS2_BASE (BCM2836_SOC_REGISTERS + MMCHS2_OFFSET)\n+#define MMCHS1_LENGTH 0x00000100\n+#define MMCHS2_LENGTH 0x00000100\n+\n+#endif /* __BCM2836_SDIO_H__ */\ndiff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c\nindex f978c64365..f089c48f02 100644\n--- a/drivers/pci/pcie_brcmstb.c\n+++ b/drivers/pci/pcie_brcmstb.c\n@@ -12,6 +12,7 @@\n * Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>\n */\n \n+#include <asm/arch/acpi/bcm2711.h>\n #include <errno.h>\n #include <dm.h>\n #include <dm/ofnode.h>\n@@ -21,88 +22,6 @@\n #include <linux/log2.h>\n #include <linux/iopoll.h>\n \n-/* Offset of the mandatory PCIe capability config registers */\n-#define BRCM_PCIE_CAP_REGS\t\t\t\t0x00ac\n-\n-/* The PCIe controller register offsets */\n-#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1\t\t0x0188\n-#define VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK\t0xc\n-#define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN\t\t0x0\n-\n-#define PCIE_RC_CFG_PRIV1_ID_VAL3\t\t\t0x043c\n-#define CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK\t\t0xffffff\n-\n-#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY\t\t\t0x04dc\n-#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK\t0xc00\n-\n-#define PCIE_RC_DL_MDIO_ADDR\t\t\t\t0x1100\n-#define PCIE_RC_DL_MDIO_WR_DATA\t\t\t\t0x1104\n-#define PCIE_RC_DL_MDIO_RD_DATA\t\t\t\t0x1108\n-\n-#define PCIE_MISC_MISC_CTRL\t\t\t\t0x4008\n-#define MISC_CTRL_SCB_ACCESS_EN_MASK\t\t\t0x1000\n-#define MISC_CTRL_CFG_READ_UR_MODE_MASK\t\t0x2000\n-#define MISC_CTRL_MAX_BURST_SIZE_MASK\t\t\t0x300000\n-#define MISC_CTRL_MAX_BURST_SIZE_128\t\t\t0x0\n-#define MISC_CTRL_SCB0_SIZE_MASK\t\t\t0xf8000000\n-\n-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO\t\t0x400c\n-#define PCIE_MEM_WIN0_LO(win)\t\\\n-\t\tPCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)\n-\n-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI\t\t0x4010\n-#define PCIE_MEM_WIN0_HI(win)\t\\\n-\t\tPCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)\n-\n-#define PCIE_MISC_RC_BAR1_CONFIG_LO\t\t\t0x402c\n-#define RC_BAR1_CONFIG_LO_SIZE_MASK\t\t\t0x1f\n-\n-#define PCIE_MISC_RC_BAR2_CONFIG_LO\t\t\t0x4034\n-#define RC_BAR2_CONFIG_LO_SIZE_MASK\t\t\t0x1f\n-#define PCIE_MISC_RC_BAR2_CONFIG_HI\t\t\t0x4038\n-\n-#define PCIE_MISC_RC_BAR3_CONFIG_LO\t\t\t0x403c\n-#define RC_BAR3_CONFIG_LO_SIZE_MASK\t\t\t0x1f\n-\n-#define PCIE_MISC_PCIE_STATUS\t\t\t\t0x4068\n-#define STATUS_PCIE_PORT_MASK\t\t\t\t0x80\n-#define STATUS_PCIE_PORT_SHIFT\t\t\t\t7\n-#define STATUS_PCIE_DL_ACTIVE_MASK\t\t\t0x20\n-#define STATUS_PCIE_DL_ACTIVE_SHIFT\t\t\t5\n-#define STATUS_PCIE_PHYLINKUP_MASK\t\t\t0x10\n-#define STATUS_PCIE_PHYLINKUP_SHIFT\t\t\t4\n-\n-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT\t0x4070\n-#define MEM_WIN0_BASE_LIMIT_LIMIT_MASK\t\t\t0xfff00000\n-#define MEM_WIN0_BASE_LIMIT_BASE_MASK\t\t\t0xfff0\n-#define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT\t\t12\n-#define PCIE_MEM_WIN0_BASE_LIMIT(win)\t\\\n-\t PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)\n-\n-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI\t\t0x4080\n-#define MEM_WIN0_BASE_HI_BASE_MASK\t\t\t0xff\n-#define PCIE_MEM_WIN0_BASE_HI(win)\t\\\n-\t PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)\n-\n-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI\t\t0x4084\n-#define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK\t\t0xff\n-#define PCIE_MEM_WIN0_LIMIT_HI(win)\t\\\n-\t PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)\n-\n-#define PCIE_MISC_HARD_PCIE_HARD_DEBUG\t\t\t0x4204\n-#define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK\t\t0x08000000\n-\n-#define PCIE_MSI_INTR2_CLR\t\t\t\t0x4508\n-#define PCIE_MSI_INTR2_MASK_SET\t\t\t\t0x4510\n-\n-#define PCIE_EXT_CFG_DATA\t\t\t\t0x8000\n-\n-#define PCIE_EXT_CFG_INDEX\t\t\t\t0x9000\n-\n-#define PCIE_RGR1_SW_INIT_1\t\t\t\t0x9210\n-#define RGR1_SW_INIT_1_PERST_MASK\t\t\t0x1\n-#define RGR1_SW_INIT_1_INIT_MASK\t\t\t0x2\n-\n /* PCIe parameters */\n #define BRCM_NUM_PCIE_OUT_WINS\t\t\t\t4\n \n@@ -447,7 +366,7 @@ static int brcm_pcie_probe(struct udevice *dev)\n \t * This will need to be changed when support for other SoCs is added.\n \t */\n \tsetbits_le32(base + PCIE_RGR1_SW_INIT_1,\n-\t\t RGR1_SW_INIT_1_INIT_MASK | RGR1_SW_INIT_1_PERST_MASK);\n+\t\t PCIE_RGR1_SW_INIT_1_INIT_MASK | PCIE_RGR1_SW_INIT_1_PERST_MASK);\n \t/*\n \t * The delay is a safety precaution to preclude the reset signal\n \t * from looking like a glitch.\n@@ -455,7 +374,7 @@ static int brcm_pcie_probe(struct udevice *dev)\n \tudelay(100);\n \n \t/* Take the bridge out of reset */\n-\tclrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);\n+\tclrbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK);\n \n \tclrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,\n \t\t PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);\n@@ -508,7 +427,7 @@ static int brcm_pcie_probe(struct udevice *dev)\n \n \t/* Unassert the fundamental reset */\n \tclrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1,\n-\t\t RGR1_SW_INIT_1_PERST_MASK);\n+\t\t PCIE_RGR1_SW_INIT_1_PERST_MASK);\n \n \t/*\n \t * Wait for 100ms after PERST# deassertion; see PCIe CEM specification\n@@ -552,7 +471,7 @@ static int brcm_pcie_probe(struct udevice *dev)\n \t * a PCIe-PCIe bridge (the default setting is to be EP mode).\n \t */\n \tclrsetbits_le32(base + PCIE_RC_CFG_PRIV1_ID_VAL3,\n-\t\t\tCFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400);\n+\t\t\tPCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400);\n \n \tif (pcie->ssc) {\n \t\tret = brcm_pcie_set_ssc(pcie->base);\n@@ -570,8 +489,8 @@ static int brcm_pcie_probe(struct udevice *dev)\n \t nlw, ssc_good ? \"(SSC)\" : \"(!SSC)\");\n \n \t/* PCIe->SCB endian mode for BAR */\n-\tclrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1,\n-\t\t\tVENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK,\n+\tclrsetbits_le32(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,\n+\t\t\tPCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK,\n \t\t\tVENDOR_SPECIFIC_REG1_LITTLE_ENDIAN);\n \n \t/*\n@@ -584,7 +503,7 @@ static int brcm_pcie_probe(struct udevice *dev)\n \t * let's instead just unadvertise ASPM support.\n \t */\n \tclrbits_le32(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY,\n-\t\t PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);\n+\t\t LINK_CAPABILITY_ASPM_SUPPORT_MASK);\n \n \treturn 0;\n }\n@@ -595,14 +514,14 @@ static int brcm_pcie_remove(struct udevice *dev)\n \tvoid __iomem *base = pcie->base;\n \n \t/* Assert fundamental reset */\n-\tsetbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_PERST_MASK);\n+\tsetbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_PERST_MASK);\n \n \t/* Turn off SerDes */\n \tsetbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,\n \t\t PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);\n \n \t/* Shutdown bridge */\n-\tsetbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);\n+\tsetbits_le32(base + PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK);\n \n \treturn 0;\n }\n", "prefixes": [ "11/17" ] }