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GET /api/patches/1965607/?format=api
{ "id": 1965607, "url": "http://patchwork.ozlabs.org/api/patches/1965607/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20240727071742.1735703-2-patrick.rudolph@9elements.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20240727071742.1735703-2-patrick.rudolph@9elements.com>", "list_archive_url": null, "date": "2024-07-27T07:17:02", "name": "[01/17] acpi: x86: Move SPCR and DBG2 into common code", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "0df8746a7dd7504621310896dc075a877f85e81d", "submitter": { "id": 83069, "url": "http://patchwork.ozlabs.org/api/people/83069/?format=api", "name": "Patrick Rudolph", "email": "patrick.rudolph@9elements.com" }, "delegate": { "id": 3184, "url": "http://patchwork.ozlabs.org/api/users/3184/?format=api", "username": "sjg", "first_name": "Simon", "last_name": "Glass", "email": "sjg@chromium.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20240727071742.1735703-2-patrick.rudolph@9elements.com/mbox/", "series": [ { "id": 416851, "url": "http://patchwork.ozlabs.org/api/series/416851/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=416851", "date": "2024-07-27T07:17:01", "name": "Implement ACPI on aarch64", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/416851/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1965607/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1965607/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=9elements.com header.i=@9elements.com header.a=rsa-sha256\n header.s=google header.b=frzqyMl9;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=quarantine dis=none) header.from=9elements.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n secure) header.d=9elements.com header.i=@9elements.com header.b=\"frzqyMl9\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=pass (p=quarantine dis=none)\n header.from=9elements.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=patrick.rudolph@9elements.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4WWGHD2pp1z1yY3\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 27 Jul 2024 17:20:24 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id CDAB18858C;\n\tSat, 27 Jul 2024 09:20:10 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id CA41588606; Sat, 27 Jul 2024 09:20:09 +0200 (CEST)", "from mail-ej1-x633.google.com (mail-ej1-x633.google.com\n [IPv6:2a00:1450:4864:20::633])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 739B4884DB\n for <u-boot@lists.denx.de>; Sat, 27 Jul 2024 09:20:07 +0200 (CEST)", "by mail-ej1-x633.google.com with SMTP id\n a640c23a62f3a-a6265d3ba8fso206749866b.0\n for <u-boot@lists.denx.de>; Sat, 27 Jul 2024 00:20:07 -0700 (PDT)", "from fedora.sec.9e.network\n (ip-037-049-067-221.um09.pools.vodafone-ip.de. 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Write out a DBG2 table\n- *\n- * @ctx: Current ACPI context\n- * @dev: Debug UART device to describe\n- * @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS)\n- * Return: 0 if OK, -ve on error\n- */\n-int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,\n-\t\t\t uint access_size);\n-\n /**\n * acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table\n *\ndiff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c\nindex e38ce19ff7..08fd1e54ce 100644\n--- a/arch/x86/lib/acpi_table.c\n+++ b/arch/x86/lib/acpi_table.c\n@@ -279,140 +279,6 @@ static int acpi_write_tpm2(struct acpi_ctx *ctx,\n }\n ACPI_WRITER(5tpm2, \"TPM2\", acpi_write_tpm2, 0);\n \n-int acpi_write_spcr(struct acpi_ctx *ctx, const struct acpi_writer *entry)\n-{\n-\tstruct serial_device_info serial_info = {0};\n-\tulong serial_address, serial_offset;\n-\tstruct acpi_table_header *header;\n-\tstruct acpi_spcr *spcr;\n-\tstruct udevice *dev;\n-\tuint serial_config;\n-\tuint serial_width;\n-\tint access_size;\n-\tint space_id;\n-\tint ret = -ENODEV;\n-\n-\tspcr = ctx->current;\n-\theader = &spcr->header;\n-\n-\tmemset(spcr, '\\0', sizeof(struct acpi_spcr));\n-\n-\t/* Fill out header fields */\n-\tacpi_fill_header(header, \"SPCR\");\n-\theader->length = sizeof(struct acpi_spcr);\n-\theader->revision = 2;\n-\n-\t/* Read the device once, here. It is reused below */\n-\tdev = gd->cur_serial_dev;\n-\tif (dev)\n-\t\tret = serial_getinfo(dev, &serial_info);\n-\tif (ret)\n-\t\tserial_info.type = SERIAL_CHIP_UNKNOWN;\n-\n-\t/* Encode chip type */\n-\tswitch (serial_info.type) {\n-\tcase SERIAL_CHIP_16550_COMPATIBLE:\n-\t\tspcr->interface_type = ACPI_DBG2_16550_COMPATIBLE;\n-\t\tbreak;\n-\tcase SERIAL_CHIP_UNKNOWN:\n-\tdefault:\n-\t\tspcr->interface_type = ACPI_DBG2_UNKNOWN;\n-\t\tbreak;\n-\t}\n-\n-\t/* Encode address space */\n-\tswitch (serial_info.addr_space) {\n-\tcase SERIAL_ADDRESS_SPACE_MEMORY:\n-\t\tspace_id = ACPI_ADDRESS_SPACE_MEMORY;\n-\t\tbreak;\n-\tcase SERIAL_ADDRESS_SPACE_IO:\n-\tdefault:\n-\t\tspace_id = ACPI_ADDRESS_SPACE_IO;\n-\t\tbreak;\n-\t}\n-\n-\tserial_width = serial_info.reg_width * 8;\n-\tserial_offset = serial_info.reg_offset << serial_info.reg_shift;\n-\tserial_address = serial_info.addr + serial_offset;\n-\n-\t/* Encode register access size */\n-\tswitch (serial_info.reg_shift) {\n-\tcase 0:\n-\t\taccess_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;\n-\t\tbreak;\n-\tcase 1:\n-\t\taccess_size = ACPI_ACCESS_SIZE_WORD_ACCESS;\n-\t\tbreak;\n-\tcase 2:\n-\t\taccess_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;\n-\t\tbreak;\n-\tcase 3:\n-\t\taccess_size = ACPI_ACCESS_SIZE_QWORD_ACCESS;\n-\t\tbreak;\n-\tdefault:\n-\t\taccess_size = ACPI_ACCESS_SIZE_UNDEFINED;\n-\t\tbreak;\n-\t}\n-\n-\tdebug(\"UART type %u @ %lx\\n\", spcr->interface_type, serial_address);\n-\n-\t/* Fill GAS */\n-\tspcr->serial_port.space_id = space_id;\n-\tspcr->serial_port.bit_width = serial_width;\n-\tspcr->serial_port.bit_offset = 0;\n-\tspcr->serial_port.access_size = access_size;\n-\tspcr->serial_port.addrl = lower_32_bits(serial_address);\n-\tspcr->serial_port.addrh = upper_32_bits(serial_address);\n-\n-\t/* Encode baud rate */\n-\tswitch (serial_info.baudrate) {\n-\tcase 9600:\n-\t\tspcr->baud_rate = 3;\n-\t\tbreak;\n-\tcase 19200:\n-\t\tspcr->baud_rate = 4;\n-\t\tbreak;\n-\tcase 57600:\n-\t\tspcr->baud_rate = 6;\n-\t\tbreak;\n-\tcase 115200:\n-\t\tspcr->baud_rate = 7;\n-\t\tbreak;\n-\tdefault:\n-\t\tspcr->baud_rate = 0;\n-\t\tbreak;\n-\t}\n-\n-\tserial_config = SERIAL_DEFAULT_CONFIG;\n-\tif (dev)\n-\t\tret = serial_getconfig(dev, &serial_config);\n-\n-\tspcr->parity = SERIAL_GET_PARITY(serial_config);\n-\tspcr->stop_bits = SERIAL_GET_STOP(serial_config);\n-\n-\t/* No PCI devices for now */\n-\tspcr->pci_device_id = 0xffff;\n-\tspcr->pci_vendor_id = 0xffff;\n-\n-\t/*\n-\t * SPCR has no clue if the UART base clock speed is different\n-\t * to the default one. However, the SPCR 1.04 defines baud rate\n-\t * 0 as a preconfigured state of UART and OS is supposed not\n-\t * to touch the configuration of the serial device.\n-\t */\n-\tif (serial_info.clock != SERIAL_DEFAULT_CLOCK)\n-\t\tspcr->baud_rate = 0;\n-\n-\t/* Fix checksum */\n-\theader->checksum = table_compute_checksum((void *)spcr, header->length);\n-\n-\tacpi_add_table(ctx, spcr);\n-\tacpi_inc(ctx, spcr->header.length);\n-\n-\treturn 0;\n-}\n-ACPI_WRITER(5spcr, \"SPCR\", acpi_write_spcr, 0);\n-\n int acpi_write_gnvs(struct acpi_ctx *ctx, const struct acpi_writer *entry)\n {\n \tulong addr;\n@@ -515,46 +381,6 @@ int acpi_write_hpet(struct acpi_ctx *ctx)\n \treturn 0;\n }\n \n-int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,\n-\t\t\t uint access_size)\n-{\n-\tstruct acpi_dbg2_header *dbg2 = ctx->current;\n-\tchar path[ACPI_PATH_MAX];\n-\tstruct acpi_gen_regaddr address;\n-\tphys_addr_t addr;\n-\tint ret;\n-\n-\tif (!device_active(dev)) {\n-\t\tlog_info(\"Device not enabled\\n\");\n-\t\treturn -EACCES;\n-\t}\n-\t/*\n-\t * PCI devices don't remember their resource allocation information in\n-\t * U-Boot at present. We assume that MMIO is used for the UART and that\n-\t * the address space is 32 bytes: ns16550 uses 8 registers of up to\n-\t * 32-bits each. This is only for debugging so it is not a big deal.\n-\t */\n-\taddr = dm_pci_read_bar32(dev, 0);\n-\tlog_debug(\"UART addr %lx\\n\", (ulong)addr);\n-\n-\tmemset(&address, '\\0', sizeof(address));\n-\taddress.space_id = ACPI_ADDRESS_SPACE_MEMORY;\n-\taddress.addrl = (uint32_t)addr;\n-\taddress.addrh = (uint32_t)((addr >> 32) & 0xffffffff);\n-\taddress.access_size = access_size;\n-\n-\tret = acpi_device_path(dev, path, sizeof(path));\n-\tif (ret)\n-\t\treturn log_msg_ret(\"path\", ret);\n-\tacpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT,\n-\t\t\t ACPI_DBG2_16550_COMPATIBLE, &address, 0x1000, path);\n-\n-\tacpi_inc_align(ctx, dbg2->header.length);\n-\tacpi_add_table(ctx, dbg2);\n-\n-\treturn 0;\n-}\n-\n void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,\n \t\t void *dsdt)\n {\ndiff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h\nindex 15fd61a51d..fa19ea84df 100644\n--- a/include/acpi/acpi_table.h\n+++ b/include/acpi/acpi_table.h\n@@ -846,23 +846,6 @@ int acpi_get_table_revision(enum acpi_tables table);\n */\n int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags);\n \n-/**\n- * acpi_create_dbg2() - Create a DBG2 table\n- *\n- * This table describes how to access the debug UART\n- *\n- * @dbg2: Place to put information\n- * @port_type: Serial port type (see ACPI_DBG2_...)\n- * @port_subtype: Serial port sub-type (see ACPI_DBG2_...)\n- * @address: ACPI address of port\n- * @address_size: Size of address space\n- * @device_path: Path of device (created using acpi_device_path())\n- */\n-void acpi_create_dbg2(struct acpi_dbg2_header *dbg2,\n-\t\t int port_type, int port_subtype,\n-\t\t struct acpi_gen_regaddr *address, uint32_t address_size,\n-\t\t const char *device_path);\n-\n /**\n * acpi_align() - Align the ACPI output pointer to a 16-byte boundary\n *\n@@ -943,6 +926,43 @@ void acpi_fill_header(struct acpi_table_header *header, char *signature);\n */\n int acpi_fill_csrt(struct acpi_ctx *ctx);\n \n+/**\n+ * acpi_write_dbg2_pci_uart() - Write out a DBG2 table\n+ *\n+ * @ctx: Current ACPI context\n+ * @dev: Debug UART device to describe\n+ * @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS)\n+ * Return: 0 if OK, -ve on error\n+ */\n+int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,\n+\t\t\t uint access_size);\n+\n+/**\n+ * acpi_pl011_write_dbg2_uart() - Write out a DBG2 table\n+ *\n+ * To be used for PL011 style MMIO UARTs.\n+ *\n+ * @ctx: Current ACPI context\n+ * @base: Memory base address of Debug UART\n+ * @name: ACPI device path of the Debug UART\n+ * Return: 0 if OK, -ve on error\n+ */\n+void acpi_pl011_write_dbg2_uart(struct acpi_ctx *ctx,\n+\t\t\t\tu64 base, const char *name);\n+\n+/**\n+ * acpi_16550_mmio32_write_dbg2_uart() - Write out a DBG2 table\n+ *\n+ * To be used for 16550 style MMIO UARTs.\n+ *\n+ * @ctx: Current ACPI context\n+ * @base: Memory base address of Debug UART\n+ * @name: ACPI device path of the Debug UART\n+ * Return: 0 if OK, -ve on error\n+ */\n+void acpi_16550_mmio32_write_dbg2_uart(struct acpi_ctx *ctx,\n+\t\t\t\t u64 base, const char *name);\n+\n /**\n * acpi_get_rsdp_addr() - get ACPI RSDP table address\n *\ndiff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c\nindex 6dbfdb22de..e7e074d25e 100644\n--- a/lib/acpi/acpi_table.c\n+++ b/lib/acpi/acpi_table.c\n@@ -10,8 +10,10 @@\n #include <log.h>\n #include <mapmem.h>\n #include <tables_csum.h>\n+#include <serial.h>\n #include <version_string.h>\n #include <acpi/acpi_table.h>\n+#include <acpi/acpi_device.h>\n #include <asm/global_data.h>\n #include <dm/acpi.h>\n \n@@ -200,10 +202,10 @@ int acpi_add_table(struct acpi_ctx *ctx, void *table)\n \treturn 0;\n }\n \n-void acpi_create_dbg2(struct acpi_dbg2_header *dbg2,\n-\t\t int port_type, int port_subtype,\n-\t\t struct acpi_gen_regaddr *address, u32 address_size,\n-\t\t const char *device_path)\n+static void acpi_create_dbg2(struct acpi_dbg2_header *dbg2,\n+\t\t\t int port_type, int port_subtype,\n+\t\t\t struct acpi_gen_regaddr *address, u32 address_size,\n+\t\t\t const char *device_path)\n {\n \tuintptr_t current;\n \tstruct acpi_dbg2_device *device;\n@@ -262,3 +264,225 @@ void acpi_create_dbg2(struct acpi_dbg2_header *dbg2,\n \theader->length = current - (uintptr_t)dbg2;\n \theader->checksum = table_compute_checksum(dbg2, header->length);\n }\n+\n+/**\n+ * acpi_create_dbg2() - Create a DBG2 table\n+ *\n+ * This table describes how to access the debug UART\n+ *\n+ * @dbg2: Place to put information\n+ * @port_type: Serial port type (see ACPI_DBG2_...)\n+ * @port_subtype: Serial port sub-type (see ACPI_DBG2_...)\n+ * @address: ACPI address of port\n+ * @address_size: Size of address space\n+ * @device_path: Path of device (created using acpi_device_path())\n+ */\n+static void acpi_write_dbg2_uart(struct acpi_ctx *ctx,\n+\t\t\t\t int space_id, int subtype, uint64_t base, uint32_t size,\n+\t\t\t\t int access_size, const char *name)\n+{\n+\tstruct acpi_dbg2_header *dbg2 = (struct acpi_dbg2_header *)ctx->current;\n+\tstruct acpi_gen_regaddr address;\n+\n+\tmemset(&address, 0, sizeof(address));\n+\n+\taddress.space_id = space_id;\n+\taddress.addrl = (uint32_t)base;\n+\taddress.addrh = (uint32_t)((base >> 32) & 0xffffffff);\n+\taddress.access_size = access_size;\n+\n+\tacpi_create_dbg2(dbg2,\n+\t\t\t ACPI_DBG2_SERIAL_PORT,\n+\t\t\t subtype,\n+\t\t\t &address, size,\n+\t\t\t name);\n+\n+\tif (dbg2->header.length) {\n+\t\tacpi_inc_align(ctx, dbg2->header.length);\n+\t\tacpi_add_table(ctx, dbg2);\n+\t}\n+}\n+\n+int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,\n+\t\t\t uint access_size)\n+{\n+\tchar path[ACPI_PATH_MAX];\n+\tphys_addr_t addr;\n+\tint ret;\n+\n+\tif (!device_active(dev)) {\n+\t\tlog_info(\"Device not enabled\\n\");\n+\t\treturn -EACCES;\n+\t}\n+\t/*\n+\t * PCI devices don't remember their resource allocation information in\n+\t * U-Boot at present. We assume that MMIO is used for the UART and that\n+\t * the address space is 32 bytes: ns16550 uses 8 registers of up to\n+\t * 32-bits each. This is only for debugging so it is not a big deal.\n+\t */\n+\taddr = dm_pci_read_bar32(dev, 0);\n+\tlog_debug(\"UART addr %lx\\n\", (ulong)addr);\n+\n+\tret = acpi_device_path(dev, path, sizeof(path));\n+\tif (ret)\n+\t\treturn log_msg_ret(\"path\", ret);\n+\n+\tacpi_write_dbg2_uart(ctx, ACPI_ADDRESS_SPACE_MEMORY, ACPI_DBG2_16550_COMPATIBLE,\n+\t\t\t addr, 0x1000, access_size, path);\n+\n+\treturn 0;\n+}\n+\n+void acpi_pl011_write_dbg2_uart(struct acpi_ctx *ctx,\n+\t\t\t\tu64 base, const char *name)\n+{\n+\tacpi_write_dbg2_uart(ctx, ACPI_ADDRESS_SPACE_MEMORY,\n+\t\t\t ACPI_DBG2_ARM_PL011, base, 0x1000,\n+\t\t\t ACPI_ACCESS_SIZE_DWORD_ACCESS, name);\n+}\n+\n+void acpi_16550_mmio32_write_dbg2_uart(struct acpi_ctx *ctx,\n+\t\t\t\t u64 base, const char *name)\n+{\n+\tacpi_write_dbg2_uart(ctx, ACPI_ADDRESS_SPACE_MEMORY,\n+\t\t\t ACPI_DBG2_16550_COMPATIBLE, base, 0x100,\n+\t\t\t ACPI_ACCESS_SIZE_DWORD_ACCESS, name);\n+}\n+\n+int acpi_write_spcr(struct acpi_ctx *ctx, const struct acpi_writer *entry)\n+{\n+\tstruct serial_device_info serial_info = {0};\n+\tulong serial_address, serial_offset;\n+\tstruct acpi_table_header *header;\n+\tstruct acpi_spcr *spcr;\n+\tstruct udevice *dev;\n+\tuint serial_config;\n+\tuint serial_width;\n+\tint access_size;\n+\tint space_id;\n+\tint ret = -ENODEV;\n+\n+\tspcr = ctx->current;\n+\theader = &spcr->header;\n+\n+\tmemset(spcr, '\\0', sizeof(struct acpi_spcr));\n+\n+\t/* Fill out header fields */\n+\tacpi_fill_header(header, \"SPCR\");\n+\theader->length = sizeof(struct acpi_spcr);\n+\theader->revision = 2;\n+\n+\t/* Read the device once, here. It is reused below */\n+\tdev = gd->cur_serial_dev;\n+\tif (dev)\n+\t\tret = serial_getinfo(dev, &serial_info);\n+\tif (ret)\n+\t\tserial_info.type = SERIAL_CHIP_UNKNOWN;\n+\n+\t/* Encode chip type */\n+\tswitch (serial_info.type) {\n+\tcase SERIAL_CHIP_16550_COMPATIBLE:\n+\t\tspcr->interface_type = ACPI_DBG2_16550_COMPATIBLE;\n+\t\tbreak;\n+\tcase SERIAL_CHIP_PL01X:\n+\t\tspcr->interface_type = ACPI_DBG2_ARM_PL011;\n+\t\tbreak;\n+\tcase SERIAL_CHIP_UNKNOWN:\n+\tdefault:\n+\t\tspcr->interface_type = ACPI_DBG2_UNKNOWN;\n+\t\tbreak;\n+\t}\n+\n+\t/* Encode address space */\n+\tswitch (serial_info.addr_space) {\n+\tcase SERIAL_ADDRESS_SPACE_MEMORY:\n+\t\tspace_id = ACPI_ADDRESS_SPACE_MEMORY;\n+\t\tbreak;\n+\tcase SERIAL_ADDRESS_SPACE_IO:\n+\tdefault:\n+\t\tspace_id = ACPI_ADDRESS_SPACE_IO;\n+\t\tbreak;\n+\t}\n+\n+\tserial_width = serial_info.reg_width * 8;\n+\tserial_offset = serial_info.reg_offset << serial_info.reg_shift;\n+\tserial_address = serial_info.addr + serial_offset;\n+\n+\t/* Encode register access size */\n+\tswitch (serial_info.reg_shift) {\n+\tcase 0:\n+\t\taccess_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;\n+\t\tbreak;\n+\tcase 1:\n+\t\taccess_size = ACPI_ACCESS_SIZE_WORD_ACCESS;\n+\t\tbreak;\n+\tcase 2:\n+\t\taccess_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;\n+\t\tbreak;\n+\tcase 3:\n+\t\taccess_size = ACPI_ACCESS_SIZE_QWORD_ACCESS;\n+\t\tbreak;\n+\tdefault:\n+\t\taccess_size = ACPI_ACCESS_SIZE_UNDEFINED;\n+\t\tbreak;\n+\t}\n+\n+\tdebug(\"UART type %u @ %lx\\n\", spcr->interface_type, serial_address);\n+\n+\t/* Fill GAS */\n+\tspcr->serial_port.space_id = space_id;\n+\tspcr->serial_port.bit_width = serial_width;\n+\tspcr->serial_port.bit_offset = 0;\n+\tspcr->serial_port.access_size = access_size;\n+\tspcr->serial_port.addrl = lower_32_bits(serial_address);\n+\tspcr->serial_port.addrh = upper_32_bits(serial_address);\n+\n+\t/* Encode baud rate */\n+\tswitch (serial_info.baudrate) {\n+\tcase 9600:\n+\t\tspcr->baud_rate = 3;\n+\t\tbreak;\n+\tcase 19200:\n+\t\tspcr->baud_rate = 4;\n+\t\tbreak;\n+\tcase 57600:\n+\t\tspcr->baud_rate = 6;\n+\t\tbreak;\n+\tcase 115200:\n+\t\tspcr->baud_rate = 7;\n+\t\tbreak;\n+\tdefault:\n+\t\tspcr->baud_rate = 0;\n+\t\tbreak;\n+\t}\n+\n+\tserial_config = SERIAL_DEFAULT_CONFIG;\n+\tif (dev)\n+\t\tret = serial_getconfig(dev, &serial_config);\n+\n+\tspcr->parity = SERIAL_GET_PARITY(serial_config);\n+\tspcr->stop_bits = SERIAL_GET_STOP(serial_config);\n+\n+\t/* No PCI devices for now */\n+\tspcr->pci_device_id = 0xffff;\n+\tspcr->pci_vendor_id = 0xffff;\n+\n+\t/*\n+\t * SPCR has no clue if the UART base clock speed is different\n+\t * to the default one. However, the SPCR 1.04 defines baud rate\n+\t * 0 as a preconfigured state of UART and OS is supposed not\n+\t * to touch the configuration of the serial device.\n+\t */\n+\tif (serial_info.clock != SERIAL_DEFAULT_CLOCK)\n+\t\tspcr->baud_rate = 0;\n+\n+\t/* Fix checksum */\n+\theader->checksum = table_compute_checksum((void *)spcr, header->length);\n+\n+\tacpi_add_table(ctx, spcr);\n+\tacpi_inc(ctx, spcr->header.length);\n+\n+\treturn 0;\n+}\n+\n+ACPI_WRITER(5spcr, \"SPCR\", acpi_write_spcr, 0);\n", "prefixes": [ "01/17" ] }