Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1941002/?format=api
{ "id": 1941002, "url": "http://patchwork.ozlabs.org/api/patches/1941002/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/bb30527bca12b9dc51e3c7a89cc0a709e5df2bb7.1716965617.git.ysato@users.sourceforge.jp/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<bb30527bca12b9dc51e3c7a89cc0a709e5df2bb7.1716965617.git.ysato@users.sourceforge.jp>", "list_archive_url": null, "date": "2024-05-29T08:01:02", "name": "[DO,NOT,MERGE,v8,16/36] irqchip: Add SH7751 INTC driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9080c85b4c5799de16b0624c93a950e39b222d55", "submitter": { "id": 7114, "url": "http://patchwork.ozlabs.org/api/people/7114/?format=api", "name": "Yoshinori Sato", "email": "ysato@users.sourceforge.jp" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/bb30527bca12b9dc51e3c7a89cc0a709e5df2bb7.1716965617.git.ysato@users.sourceforge.jp/mbox/", "series": [ { "id": 408652, "url": "http://patchwork.ozlabs.org/api/series/408652/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=408652", "date": "2024-05-29T08:00:51", "name": "Device Tree support for SH7751 based board", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/408652/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1941002/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1941002/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-7970-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2604:1380:40f1:3f00::1; helo=sy.mirrors.kernel.org;\n envelope-from=linux-pci+bounces-7970-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=153.127.30.23", "smtp.subspace.kernel.org;\n dmarc=none (p=none dis=none) header.from=users.sourceforge.jp", "smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=users.sourceforge.jp" ], "Received": [ "from sy.mirrors.kernel.org (sy.mirrors.kernel.org\n [IPv6:2604:1380:40f1:3f00::1])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4Vq2522C2Yz20Pr\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 29 May 2024 18:05:58 +1000 (AEST)", "from smtp.subspace.kernel.org (wormhole.subspace.kernel.org\n [52.25.139.140])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby sy.mirrors.kernel.org (Postfix) with ESMTPS id DA589B2765D\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 29 May 2024 08:05:57 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id EA372179951;\n\tWed, 29 May 2024 08:02:00 +0000 (UTC)", "from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp\n [153.127.30.23])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id D7B7F177992;\n\tWed, 29 May 2024 08:01:58 +0000 (UTC)", "from SIOS1075.ysato.name (al128006.dynamic.ppp.asahi-net.or.jp\n [111.234.128.6])\n\tby sakura.ysato.name (Postfix) with ESMTPSA id DA6C21C0F6C;\n\tWed, 29 May 2024 17:01:56 +0900 (JST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1716969720; cv=none;\n b=Y+uRsw/Ny/z8KHk629Qqrhnqj5mWNzqD8E51FXcjdRyY3fpikCzNAQgxNG7bAZMlLl7Ey4aThQyJISFMp6FKlRjjN/Pz48vrF91oggJBYiJtd2FMppw0hxi/lvk2BeB4DmsxRNcsiXeqEpcosP3E4nabutg76WMeQmTNl1bEM9E=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1716969720; c=relaxed/simple;\n\tbh=z1R2WM6+MDn322XDwM0+gJz+HFcml26ExuUqyFGPt6k=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:\n\t MIME-Version;\n b=lMvVsh9I1TNk029rZ4jRC1LteSUs65F+j8NIs9K53+/P0kav8bcWJ9V+4s80JjcSE8s6lKfLaqtyQTrJQa/noaW89c1jTvuy3DH2HtD+SRjusvMXzz7StVcGSxx24SZ5AKr/S0Vw/P9N8Gqz0AItjdicQfTkN4esFoUpgxCx0Ig=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=none (p=none dis=none) header.from=users.sourceforge.jp;\n spf=fail smtp.mailfrom=users.sourceforge.jp;\n arc=none smtp.client-ip=153.127.30.23", "From": "Yoshinori Sato <ysato@users.sourceforge.jp>", "To": "linux-sh@vger.kernel.org", "Cc": "Yoshinori Sato <ysato@users.sourceforge.jp>,\n Damien Le Moal <dlemoal@kernel.org>, Niklas Cassel <cassel@kernel.org>,\n Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n Geert Uytterhoeven <geert+renesas@glider.be>,\n Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>,\n David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,\n Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,\n Maxime Ripard <mripard@kernel.org>, Thomas Zimmermann <tzimmermann@suse.de>,\n Thomas Gleixner <tglx@linutronix.de>, Bjorn Helgaas <bhelgaas@google.com>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kw@linux.com>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n Jiri Slaby <jirislaby@kernel.org>, Magnus Damm <magnus.damm@gmail.com>,\n Daniel Lezcano <daniel.lezcano@linaro.org>, Rich Felker <dalias@libc.org>,\n John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>,\n Lee Jones <lee@kernel.org>, Helge Deller <deller@gmx.de>,\n Heiko Stuebner <heiko.stuebner@cherry.de>,\n Neil Armstrong <neil.armstrong@linaro.org>,\n Chris Morgan <macromorgan@hotmail.com>, Sebastian Reichel <sre@kernel.org>,\n Linus Walleij <linus.walleij@linaro.org>, Arnd Bergmann <arnd@arndb.de>,\n Masahiro Yamada <masahiroy@kernel.org>, Baoquan He <bhe@redhat.com>,\n Andrew Morton <akpm@linux-foundation.org>,\n Guenter Roeck <linux@roeck-us.net>, Kefeng Wang <wangkefeng.wang@huawei.com>,\n Stephen Rothwell <sfr@canb.auug.org.au>,\n Azeem Shaikh <azeemshaikh38@gmail.com>, Guo Ren <guoren@kernel.org>,\n Max Filippov <jcmvbkbc@gmail.com>, Jernej Skrabec <jernej.skrabec@gmail.com>,\n Herve Codina <herve.codina@bootlin.com>,\n Andy Shevchenko <andriy.shevchenko@linux.intel.com>,\n Anup Patel <apatel@ventanamicro.com>, Jacky Huang <ychuang3@nuvoton.com>,\n Hugo Villeneuve <hvilleneuve@dimonoff.com>, Jonathan Corbet <corbet@lwn.net>,\n Wolfram Sang <wsa+renesas@sang-engineering.com>, =?utf-8?q?Uwe_Kleine-K?=\n\t=?utf-8?q?=C3=B6nig?= <u.kleine-koenig@pengutronix.de>,\n Christophe JAILLET <christophe.jaillet@wanadoo.fr>,\n Sam Ravnborg <sam@ravnborg.org>,\n Javier Martinez Canillas <javierm@redhat.com>,\n Sergey Shtylyov <s.shtylyov@omp.ru>,\n Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>,\n linux-ide@vger.kernel.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,\n linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org,\n linux-pci@vger.kernel.org, linux-serial@vger.kernel.org,\n linux-fbdev@vger.kernel.org", "Subject": "[DO NOT MERGE v8 16/36] irqchip: Add SH7751 INTC driver", "Date": "Wed, 29 May 2024 17:01:02 +0900", "Message-Id": "\n <bb30527bca12b9dc51e3c7a89cc0a709e5df2bb7.1716965617.git.ysato@users.sourceforge.jp>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<cover.1716965617.git.ysato@users.sourceforge.jp>", "References": "<cover.1716965617.git.ysato@users.sourceforge.jp>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Renesas SH7751 Internal interrupt controller driver.\n\nSigned-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>\n---\n drivers/irqchip/Kconfig | 8 +\n drivers/irqchip/Makefile | 1 +\n drivers/irqchip/irq-renesas-sh7751.c | 282 +++++++++++++++++++++++++++\n 3 files changed, 291 insertions(+)\n create mode 100644 drivers/irqchip/irq-renesas-sh7751.c", "diff": "diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig\nindex 14464716bacb..f45a229963d4 100644\n--- a/drivers/irqchip/Kconfig\n+++ b/drivers/irqchip/Kconfig\n@@ -715,4 +715,12 @@ config SUNPLUS_SP7021_INTC\n \t chained controller, routing all interrupt source in P-Chip to\n \t the primary controller on C-Chip.\n \n+config RENESAS_SH7751_INTC\n+\tbool \"Renesas SH7751 Interrupt Controller\"\n+\tdepends on SH_DEVICE_TREE || COMPILE_TEST\n+\tselect IRQ_DOMAIN_HIERARCHY\n+\thelp\n+\t Support for the Renesas SH7751 On-chip interrupt controller.\n+\t And external interrupt encoder for some targets.\n+\n endmenu\ndiff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile\nindex d9dc3d99aaa8..7bde45f05a1e 100644\n--- a/drivers/irqchip/Makefile\n+++ b/drivers/irqchip/Makefile\n@@ -124,3 +124,4 @@ obj-$(CONFIG_IRQ_IDT3243X)\t\t+= irq-idt3243x.o\n obj-$(CONFIG_APPLE_AIC)\t\t\t+= irq-apple-aic.o\n obj-$(CONFIG_MCHP_EIC)\t\t\t+= irq-mchp-eic.o\n obj-$(CONFIG_SUNPLUS_SP7021_INTC)\t+= irq-sp7021-intc.o\n+obj-$(CONFIG_RENESAS_SH7751_INTC)\t+= irq-renesas-sh7751.o\ndiff --git a/drivers/irqchip/irq-renesas-sh7751.c b/drivers/irqchip/irq-renesas-sh7751.c\nnew file mode 100644\nindex 000000000000..91d6dc3ed04c\n--- /dev/null\n+++ b/drivers/irqchip/irq-renesas-sh7751.c\n@@ -0,0 +1,282 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Renesas SH7751 interrupt controller driver\n+ *\n+ * Copyright 2023 Yoshinori Sato <ysato@users.sourceforge.jp>\n+ */\n+\n+#include <linux/irq.h>\n+#include <linux/irqchip.h>\n+#include <linux/of_address.h>\n+#include <linux/of_irq.h>\n+#include <linux/of.h>\n+#include <linux/io.h>\n+#include <dt-bindings/interrupt-controller/renesas,sh7751-intc.h>\n+\n+struct ipr {\n+\tu16 off;\n+\tu16 idx;\n+};\n+\n+struct sh7751_intc_priv {\n+\tconst struct ipr *iprmap;\n+\tvoid __iomem *base;\n+\tvoid __iomem *intpri00;\n+\tbool\t irlm;\n+};\n+\n+enum {\n+\tR_ICR = 0x00,\n+\tR_IPR = 0x04,\n+\tR_INTPRI00 = 0x00,\n+\tR_INTREQ00 = 0x20,\n+\tR_INTMSK00 = 0x40,\n+\tR_INTMSKCLR00 = 0x60,\n+};\n+\n+#define ICR_IRLM BIT(7)\n+\n+/*\n+ * SH7751 IRQ mapping\n+ * IRQ16 - 63: Group0 - IPRA to IPRD\n+ * IRQ16 - 31: external IRL input (ICR.IRLM is 0)\n+ * IRQ80 - 92: Group1 - INTPRI00\n+ */\n+#define IRQ_START\t16\n+#define MAX_IRL\t\t(IRQ_START + NR_IRL)\n+#define GRP0_IRQ_END\t63\n+#define GRP1_IRQ_START\t80\n+#define IRQ_END\t\t92\n+\n+#define NR_IPRMAP0\t(GRP0_IRQ_END - IRQ_START + 1)\n+#define NR_IPRMAP1\t(IRQ_END - GRP1_IRQ_START)\n+#define IPR_PRI_MASK\t0x000f\n+\n+#define IPRA\t\t\t0\n+#define IPRB\t\t\t4\n+#define IPRC\t\t\t8\n+#define IPRD\t\t\t12\n+#define INTPRI00\t\t256\n+#define IPR_B12\t\t\t12\n+#define IPR_B8\t\t\t8\n+#define IPR_B4\t\t\t4\n+#define IPR_B0\t\t\t0\n+\n+/* SH7751 EVT to IPR mapping table */\n+static const struct ipr sh7751_iprmap[] = {\n+\t[evt2irq(0x240)] = {IPRD, IPR_B12},\t/* IRL0 (ICR.IRLM=1) */\n+\t[evt2irq(0x2a0)] = {IPRD, IPR_B8},\t/* IRL1 (ICR.IRLM=1) */\n+\t[evt2irq(0x300)] = {IPRD, IPR_B4},\t/* IRL2 (ICR.IRLM=1) */\n+\t[evt2irq(0x360)] = {IPRD, IPR_B0},\t/* IRL3 (ICR.IRLM=1) */\n+\t[evt2irq(0x400)] = {IPRA, IPR_B12},\t/* TMU0 */\n+\t[evt2irq(0x420)] = {IPRA, IPR_B8},\t/* TMU1 */\n+\t[evt2irq(0x440)] = {IPRA, IPR_B4},\t/* TMU2 TNUI */\n+\t[evt2irq(0x460)] = {IPRA, IPR_B4},\t/* TMU2 TICPI */\n+\t[evt2irq(0x480)] = {IPRA, IPR_B0},\t/* RTC ATI */\n+\t[evt2irq(0x4a0)] = {IPRA, IPR_B0},\t/* RTC PRI */\n+\t[evt2irq(0x4c0)] = {IPRA, IPR_B0},\t/* RTC CUI */\n+\t[evt2irq(0x4e0)] = {IPRB, IPR_B4},\t/* SCI ERI */\n+\t[evt2irq(0x500)] = {IPRB, IPR_B4},\t/* SCI RXI */\n+\t[evt2irq(0x520)] = {IPRB, IPR_B4},\t/* SCI TXI */\n+\t[evt2irq(0x540)] = {IPRB, IPR_B4},\t/* SCI TEI */\n+\t[evt2irq(0x560)] = {IPRB, IPR_B12},\t/* WDT */\n+\t[evt2irq(0x580)] = {IPRB, IPR_B8},\t/* REF RCMI */\n+\t[evt2irq(0x5a0)] = {IPRB, IPR_B4},\t/* REF ROVI */\n+\t[evt2irq(0x600)] = {IPRC, IPR_B0},\t/* H-UDI */\n+\t[evt2irq(0x620)] = {IPRC, IPR_B12},\t/* GPIO */\n+\t[evt2irq(0x640)] = {IPRC, IPR_B8},\t/* DMAC DMTE0 */\n+\t[evt2irq(0x660)] = {IPRC, IPR_B8},\t/* DMAC DMTE1 */\n+\t[evt2irq(0x680)] = {IPRC, IPR_B8},\t/* DMAC DMTE2 */\n+\t[evt2irq(0x6a0)] = {IPRC, IPR_B8},\t/* DMAC DMTE3 */\n+\t[evt2irq(0x6c0)] = {IPRC, IPR_B8},\t/* DMAC DMAE */\n+\t[evt2irq(0x700)] = {IPRC, IPR_B4},\t/* SCIF ERI */\n+\t[evt2irq(0x720)] = {IPRC, IPR_B4},\t/* SCIF RXI */\n+\t[evt2irq(0x740)] = {IPRC, IPR_B4},\t/* SCIF BRI */\n+\t[evt2irq(0x760)] = {IPRC, IPR_B4},\t/* SCIF TXI */\n+\t[evt2irq(0x780)] = {IPRC, IPR_B8},\t/* DMAC DMTE4 */\n+\t[evt2irq(0x7a0)] = {IPRC, IPR_B8},\t/* DMAC DMTE5 */\n+\t[evt2irq(0x7c0)] = {IPRC, IPR_B8},\t/* DMAC DMTE6 */\n+\t[evt2irq(0x7e0)] = {IPRC, IPR_B8},\t/* DMAC DMTE7 */\n+\t[evt2irq(0xa00)] = {INTPRI00, IPR_B0},\t/* PCIC PCISERR */\n+\t[evt2irq(0xa20)] = {INTPRI00, IPR_B4},\t/* PCIC PCIDMA3 */\n+\t[evt2irq(0xa40)] = {INTPRI00, IPR_B4},\t/* PCIC PCIDMA2 */\n+\t[evt2irq(0xa60)] = {INTPRI00, IPR_B4},\t/* PCIC PCIDMA1 */\n+\t[evt2irq(0xa80)] = {INTPRI00, IPR_B4},\t/* PCIC PCIDMA0 */\n+\t[evt2irq(0xaa0)] = {INTPRI00, IPR_B4},\t/* PCIC PCIPWON */\n+\t[evt2irq(0xac0)] = {INTPRI00, IPR_B4},\t/* PCIC PCIPWDWN */\n+\t[evt2irq(0xae0)] = {INTPRI00, IPR_B4},\t/* PCIC PCIERR */\n+\t[evt2irq(0xb00)] = {INTPRI00, IPR_B8},\t/* TMU3 */\n+\t[evt2irq(0xb80)] = {INTPRI00, IPR_B12},\t/* TMU4 */\n+};\n+\n+/*\n+ * IPR registers have 4bit priority x 4 entry (16bits)\n+ */\n+static void update_ipr(struct sh7751_intc_priv *priv, unsigned int irq, u16 pri)\n+{\n+\tconst struct ipr *ipr = NULL;\n+\tvoid __iomem *ipr_base;\n+\tunsigned int offset;\n+\tu16 mask;\n+\n+\tipr = priv->iprmap + irq;\n+\tif (irq < GRP1_IRQ_START) {\n+\t\t/* Group0 */\n+\t\tipr_base = priv->base + R_IPR;\n+\t\toffset = ipr->off;\n+\t} else {\n+\t\t/* Group1 */\n+\t\tipr_base = priv->intpri00;\n+\t\toffset = ipr->off - INTPRI00;\n+\t}\n+\tmask = ~(IPR_PRI_MASK << ipr->idx);\n+\tpri = (pri & IPR_PRI_MASK) << ipr->idx;\n+\tmask &= __raw_readw(ipr_base + offset);\n+\t__raw_writew(mask | pri, ipr_base + offset);\n+}\n+\n+static inline bool is_valid_irq(unsigned int irq)\n+{\n+\t/* IRQ16 - 63 */\n+\tif (irq >= IRQ_START && irq < IRQ_START + NR_IPRMAP0)\n+\t\treturn true;\n+\t/* IRQ80 - 92 */\n+\tif (irq >= GRP1_IRQ_START && irq <= IRQ_END)\n+\t\treturn true;\n+\treturn false;\n+}\n+\n+static inline struct sh7751_intc_priv *irq_data_to_priv(struct irq_data *data)\n+{\n+\treturn data->domain->host_data;\n+}\n+\n+/* Interrupt unmask priority is 1, mask priority is 0 */\n+#define PRI_ENABLE 1\n+#define PRI_DISABLE 0\n+static void endisable_irq(struct irq_data *data, bool enable)\n+{\n+\tstruct sh7751_intc_priv *priv;\n+\tunsigned int irq;\n+\n+\tpriv = irq_data_to_priv(data);\n+\n+\tirq = irqd_to_hwirq(data);\n+\tif (!is_valid_irq(irq)) {\n+\t\t/* IRQ out of range */\n+\t\tpr_warn_once(\"%s: IRQ %u is out of range\\n\", __FILE__, irq);\n+\t\treturn;\n+\t}\n+\n+\tif (irq <= MAX_IRL && !priv->irlm) {\n+\t\t/* IRL encoded external interrupt */\n+\t\t/* enable and disable from SR.IMASK */\n+\t\tupdate_sr_imask(irq - IRQ_START, enable);\n+\t} else {\n+\t\t/* Internal peripheral interrupt */\n+\t\t/* enable and disable from interrupt priority */\n+\t\tupdate_ipr(priv, irq, enable ? PRI_ENABLE : PRI_DISABLE);\n+\t}\n+}\n+\n+static void sh7751_mask_irq(struct irq_data *data)\n+{\n+\tendisable_irq(data, false);\n+}\n+\n+static void sh7751_unmask_irq(struct irq_data *data)\n+{\n+\tendisable_irq(data, true);\n+}\n+\n+static const struct irq_chip sh7751_irq_chip = {\n+\t.name\t\t= \"SH7751-INTC\",\n+\t.irq_unmask\t= sh7751_unmask_irq,\n+\t.irq_mask\t= sh7751_mask_irq,\n+};\n+\n+static int irq_sh7751_map(struct irq_domain *h, unsigned int virq,\n+\t\t\t irq_hw_number_t hw_irq_num)\n+{\n+\tirq_set_chip_and_handler(virq, &sh7751_irq_chip, handle_level_irq);\n+\tirq_get_irq_data(virq)->chip_data = h->host_data;\n+\tirq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOPROBE);\n+\treturn 0;\n+}\n+\n+static int irq_sh7751_xlate(struct irq_domain *d, struct device_node *ctrlr,\n+\t\t\t const u32 *intspec, unsigned int intsize,\n+\t\t\t unsigned long *out_hwirq, unsigned int *out_type)\n+{\n+\tif (WARN_ON(intsize < 1))\n+\t\treturn -EINVAL;\n+\t*out_hwirq = evt2irq(intspec[0]);\n+\t*out_type = IRQ_TYPE_NONE;\n+\treturn 0;\n+}\n+\n+static const struct irq_domain_ops irq_ops = {\n+\t.map = irq_sh7751_map,\n+\t.xlate = irq_sh7751_xlate,\n+};\n+\n+static int __init shintc_of_init(struct device_node *intc, struct device_node *parent,\n+\t\t\t\t const struct ipr *iprmap)\n+{\n+\tstruct sh7751_intc_priv *priv;\n+\tvoid __iomem *base, *base2;\n+\tstruct irq_domain *domain;\n+\tu16 icr;\n+\tint ret;\n+\n+\tpriv = kzalloc(sizeof(struct sh7751_intc_priv), GFP_KERNEL);\n+\tif (priv == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tbase = of_iomap(intc, 0);\n+\tbase2 = of_iomap(intc, 1);\n+\tif (!base || !base2) {\n+\t\tpr_err(\"%pOFP: Invalid register definition\\n\", intc);\n+\t\tret = -EINVAL;\n+\t\tgoto error;\n+\t}\n+\n+\tpriv->base = base;\n+\tpriv->intpri00 = base2;\n+\tpriv->iprmap = iprmap;\n+\n+\tif (of_property_read_bool(intc, \"renesas,irlm\")) {\n+\t\tpriv->irlm = true;\n+\t\ticr = __raw_readw(priv->base + R_ICR);\n+\t\ticr |= ICR_IRLM;\n+\t\t__raw_writew(icr, priv->base + R_ICR);\n+\t}\n+\n+\tdomain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, priv);\n+\tif (domain == NULL) {\n+\t\tpr_err(\"%pOFP: cannot initialize irq domain\\n\", intc);\n+\t\tret = -ENOMEM;\n+\t\tgoto error;\n+\t}\n+\n+\tirq_set_default_host(domain);\n+\tpr_info(\"%pOFP: SH7751 Interrupt controller (%s external IRQ)\",\n+\t\tintc, priv->irlm ? \"4 lines\" : \"15 level\");\n+\treturn 0;\n+\n+error:\n+\tif (base)\n+\t\tiounmap(base);\n+\tif (base2)\n+\t\tiounmap(base);\n+\tkfree(priv);\n+\treturn ret;\n+}\n+\n+static int __init sh7751_intc_of_init(struct device_node *intc,\n+\t\t\t\t struct device_node *parent)\n+{\n+\treturn shintc_of_init(intc, parent, sh7751_iprmap);\n+}\n+\n+IRQCHIP_DECLARE(sh_7751_intc, \"renesas,sh7751-intc\", sh7751_intc_of_init);\n", "prefixes": [ "DO", "NOT", "MERGE", "v8", "16/36" ] }