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GET /api/patches/1940998/?format=api
{ "id": 1940998, "url": "http://patchwork.ozlabs.org/api/patches/1940998/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/a3bed3c2940edc238afbc191d595a727944892f3.1716965617.git.ysato@users.sourceforge.jp/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<a3bed3c2940edc238afbc191d595a727944892f3.1716965617.git.ysato@users.sourceforge.jp>", "list_archive_url": null, "date": "2024-05-29T08:01:00", "name": "[DO,NOT,MERGE,v8,14/36] clk: Compatible with narrow registers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3c64b1c059480d6f4719d777749e2920d272c154", "submitter": { "id": 7114, "url": "http://patchwork.ozlabs.org/api/people/7114/?format=api", "name": "Yoshinori Sato", "email": "ysato@users.sourceforge.jp" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/a3bed3c2940edc238afbc191d595a727944892f3.1716965617.git.ysato@users.sourceforge.jp/mbox/", "series": [ { "id": 408652, "url": "http://patchwork.ozlabs.org/api/series/408652/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=408652", "date": "2024-05-29T08:00:51", "name": "Device Tree support for SH7751 based board", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/408652/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1940998/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1940998/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-7968-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2604:1380:45d1:ec00::1; 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Wed, 29 May 2024 08:05:22 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 7802E175579;\n\tWed, 29 May 2024 08:01:57 +0000 (UTC)", "from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp\n [153.127.30.23])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 3E90F171E69;\n\tWed, 29 May 2024 08:01:55 +0000 (UTC)", "from SIOS1075.ysato.name (al128006.dynamic.ppp.asahi-net.or.jp\n [111.234.128.6])\n\tby sakura.ysato.name (Postfix) with ESMTPSA id 2BFAF1C0EED;\n\tWed, 29 May 2024 17:01:53 +0900 (JST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1716969717; cv=none;\n b=YnuAilvmLjfNQF3dPEaxm3hWm0/Ml4ZLwDH2BZhF5KDGqvU4iyoGfYFL4Yvz7/w9DCtapkrOBL1o1COCp+7GOBdjh88LXYbIKV/vHTngEBvgxrriicJcc69IxdGdUVLFYrgFYo4xh/9jfalXFVW8+baDD1ubDve7VRHoTqYA/jc=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1716969717; c=relaxed/simple;\n\tbh=8wuAJgyl9hbSD3Dvnc4iquvn20ExBICiZtptkO8WKeE=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:\n\t MIME-Version;\n b=CklCWu/n2gUAN6+cbEK0f0J5bsX4M2oyIVWKpbTtJR/zFSJb6IvYnxZZmWjhGI5Ibjm2ATOYwq+5N0IiDj7bvAy/Mr4z+PhrLjCPYjXbf/KjO4rj9ayzgcsoaljwwWnfpb+ZS3K/vUPRw8vYCecoeWx4NoQRYAXmUju/rR9lg48=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=none (p=none dis=none) header.from=users.sourceforge.jp;\n spf=fail smtp.mailfrom=users.sourceforge.jp;\n arc=none smtp.client-ip=153.127.30.23", "From": "Yoshinori Sato <ysato@users.sourceforge.jp>", "To": "linux-sh@vger.kernel.org", "Cc": "Yoshinori Sato <ysato@users.sourceforge.jp>,\n Damien Le Moal <dlemoal@kernel.org>, Niklas Cassel <cassel@kernel.org>,\n Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n Geert Uytterhoeven <geert+renesas@glider.be>,\n Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>,\n David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,\n Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,\n Maxime Ripard <mripard@kernel.org>, Thomas Zimmermann <tzimmermann@suse.de>,\n Thomas Gleixner <tglx@linutronix.de>, Bjorn Helgaas <bhelgaas@google.com>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kw@linux.com>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n Jiri Slaby <jirislaby@kernel.org>, Magnus Damm <magnus.damm@gmail.com>,\n Daniel Lezcano <daniel.lezcano@linaro.org>, Rich Felker <dalias@libc.org>,\n John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>,\n Lee Jones <lee@kernel.org>, Helge Deller <deller@gmx.de>,\n Heiko Stuebner <heiko.stuebner@cherry.de>,\n Neil Armstrong <neil.armstrong@linaro.org>,\n Chris Morgan <macromorgan@hotmail.com>, Sebastian Reichel <sre@kernel.org>,\n Linus Walleij <linus.walleij@linaro.org>, Arnd Bergmann <arnd@arndb.de>,\n Masahiro Yamada <masahiroy@kernel.org>, Baoquan He <bhe@redhat.com>,\n Andrew Morton <akpm@linux-foundation.org>,\n Guenter Roeck <linux@roeck-us.net>, Kefeng Wang <wangkefeng.wang@huawei.com>,\n Stephen Rothwell <sfr@canb.auug.org.au>,\n Azeem Shaikh <azeemshaikh38@gmail.com>, Guo Ren <guoren@kernel.org>,\n Max Filippov <jcmvbkbc@gmail.com>, Jernej Skrabec <jernej.skrabec@gmail.com>,\n Herve Codina <herve.codina@bootlin.com>,\n Andy Shevchenko <andriy.shevchenko@linux.intel.com>,\n Anup Patel <apatel@ventanamicro.com>, Jacky Huang <ychuang3@nuvoton.com>,\n Hugo Villeneuve <hvilleneuve@dimonoff.com>, Jonathan Corbet <corbet@lwn.net>,\n Wolfram Sang <wsa+renesas@sang-engineering.com>, =?utf-8?q?Uwe_Kleine-K?=\n\t=?utf-8?q?=C3=B6nig?= <u.kleine-koenig@pengutronix.de>,\n Christophe JAILLET <christophe.jaillet@wanadoo.fr>,\n Sam Ravnborg <sam@ravnborg.org>,\n Javier Martinez Canillas <javierm@redhat.com>,\n Sergey Shtylyov <s.shtylyov@omp.ru>,\n Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>,\n linux-ide@vger.kernel.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,\n linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org,\n linux-pci@vger.kernel.org, linux-serial@vger.kernel.org,\n linux-fbdev@vger.kernel.org", "Subject": "[DO NOT MERGE v8 14/36] clk: Compatible with narrow registers", "Date": "Wed, 29 May 2024 17:01:00 +0900", "Message-Id": "\n <a3bed3c2940edc238afbc191d595a727944892f3.1716965617.git.ysato@users.sourceforge.jp>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<cover.1716965617.git.ysato@users.sourceforge.jp>", "References": "<cover.1716965617.git.ysato@users.sourceforge.jp>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "divider and gate only support 32-bit registers.\nOlder hardware uses narrower registers, so I want to be able to handle\n8-bit and 16-bit wide registers.\n\nSeven clk_divider flags are used, and if I add flags for 8bit access and\n16bit access, 8bit will not be enough, so I expanded it to u16.\n\nSigned-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>\n---\n drivers/clk/clk-divider.c | 41 +++++++++++++++++++++---------\n drivers/clk/clk-gate.c | 49 ++++++++++++++++++++++++++++++++----\n include/linux/clk-provider.h | 20 ++++++++++++---\n 3 files changed, 89 insertions(+), 21 deletions(-)", "diff": "diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c\nindex a2c2b5203b0a..abafcbbb6578 100644\n--- a/drivers/clk/clk-divider.c\n+++ b/drivers/clk/clk-divider.c\n@@ -26,17 +26,34 @@\n * parent - fixed parent. No clk_set_parent support\n */\n \n-static inline u32 clk_div_readl(struct clk_divider *divider)\n-{\n+static inline u32 clk_div_read(struct clk_divider *divider)\n+{\n+\tif (divider->flags & CLK_DIVIDER_REG_8BIT)\n+\t\treturn readb(divider->reg);\n+\tif (divider->flags & CLK_DIVIDER_REG_16BIT) {\n+\t\tif (divider->flags & CLK_DIVIDER_BIG_ENDIAN) {\n+\t\t\treturn ioread16be(divider->reg);\n+\t\t} else {\n+\t\t\treturn readw(divider->reg);\n+\t\t}\n+\t}\n \tif (divider->flags & CLK_DIVIDER_BIG_ENDIAN)\n \t\treturn ioread32be(divider->reg);\n \n \treturn readl(divider->reg);\n }\n \n-static inline void clk_div_writel(struct clk_divider *divider, u32 val)\n+static inline void clk_div_write(struct clk_divider *divider, u32 val)\n {\n-\tif (divider->flags & CLK_DIVIDER_BIG_ENDIAN)\n+\tif (divider->flags & CLK_DIVIDER_REG_8BIT)\n+\t\twriteb(val, divider->reg);\n+\telse if (divider->flags & CLK_DIVIDER_REG_16BIT) {\n+\t\tif (divider->flags & CLK_DIVIDER_BIG_ENDIAN) {\n+\t\t\tiowrite16be(val, divider->reg);\n+\t\t} else {\n+\t\t\twritew(val, divider->reg);\n+\t\t}\n+\t} else if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)\n \t\tiowrite32be(val, divider->reg);\n \telse\n \t\twritel(val, divider->reg);\n@@ -152,7 +169,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,\n \tstruct clk_divider *divider = to_clk_divider(hw);\n \tunsigned int val;\n \n-\tval = clk_div_readl(divider) >> divider->shift;\n+\tval = clk_div_read(divider) >> divider->shift;\n \tval &= clk_div_mask(divider->width);\n \n \treturn divider_recalc_rate(hw, parent_rate, val, divider->table,\n@@ -434,7 +451,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,\n \tif (divider->flags & CLK_DIVIDER_READ_ONLY) {\n \t\tu32 val;\n \n-\t\tval = clk_div_readl(divider) >> divider->shift;\n+\t\tval = clk_div_read(divider) >> divider->shift;\n \t\tval &= clk_div_mask(divider->width);\n \n \t\treturn divider_ro_round_rate(hw, rate, prate, divider->table,\n@@ -455,7 +472,7 @@ static int clk_divider_determine_rate(struct clk_hw *hw,\n \tif (divider->flags & CLK_DIVIDER_READ_ONLY) {\n \t\tu32 val;\n \n-\t\tval = clk_div_readl(divider) >> divider->shift;\n+\t\tval = clk_div_read(divider) >> divider->shift;\n \t\tval &= clk_div_mask(divider->width);\n \n \t\treturn divider_ro_determine_rate(hw, req, divider->table,\n@@ -505,11 +522,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,\n \tif (divider->flags & CLK_DIVIDER_HIWORD_MASK) {\n \t\tval = clk_div_mask(divider->width) << (divider->shift + 16);\n \t} else {\n-\t\tval = clk_div_readl(divider);\n+\t\tval = clk_div_read(divider);\n \t\tval &= ~(clk_div_mask(divider->width) << divider->shift);\n \t}\n \tval |= (u32)value << divider->shift;\n-\tclk_div_writel(divider, val);\n+\tclk_div_write(divider, val);\n \n \tif (divider->lock)\n \t\tspin_unlock_irqrestore(divider->lock, flags);\n@@ -538,7 +555,7 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev,\n \t\tstruct device_node *np, const char *name,\n \t\tconst char *parent_name, const struct clk_hw *parent_hw,\n \t\tconst struct clk_parent_data *parent_data, unsigned long flags,\n-\t\tvoid __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,\n+\t\tvoid __iomem *reg, u8 shift, u8 width, u16 clk_divider_flags,\n \t\tconst struct clk_div_table *table, spinlock_t *lock)\n {\n \tstruct clk_divider *div;\n@@ -610,7 +627,7 @@ EXPORT_SYMBOL_GPL(__clk_hw_register_divider);\n struct clk *clk_register_divider_table(struct device *dev, const char *name,\n \t\tconst char *parent_name, unsigned long flags,\n \t\tvoid __iomem *reg, u8 shift, u8 width,\n-\t\tu8 clk_divider_flags, const struct clk_div_table *table,\n+\t\tu16 clk_divider_flags, const struct clk_div_table *table,\n \t\tspinlock_t *lock)\n {\n \tstruct clk_hw *hw;\n@@ -664,7 +681,7 @@ struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,\n \t\tstruct device_node *np, const char *name,\n \t\tconst char *parent_name, const struct clk_hw *parent_hw,\n \t\tconst struct clk_parent_data *parent_data, unsigned long flags,\n-\t\tvoid __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,\n+\t\tvoid __iomem *reg, u8 shift, u8 width, u16 clk_divider_flags,\n \t\tconst struct clk_div_table *table, spinlock_t *lock)\n {\n \tstruct clk_hw **ptr, *hw;\ndiff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c\nindex 68e585a02fd9..22425568809e 100644\n--- a/drivers/clk/clk-gate.c\n+++ b/drivers/clk/clk-gate.c\n@@ -24,16 +24,37 @@\n * parent - fixed parent. No clk_set_parent support\n */\n \n-static inline u32 clk_gate_readl(struct clk_gate *gate)\n+static inline u32 clk_gate_read(struct clk_gate *gate)\n {\n+\tif (gate->flags & CLK_GATE_REG_8BIT)\n+\t\treturn readb(gate->reg);\n+\tif (gate->flags & CLK_GATE_REG_16BIT) {\n+\t\tif (gate->flags & CLK_GATE_BIG_ENDIAN) {\n+\t\t\treturn ioread16be(gate->reg);\n+\t\t} else {\n+\t\t\treturn readw(gate->reg);\n+\t\t}\n+\t}\n \tif (gate->flags & CLK_GATE_BIG_ENDIAN)\n \t\treturn ioread32be(gate->reg);\n \n \treturn readl(gate->reg);\n }\n \n-static inline void clk_gate_writel(struct clk_gate *gate, u32 val)\n+static inline void clk_gate_write(struct clk_gate *gate, u32 val)\n {\n+\tif (gate->flags & CLK_GATE_REG_8BIT) {\n+\t\twriteb(val, gate->reg);\n+\t\treturn;\n+\t}\n+\tif (gate->flags & CLK_GATE_REG_16BIT) {\n+\t\tif (gate->flags & CLK_GATE_BIG_ENDIAN) {\n+\t\t\tiowrite16be(val, gate->reg);\n+\t\t} else {\n+\t\t\twritew(val, gate->reg);\n+\t\t}\n+\t\treturn;\n+\t}\n \tif (gate->flags & CLK_GATE_BIG_ENDIAN)\n \t\tiowrite32be(val, gate->reg);\n \telse\n@@ -72,7 +93,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)\n \t\tif (set)\n \t\t\treg |= BIT(gate->bit_idx);\n \t} else {\n-\t\treg = clk_gate_readl(gate);\n+\t\treg = clk_gate_read(gate);\n \n \t\tif (set)\n \t\t\treg |= BIT(gate->bit_idx);\n@@ -80,7 +101,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)\n \t\t\treg &= ~BIT(gate->bit_idx);\n \t}\n \n-\tclk_gate_writel(gate, reg);\n+\tclk_gate_write(gate, reg);\n \n \tif (gate->lock)\n \t\tspin_unlock_irqrestore(gate->lock, flags);\n@@ -105,7 +126,7 @@ int clk_gate_is_enabled(struct clk_hw *hw)\n \tu32 reg;\n \tstruct clk_gate *gate = to_clk_gate(hw);\n \n-\treg = clk_gate_readl(gate);\n+\treg = clk_gate_read(gate);\n \n \t/* if a set bit disables this clk, flip it before masking */\n \tif (gate->flags & CLK_GATE_SET_TO_DISABLE)\n@@ -137,12 +158,30 @@ struct clk_hw *__clk_hw_register_gate(struct device *dev,\n \tstruct clk_init_data init = {};\n \tint ret = -EINVAL;\n \n+\t/* validate register size option and bit_idx */\n \tif (clk_gate_flags & CLK_GATE_HIWORD_MASK) {\n \t\tif (bit_idx > 15) {\n \t\t\tpr_err(\"gate bit exceeds LOWORD field\\n\");\n \t\t\treturn ERR_PTR(-EINVAL);\n \t\t}\n \t}\n+\tif (clk_gate_flags & CLK_GATE_REG_16BIT) {\n+\t\tif (bit_idx > 15) {\n+\t\t\tpr_err(\"gate bit exceeds 16 bits\\n\");\n+\t\t\treturn ERR_PTR(-EINVAL);\n+\t\t}\n+\t}\n+\tif (clk_gate_flags & CLK_GATE_REG_8BIT) {\n+\t\tif (bit_idx > 7) {\n+\t\t\tpr_err(\"gate bit exceeds 8 bits\\n\");\n+\t\t\treturn ERR_PTR(-EINVAL);\n+\t\t}\n+\t}\n+\tif ((clk_gate_flags & CLK_GATE_HIWORD_MASK) &&\n+\t (clk_gate_flags & (CLK_GATE_REG_8BIT | CLK_GATE_REG_16BIT))) {\n+\t\tpr_err(\"HIWORD_MASK required 32-bit register\\n\");\n+\t\treturn ERR_PTR(-EINVAL);\n+\t}\n \n \t/* allocate the gate */\n \tgate = kzalloc(sizeof(*gate), GFP_KERNEL);\ndiff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h\nindex 4a537260f655..25f61bd5b952 100644\n--- a/include/linux/clk-provider.h\n+++ b/include/linux/clk-provider.h\n@@ -508,6 +508,10 @@ void of_fixed_clk_setup(struct device_node *np);\n * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for\n *\tthe gate register. Setting this flag makes the register accesses big\n *\tendian.\n+ * CLK_GATE_REG_8BIT - by default 32bit register accesses are used for\n+ *\tthe gate register. Setting this flag makes the register accesses 8bit.\n+ * CLK_GATE_REG_16BIT - by default 32bit register accesses are used for\n+ *\tthe gate register. Setting this flag makes the register accesses 16bit.\n */\n struct clk_gate {\n \tstruct clk_hw hw;\n@@ -522,6 +526,8 @@ struct clk_gate {\n #define CLK_GATE_SET_TO_DISABLE\t\tBIT(0)\n #define CLK_GATE_HIWORD_MASK\t\tBIT(1)\n #define CLK_GATE_BIG_ENDIAN\t\tBIT(2)\n+#define CLK_GATE_REG_8BIT\t\tBIT(3)\n+#define CLK_GATE_REG_16BIT\t\tBIT(4)\n \n extern const struct clk_ops clk_gate_ops;\n struct clk_hw *__clk_hw_register_gate(struct device *dev,\n@@ -675,13 +681,17 @@ struct clk_div_table {\n * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used\n *\tfor the divider register. Setting this flag makes the register accesses\n *\tbig endian.\n+ * CLK_DIVIDER_REG_8BIT - by default 32bit register accesses are used for\n+ *\tthe gate register. Setting this flag makes the register accesses 8bit.\n+ * CLK_DIVIDER_REG_16BIT - by default 32bit register accesses are used for\n+ *\tthe gate register. Setting this flag makes the register accesses 16bit.\n */\n struct clk_divider {\n \tstruct clk_hw\thw;\n \tvoid __iomem\t*reg;\n \tu8\t\tshift;\n \tu8\t\twidth;\n-\tu8\t\tflags;\n+\tu16\t\tflags;\n \tconst struct clk_div_table\t*table;\n \tspinlock_t\t*lock;\n };\n@@ -697,6 +707,8 @@ struct clk_divider {\n #define CLK_DIVIDER_READ_ONLY\t\tBIT(5)\n #define CLK_DIVIDER_MAX_AT_ZERO\t\tBIT(6)\n #define CLK_DIVIDER_BIG_ENDIAN\t\tBIT(7)\n+#define CLK_DIVIDER_REG_8BIT\t\tBIT(8)\n+#define CLK_DIVIDER_REG_16BIT\t\tBIT(9)\n \n extern const struct clk_ops clk_divider_ops;\n extern const struct clk_ops clk_divider_ro_ops;\n@@ -726,18 +738,18 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev,\n \t\tstruct device_node *np, const char *name,\n \t\tconst char *parent_name, const struct clk_hw *parent_hw,\n \t\tconst struct clk_parent_data *parent_data, unsigned long flags,\n-\t\tvoid __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,\n+\t\tvoid __iomem *reg, u8 shift, u8 width, u16 clk_divider_flags,\n \t\tconst struct clk_div_table *table, spinlock_t *lock);\n struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,\n \t\tstruct device_node *np, const char *name,\n \t\tconst char *parent_name, const struct clk_hw *parent_hw,\n \t\tconst struct clk_parent_data *parent_data, unsigned long flags,\n-\t\tvoid __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,\n+\t\tvoid __iomem *reg, u8 shift, u8 width, u16 clk_divider_flags,\n \t\tconst struct clk_div_table *table, spinlock_t *lock);\n struct clk *clk_register_divider_table(struct device *dev, const char *name,\n \t\tconst char *parent_name, unsigned long flags,\n \t\tvoid __iomem *reg, u8 shift, u8 width,\n-\t\tu8 clk_divider_flags, const struct clk_div_table *table,\n+\t\tu16 clk_divider_flags, const struct clk_div_table *table,\n \t\tspinlock_t *lock);\n /**\n * clk_register_divider - register a divider clock with the clock framework\n", "prefixes": [ "DO", "NOT", "MERGE", "v8", "14/36" ] }