Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1940990/?format=api
{ "id": 1940990, "url": "http://patchwork.ozlabs.org/api/patches/1940990/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/1f1420a50fbdee5f5e07a3345a6dd6b921c78969.1716965617.git.ysato@users.sourceforge.jp/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1f1420a50fbdee5f5e07a3345a6dd6b921c78969.1716965617.git.ysato@users.sourceforge.jp>", "list_archive_url": null, "date": "2024-05-29T08:00:57", "name": "[DO,NOT,MERGE,v8,11/36] pci: pci-sh7751: Add SH7751 PCI driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7e37138e3edb4f72cb4fca8258f2372da59f10ce", "submitter": { "id": 7114, "url": "http://patchwork.ozlabs.org/api/people/7114/?format=api", "name": "Yoshinori Sato", "email": "ysato@users.sourceforge.jp" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/1f1420a50fbdee5f5e07a3345a6dd6b921c78969.1716965617.git.ysato@users.sourceforge.jp/mbox/", "series": [ { "id": 408652, "url": "http://patchwork.ozlabs.org/api/series/408652/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=408652", "date": "2024-05-29T08:00:51", "name": "Device Tree support for SH7751 based board", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/408652/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1940990/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1940990/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-7965-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=147.75.199.223; helo=ny.mirrors.kernel.org;\n envelope-from=linux-pci+bounces-7965-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=153.127.30.23", "smtp.subspace.kernel.org;\n dmarc=none (p=none dis=none) header.from=users.sourceforge.jp", "smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=users.sourceforge.jp" ], "Received": [ "from ny.mirrors.kernel.org (ny.mirrors.kernel.org [147.75.199.223])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4Vq2364fvRz20Pc\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 29 May 2024 18:04:18 +1000 (AEST)", "from smtp.subspace.kernel.org (wormhole.subspace.kernel.org\n [52.25.139.140])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ny.mirrors.kernel.org (Postfix) with ESMTPS id B1F051C247DD\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 29 May 2024 08:04:16 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 0544816F0D0;\n\tWed, 29 May 2024 08:01:52 +0000 (UTC)", "from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp\n [153.127.30.23])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id B0561168C19;\n\tWed, 29 May 2024 08:01:49 +0000 (UTC)", "from SIOS1075.ysato.name (al128006.dynamic.ppp.asahi-net.or.jp\n [111.234.128.6])\n\tby sakura.ysato.name (Postfix) with ESMTPSA id B37D71C09E7;\n\tWed, 29 May 2024 17:01:47 +0900 (JST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1716969711; cv=none;\n b=o26+Xv14F/jIhcSiD0i3ulzYQG7ONgc/LD6rGSF4f2Nskl1IkiuZcL7AALciq+1uwhUz/ZLTZR6XcXacp9+eInauLevRtgwWWPXj8+fsZbDLiwaLV6esMiRcffAWYIC51Lcs7Q5k6qQMr45XPGm3jvNgYDiQgqW/ZSfbBX/wyYQ=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1716969711; c=relaxed/simple;\n\tbh=sLbTYAMzZyQ8pRDqLCryisybva0I4q0vAgBJlm0LX8w=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:\n\t MIME-Version;\n b=DSR/i5V5ANLVlT+8HO1Vci50nP8tb/1ZlEJYkLylt54k8A/8M0TuQGGKJwncmhB20WTKEnz2tzvTjZ5gULWNK2MCXS5GYD5q4DymVM5OQ4rAgdBG+FiPNMUYa9K4SJZ7zGrfMEDVTBZonkrtsWE7UcJsbEdukbbqcGoJa+tGZKk=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=none (p=none dis=none) header.from=users.sourceforge.jp;\n spf=fail smtp.mailfrom=users.sourceforge.jp;\n arc=none smtp.client-ip=153.127.30.23", "From": "Yoshinori Sato <ysato@users.sourceforge.jp>", "To": "linux-sh@vger.kernel.org", "Cc": "Yoshinori Sato <ysato@users.sourceforge.jp>,\n Damien Le Moal <dlemoal@kernel.org>, Niklas Cassel <cassel@kernel.org>,\n Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n Geert Uytterhoeven <geert+renesas@glider.be>,\n Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>,\n David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,\n Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,\n Maxime Ripard <mripard@kernel.org>, Thomas Zimmermann <tzimmermann@suse.de>,\n Thomas Gleixner <tglx@linutronix.de>, Bjorn Helgaas <bhelgaas@google.com>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kw@linux.com>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n Jiri Slaby <jirislaby@kernel.org>, Magnus Damm <magnus.damm@gmail.com>,\n Daniel Lezcano <daniel.lezcano@linaro.org>, Rich Felker <dalias@libc.org>,\n John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>,\n Lee Jones <lee@kernel.org>, Helge Deller <deller@gmx.de>,\n Heiko Stuebner <heiko.stuebner@cherry.de>,\n Neil Armstrong <neil.armstrong@linaro.org>,\n Chris Morgan <macromorgan@hotmail.com>, Sebastian Reichel <sre@kernel.org>,\n Linus Walleij <linus.walleij@linaro.org>, Arnd Bergmann <arnd@arndb.de>,\n Masahiro Yamada <masahiroy@kernel.org>, Baoquan He <bhe@redhat.com>,\n Andrew Morton <akpm@linux-foundation.org>,\n Guenter Roeck <linux@roeck-us.net>, Kefeng Wang <wangkefeng.wang@huawei.com>,\n Stephen Rothwell <sfr@canb.auug.org.au>,\n Azeem Shaikh <azeemshaikh38@gmail.com>, Guo Ren <guoren@kernel.org>,\n Max Filippov <jcmvbkbc@gmail.com>, Jernej Skrabec <jernej.skrabec@gmail.com>,\n Herve Codina <herve.codina@bootlin.com>,\n Andy Shevchenko <andriy.shevchenko@linux.intel.com>,\n Anup Patel <apatel@ventanamicro.com>, Jacky Huang <ychuang3@nuvoton.com>,\n Hugo Villeneuve <hvilleneuve@dimonoff.com>, Jonathan Corbet <corbet@lwn.net>,\n Wolfram Sang <wsa+renesas@sang-engineering.com>, =?utf-8?q?Uwe_Kleine-K?=\n\t=?utf-8?q?=C3=B6nig?= <u.kleine-koenig@pengutronix.de>,\n Christophe JAILLET <christophe.jaillet@wanadoo.fr>,\n Sam Ravnborg <sam@ravnborg.org>,\n Javier Martinez Canillas <javierm@redhat.com>,\n Sergey Shtylyov <s.shtylyov@omp.ru>,\n Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>,\n linux-ide@vger.kernel.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,\n linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org,\n linux-pci@vger.kernel.org, linux-serial@vger.kernel.org,\n linux-fbdev@vger.kernel.org", "Subject": "[DO NOT MERGE v8 11/36] pci: pci-sh7751: Add SH7751 PCI driver", "Date": "Wed, 29 May 2024 17:00:57 +0900", "Message-Id": "\n <1f1420a50fbdee5f5e07a3345a6dd6b921c78969.1716965617.git.ysato@users.sourceforge.jp>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<cover.1716965617.git.ysato@users.sourceforge.jp>", "References": "<cover.1716965617.git.ysato@users.sourceforge.jp>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Renesas SH7751 CPU Internal PCI Controller driver.\n\nSigned-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>\n---\n drivers/pci/controller/Kconfig | 9 +\n drivers/pci/controller/Makefile | 1 +\n drivers/pci/controller/pci-sh7751.c | 335 ++++++++++++++++++++++++++++\n 3 files changed, 345 insertions(+)\n create mode 100644 drivers/pci/controller/pci-sh7751.c", "diff": "diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig\nindex e534c02ee34f..a2fd917a2e03 100644\n--- a/drivers/pci/controller/Kconfig\n+++ b/drivers/pci/controller/Kconfig\n@@ -353,6 +353,15 @@ config PCIE_XILINX_CPM\n \t Say 'Y' here if you want kernel support for the\n \t Xilinx Versal CPM host bridge.\n \n+config PCI_SH7751\n+\tbool \"Renesas SH7751 PCI controller\"\n+\tdepends on OF\n+\tdepends on CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R || COMPILE_TEST\n+\tselect PCI_HOST_COMMON\n+\thelp\n+\t Say 'Y' here if you want kernel to support the Renesas SH7751 PCI\n+\t Host Bridge driver.\n+\n source \"drivers/pci/controller/cadence/Kconfig\"\n source \"drivers/pci/controller/dwc/Kconfig\"\n source \"drivers/pci/controller/mobiveil/Kconfig\"\ndiff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile\nindex f2b19e6174af..aa97e5d74e58 100644\n--- a/drivers/pci/controller/Makefile\n+++ b/drivers/pci/controller/Makefile\n@@ -40,6 +40,7 @@ obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o\n obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o\n obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o\n obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o\n+obj-$(CONFIG_PCI_SH7751) += pci-sh7751.o\n \n # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW\n obj-y\t\t\t\t+= dwc/\ndiff --git a/drivers/pci/controller/pci-sh7751.c b/drivers/pci/controller/pci-sh7751.c\nnew file mode 100644\nindex 000000000000..73ccc14800f7\n--- /dev/null\n+++ b/drivers/pci/controller/pci-sh7751.c\n@@ -0,0 +1,335 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * SH7751 PCI driver\n+ * Copyright (C) 2023 Yoshinori Sato\n+ */\n+\n+#include <linux/dma-direct.h>\n+#include <linux/io.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of_address.h>\n+#include <linux/of_pci.h>\n+#include <linux/of_platform.h>\n+#include <linux/pci.h>\n+#include <linux/pci-ecam.h>\n+#include <linux/platform_device.h>\n+#include <asm/addrspace.h>\n+\n+/* PCICR and PCICLKCR write enable magic key */\n+#define PCIC_WE_KEY\t\t(0xa5 << 24)\n+\n+/* PCIC registers */\n+/* 0x0000 - 0x00ff mapped to PCI device configuration space */\n+#define PCIC_PCICR\t\t0x100\t/* PCI Control Register */\n+#define PCIC_PCICR_TRSB\t\tBIT(9)\t/* Target Read Single */\n+#define PCIC_PCICR_BSWP\t\tBIT(8)\t/* Target Byte Swap */\n+#define PCIC_PCICR_PLUP\t\tBIT(7)\t/* Enable PCI Pullup */\n+#define PCIC_PCICR_ARBM\t\tBIT(6)\t/* PCI Arbitration Mode */\n+#define PCIC_PCICR_MD10\t\tBIT(5)\t/* MD10 status */\n+#define PCIC_PCICR_MD9\t\tBIT(4)\t/* MD9 status */\n+#define PCIC_PCICR_SERR\t\tBIT(3)\t/* SERR output assert */\n+#define PCIC_PCICR_INTA\t\tBIT(2)\t/* INTA output assert */\n+#define PCIC_PCICR_PRST\t\tBIT(1)\t/* PCI Reset Assert */\n+#define PCIC_PCICR_CFIN\t\tBIT(0)\t/* Central Fun. Init Done */\n+\n+#define PCIC_PCILSR0\t\t0x104\t/* PCI Local Space Register0 */\n+#define PCIC_PCILSR1\t\t0x108\t/* PCI Local Space Register1 */\n+#define PCIC_PCILAR0\t\t0x10c\t/* PCI Local Addr Register1 */\n+#define PCIC_PCILAR1\t\t0x110\t/* PCI Local Addr Register1 */\n+#define PCIC_PCIINT\t\t0x114\t/* PCI Interrupt Register */\n+#define PCIC_PCIINTM\t\t0x118\t/* PCI Interrupt Mask */\n+#define PCIC_PCIALR\t\t0x11c\t/* Error Address Register */\n+#define PCIC_PCICLR\t\t0x120\t/* Error Command/Data */\n+#define PCIC_PCIAINT\t\t0x130\t/* Arbiter Interrupt Register */\n+#define PCIC_PCIAINTM\t\t0x134\t/* Arbiter Int. Mask Register */\n+#define PCIC_PCIBMLR\t\t0x138\t/* Error Bus Master Register */\n+#define PCIC_PCIDMABT\t\t0x140\t/* DMA Transfer Arb. Register */\n+#define PCIC_PCIPAR\t\t0x1c0\t/* PIO Address Register */\n+#define PCIC_PCIMBR\t\t0x1c4\t/* Memory Base Address */\n+#define PCIC_PCIIOBR\t\t0x1c8\t/* I/O Base Address Register */\n+\n+#define PCIC_PCIPINT\t\t0x1cc\t/* Power Mgmnt Int. Register */\n+#define PCIC_PCIPINT_D3\t\tBIT(1)\t/* D3 Pwr Mgmt. Interrupt */\n+#define PCIC_PCIPINT_D0\t\tBIT(0)\t/* D0 Pwr Mgmt. Interrupt */\n+\n+#define PCIC_PCIPINTM\t\t0x1d0\t/* Power Mgmnt Mask Register */\n+#define PCIC_PCICLKR\t\t0x1d4\t/* Clock Ctrl. Register */\n+#define PCIC_PCIBCR1\t\t0x1e0\t/* Memory BCR1 Register */\n+#define PCIC_PCIBCR2\t\t0x1e4\t/* Memory BCR2 Register */\n+#define PCIC_PCIWCR1\t\t0x1e8\t/* Wait Control 1 Register */\n+#define PCIC_PCIWCR2\t\t0x1ec\t/* Wait Control 2 Register */\n+#define PCIC_PCIWCR3\t\t0x1f0\t/* Wait Control 3 Register */\n+#define PCIC_PCIMCR\t\t0x1f4\t/* Memory Control Register */\n+#define PCIC_PCIBCR3\t\t0x1f8\t/* Memory BCR3 Register */\n+#define PCIC_PCIPDR\t\t0x220\t/* Port IO Data Register */\n+\n+/* PCI IDs */\n+/*\n+ * Hitachi is the company that led to Renesas.\n+ * The SH7751 was designed by Hitachi, so it has a Hitachi ID.\n+ */\n+#define PCI_VENDOR_ID_HITACHI\t0x1054\n+#define PCI_DEVICE_ID_SH7751\t0x3505\n+#define PCI_DEVICE_ID_SH7751R\t0x350e\n+\n+/* BSC registers */\n+/* Copy BSC setting to PCI BSC */\n+#define BSC_BCR1\t\t0x0000\n+#define BSC_BCR1_SLAVE\t\tBIT(30)\n+#define BSC_BCR1_BRQEN\t\tBIT(19)\n+#define BSC_BCR2\t\t0x0004\n+#define BSC_BCR3\t\t0x0050\n+#define BSC_WCR1\t\t0x0008\n+#define BSC_WCR2\t\t0x000c\n+#define BSC_WCR3\t\t0x0010\n+#define BSC_MCR\t\t\t0x0014\n+#define BSC_MCR_MRSET\t\tBIT(30)\n+#define BSC_MCR_RFSH\t\tBIT(2)\n+\n+/*\n+ * We need to avoid collisions with `mirrored' VGA ports\n+ * and other strange ISA hardware, so we always want the\n+ * addresses to be allocated in the 0x000-0x0ff region\n+ * modulo 0x400.\n+ */\n+#define IO_REGION_BASE 0x1000\n+resource_size_t pcibios_align_resource(void *data, const struct resource *res,\n+\t\t\t\tresource_size_t size, resource_size_t align)\n+{\n+\tresource_size_t start = res->start;\n+\n+\tif (res->flags & IORESOURCE_IO) {\n+\t\tif (start < PCIBIOS_MIN_IO + IO_REGION_BASE)\n+\t\t\tstart = PCIBIOS_MIN_IO + IO_REGION_BASE;\n+\n+\t\t/*\n+\t\t * Put everything into 0x00-0xff region modulo 0x400.\n+\t\t */\n+\t\tif (start & 0x300)\n+\t\t\tstart = (start + 0x3ff) & ~0x3ff;\n+\t}\n+\n+\treturn start;\n+}\n+\n+static int setup_pci_bsc(struct device *dev, void __iomem *pcic,\n+\t\t\t void __iomem *bsc, unsigned int area, bool bcr3)\n+{\n+\tu32 word;\n+\n+\tword = __raw_readl(bsc + BSC_BCR1);\n+\t/* check BCR for SDRAM in area */\n+\tif (((word >> area) & 1) == 0) {\n+\t\tdev_err(dev, \"Area %u is not configured for SDRAM. BCR1=0x%x\\n\",\n+\t\t\tarea, word);\n+\t\treturn -EINVAL;\n+\t}\n+\tword |= BSC_BCR1_SLAVE;\t\t/* PCIC BSC is slave only */\n+\twritel(word, pcic + PCIC_PCIBCR1);\n+\n+\tword = __raw_readw(bsc + BSC_BCR2);\n+\t/* check BCR2 for 32bit SDRAM interface*/\n+\tif (((word >> (area << 1)) & 0x3) != 0x3) {\n+\t\tdev_err(dev, \"Area %u is not 32 bit SDRAM. BCR2=0x%x\\n\",\n+\t\t\tarea, word);\n+\t\treturn -EINVAL;\n+\t}\n+\twritel(word, pcic + PCIC_PCIBCR2);\n+\n+\tif (bcr3) {\n+\t\t/* BCR3 have only SH7751R */\n+\t\tword = __raw_readw(bsc + BSC_BCR3);\n+\t\twritel(word, pcic + PCIC_PCIBCR3);\n+\t}\n+\n+\t/* configure the wait control registers */\n+\tword = __raw_readl(bsc + BSC_WCR1);\n+\twritel(word, pcic + PCIC_PCIWCR1);\n+\tword = __raw_readl(bsc + BSC_WCR2);\n+\twritel(word, pcic + PCIC_PCIWCR2);\n+\tword = __raw_readl(bsc + BSC_WCR3);\n+\twritel(word, pcic + PCIC_PCIWCR3);\n+\tword = __raw_readl(bsc + BSC_MCR);\n+\t/* Clear MRSET and RFSH bit */\n+\tword &= ~(BSC_MCR_MRSET | BSC_MCR_RFSH);\n+\twritel(word, pcic + PCIC_PCIMCR);\n+\n+\treturn 0;\n+}\n+\n+#define NUM_AREA 7\n+static int set_pci_ranges(struct device *dev,\n+\t\t\t void __iomem *pcic, void __iomem *bsc, bool bcr3)\n+{\n+\tstruct resource_entry *dma, *tmp;\n+\tstruct pci_host_bridge *bridge;\n+\tu32 bsc_done[NUM_AREA];\n+\tunsigned int la;\n+\n+\tbridge = dev_get_drvdata(dev);\n+\twritel(0, pcic + PCIC_PCILAR0);\n+\twritel(0, pcic + PCIC_PCILAR1);\n+\tla = 0;\n+\tmemset(&bsc_done, 0, sizeof(bsc_done));\n+\tresource_list_for_each_entry_safe(dma, tmp, &bridge->dma_ranges) {\n+\t\tstruct resource *res = dma->res;\n+\t\tunsigned int area;\n+\t\tu32 word;\n+\n+\t\tswitch (resource_type(res)) {\n+\t\tcase IORESOURCE_REG:\n+\t\t\tword = res->start | 1;\n+\t\t\twritel(word, pcic + PCI_BASE_ADDRESS_0);\n+\t\t\tword = readl(pcic + PCI_COMMAND);\n+\t\t\tword |= PCI_COMMAND_IO;\n+\t\t\twritel(word, pcic + PCI_COMMAND);\n+\t\t\tbreak;\n+\t\tcase IORESOURCE_MEM:\n+\t\t\tif (la > 4) {\n+\t\t\t\tdev_err(dev, \"Invalid range definition.\\n\");\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t\tarea = (res->start >> 26) & 0x07;\n+\t\t\tif (area >= NUM_AREA) {\n+\t\t\t\t/* Area 7 is reserved. */\n+\t\t\t\tdev_info(dev, \"Invalid local address 0x%08x. Ignore it.\\n\",\n+\t\t\t\t\t res->start);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\twritel(res->start, pcic + PCI_BASE_ADDRESS_1 + la);\n+\t\t\tword = res->end - res->start;\n+\t\t\t/* if dummy entry, skip BSC setup */\n+\t\t\tif (word <= 4)\n+\t\t\t\tbreak;\n+\t\t\t/* BAR1 is local area 0, BAR2 is local area 1 */\n+\t\t\twritel(word, pcic + PCIC_PCILSR0 + la);\n+\t\t\tword = P2SEGADDR(res->start);\n+\t\t\twritel(word, pcic + PCIC_PCILAR0 + la);\n+\t\t\tla += 4;\n+\t\t\tif (!bsc_done[area]) {\n+\t\t\t\t/* check BCR for SDRAM in specified area. And setup PCI BSC. */\n+\t\t\t\tif (setup_pci_bsc(dev, pcic, bsc, area, bcr3))\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\tbsc_done[area] = 1;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n+static int sh7751_pci_probe(struct platform_device *pdev)\n+{\n+\tstruct resource *res, *bscres;\n+\tvoid __iomem *pcic;\n+\tvoid __iomem *bsc;\n+\tu16 vid, did;\n+\tu32 word;\n+\tint ret;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tif (IS_ERR(res))\n+\t\treturn PTR_ERR(res);\n+\tpcic = ioremap(res->start, res->end - res->start + 1);\n+\n+\tbscres = platform_get_resource(pdev, IORESOURCE_MEM, 1);\n+\tbsc = devm_ioremap_resource(&pdev->dev, bscres);\n+\tif (IS_ERR(bsc))\n+\t\treturn PTR_ERR(bsc);\n+\n+\t/* check for SH7751/SH7751R hardware */\n+\tword = readl(pcic + PCI_VENDOR_ID);\n+\tvid = word & 0xffff;\n+\tdid = word >> 16;\n+\tif ((vid != PCI_VENDOR_ID_HITACHI) ||\n+\t ((did != PCI_DEVICE_ID_SH7751) &&\n+\t (did != PCI_DEVICE_ID_SH7751R))) {\n+\t\tdev_err(&pdev->dev, \"This is not an SH7751(R)\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\tdev_info(&pdev->dev, \"PCI core found at %pR\\n\", res);\n+\n+\t/* Set the BCR's to enable PCI access */\n+\tword = __raw_readl(bsc + BSC_BCR1);\n+\tword |= BSC_BCR1_BRQEN;\n+\t__raw_writel(word, bsc + BSC_BCR1);\n+\n+\t/* Turn the clocks back on (not done in reset)*/\n+\twritel(PCIC_WE_KEY | 0, pcic + PCIC_PCICLKR);\n+\t/* Clear Powerdown IRQ's (not done in reset) */\n+\twritel(PCIC_PCIPINT_D3 | PCIC_PCIPINT_D0, pcic + PCIC_PCIPINT);\n+\t/* set the command/status */\n+\tword = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |\n+\t\tPCI_COMMAND_PARITY | PCI_COMMAND_WAIT;\n+\twritel(word, pcic + PCI_COMMAND);\n+\n+\t/* define this host as the host bridge */\n+\twritel(PCI_BASE_CLASS_BRIDGE << 24, pcic + PCI_CLASS_REVISION);\n+\n+\tret = pci_host_common_probe(pdev);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Initialize failed (%d)\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Set IO and Mem windows to local address */\n+\tif (set_pci_ranges(&pdev->dev, pcic, bsc,\n+\t\t\t did == PCI_DEVICE_ID_SH7751R))\n+\t\treturn -EINVAL;\n+\twritel(0, pcic + PCIC_PCIIOBR);\n+\n+\tif (of_property_read_bool(pdev->dev.of_node, \"renesas,bus-arbit-round-robin\"))\n+\t\tword = BIT(0);\n+\telse\n+\t\tword = 0;\n+\twritel(word, pcic + PCIC_PCIDMABT);\n+\n+\t/* SH7751 init done, set central function init complete */\n+\t/* use round robin mode to stop a device starving/overrunning */\n+\twritel(PCIC_WE_KEY | PCIC_PCICR_CFIN | PCIC_PCICR_ARBM, pcic + PCIC_PCICR);\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Direct access to PCI hardware...\n+ */\n+#define CONFIG_CMD(bus, devfn, where) \\\n+\t(0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))\n+\n+static void __iomem *sh4_pci_map_bus(struct pci_bus *bus,\n+\t\t\t\t unsigned int devfn, int where)\n+{\n+\tstruct pci_config_window *cfg = bus->sysdata;\n+\tvoid __iomem *pcic = (void __iomem *)cfg->res.start;\n+\n+\twritel(CONFIG_CMD(bus, devfn, where), pcic + PCIC_PCIPAR);\n+\treturn pcic + PCIC_PCIPDR;\n+}\n+\n+static const struct pci_ecam_ops pci_sh7751_bus_ops = {\n+\t.pci_ops\t= {\n+\t\t.map_bus = sh4_pci_map_bus,\n+\t\t.read = pci_generic_config_read32,\n+\t\t.write = pci_generic_config_write32,\n+\t}\n+};\n+\n+static const struct of_device_id sh7751_pci_of_match[] = {\n+\t{ .compatible = \"renesas,sh7751-pci\",\n+\t .data = &pci_sh7751_bus_ops },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, sh7751_pci_of_match);\n+\n+static struct platform_driver sh7751_pci_driver = {\n+\t.driver = {\n+\t\t.name = \"sh7751-pci\",\n+\t\t.of_match_table = sh7751_pci_of_match,\n+\t},\n+\t.probe = sh7751_pci_probe,\n+};\n+module_platform_driver(sh7751_pci_driver);\n+\n+MODULE_DESCRIPTION(\"SH7751 PCI driver\");\n", "prefixes": [ "DO", "NOT", "MERGE", "v8", "11/36" ] }