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GET /api/patches/1936189/?format=api
{ "id": 1936189, "url": "http://patchwork.ozlabs.org/api/patches/1936189/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20240516181907.3468796-16-eajames@linux.ibm.com/", "project": { "id": 57, "url": "http://patchwork.ozlabs.org/api/projects/57/?format=api", "name": "Linux ASPEED SoC development", "link_name": "linux-aspeed", "list_id": "linux-aspeed.lists.ozlabs.org", "list_email": "linux-aspeed@lists.ozlabs.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20240516181907.3468796-16-eajames@linux.ibm.com>", "list_archive_url": null, "date": "2024-05-16T18:18:42", "name": "[v3,15/40] fsi: aspeed: Use common initialization and link enable", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b56041bba33c902c1eb9c4901a5dc7f6861fc738", "submitter": { "id": 74989, "url": "http://patchwork.ozlabs.org/api/people/74989/?format=api", "name": "Eddie James", "email": "eajames@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20240516181907.3468796-16-eajames@linux.ibm.com/mbox/", "series": [ { "id": 407101, "url": "http://patchwork.ozlabs.org/api/series/407101/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/list/?series=407101", "date": "2024-05-16T18:18:31", "name": "fsi: Add interrupt support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/407101/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1936189/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1936189/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-aspeed@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "linux-aspeed@lists.ozlabs.org" ], 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smtpav05.dal12v.mail.ibm.com (smtpav05.dal12v.mail.ibm.com\n [10.241.53.104])\n\tby smtprelay05.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n 44GIJC0d26411652\n\t(version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK);\n\tThu, 16 May 2024 18:19:14 GMT", "from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 2099358084;\n\tThu, 16 May 2024 18:19:12 +0000 (GMT)", "from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id CF4F158073;\n\tThu, 16 May 2024 18:19:11 +0000 (GMT)", "from slate16.aus.stglabs.ibm.com (unknown [9.61.107.19])\n\tby smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTP;\n\tThu, 16 May 2024 18:19:11 +0000 (GMT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com;\n h=from : to : cc : subject\n : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding; s=pp1;\n bh=i2C43nvKw0UyLSXoCA7myzkhI4FP4JjR32/Jp3Q/4S8=;\n b=kcxeOmqUNSeqYlzzh415K6o8upP8u549P6khtI4vRZOsD3IkfW4U+49dzOShgGfopF0V\n ktxpc9WLtFUZVAovh2rs3s5JTnT+ATCjAto4nTtjVbhV/9eOCLeJK32JJEins4mUiirw\n 0c2anHy/5BcyeGToZqn0Zwl/78SDMVvobiRdFtG/1ZefF+c1nuIMeSxYPMuVIH6cl/sA\n LHWSA4P9VnoUQNq37jHcADftlM7opMC1PKkF6Fq3uWxYmnnionpWc6P/GM8BA5ruAbqV\n 1YpbyX36KbaQ21CvZRoco8usUzoUrpiGGIegQbyQfFEUGxWds6XxKG6SzTThl0mVwFaj Qg==", "From": "Eddie James <eajames@linux.ibm.com>", "To": "linux-fsi@lists.ozlabs.org", "Subject": "[PATCH v3 15/40] fsi: aspeed: Use common initialization and link\n enable", "Date": "Thu, 16 May 2024 13:18:42 -0500", "Message-Id": "<20240516181907.3468796-16-eajames@linux.ibm.com>", "X-Mailer": "git-send-email 2.39.3", "In-Reply-To": "<20240516181907.3468796-1-eajames@linux.ibm.com>", "References": "<20240516181907.3468796-1-eajames@linux.ibm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-TM-AS-GCONF": "00", "X-Proofpoint-ORIG-GUID": "c_Cs3YasAoQVJu-SuocsWfkfMryTR1xg", "X-Proofpoint-GUID": "c_Cs3YasAoQVJu-SuocsWfkfMryTR1xg", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26\n definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n bulkscore=0 adultscore=0\n suspectscore=0 lowpriorityscore=0 mlxscore=0 priorityscore=1501\n spamscore=0 impostorscore=0 phishscore=0 mlxlogscore=999 clxscore=1015\n malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1\n engine=8.12.0-2405010000 definitions=main-2405160132", "X-BeenThere": "linux-aspeed@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux ASPEED SoC development <linux-aspeed.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linux-aspeed>,\n <mailto:linux-aspeed-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linux-aspeed/>", "List-Post": "<mailto:linux-aspeed@lists.ozlabs.org>", "List-Help": "<mailto:linux-aspeed-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linux-aspeed>,\n <mailto:linux-aspeed-request@lists.ozlabs.org?subject=subscribe>", "Cc": "andi.shyti@kernel.org, linux-aspeed@lists.ozlabs.org, jk@ozlabs.org,\n alistair@popple.id.au, linux-kernel@vger.kernel.org,\n linux-spi@vger.kernel.org, broonie@kernel.org, andrew@codeconstruct.com.au,\n linux-i2c@vger.kernel.org", "Errors-To": "linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Linux-aspeed\"\n <linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "Create a regmap for accessing the master registers over OPB\nto use the new common master initialization and link enable procedures.\n\nSigned-off-by: Eddie James <eajames@linux.ibm.com>\n---\nChanges since v2:\n - Add AST2700 direct AHB access of master registers\n\n drivers/fsi/fsi-master-aspeed.c | 173 +++++++++++++-------------------\n 1 file changed, 68 insertions(+), 105 deletions(-)", "diff": "diff --git a/drivers/fsi/fsi-master-aspeed.c b/drivers/fsi/fsi-master-aspeed.c\nindex 3d15e867237df..a67f185bb8814 100644\n--- a/drivers/fsi/fsi-master-aspeed.c\n+++ b/drivers/fsi/fsi-master-aspeed.c\n@@ -27,6 +27,7 @@ struct fsi_master_aspeed {\n \tstruct mutex\t\tlock;\t/* protect HW access */\n \tstruct device\t\t*dev;\n \tvoid __iomem\t\t*base;\n+\tvoid __iomem\t\t*ctrl;\n \tstruct clk\t\t*clk;\n \tstruct gpio_desc\t*cfam_reset_gpio;\n };\n@@ -95,14 +96,6 @@ static const u32 fsi_base = 0xa0000000;\n #define CREATE_TRACE_POINTS\n #include <trace/events/fsi_master_aspeed.h>\n \n-#define FSI_LINK_ENABLE_SETUP_TIME\t10\t/* in mS */\n-\n-/* Run the bus at maximum speed by default */\n-#define FSI_DIVISOR_DEFAULT 1\n-#define FSI_DIVISOR_CABLED 2\n-static u16 aspeed_fsi_divisor = FSI_DIVISOR_DEFAULT;\n-module_param_named(bus_div,aspeed_fsi_divisor, ushort, 0);\n-\n #define OPB_POLL_TIMEOUT\t\t500\n \n static int __opb_write(struct fsi_master_aspeed *aspeed, u32 addr,\n@@ -333,35 +326,6 @@ static int aspeed_master_write(struct fsi_master *master, int link,\n \treturn ret;\n }\n \n-static int aspeed_master_link_enable(struct fsi_master *master, int link,\n-\t\t\t\t bool enable)\n-{\n-\tstruct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master);\n-\tint idx, bit, ret;\n-\t__be32 reg;\n-\n-\tidx = link / 32;\n-\tbit = link % 32;\n-\n-\treg = cpu_to_be32(0x80000000 >> bit);\n-\n-\tmutex_lock(&aspeed->lock);\n-\n-\tif (!enable) {\n-\t\tret = opb_writel(aspeed, ctrl_base + FSI_MCENP0 + (4 * idx), reg);\n-\t\tgoto done;\n-\t}\n-\n-\tret = opb_writel(aspeed, ctrl_base + FSI_MSENP0 + (4 * idx), reg);\n-\tif (ret)\n-\t\tgoto done;\n-\n-\tmdelay(FSI_LINK_ENABLE_SETUP_TIME);\n-done:\n-\tmutex_unlock(&aspeed->lock);\n-\treturn ret;\n-}\n-\n static int aspeed_master_term(struct fsi_master *master, int link, uint8_t id)\n {\n \tuint32_t addr;\n@@ -389,72 +353,54 @@ static void aspeed_master_release(struct device *dev)\n \tstruct fsi_master_aspeed *aspeed =\n \t\tto_fsi_master_aspeed(to_fsi_master(dev));\n \n+\tregmap_exit(aspeed->master.map);\n \tkfree(aspeed);\n }\n \n-/* mmode encoders */\n-static inline u32 fsi_mmode_crs0(u32 x)\n+static int regmap_aspeed_opb_read(void *context, unsigned int reg, unsigned int *val)\n {\n-\treturn (x & FSI_MMODE_CRS0MASK) << FSI_MMODE_CRS0SHFT;\n-}\n+\t__be32 v;\n+\tint ret;\n \n-static inline u32 fsi_mmode_crs1(u32 x)\n-{\n-\treturn (x & FSI_MMODE_CRS1MASK) << FSI_MMODE_CRS1SHFT;\n+\tret = opb_readl(context, ctrl_base + reg, &v);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t*val = be32_to_cpu(v);\n+\treturn 0;\n }\n \n-static int aspeed_master_init(struct fsi_master_aspeed *aspeed)\n+static int regmap_aspeed_opb_write(void *context, unsigned int reg, unsigned int val)\n {\n-\t__be32 reg;\n-\n-\treg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK\n-\t\t\t| FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE);\n-\topb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);\n-\n-\t/* Initialize the MFSI (hub master) engine */\n-\treg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK\n-\t\t\t| FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE);\n-\topb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);\n-\n-\treg = cpu_to_be32(FSI_MECTRL_EOAE | FSI_MECTRL_P8_AUTO_TERM);\n-\topb_writel(aspeed, ctrl_base + FSI_MECTRL, reg);\n-\n-\treg = cpu_to_be32(FSI_MMODE_ECRC | FSI_MMODE_EPC | FSI_MMODE_RELA\n-\t\t\t| fsi_mmode_crs0(aspeed_fsi_divisor)\n-\t\t\t| fsi_mmode_crs1(aspeed_fsi_divisor)\n-\t\t\t| FSI_MMODE_P8_TO_LSB);\n-\tdev_info(aspeed->dev, \"mmode set to %08x (divisor %d)\\n\",\n-\t\t\tbe32_to_cpu(reg), aspeed_fsi_divisor);\n-\topb_writel(aspeed, ctrl_base + FSI_MMODE, reg);\n-\n-\treg = cpu_to_be32(0xffff0000);\n-\topb_writel(aspeed, ctrl_base + FSI_MDLYR, reg);\n-\n-\treg = cpu_to_be32(~0);\n-\topb_writel(aspeed, ctrl_base + FSI_MSENP0, reg);\n-\n-\t/* Leave enabled long enough for master logic to set up */\n-\tmdelay(FSI_LINK_ENABLE_SETUP_TIME);\n-\n-\topb_writel(aspeed, ctrl_base + FSI_MCENP0, reg);\n-\n-\topb_readl(aspeed, ctrl_base + FSI_MAEB, NULL);\n+\treturn opb_writel(context, ctrl_base + reg, cpu_to_be32(val));\n+}\n \n-\treg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK);\n-\topb_writel(aspeed, ctrl_base + FSI_MRESP0, reg);\n+static const struct regmap_bus regmap_aspeed_opb = {\n+\t.reg_write = regmap_aspeed_opb_write,\n+\t.reg_read = regmap_aspeed_opb_read,\n+};\n \n-\topb_readl(aspeed, ctrl_base + FSI_MLEVP0, NULL);\n+static int regmap_ast2700_read(void *context, unsigned int reg, unsigned int *val)\n+{\n+\tstruct fsi_master_aspeed *aspeed = context;\n \n-\t/* Reset the master bridge */\n-\treg = cpu_to_be32(FSI_MRESB_RST_GEN);\n-\topb_writel(aspeed, ctrl_base + FSI_MRESB0, reg);\n+\t*val = readl(aspeed->ctrl + reg);\n+\treturn 0;\n+}\n \n-\treg = cpu_to_be32(FSI_MRESB_RST_ERR);\n-\topb_writel(aspeed, ctrl_base + FSI_MRESB0, reg);\n+static int regmap_ast2700_write(void *context, unsigned int reg, unsigned int val)\n+{\n+\tstruct fsi_master_aspeed *aspeed = context;\n \n+\twritel(val, aspeed->ctrl + reg);\n \treturn 0;\n }\n \n+static const struct regmap_bus regmap_ast2700 = {\n+\t.reg_write = regmap_ast2700_write,\n+\t.reg_read = regmap_ast2700_read,\n+};\n+\n static ssize_t cfam_reset_store(struct device *dev, struct device_attribute *attr,\n \t\t\t\tconst char *buf, size_t count)\n {\n@@ -466,7 +412,7 @@ static ssize_t cfam_reset_store(struct device *dev, struct device_attribute *att\n \tusleep_range(900, 1000);\n \tgpiod_set_value(aspeed->cfam_reset_gpio, 0);\n \tusleep_range(900, 1000);\n-\topb_writel(aspeed, ctrl_base + FSI_MRESP0, cpu_to_be32(FSI_MRESP_RST_ALL_MASTER));\n+\tregmap_write(aspeed->master.map, FSI_MRESP0, FSI_MRESP_RST_ALL_MASTER);\n \tmutex_unlock(&aspeed->lock);\n \ttrace_fsi_master_aspeed_cfam_reset(false);\n \n@@ -526,14 +472,6 @@ static int tacoma_cabled_fsi_fixup(struct device *dev)\n \n \t/* If the routing GPIO is high we should set the mux to low. */\n \tif (gpio) {\n-\t\t/*\n-\t\t * Cable signal integrity means we should run the bus\n-\t\t * slightly slower. Do not override if a kernel param\n-\t\t * has already overridden.\n-\t\t */\n-\t\tif (aspeed_fsi_divisor == FSI_DIVISOR_DEFAULT)\n-\t\t\taspeed_fsi_divisor = FSI_DIVISOR_CABLED;\n-\n \t\tgpiod_direction_output(mux_gpio, 0);\n \t\tdev_info(dev, \"FSI configured for external cable\\n\");\n \t} else {\n@@ -549,9 +487,13 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev)\n {\n \tconst struct fsi_master_aspeed_data *md = of_device_get_match_data(&pdev->dev);\n \tu32 opb_retry_counter = md ? md->opb_retry_counter : OPB_RC_DEFAULT;\n+\tconst struct regmap_bus *bus = ®map_aspeed_opb;\n+\tstruct regmap_config aspeed_master_regmap_config;\n \tstruct fsi_master_aspeed *aspeed;\n-\tint rc, links, reg;\n-\t__be32 raw;\n+\tu32 opb_ctrl_base = ctrl_base;\n+\tstruct resource *res;\n+\tunsigned int reg;\n+\tint rc, links;\n \n \trc = tacoma_cabled_fsi_fixup(&pdev->dev);\n \tif (rc) {\n@@ -571,6 +513,17 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev)\n \t\tgoto err_free_aspeed;\n \t}\n \n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"ctrl\");\n+\tif (res) {\n+\t\taspeed->ctrl = devm_ioremap_resource(&pdev->dev, res);\n+\t\tif (!IS_ERR(aspeed->ctrl)) {\n+\t\t\t/* Access FSI controller over AHB */\n+\t\t\topb_ctrl_base = res->start;\n+\t\t\topb_retry_counter &= ~OPB_RC_CTRL_OPB;\n+\t\t\tbus = ®map_ast2700;\n+\t\t}\n+\t}\n+\n \taspeed->clk = devm_clk_get(aspeed->dev, NULL);\n \tif (IS_ERR(aspeed->clk)) {\n \t\tdev_err(aspeed->dev, \"couldn't get clock\\n\");\n@@ -594,7 +547,7 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev)\n \n \twritel(opb_retry_counter, aspeed->base + OPB_RETRY_COUNTER);\n \n-\twritel(ctrl_base, aspeed->base + OPB_CTRL_BASE);\n+\twritel(opb_ctrl_base, aspeed->base + OPB_CTRL_BASE);\n \twritel(fsi_base, aspeed->base + OPB_FSI_BASE);\n \n \t/* Set read data order */\n@@ -611,13 +564,19 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev)\n \t */\n \twritel(0x1, aspeed->base + OPB0_SELECT);\n \n-\trc = opb_readl(aspeed, ctrl_base + FSI_MVER, &raw);\n+\tfsi_master_regmap_config(&aspeed_master_regmap_config);\n+\taspeed->master.map = regmap_init(&pdev->dev, bus, aspeed, &aspeed_master_regmap_config);\n+\tif (IS_ERR(aspeed->master.map)) {\n+\t\trc = PTR_ERR(aspeed->master.map);\n+\t\tgoto err_release;\n+\t}\n+\n+\trc = regmap_read(aspeed->master.map, FSI_MVER, ®);\n \tif (rc) {\n \t\tdev_err(&pdev->dev, \"failed to read hub version\\n\");\n-\t\tgoto err_release;\n+\t\tgoto err_regmap;\n \t}\n \n-\treg = be32_to_cpu(raw);\n \tlinks = (reg >> 8) & 0xff;\n \tdev_info(&pdev->dev, \"hub version %08x (%d links)\\n\", reg, links);\n \n@@ -626,20 +585,22 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev)\n \taspeed->master.dev.of_node = of_node_get(dev_of_node(&pdev->dev));\n \n \taspeed->master.n_links = links;\n+\taspeed->master.flags = FSI_MASTER_FLAG_RELA;\n \taspeed->master.read = aspeed_master_read;\n \taspeed->master.write = aspeed_master_write;\n \taspeed->master.send_break = aspeed_master_break;\n \taspeed->master.term = aspeed_master_term;\n-\taspeed->master.link_enable = aspeed_master_link_enable;\n \n \tdev_set_drvdata(&pdev->dev, aspeed);\n \n \tmutex_init(&aspeed->lock);\n-\taspeed_master_init(aspeed);\n+\trc = fsi_master_init(&aspeed->master, clk_get_rate(aspeed->clk));\n+\tif (rc)\n+\t\tgoto err_regmap;\n \n \trc = fsi_master_register(&aspeed->master);\n \tif (rc)\n-\t\tgoto err_release;\n+\t\tgoto err_regmap;\n \n \t/* At this point, fsi_master_register performs the device_initialize(),\n \t * and holds the sole reference on master.dev. This means the device\n@@ -651,6 +612,8 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev)\n \tget_device(&aspeed->master.dev);\n \treturn 0;\n \n+err_regmap:\n+\tregmap_exit(aspeed->master.map);\n err_release:\n \tclk_disable_unprepare(aspeed->clk);\n err_free_aspeed:\n", "prefixes": [ "v3", "15/40" ] }