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GET /api/patches/1936172/?format=api
{ "id": 1936172, "url": "http://patchwork.ozlabs.org/api/patches/1936172/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20240516181907.3468796-13-eajames@linux.ibm.com/", "project": { "id": 57, "url": "http://patchwork.ozlabs.org/api/projects/57/?format=api", "name": "Linux ASPEED SoC development", "link_name": "linux-aspeed", "list_id": "linux-aspeed.lists.ozlabs.org", "list_email": "linux-aspeed@lists.ozlabs.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20240516181907.3468796-13-eajames@linux.ibm.com>", "list_archive_url": null, "date": "2024-05-16T18:18:39", "name": "[v3,12/40] fsi: core: Add common regmap master functions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2470f1de06a91221150c5d6ebee56f1760b805fd", "submitter": { "id": 74989, "url": "http://patchwork.ozlabs.org/api/people/74989/?format=api", "name": "Eddie James", "email": "eajames@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20240516181907.3468796-13-eajames@linux.ibm.com/mbox/", "series": [ { "id": 407101, "url": "http://patchwork.ozlabs.org/api/series/407101/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/list/?series=407101", "date": "2024-05-16T18:18:31", "name": "fsi: Add interrupt support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/407101/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1936172/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1936172/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-aspeed@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "linux-aspeed@lists.ozlabs.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=WqLzWZ1u;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=112.213.38.117; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com;\n h=from : to : cc : subject\n : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding; s=pp1;\n bh=7LvYEOFTpxw+bjzxPj1usx5i+DdKwa2ycgUgMyTmWhY=;\n b=WqLzWZ1uZSVkblecTXSc3R/TVZ+tJVfhpr6ta/JHb9lL+GYWolIhn1p+GDPB9f5jqJ0Y\n 05xDdvgGPJBwl3Zsob26m+aixe3BZbcA4j256XEG7CvCzidvpsZp8IbpxrcACuUJY9jO\n rL7HykoI/hOpBIx/fQUAIMyHgZTi2ZvzOl2tM7hS4ZCgwex0AU3K6B3J25jC50F3AO7n\n AXO3zGzDV8krEpQOy5+msku/J3IoZAtru1KFK+N9X4jsWMs/WWseNa30F3F1Wky9qZ1O\n OleqcfsEKf4EiyjoCCkTLFOZbFvfFzIuzgewLyRlTJ+2FQQAwtohJcL4qLySezcIiK+C kg==", "From": "Eddie James <eajames@linux.ibm.com>", "To": "linux-fsi@lists.ozlabs.org", "Subject": "[PATCH v3 12/40] fsi: core: Add common regmap master functions", "Date": "Thu, 16 May 2024 13:18:39 -0500", "Message-Id": "<20240516181907.3468796-13-eajames@linux.ibm.com>", "X-Mailer": "git-send-email 2.39.3", "In-Reply-To": "<20240516181907.3468796-1-eajames@linux.ibm.com>", "References": "<20240516181907.3468796-1-eajames@linux.ibm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-TM-AS-GCONF": "00", "X-Proofpoint-GUID": "Jlr-WwbmGT8S9WoBXaDQDVCLCIiud5Hn", "X-Proofpoint-ORIG-GUID": "Jlr-WwbmGT8S9WoBXaDQDVCLCIiud5Hn", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26\n definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n mlxlogscore=999 phishscore=0\n adultscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0\n mlxscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015\n classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000\n definitions=main-2405160132", "X-BeenThere": "linux-aspeed@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux ASPEED SoC development <linux-aspeed.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linux-aspeed>,\n <mailto:linux-aspeed-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linux-aspeed/>", "List-Post": "<mailto:linux-aspeed@lists.ozlabs.org>", "List-Help": "<mailto:linux-aspeed-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linux-aspeed>,\n <mailto:linux-aspeed-request@lists.ozlabs.org?subject=subscribe>", "Cc": "andi.shyti@kernel.org, linux-aspeed@lists.ozlabs.org, jk@ozlabs.org,\n alistair@popple.id.au, linux-kernel@vger.kernel.org,\n linux-spi@vger.kernel.org, broonie@kernel.org, andrew@codeconstruct.com.au,\n linux-i2c@vger.kernel.org", "Errors-To": "linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Linux-aspeed\"\n <linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "For hardware FSI masters (Aspeed and hub at the moment), the\ninitialization, link enable, and error recovery procedures are\ncommon. Add a regmap pointer to the master structure so that master\ndrivers can let the common code handle these procedures.\n\nSigned-off-by: Eddie James <eajames@linux.ibm.com>\n---\nChanges since v2:\n - Zero the regmap_config structure in the common FSI initialization\n function\n\n drivers/fsi/Kconfig | 2 +\n drivers/fsi/fsi-core.c | 162 ++++++++++++++++++++++++++++++++++++-\n drivers/fsi/fsi-master.h | 16 ++++\n include/trace/events/fsi.h | 17 ++++\n 4 files changed, 195 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/fsi/Kconfig b/drivers/fsi/Kconfig\nindex 79a31593618a6..a6760870538d3 100644\n--- a/drivers/fsi/Kconfig\n+++ b/drivers/fsi/Kconfig\n@@ -7,6 +7,7 @@ menuconfig FSI\n \ttristate \"FSI support\"\n \tdepends on OF\n \tselect CRC4\n+\tselect REGMAP\n \thelp\n \t FSI - the FRU Support Interface - is a simple bus for low-level\n \t access to POWER-based hardware.\n@@ -37,6 +38,7 @@ config FSI_MASTER_GPIO\n \n config FSI_MASTER_HUB\n \ttristate \"FSI hub master\"\n+\tselect REGMAP_FSI\n \thelp\n \tThis option enables a FSI hub master driver. Hub is a type of FSI\n \tmaster that is connected to the upstream master via a slave. Hubs\ndiff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c\nindex 36e31eafad3d0..bfb147de90efc 100644\n--- a/drivers/fsi/fsi-core.c\n+++ b/drivers/fsi/fsi-core.c\n@@ -18,6 +18,7 @@\n #include <linux/of.h>\n #include <linux/of_address.h>\n #include <linux/of_device.h>\n+#include <linux/regmap.h>\n #include <linux/slab.h>\n #include <linux/bitops.h>\n #include <linux/cdev.h>\n@@ -1155,18 +1156,50 @@ static int fsi_master_write(struct fsi_master *master, int link,\n \treturn rc;\n }\n \n+int fsi_master_link_enable(struct fsi_master *master, int link, bool enable)\n+{\n+\tu32 msiep = 0x80000000 >> (4 * (link % 8));\n+\tu32 menp = 0x80000000 >> (link % 32);\n+\tint enable_idx = 4 * (link / 32);\n+\tint irq_idx = 4 * (link / 8);\n+\tint rc;\n+\n+\tif (enable) {\n+\t\trc = regmap_write(master->map, FSI_MSENP0 + enable_idx, menp);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\tmdelay(FSI_LINK_ENABLE_SETUP_TIME);\n+\n+\t\trc = regmap_write(master->map, FSI_MSSIEP0 + irq_idx, msiep);\n+\t} else {\n+\t\trc = regmap_write(master->map, FSI_MCSIEP0 + irq_idx, msiep);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\trc = regmap_write(master->map, FSI_MCENP0 + enable_idx, menp);\n+\t}\n+\n+\treturn rc;\n+}\n+EXPORT_SYMBOL_GPL(fsi_master_link_enable);\n+\n static int fsi_master_link_disable(struct fsi_master *master, int link)\n {\n \tif (master->link_enable)\n \t\treturn master->link_enable(master, link, false);\n+\telse if (master->map)\n+\t\treturn fsi_master_link_enable(master, link, false);\n \n \treturn 0;\n }\n \n-static int fsi_master_link_enable(struct fsi_master *master, int link)\n+static int _fsi_master_link_enable(struct fsi_master *master, int link)\n {\n \tif (master->link_enable)\n \t\treturn master->link_enable(master, link, true);\n+\telse if (master->map)\n+\t\treturn fsi_master_link_enable(master, link, true);\n \n \treturn 0;\n }\n@@ -1194,7 +1227,7 @@ static int fsi_master_scan(struct fsi_master *master)\n \n \ttrace_fsi_master_scan(master, true);\n \tfor (link = 0; link < master->n_links; link++) {\n-\t\trc = fsi_master_link_enable(master, link);\n+\t\trc = _fsi_master_link_enable(master, link);\n \t\tif (rc) {\n \t\t\tdev_dbg(&master->dev,\n \t\t\t\t\"enable link %d failed: %d\\n\", link, rc);\n@@ -1291,6 +1324,131 @@ static struct class fsi_master_class = {\n \t.dev_groups = master_groups,\n };\n \n+void fsi_master_error(struct fsi_master *master, int link)\n+{\n+\tu32 bits = FSI_MMODE_EIP | FSI_MMODE_RELA;\n+\tbool mmode = master->mmode & bits;\n+\n+\tif (trace_fsi_master_error_regs_enabled()) {\n+\t\tunsigned int mesrb = 0xffffffff;\n+\t\tunsigned int mstap = 0xffffffff;\n+\n+\t\tregmap_read(master->map, FSI_MESRB0, &mesrb);\n+\t\tregmap_read(master->map, FSI_MSTAP0 + (link * 4), &mstap);\n+\n+\t\ttrace_fsi_master_error_regs(master->idx, mesrb, mstap);\n+\t}\n+\n+\tif (mmode)\n+\t\tregmap_write(master->map, FSI_MMODE, master->mmode & ~bits);\n+\n+\tregmap_write(master->map, FSI_MRESP0, FSI_MRESP_RST_ALL_MASTER);\n+\n+\tif (mmode)\n+\t\tregmap_write(master->map, FSI_MMODE, master->mmode);\n+}\n+EXPORT_SYMBOL_GPL(fsi_master_error);\n+\n+static inline u32 fsi_mmode_crs0(u32 x)\n+{\n+\treturn (x & FSI_MMODE_CRS0MASK) << FSI_MMODE_CRS0SHFT;\n+}\n+\n+static inline u32 fsi_mmode_crs1(u32 x)\n+{\n+\treturn (x & FSI_MMODE_CRS1MASK) << FSI_MMODE_CRS1SHFT;\n+}\n+\n+int fsi_master_init(struct fsi_master *master, unsigned long parent_clock_frequency)\n+{\n+\tunsigned int mlevp;\n+\tunsigned int maeb;\n+\tint div = 1;\n+\tint rc;\n+\n+\tif (parent_clock_frequency) {\n+\t\tu32 clock_frequency;\n+\n+\t\tif (device_property_read_u32(&master->dev, \"clock-frequency\", &clock_frequency) ||\n+\t\t !clock_frequency)\n+\t\t\tclock_frequency = parent_clock_frequency;\n+\n+\t\tdiv = DIV_ROUND_UP(parent_clock_frequency, clock_frequency);\n+\t\tmaster->clock_frequency = parent_clock_frequency / div;\n+\t}\n+\n+\trc = regmap_write(master->map, FSI_MRESP0, FSI_MRESP_RST_ALL_MASTER |\n+\t\t\t FSI_MRESP_RST_ALL_LINK | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trc = regmap_write(master->map, FSI_MECTRL, FSI_MECTRL_EOAE | FSI_MECTRL_P8_AUTO_TERM);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tmaster->mmode = FSI_MMODE_ECRC | FSI_MMODE_EPC | fsi_mmode_crs0(div) |\n+\t\tfsi_mmode_crs1(div) | FSI_MMODE_P8_TO_LSB;\n+\trc = regmap_write(master->map, FSI_MMODE, master->mmode);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trc = regmap_write(master->map, FSI_MDLYR, 0xffff0000);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trc = regmap_write(master->map, FSI_MSENP0, 0xffffffff);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tmdelay(FSI_LINK_ENABLE_SETUP_TIME);\n+\n+\trc = regmap_write(master->map, FSI_MCENP0, 0xffffffff);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trc = regmap_read(master->map, FSI_MAEB, &maeb);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trc = regmap_write(master->map, FSI_MRESP0, FSI_MRESP_RST_ALL_MASTER |\n+\t\t\t FSI_MRESP_RST_ALL_LINK);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trc = regmap_read(master->map, FSI_MLEVP0, &mlevp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trc = regmap_write(master->map, FSI_MRESB0, FSI_MRESB_RST_GEN);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trc = regmap_write(master->map, FSI_MRESB0, FSI_MRESB_RST_ERR);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (master->flags & FSI_MASTER_FLAG_INTERRUPT)\n+\t\tmaster->mmode |= FSI_MMODE_EIP;\n+\tif (master->flags & FSI_MASTER_FLAG_RELA)\n+\t\tmaster->mmode |= FSI_MMODE_RELA;\n+\treturn regmap_write(master->map, FSI_MMODE, master->mmode);\n+}\n+EXPORT_SYMBOL_GPL(fsi_master_init);\n+\n+void fsi_master_regmap_config(struct regmap_config *config)\n+{\n+\tmemset(config, 0, sizeof(*config));\n+\n+\tconfig->reg_bits = 32;\n+\tconfig->val_bits = 32;\n+\tconfig->disable_locking = true;\t// master driver will lock\n+\tconfig->fast_io = true;\n+\tconfig->cache_type = REGCACHE_NONE;\n+\tconfig->val_format_endian = REGMAP_ENDIAN_NATIVE;\n+\tconfig->can_sleep = false;\n+}\n+EXPORT_SYMBOL_GPL(fsi_master_regmap_config);\n+\n int fsi_master_register(struct fsi_master *master)\n {\n \tint rc;\ndiff --git a/drivers/fsi/fsi-master.h b/drivers/fsi/fsi-master.h\nindex ff23983ea84c8..8ea2f69ec4922 100644\n--- a/drivers/fsi/fsi-master.h\n+++ b/drivers/fsi/fsi-master.h\n@@ -27,6 +27,9 @@\n #define FSI_MLEVP0\t\t0x18\t\t/* R: plug detect */\n #define FSI_MSENP0\t\t0x18\t\t/* S: Set enable */\n #define FSI_MCENP0\t\t0x20\t\t/* C: Clear enable */\n+#define FSI_MSIEP0\t\t0x30\t\t/* R/W: interrupt enable */\n+#define FSI_MSSIEP0\t\t0x50\t\t/* S: Set interrupt enable */\n+#define FSI_MCSIEP0\t\t0x70\t\t/* C: Clear interrupt enable */\n #define FSI_MAEB\t\t0x70\t\t/* R: Error address */\n #define FSI_MVER\t\t0x74\t\t/* R: master version/type */\n #define FSI_MSTAP0\t\t0xd0\t\t/* R: Port status */\n@@ -108,10 +111,16 @@\n \n /* Misc */\n #define\tFSI_CRC_SIZE\t\t4\n+#define FSI_LINK_ENABLE_SETUP_TIME\t10\t/* in mS */\n \n /* fsi-master definition and flags */\n #define FSI_MASTER_FLAG_SWCLOCK\t\t0x1\n #define FSI_MASTER_FLAG_NO_BREAK_SID\t0x2\n+#define FSI_MASTER_FLAG_INTERRUPT\t0x4\n+#define FSI_MASTER_FLAG_RELA\t\t0x8\n+\n+struct regmap;\n+struct regmap_config;\n \n /*\n * Structures and function prototypes\n@@ -121,6 +130,8 @@\n \n struct fsi_master {\n \tstruct device\tdev;\n+\tstruct regmap\t*map;\n+\tu32\t\tmmode;\n \tunsigned long\tclock_frequency;\n \tint\t\tidx;\n \tint\t\tn_links;\n@@ -140,6 +151,11 @@ struct fsi_master {\n \n #define to_fsi_master(d) container_of(d, struct fsi_master, dev)\n \n+void fsi_master_error(struct fsi_master *master, int link);\n+int fsi_master_init(struct fsi_master *master, unsigned long parent_clock_frequency);\n+int fsi_master_link_enable(struct fsi_master *master, int link, bool enable);\n+void fsi_master_regmap_config(struct regmap_config *config);\n+\n /**\n * fsi_master registration & lifetime: the fsi_master_register() and\n * fsi_master_unregister() functions will take ownership of the master, and\ndiff --git a/include/trace/events/fsi.h b/include/trace/events/fsi.h\nindex 5509afc98ee8b..da977d59e163e 100644\n--- a/include/trace/events/fsi.h\n+++ b/include/trace/events/fsi.h\n@@ -67,6 +67,23 @@ TRACE_EVENT(fsi_master_error,\n \t\t &__entry->data, __entry->ret)\n );\n \n+TRACE_EVENT(fsi_master_error_regs,\n+\tTP_PROTO(int master_idx, uint32_t mesrb, uint32_t mstap),\n+\tTP_ARGS(master_idx, mesrb, mstap),\n+\tTP_STRUCT__entry(\n+\t\t__field(int, master_idx)\n+\t\t__field(uint32_t, mesrb)\n+\t\t__field(uint32_t, mstap)\n+\t),\n+\tTP_fast_assign(\n+\t\t__entry->master_idx = master_idx;\n+\t\t__entry->mesrb = mesrb;\n+\t\t__entry->mstap = mstap;\n+\t),\n+\tTP_printk(\"fsi%d mesrb:%08x mstap:%08x\", __entry->master_idx, __entry->mesrb,\n+\t\t __entry->mstap)\n+);\n+\n TRACE_EVENT(fsi_master_break,\n \tTP_PROTO(const struct fsi_master *master, int link),\n \tTP_ARGS(master, link),\n", "prefixes": [ "v3", "12/40" ] }