Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1936162/?format=api
{ "id": 1936162, "url": "http://patchwork.ozlabs.org/api/patches/1936162/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20240516181907.3468796-36-eajames@linux.ibm.com/", "project": { "id": 57, "url": "http://patchwork.ozlabs.org/api/projects/57/?format=api", "name": "Linux ASPEED SoC development", "link_name": "linux-aspeed", "list_id": "linux-aspeed.lists.ozlabs.org", "list_email": "linux-aspeed@lists.ozlabs.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20240516181907.3468796-36-eajames@linux.ibm.com>", "list_archive_url": null, "date": "2024-05-16T18:19:02", "name": "[v3,35/40] fsi: core: Add slave register read-only sysfs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7b4427f547e8ae1f96eb50bc1e44eb8a63e923bb", "submitter": { "id": 74989, "url": "http://patchwork.ozlabs.org/api/people/74989/?format=api", "name": "Eddie James", "email": "eajames@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20240516181907.3468796-36-eajames@linux.ibm.com/mbox/", "series": [ { "id": 407101, "url": "http://patchwork.ozlabs.org/api/series/407101/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/list/?series=407101", "date": "2024-05-16T18:18:31", "name": "fsi: Add interrupt support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/407101/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1936162/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1936162/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-aspeed@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "linux-aspeed@lists.ozlabs.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=AEia5N9s;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org;\n envelope-from=linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n receiver=patchwork.ozlabs.org)", "lists.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=AEia5N9s;\n\tdkim-atps=neutral", "lists.ozlabs.org;\n dmarc=pass (p=none dis=none) header.from=linux.ibm.com", "lists.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=AEia5N9s;\n\tdkim-atps=neutral", "lists.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com\n (client-ip=148.163.158.5; helo=mx0b-001b2d01.pphosted.com;\n envelope-from=eajames@linux.ibm.com; receiver=lists.ozlabs.org)" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org\n [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4VgJMk639nz1yfq\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 May 2024 04:21:54 +1000 (AEST)", "from boromir.ozlabs.org (localhost [IPv6:::1])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 4VgJMk3sRCz3frG\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 May 2024 04:21:54 +1000 (AEST)", "from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n [148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 4VgJK45mXYz3ftD;\n\tFri, 17 May 2024 04:19:36 +1000 (AEST)", "from pps.filterd (m0353725.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 44GF0D2X001858;\n\tThu, 16 May 2024 18:19:22 GMT", "from ppma12.dal12v.mail.ibm.com\n (dc.9e.1632.ip4.static.sl-reverse.com [50.22.158.220])\n\tby mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3y5mce8frv-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n\tThu, 16 May 2024 18:19:21 +0000", "from pps.filterd (ppma12.dal12v.mail.ibm.com [127.0.0.1])\n\tby ppma12.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id\n 44GGV9SF018764;\n\tThu, 16 May 2024 18:19:21 GMT", "from smtprelay02.wdc07v.mail.ibm.com ([172.16.1.69])\n\tby ppma12.dal12v.mail.ibm.com (PPS) with ESMTPS id 3y2k0tuqeg-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n\tThu, 16 May 2024 18:19:21 +0000", "from smtpav05.dal12v.mail.ibm.com (smtpav05.dal12v.mail.ibm.com\n [10.241.53.104])\n\tby smtprelay02.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n 44GIJI7V28050008\n\t(version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK);\n\tThu, 16 May 2024 18:19:20 GMT", "from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 08F5558065;\n\tThu, 16 May 2024 18:19:18 +0000 (GMT)", "from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id B44DD58074;\n\tThu, 16 May 2024 18:19:17 +0000 (GMT)", "from slate16.aus.stglabs.ibm.com (unknown [9.61.107.19])\n\tby smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTP;\n\tThu, 16 May 2024 18:19:17 +0000 (GMT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com;\n h=from : to : cc : subject\n : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding; s=pp1;\n bh=rh16LoMvI5aSfDuJEJUykTNuVLuDCD0QxyjI1piREzo=;\n b=AEia5N9stBz/6PlUWlSTkGRV4blLVzLWjUoS+DsOKILWopa5BxEc5DJEuUGxA7CkVgtf\n maKcTcYgRor6DqSzMSw0tdcO1wiZHSb4RKUdoLTcUpXYTlUVRpI6JOve3n0C5pDdYCXF\n +wszPJFYE6uiR79h8y7KIAXNuaRQtyVH9q0MW6CmjNYG4Nd44MFBpkOFCnAWNipeQ1vQ\n xE0kap4HMkiOem0ouamsAc6xCqQD0uCbTEcE9DvKqVYdWVV4/aUx1ZXBnB8+3E9uG84+\n v0Gzksgy6g6Tc4cUpMPRo/oy1sye1MCl+5S+Vf+01tL5AppA/JRrDjOEGaDNRojh4xJE 3w==", "From": "Eddie James <eajames@linux.ibm.com>", "To": "linux-fsi@lists.ozlabs.org", "Subject": "[PATCH v3 35/40] fsi: core: Add slave register read-only sysfs", "Date": "Thu, 16 May 2024 13:19:02 -0500", "Message-Id": "<20240516181907.3468796-36-eajames@linux.ibm.com>", "X-Mailer": "git-send-email 2.39.3", "In-Reply-To": "<20240516181907.3468796-1-eajames@linux.ibm.com>", "References": "<20240516181907.3468796-1-eajames@linux.ibm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-TM-AS-GCONF": "00", "X-Proofpoint-GUID": "1YthwWDd3b8-ixTTYuqMQDMbuMyPoReq", "X-Proofpoint-ORIG-GUID": "1YthwWDd3b8-ixTTYuqMQDMbuMyPoReq", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26\n definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n mlxlogscore=999 phishscore=0\n adultscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0\n mlxscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015\n classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000\n definitions=main-2405160132", "X-BeenThere": "linux-aspeed@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux ASPEED SoC development <linux-aspeed.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linux-aspeed>,\n <mailto:linux-aspeed-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linux-aspeed/>", "List-Post": "<mailto:linux-aspeed@lists.ozlabs.org>", "List-Help": "<mailto:linux-aspeed-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linux-aspeed>,\n <mailto:linux-aspeed-request@lists.ozlabs.org?subject=subscribe>", "Cc": "andi.shyti@kernel.org, linux-aspeed@lists.ozlabs.org, jk@ozlabs.org,\n alistair@popple.id.au, linux-kernel@vger.kernel.org,\n linux-spi@vger.kernel.org, broonie@kernel.org, andrew@codeconstruct.com.au,\n linux-i2c@vger.kernel.org", "Errors-To": "linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Linux-aspeed\"\n <linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "The slave registers are commonly used for debugging or diagnosis\nso provide them in sysfs files.\n\nSigned-off-by: Eddie James <eajames@linux.ibm.com>\n---\n drivers/fsi/fsi-core.c | 144 +++++++++++++++++++++++++++++++++++++---\n drivers/fsi/fsi-slave.h | 21 ++++++\n 2 files changed, 155 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c\nindex 096b26c6421f2..3d2bedb3ad51b 100644\n--- a/drivers/fsi/fsi-core.c\n+++ b/drivers/fsi/fsi-core.c\n@@ -887,22 +887,146 @@ static ssize_t cfam_id_show(struct device *dev,\n \n static DEVICE_ATTR_RO(cfam_id);\n \n-static struct attribute *cfam_attr[] = {\n+static ssize_t config_table_show(struct device *dev, struct device_attribute *attr, char *buf)\n+{\n+\tconst unsigned int end = engine_page_size / sizeof(u32);\n+\tstruct fsi_slave *slave = to_fsi_slave(dev);\n+\t__be32 data;\n+\tint len = 0;\n+\tu32 conf;\n+\tint rc;\n+\n+\tfor (unsigned int i = 0; i < end; ++i) {\n+\t\trc = fsi_slave_read(slave, i * sizeof(data), &data, sizeof(data));\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\tconf = be32_to_cpu(data);\n+\t\tif (crc4(0, conf, 32))\n+\t\t\treturn -EBADMSG;\n+\n+\t\tlen += sysfs_emit_at(buf, len, \"%08x\\n\", conf);\n+\t\tif (!(conf & FSI_SLAVE_CONF_NEXT_MASK))\n+\t\t\tbreak;\n+\t}\n+\n+\treturn len;\n+}\n+\n+static DEVICE_ATTR_RO(config_table);\n+\n+struct fsi_slave_attribute {\n+\tstruct device_attribute attr;\n+\tint reg;\n+};\n+\n+static ssize_t slave_reg_show(struct device *dev, struct device_attribute *attr, char *buf)\n+{\n+\tstruct fsi_slave_attribute *fattr = container_of(attr, struct fsi_slave_attribute, attr);\n+\tstruct fsi_slave *slave = to_fsi_slave(dev);\n+\t__be32 data;\n+\tint rc;\n+\n+\trc = fsi_slave_read(slave, FSI_SLAVE_BASE + fattr->reg, &data, sizeof(data));\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treturn sysfs_emit(buf, \"%08x\\n\", be32_to_cpu(data));\n+}\n+\n+static ssize_t slave_reg_8bpp_show(struct device *dev, struct device_attribute *attr, char *buf)\n+{\n+\tstruct fsi_slave_attribute *fattr = container_of(attr, struct fsi_slave_attribute, attr);\n+\tstruct fsi_slave *slave = to_fsi_slave(dev);\n+\t__be32 data;\n+\tint len = 0;\n+\tint rc;\n+\tint i;\n+\n+\tfor (i = 0; i < 2; ++i) {\n+\t\trc = fsi_slave_read(slave, FSI_SLAVE_BASE + fattr->reg + (i * 4), &data,\n+\t\t\t\t sizeof(data));\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\tlen += sysfs_emit_at(buf, len, \"%08x\\n\", be32_to_cpu(data));\n+\t}\n+\n+\treturn len;\n+}\n+\n+#define FSI_SLAVE_ATTR(name, reg) \\\n+\tstruct fsi_slave_attribute dev_attr_##name = { __ATTR(name, 0444, slave_reg_show, NULL), reg }\n+#define FSI_SLAVE_ATTR_8BPP(name, reg) \\\n+\tstruct fsi_slave_attribute dev_attr_##name = { __ATTR(name, 0444, slave_reg_8bpp_show, NULL), reg }\n+\n+static FSI_SLAVE_ATTR(smode, FSI_SMODE);\n+static FSI_SLAVE_ATTR(sdma, FSI_SDMA);\n+static FSI_SLAVE_ATTR(sisc, FSI_SISC);\n+static FSI_SLAVE_ATTR(sism, FSI_SISM);\n+static FSI_SLAVE_ATTR(siss, FSI_SISS);\n+static FSI_SLAVE_ATTR(sstat, FSI_SSTAT);\n+static FSI_SLAVE_ATTR(si1m, FSI_SI1M);\n+static FSI_SLAVE_ATTR(si1s, FSI_SI1S);\n+static FSI_SLAVE_ATTR(sic, FSI_SIC);\n+static FSI_SLAVE_ATTR(si2m, FSI_SI2M);\n+static FSI_SLAVE_ATTR(si2s, FSI_SI2S);\n+static FSI_SLAVE_ATTR(scmdt, FSI_SCMDT);\n+static FSI_SLAVE_ATTR(sdata, FSI_SDATA);\n+static FSI_SLAVE_ATTR(slastd, FSI_SLASTD);\n+static FSI_SLAVE_ATTR(smbl, FSI_SMBL);\n+static FSI_SLAVE_ATTR(soml, FSI_SOML);\n+static FSI_SLAVE_ATTR(snml, FSI_SNML);\n+static FSI_SLAVE_ATTR(smbr, FSI_SMBR);\n+static FSI_SLAVE_ATTR(somr, FSI_SOMR);\n+static FSI_SLAVE_ATTR(snmr, FSI_SNMR);\n+static FSI_SLAVE_ATTR_8BPP(scrsic, FSI_ScRSIC0);\n+static FSI_SLAVE_ATTR_8BPP(scrsim, FSI_ScRSIM0);\n+static FSI_SLAVE_ATTR_8BPP(scrsis, FSI_ScRSIS0);\n+static FSI_SLAVE_ATTR_8BPP(srsic, FSI_SRSIC0);\n+static FSI_SLAVE_ATTR_8BPP(srsim, FSI_SRSIM0);\n+static FSI_SLAVE_ATTR_8BPP(srsis, FSI_SRSIS0);\n+static FSI_SLAVE_ATTR(llmode, FSI_LLMODE);\n+static FSI_SLAVE_ATTR(llstat, FSI_LLSTAT);\n+\n+static struct attribute *cfam_attrs[] = {\n \t&dev_attr_send_echo_delays.attr,\n \t&dev_attr_chip_id.attr,\n \t&dev_attr_cfam_id.attr,\n \t&dev_attr_send_term.attr,\n+\t&dev_attr_config_table.attr,\n+\t&dev_attr_smode.attr.attr,\n+\t&dev_attr_sdma.attr.attr,\n+\t&dev_attr_sisc.attr.attr,\n+\t&dev_attr_sism.attr.attr,\n+\t&dev_attr_siss.attr.attr,\n+\t&dev_attr_sstat.attr.attr,\n+\t&dev_attr_si1m.attr.attr,\n+\t&dev_attr_si1s.attr.attr,\n+\t&dev_attr_sic.attr.attr,\n+\t&dev_attr_si2m.attr.attr,\n+\t&dev_attr_si2s.attr.attr,\n+\t&dev_attr_scmdt.attr.attr,\n+\t&dev_attr_sdata.attr.attr,\n+\t&dev_attr_slastd.attr.attr,\n+\t&dev_attr_smbl.attr.attr,\n+\t&dev_attr_soml.attr.attr,\n+\t&dev_attr_snml.attr.attr,\n+\t&dev_attr_smbr.attr.attr,\n+\t&dev_attr_somr.attr.attr,\n+\t&dev_attr_snmr.attr.attr,\n+\t&dev_attr_scrsic.attr.attr,\n+\t&dev_attr_scrsim.attr.attr,\n+\t&dev_attr_scrsis.attr.attr,\n+\t&dev_attr_srsic.attr.attr,\n+\t&dev_attr_srsim.attr.attr,\n+\t&dev_attr_srsis.attr.attr,\n+\t&dev_attr_llmode.attr.attr,\n+\t&dev_attr_llstat.attr.attr,\n \tNULL,\n };\n \n-static const struct attribute_group cfam_attr_group = {\n-\t.attrs = cfam_attr,\n-};\n-\n-static const struct attribute_group *cfam_attr_groups[] = {\n-\t&cfam_attr_group,\n-\tNULL,\n-};\n+ATTRIBUTE_GROUPS(cfam);\n \n static char *cfam_devnode(const struct device *dev, umode_t *mode,\n \t\t\t kuid_t *uid, kgid_t *gid)\n@@ -919,7 +1043,7 @@ static char *cfam_devnode(const struct device *dev, umode_t *mode,\n static const struct device_type cfam_type = {\n \t.name = \"cfam\",\n \t.devnode = cfam_devnode,\n-\t.groups = cfam_attr_groups\n+\t.groups = cfam_groups\n };\n \n static char *fsi_cdev_devnode(const struct device *dev, umode_t *mode,\ndiff --git a/drivers/fsi/fsi-slave.h b/drivers/fsi/fsi-slave.h\nindex 0468ec1c60db2..1478ee561b85c 100644\n--- a/drivers/fsi/fsi-slave.h\n+++ b/drivers/fsi/fsi-slave.h\n@@ -14,6 +14,7 @@\n * FSI slave engine control register offsets\n */\n #define FSI_SMODE\t\t0x0\t/* R/W: Mode register */\n+#define FSI_SDMA\t\t0x4\t/* R/W: DMA control */\n #define FSI_SISC\t\t0x8\t/* R : Interrupt condition */\n #define FSI_SCISC\t\t0x8\t/* C : Clear interrupt condition */\n #define FSI_SISM\t\t0xc\t/* R/W: Interrupt mask */\n@@ -21,11 +22,30 @@\n #define FSI_SSISM\t\t0x10\t/* S : Set interrupt mask */\n #define FSI_SCISM\t\t0x14\t/* C : Clear interrupt mask */\n #define FSI_SSTAT\t\t0x14\t/* R : Slave status */\n+#define FSI_SI1M\t\t0x18\t/* R/W: Interrupt 1 mask */\n #define FSI_SI1S\t\t0x1c\t/* R : Slave interrupt 1 status */\n #define FSI_SSI1M\t\t0x1c\t/* S : Set slave interrupt 1 mask */\n+#define FSI_SIC\t\t\t0x20\t/* R : Interrupt 1 condition */\n #define FSI_SCI1M\t\t0x20\t/* C : Clear slave interrupt 1 mask */\n+#define FSI_SI2M\t\t0x24\t/* R/W: Interrupt 2 mask */\n+#define FSI_SI2S\t\t0x28\t/* R : Interrupt 2 status */\n+#define FSI_SCMDT\t\t0x2c\t/* R : Last command trace */\n+#define FSI_SDATA\t\t0x30\t/* R : Last data trace */\n #define FSI_SLBUS\t\t0x30\t/* W : LBUS Ownership */\n+#define FSI_SLASTD\t\t0x34\t/* R : Last data sent */\n #define FSI_SRES\t\t0x34\t/* W : Reset */\n+#define FSI_SMBL\t\t0x38\n+#define FSI_SOML\t\t0x3c\n+#define FSI_SNML\t\t0x40\n+#define FSI_SMBR\t\t0x44\n+#define FSI_SOMR\t\t0x48\n+#define FSI_SNMR\t\t0x4c\n+#define FSI_ScRSIC0\t\t0x50\n+#define FSI_ScRSIC4\t\t0x54\n+#define FSI_ScRSIM0\t\t0x58\n+#define FSI_ScRSIM4\t\t0x5c\n+#define FSI_ScRSIS0\t\t0x60\n+#define FSI_ScRSIS4\t\t0x64\n #define FSI_SRSIC0\t\t0x68\t/* C : Clear remote interrupt condition */\n #define FSI_SRSIC4\t\t0x6c\t/* C : Clear remote interrupt condition */\n #define FSI_SRSIM0\t\t0x70\t/* R/W: Remote interrupt mask */\n@@ -33,6 +53,7 @@\n #define FSI_SRSIS0\t\t0x78\t/* R : Remote interrupt status */\n #define FSI_SRSIS4\t\t0x7c\t/* R : Remote interrupt status */\n #define FSI_LLMODE\t\t0x100\t/* R/W: Link layer mode register */\n+#define FSI_LLSTAT\t\t0x104\n \n /*\n * SMODE fields\n", "prefixes": [ "v3", "35/40" ] }