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GET /api/patches/1886148/?format=api
{ "id": 1886148, "url": "http://patchwork.ozlabs.org/api/patches/1886148/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20240112142621.13525-2-prabhakar.mahadev-lad.rj@bp.renesas.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20240112142621.13525-2-prabhakar.mahadev-lad.rj@bp.renesas.com>", "list_archive_url": null, "date": "2024-01-12T14:26:18", "name": "[v4,1/4] pinctrl: renesas: rzg2l: Improve code for readability", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "426ea18ffa299900c28cb02121b0e1b8b543fddc", "submitter": { "id": 9539, "url": "http://patchwork.ozlabs.org/api/people/9539/?format=api", "name": "Lad, Prabhakar", "email": "prabhakar.csengg@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20240112142621.13525-2-prabhakar.mahadev-lad.rj@bp.renesas.com/mbox/", "series": [ { "id": 390295, "url": "http://patchwork.ozlabs.org/api/series/390295/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=390295", "date": "2024-01-12T14:26:17", "name": "Add missing port pins for RZ/Five SoC", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/390295/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1886148/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1886148/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-2166-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], 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<prabhakar.mahadev-lad.rj@bp.renesas.com>", "Subject": "[PATCH v4 1/4] pinctrl: renesas: rzg2l: Improve code for readability", "Date": "Fri, 12 Jan 2024 14:26:18 +0000", "Message-Id": "<20240112142621.13525-2-prabhakar.mahadev-lad.rj@bp.renesas.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240112142621.13525-1-prabhakar.mahadev-lad.rj@bp.renesas.com>", "References": "<20240112142621.13525-1-prabhakar.mahadev-lad.rj@bp.renesas.com>", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>\n\nAs the RZ/G2L pinctrl driver is extensively utilized by numerous SoCs and\nhas experienced substantial growth, enhance code readability by\nincorporating FIELD_PREP_CONST/FIELD_GET macros wherever necessary.\n\nSigned-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>\n---\n drivers/pinctrl/renesas/pinctrl-rzg2l.c | 41 +++++++++++++++----------\n 1 file changed, 24 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\nindex e90d47136889..fee348b80892 100644\n--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n@@ -5,6 +5,7 @@\n * Copyright (C) 2021 Renesas Electronics Corporation.\n */\n \n+#include <linux/bitfield.h>\n #include <linux/bitops.h>\n #include <linux/clk.h>\n #include <linux/gpio/driver.h>\n@@ -38,8 +39,6 @@\n */\n #define MUX_PIN_ID_MASK\t\tGENMASK(15, 0)\n #define MUX_FUNC_MASK\t\tGENMASK(31, 16)\n-#define MUX_FUNC_OFFS\t\t16\n-#define MUX_FUNC(pinconf)\t(((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)\n \n /* PIN capabilities */\n #define PIN_CFG_IOLH_A\t\t\tBIT(0)\n@@ -81,8 +80,12 @@\n * n indicates number of pins in the port, a is the register index\n * and f is pin configuration capabilities supported.\n */\n-#define RZG2L_GPIO_PORT_PACK(n, a, f)\t(((n) << 28) | ((a) << 20) | (f))\n-#define RZG2L_GPIO_PORT_GET_PINCNT(x)\t(((x) & GENMASK(30, 28)) >> 28)\n+#define PIN_CFG_PIN_CNT_MASK\t\tGENMASK(30, 28)\n+#define PIN_CFG_PIN_REG_MASK\t\tGENMASK(27, 20)\n+#define PIN_CFG_MASK\t\t\tGENMASK(19, 0)\n+#define RZG2L_GPIO_PORT_PACK(n, a, f)\t(FIELD_PREP_CONST(PIN_CFG_PIN_CNT_MASK, (n)) | \\\n+\t\t\t\t\t FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \\\n+\t\t\t\t\t FIELD_PREP_CONST(PIN_CFG_MASK, (f)))\n \n /*\n * BIT(31) indicates dedicated pin, p is the register index while\n@@ -90,14 +93,18 @@\n * (b * 8) and f is the pin configuration capabilities supported.\n */\n #define RZG2L_SINGLE_PIN\t\tBIT(31)\n+#define RZG2L_SINGLE_PIN_INDEX_MASK\tGENMASK(30, 24)\n+#define RZG2L_SINGLE_PIN_BITS_MASK\tGENMASK(22, 20)\n+\n #define RZG2L_SINGLE_PIN_PACK(p, b, f)\t(RZG2L_SINGLE_PIN | \\\n-\t\t\t\t\t ((p) << 24) | ((b) << 20) | (f))\n-#define RZG2L_SINGLE_PIN_GET_BIT(x)\t(((x) & GENMASK(22, 20)) >> 20)\n+\t\t\t\t\t FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \\\n+\t\t\t\t\t FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \\\n+\t\t\t\t\t FIELD_PREP_CONST(PIN_CFG_MASK, (f)))\n \n-#define RZG2L_PIN_CFG_TO_CAPS(cfg)\t\t((cfg) & GENMASK(19, 0))\n+#define RZG2L_PIN_CFG_TO_CAPS(cfg)\t\t((cfg) & PIN_CFG_MASK)\n #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg)\t((cfg) & RZG2L_SINGLE_PIN ? \\\n-\t\t\t\t\t\t(((cfg) & GENMASK(30, 24)) >> 24) : \\\n-\t\t\t\t\t\t(((cfg) & GENMASK(26, 20)) >> 20))\n+\t\t\t\t\t\t FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \\\n+\t\t\t\t\t\t FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg)))\n \n #define P(off)\t\t\t(0x0000 + (off))\n #define PM(off)\t\t\t(0x0100 + (off) * 2)\n@@ -432,8 +439,8 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,\n \t\tret = of_property_read_u32_index(np, \"pinmux\", i, &value);\n \t\tif (ret)\n \t\t\tgoto done;\n-\t\tpins[i] = value & MUX_PIN_ID_MASK;\n-\t\tpsel_val[i] = MUX_FUNC(value);\n+\t\tpins[i] = FIELD_GET(MUX_PIN_ID_MASK, value);\n+\t\tpsel_val[i] = FIELD_GET(MUX_FUNC_MASK, value);\n \t}\n \n \tif (parent) {\n@@ -560,7 +567,7 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,\n static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,\n \t\t\t\t u32 cfg, u32 port, u8 bit)\n {\n-\tu8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg);\n+\tu8 pincount = FIELD_GET(PIN_CFG_PIN_CNT_MASK, cfg);\n \tu32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);\n \tu32 data;\n \n@@ -868,7 +875,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,\n \toff = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);\n \tcfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data);\n \tif (*pin_data & RZG2L_SINGLE_PIN) {\n-\t\tbit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);\n+\t\tbit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data);\n \t} else {\n \t\tbit = RZG2L_PIN_ID_TO_PIN(_pin);\n \n@@ -972,7 +979,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,\n \toff = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);\n \tcfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data);\n \tif (*pin_data & RZG2L_SINGLE_PIN) {\n-\t\tbit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);\n+\t\tbit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data);\n \t} else {\n \t\tbit = RZG2L_PIN_ID_TO_PIN(_pin);\n \n@@ -1608,12 +1615,12 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_\n \tbit = virq % 8;\n \n \tif (port >= data->n_ports ||\n-\t bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port]))\n+\t bit >= FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[port]))\n \t\treturn -EINVAL;\n \n \tgpioint = bit;\n \tfor (i = 0; i < port; i++)\n-\t\tgpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]);\n+\t\tgpioint += FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[i]);\n \n \treturn gpioint;\n }\n@@ -1788,7 +1795,7 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc,\n \t\tbit = offset % 8;\n \n \t\tif (port >= pctrl->data->n_ports ||\n-\t\t bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port]))\n+\t\t bit >= FIELD_GET(PIN_CFG_PIN_CNT_MASK, pctrl->data->port_pin_configs[port]))\n \t\t\tclear_bit(offset, valid_mask);\n \t}\n }\n", "prefixes": [ "v4", "1/4" ] }